1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AVR specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "AVRTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/LegacyPassManager.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/Support/TargetRegistry.h"
23 #include "AVRTargetObjectFile.h"
24 #include "MCTargetDesc/AVRMCTargetDesc.h"
28 static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8";
30 /// Processes a CPU name.
31 static StringRef getCPU(StringRef CPU) {
32 if (CPU.empty() || CPU == "generic") {
39 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
40 return RM.hasValue() ? *RM : Reloc::Static;
43 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
44 StringRef CPU, StringRef FS,
45 const TargetOptions &Options,
46 Optional<Reloc::Model> RM, CodeModel::Model CM,
50 getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL),
51 SubTarget(TT, getCPU(CPU), FS, *this) {
52 this->TLOF = make_unique<AVRTargetObjectFile>();
57 /// AVR Code Generator Pass Configuration Options.
58 class AVRPassConfig : public TargetPassConfig {
60 AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
61 : TargetPassConfig(TM, PM) {}
63 AVRTargetMachine &getAVRTargetMachine() const {
64 return getTM<AVRTargetMachine>();
67 bool addInstSelector() override;
68 void addPreSched2() override;
69 void addPreEmitPass() override;
70 void addPreRegAlloc() override;
74 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
75 return new AVRPassConfig(*this, PM);
78 extern "C" void LLVMInitializeAVRTarget() {
79 // Register the target.
80 RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
82 auto &PR = *PassRegistry::getPassRegistry();
83 initializeAVRExpandPseudoPass(PR);
84 initializeAVRInstrumentFunctionsPass(PR);
85 initializeAVRRelaxMemPass(PR);
88 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
92 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
96 //===----------------------------------------------------------------------===//
97 // Pass Pipeline Configuration
98 //===----------------------------------------------------------------------===//
100 bool AVRPassConfig::addInstSelector() {
101 // Install an instruction selector.
102 addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
103 // Create the frame analyzer pass used by the PEI pass.
104 addPass(createAVRFrameAnalyzerPass());
109 void AVRPassConfig::addPreRegAlloc() {
110 // Create the dynalloc SP save/restore pass to handle variable sized allocas.
111 addPass(createAVRDynAllocaSRPass());
114 void AVRPassConfig::addPreSched2() {
115 addPass(createAVRRelaxMemPass());
116 addPass(createAVRExpandPseudoPass());
119 void AVRPassConfig::addPreEmitPass() {
120 // Must run branch selection immediately preceding the asm printer.
121 addPass(&BranchRelaxationPassID);
124 } // end of namespace llvm