1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCELFStreamer.h"
13 #include "MCTargetDesc/AVRMCExpr.h"
14 #include "MCTargetDesc/AVRMCTargetDesc.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstBuilder.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MCValue.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/TargetRegistry.h"
35 #define DEBUG_TYPE "avr-asm-parser"
39 /// Parses AVR assembly from a stream.
40 class AVRAsmParser : public MCTargetAsmParser {
41 const MCSubtargetInfo &STI;
43 const MCRegisterInfo *MRI;
44 const std::string GENERATE_STUBS = "gs";
46 #define GET_ASSEMBLER_HEADER
47 #include "AVRGenAsmMatcher.inc"
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
54 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
56 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
57 SMLoc NameLoc, OperandVector &Operands) override;
59 bool ParseDirective(AsmToken DirectiveID) override;
61 OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
63 bool parseOperand(OperandVector &Operands);
64 int parseRegisterName(unsigned (*matchFn)(StringRef));
65 int parseRegisterName();
67 bool tryParseRegisterOperand(OperandVector &Operands);
68 bool tryParseExpression(OperandVector &Operands);
69 bool tryParseRelocExpression(OperandVector &Operands);
72 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
73 unsigned Kind) override;
75 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
76 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
77 return MRI->getMatchingSuperReg(Reg, From, Class);
80 bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
81 bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
82 uint64_t const &ErrorInfo);
83 bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
85 bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
88 AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
89 const MCInstrInfo &MII, const MCTargetOptions &Options)
90 : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
91 MCAsmParserExtension::Initialize(Parser);
92 MRI = getContext().getRegisterInfo();
94 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
97 MCAsmParser &getParser() const { return Parser; }
98 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 /// An parsed AVR assembly operand.
102 class AVROperand : public MCParsedAsmOperand {
103 typedef MCParsedAsmOperand Base;
104 enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
107 AVROperand(StringRef Tok, SMLoc const &S)
108 : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
109 AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
110 : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
111 AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
112 : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
113 AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
114 : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
116 struct RegisterImmediate {
122 RegisterImmediate RegImm;
128 void addRegOperands(MCInst &Inst, unsigned N) const {
129 assert(Kind == k_Register && "Unexpected operand kind");
130 assert(N == 1 && "Invalid number of operands!");
132 Inst.addOperand(MCOperand::createReg(getReg()));
135 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
136 // Add as immediate when possible
138 Inst.addOperand(MCOperand::createImm(0));
139 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
140 Inst.addOperand(MCOperand::createImm(CE->getValue()));
142 Inst.addOperand(MCOperand::createExpr(Expr));
145 void addImmOperands(MCInst &Inst, unsigned N) const {
146 assert(Kind == k_Immediate && "Unexpected operand kind");
147 assert(N == 1 && "Invalid number of operands!");
149 const MCExpr *Expr = getImm();
153 /// Adds the contained reg+imm operand to an instruction.
154 void addMemriOperands(MCInst &Inst, unsigned N) const {
155 assert(Kind == k_Memri && "Unexpected operand kind");
156 assert(N == 2 && "Invalid number of operands");
158 Inst.addOperand(MCOperand::createReg(getReg()));
159 addExpr(Inst, getImm());
162 bool isReg() const { return Kind == k_Register; }
163 bool isImm() const { return Kind == k_Immediate; }
164 bool isToken() const { return Kind == k_Token; }
165 bool isMem() const { return Kind == k_Memri; }
166 bool isMemri() const { return Kind == k_Memri; }
168 StringRef getToken() const {
169 assert(Kind == k_Token && "Invalid access!");
173 unsigned getReg() const {
174 assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
179 const MCExpr *getImm() const {
180 assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
184 static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
185 return make_unique<AVROperand>(Str, S);
188 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
190 return make_unique<AVROperand>(RegNum, S, E);
193 static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
195 return make_unique<AVROperand>(Val, S, E);
198 static std::unique_ptr<AVROperand>
199 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
200 return make_unique<AVROperand>(RegNum, Val, S, E);
203 void makeToken(StringRef Token) {
208 void makeReg(unsigned RegNo) {
210 RegImm = {RegNo, nullptr};
213 void makeImm(MCExpr const *Ex) {
218 void makeMemri(unsigned RegNo, MCExpr const *Imm) {
220 RegImm = {RegNo, Imm};
223 SMLoc getStartLoc() const { return Start; }
224 SMLoc getEndLoc() const { return End; }
226 virtual void print(raw_ostream &O) const {
229 O << "Token: \"" << getToken() << "\"";
232 O << "Register: " << getReg();
235 O << "Immediate: \"" << *getImm() << "\"";
238 // only manually print the size for non-negative values,
239 // as the sign is inserted automatically.
240 O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
248 // Auto-generated Match Functions
250 /// Maps from the set of all register names to a register number.
251 /// \note Generated by TableGen.
252 static unsigned MatchRegisterName(StringRef Name);
254 /// Maps from the set of all alternative registernames to a register number.
255 /// \note Generated by TableGen.
256 static unsigned MatchRegisterAltName(StringRef Name);
258 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
259 OperandVector const &Operands,
260 uint64_t const &ErrorInfo) {
261 SMLoc ErrorLoc = Loc;
262 char const *Diag = 0;
264 if (ErrorInfo != ~0U) {
265 if (ErrorInfo >= Operands.size()) {
266 Diag = "too few operands for instruction.";
268 AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
270 // TODO: See if we can do a better error than just "invalid ...".
271 if (Op.getStartLoc() != SMLoc()) {
272 ErrorLoc = Op.getStartLoc();
278 Diag = "invalid operand for instruction";
281 return Error(ErrorLoc, Diag);
284 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
285 uint64_t const &ErrorInfo) {
286 return Error(Loc, "instruction requires a CPU feature not currently enabled");
289 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
291 Out.EmitInstruction(Inst, STI);
296 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
297 OperandVector &Operands,
298 MCStreamer &Out, uint64_t &ErrorInfo,
299 bool MatchingInlineAsm) {
301 unsigned MatchResult =
302 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
304 switch (MatchResult) {
305 case Match_Success: return emit(Inst, Loc, Out);
306 case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
307 case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
308 case Match_MnemonicFail: return Error(Loc, "invalid instruction");
309 default: return true;
313 /// Parses a register name using a given matching function.
314 /// Checks for lowercase or uppercase if necessary.
315 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
316 StringRef Name = Parser.getTok().getString();
318 int RegNum = matchFn(Name);
320 // GCC supports case insensitive register names. Some of the AVR registers
321 // are all lower case, some are all upper case but non are mixed. We prefer
322 // to use the original names in the register definitions. That is why we
323 // have to test both upper and lower case here.
324 if (RegNum == AVR::NoRegister) {
325 RegNum = matchFn(Name.lower());
327 if (RegNum == AVR::NoRegister) {
328 RegNum = matchFn(Name.upper());
334 int AVRAsmParser::parseRegisterName() {
335 int RegNum = parseRegisterName(&MatchRegisterName);
337 if (RegNum == AVR::NoRegister)
338 RegNum = parseRegisterName(&MatchRegisterAltName);
343 int AVRAsmParser::parseRegister() {
344 int RegNum = AVR::NoRegister;
346 if (Parser.getTok().is(AsmToken::Identifier)) {
347 // Check for register pair syntax
348 if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
350 Parser.Lex(); // Eat high (odd) register and colon
352 if (Parser.getTok().is(AsmToken::Identifier)) {
353 // Convert lower (even) register to DREG
354 RegNum = toDREG(parseRegisterName());
357 RegNum = parseRegisterName();
363 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
364 int RegNo = parseRegister();
366 if (RegNo == AVR::NoRegister)
369 AsmToken const &T = Parser.getTok();
370 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
371 Parser.Lex(); // Eat register token.
376 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
377 SMLoc S = Parser.getTok().getLoc();
379 if (!tryParseRelocExpression(Operands))
382 if ((Parser.getTok().getKind() == AsmToken::Plus ||
383 Parser.getTok().getKind() == AsmToken::Minus) &&
384 Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
385 // Don't handle this case - it should be split into two
390 // Parse (potentially inner) expression
391 MCExpr const *Expression;
392 if (getParser().parseExpression(Expression))
395 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
396 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
400 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
401 bool isNegated = false;
402 AVRMCExpr::VariantKind ModifierKind = AVRMCExpr::VK_AVR_None;
404 SMLoc S = Parser.getTok().getLoc();
408 size_t ReadCount = Parser.getLexer().peekTokens(tokens);
410 if (ReadCount == 2) {
411 if ((tokens[0].getKind() == AsmToken::Identifier &&
412 tokens[1].getKind() == AsmToken::LParen) ||
413 (tokens[0].getKind() == AsmToken::LParen &&
414 tokens[1].getKind() == AsmToken::Minus)) {
416 AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
417 if (CurTok == AsmToken::Minus ||
418 tokens[1].getKind() == AsmToken::Minus) {
421 assert(CurTok == AsmToken::Plus);
426 if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
431 // Check if we have a target specific modifier (lo8, hi8, &c)
432 if (Parser.getTok().getKind() != AsmToken::Identifier ||
433 Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
437 StringRef ModifierName = Parser.getTok().getString();
438 ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
440 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
442 Parser.Lex(); // Eat modifier name and parenthesis
443 if (Parser.getTok().getString() == GENERATE_STUBS &&
444 Parser.getTok().getKind() == AsmToken::Identifier) {
445 std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
446 ModifierKind = AVRMCExpr::getKindByName(GSModName.c_str());
447 if (ModifierKind != AVRMCExpr::VK_AVR_None)
448 Parser.Lex(); // Eat gs modifier name
451 return Error(Parser.getTok().getLoc(), "unknown modifier");
454 if (tokens[1].getKind() == AsmToken::Minus ||
455 tokens[1].getKind() == AsmToken::Plus) {
457 assert(Parser.getTok().getKind() == AsmToken::LParen);
458 Parser.Lex(); // Eat the sign and parenthesis
461 MCExpr const *InnerExpression;
462 if (getParser().parseExpression(InnerExpression))
465 if (tokens[1].getKind() == AsmToken::Minus ||
466 tokens[1].getKind() == AsmToken::Plus) {
467 assert(Parser.getTok().getKind() == AsmToken::RParen);
468 Parser.Lex(); // Eat closing parenthesis
471 // If we have a modifier wrap the inner expression
472 assert(Parser.getTok().getKind() == AsmToken::RParen);
473 Parser.Lex(); // Eat closing parenthesis
475 MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
476 isNegated, getContext());
478 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
479 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
484 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
485 LLVM_DEBUG(dbgs() << "parseOperand\n");
487 switch (getLexer().getKind()) {
489 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
491 case AsmToken::Identifier:
492 // Try to parse a register, if it fails,
493 // fall through to the next case.
494 if (!tryParseRegisterOperand(Operands)) {
498 case AsmToken::LParen:
499 case AsmToken::Integer:
501 return tryParseExpression(Operands);
503 case AsmToken::Minus: {
504 // If the sign preceeds a number, parse the number,
505 // otherwise treat the sign a an independent token.
506 switch (getLexer().peekTok().getKind()) {
507 case AsmToken::Integer:
508 case AsmToken::BigNum:
509 case AsmToken::Identifier:
511 if (!tryParseExpression(Operands))
516 // Treat the token as an independent token.
517 Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
518 Parser.getTok().getLoc()));
519 Parser.Lex(); // Eat the token.
524 // Could not parse operand
529 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
530 LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
533 MCExpr const *Expression;
538 RegNo = parseRegister();
540 if (RegNo == AVR::NoRegister)
541 return MatchOperand_ParseFail;
543 S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
544 Parser.Lex(); // Eat register token.
549 if (getParser().parseExpression(Expression))
550 return MatchOperand_ParseFail;
552 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
555 Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
557 return MatchOperand_Success;
560 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
562 StartLoc = Parser.getTok().getLoc();
563 RegNo = parseRegister();
564 EndLoc = Parser.getTok().getLoc();
566 return (RegNo == AVR::NoRegister);
569 void AVRAsmParser::eatComma() {
570 if (getLexer().is(AsmToken::Comma)) {
573 // GCC allows commas to be omitted.
577 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
578 StringRef Mnemonic, SMLoc NameLoc,
579 OperandVector &Operands) {
580 Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
583 while (getLexer().isNot(AsmToken::EndOfStatement)) {
584 if (!first) eatComma();
588 auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
590 if (MatchResult == MatchOperand_Success) {
594 if (MatchResult == MatchOperand_ParseFail) {
595 SMLoc Loc = getLexer().getLoc();
596 Parser.eatToEndOfStatement();
598 return Error(Loc, "failed to parse register and immediate pair");
601 if (parseOperand(Operands)) {
602 SMLoc Loc = getLexer().getLoc();
603 Parser.eatToEndOfStatement();
604 return Error(Loc, "unexpected token in argument list");
607 Parser.Lex(); // Consume the EndOfStatement
611 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
612 StringRef IDVal = DirectiveID.getIdentifier();
613 if (IDVal.lower() == ".long") {
614 parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
615 } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
616 parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
617 } else if (IDVal.lower() == ".byte") {
618 parseLiteralValues(1, DirectiveID.getLoc());
623 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
624 MCAsmParser &Parser = getParser();
625 AVRMCELFStreamer &AVRStreamer =
626 static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
628 size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
629 if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
630 Tokens[0].getKind() == AsmToken::Minus &&
631 Tokens[1].getKind() == AsmToken::Identifier) {
632 MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
633 AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L,
634 AVRMCExpr::VK_AVR_None);
638 if (Parser.getTok().getKind() == AsmToken::Identifier &&
639 Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
640 StringRef ModifierName = Parser.getTok().getString();
641 AVRMCExpr::VariantKind ModifierKind =
642 AVRMCExpr::getKindByName(ModifierName.str().c_str());
643 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
645 Parser.Lex(); // Eat the modifier and parenthesis
647 return Error(Parser.getTok().getLoc(), "unknown modifier");
650 getContext().getOrCreateSymbol(Parser.getTok().getString());
651 AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
655 auto parseOne = [&]() -> bool {
657 if (Parser.parseExpression(Value))
659 Parser.getStreamer().EmitValue(Value, SizeInBytes, L);
662 return (parseMany(parseOne));
665 extern "C" void LLVMInitializeAVRAsmParser() {
666 RegisterMCAsmParser<AVRAsmParser> X(getTheAVRTarget());
669 #define GET_REGISTER_MATCHER
670 #define GET_MATCHER_IMPLEMENTATION
671 #include "AVRGenAsmMatcher.inc"
673 // Uses enums defined in AVRGenAsmMatcher.inc
674 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
675 unsigned ExpectedKind) {
676 AVROperand &Op = static_cast<AVROperand &>(AsmOp);
677 MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
679 // If need be, GCC converts bare numbers to register names
680 // It's ugly, but GCC supports it.
682 if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
683 int64_t RegNum = Const->getValue();
684 std::ostringstream RegName;
685 RegName << "r" << RegNum;
686 RegNum = MatchRegisterName(RegName.str().c_str());
687 if (RegNum != AVR::NoRegister) {
689 if (validateOperandClass(Op, Expected) == Match_Success) {
690 return Match_Success;
693 // Let the other quirks try their magic.
698 // If the instruction uses a register pair but we got a single, lower
699 // register we perform a "class cast".
700 if (isSubclass(Expected, MCK_DREGS)) {
701 unsigned correspondingDREG = toDREG(Op.getReg());
703 if (correspondingDREG != AVR::NoRegister) {
704 Op.makeReg(correspondingDREG);
705 return validateOperandClass(Op, Expected);
709 return Match_InvalidOperand;
712 } // end of namespace llvm