1 //===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AVRAsmBackend class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/AVRAsmBackend.h"
15 #include "MCTargetDesc/AVRFixupKinds.h"
16 #include "MCTargetDesc/AVRMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCValue.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/Support/raw_ostream.h"
31 // FIXME: we should be doing checks to make sure asm operands
32 // are not out of bounds.
38 void signed_width(unsigned Width, uint64_t Value, std::string Description,
39 const MCFixup &Fixup, MCContext *Ctx = nullptr) {
40 if (!isIntN(Width, Value)) {
41 std::string Diagnostic = "out of range " + Description;
43 int64_t Min = minIntN(Width);
44 int64_t Max = maxIntN(Width);
46 Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
47 " to " + std::to_string(Max) + ")";
50 Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
52 llvm_unreachable(Diagnostic.c_str());
57 void unsigned_width(unsigned Width, uint64_t Value, std::string Description,
58 const MCFixup &Fixup, MCContext *Ctx = nullptr) {
59 if (!isUIntN(Width, Value)) {
60 std::string Diagnostic = "out of range " + Description;
62 int64_t Max = maxUIntN(Width);
64 Diagnostic += " (expected an integer in the range 0 to " +
65 std::to_string(Max) + ")";
68 Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
70 llvm_unreachable(Diagnostic.c_str());
75 /// Adjusts the value of a branch target before fixup application.
76 void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
77 MCContext *Ctx = nullptr) {
78 // We have one extra bit of precision because the value is rightshifted by
80 unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
82 // Rightshifts the value by one.
83 AVR::fixups::adjustBranchTarget(Value);
86 /// Adjusts the value of a relative branch target before fixup application.
87 void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
88 MCContext *Ctx = nullptr) {
89 // We have one extra bit of precision because the value is rightshifted by
91 signed_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
95 // Rightshifts the value by one.
96 AVR::fixups::adjustBranchTarget(Value);
99 /// 22-bit absolute fixup.
102 /// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
104 /// Offset of 0 (so the result is left shifted by 3 bits before application).
105 void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
106 MCContext *Ctx = nullptr) {
107 adjustBranch(Size, Fixup, Value, Ctx);
109 auto top = Value & (0xf00000 << 6); // the top four bits
110 auto middle = Value & (0x1ffff << 5); // the middle 13 bits
111 auto bottom = Value & 0x1f; // end bottom 5 bits
113 Value = (top << 6) | (middle << 3) | (bottom << 0);
116 /// 7-bit PC-relative fixup.
119 /// 0000 00kk kkkk k000
120 /// Offset of 0 (so the result is left shifted by 3 bits before application).
121 void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
122 MCContext *Ctx = nullptr) {
123 adjustRelativeBranch(Size, Fixup, Value, Ctx);
125 // Because the value may be negative, we must mask out the sign bits
129 /// 12-bit PC-relative fixup.
130 /// Yes, the fixup is 12 bits even though the name says otherwise.
133 /// 0000 kkkk kkkk kkkk
134 /// Offset of 0 (so the result isn't left-shifted before application).
135 void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
136 MCContext *Ctx = nullptr) {
137 adjustRelativeBranch(Size, Fixup, Value, Ctx);
139 // Because the value may be negative, we must mask out the sign bits
143 /// 6-bit fixup for the immediate operand of the ADIW family of
147 /// 0000 0000 kk00 kkkk
148 void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
149 MCContext *Ctx = nullptr) {
150 unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
152 Value = ((Value & 0x30) << 2) | (Value & 0x0f);
155 /// 5-bit port number fixup on the SBIC family of instructions.
158 /// 0000 0000 AAAA A000
159 void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
160 MCContext *Ctx = nullptr) {
161 unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
168 /// 6-bit port number fixup on the `IN` family of instructions.
171 /// 1011 0AAd dddd AAAA
172 void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
173 MCContext *Ctx = nullptr) {
174 unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
176 Value = ((Value & 0x30) << 5) | (Value & 0x0f);
179 /// Adjusts a program memory address.
180 /// This is a simple right-shift.
181 void pm(uint64_t &Value) {
185 /// Fixups relating to the LDI instruction.
188 /// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
191 /// 0000 KKKK 0000 KKKK
192 /// Offset of 0 (so the result isn't left-shifted before application).
193 void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
194 MCContext *Ctx = nullptr) {
195 uint64_t upper = Value & 0xf0;
196 uint64_t lower = Value & 0x0f;
198 Value = (upper << 4) | lower;
201 void neg(uint64_t &Value) { Value *= -1; }
203 void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
204 MCContext *Ctx = nullptr) {
206 ldi::fixup(Size, Fixup, Value, Ctx);
209 void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
210 MCContext *Ctx = nullptr) {
211 Value = (Value & 0xff00) >> 8;
212 ldi::fixup(Size, Fixup, Value, Ctx);
215 void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
216 MCContext *Ctx = nullptr) {
217 Value = (Value & 0xff0000) >> 16;
218 ldi::fixup(Size, Fixup, Value, Ctx);
221 void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
222 MCContext *Ctx = nullptr) {
223 Value = (Value & 0xff000000) >> 24;
224 ldi::fixup(Size, Fixup, Value, Ctx);
227 } // end of ldi namespace
228 } // end of adjust namespace
232 // Prepare value for the target space for it
233 void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
234 const MCValue &Target,
236 MCContext *Ctx) const {
237 // The size of the fixup in bits.
238 uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
240 unsigned Kind = Fixup.getKind();
242 // Parsed LLVM-generated temporary labels are already
243 // adjusted for instruction size, but normal labels aren't.
245 // To handle both cases, we simply un-adjust the temporary label
246 // case so it acts like all other labels.
247 if (const MCSymbolRefExpr *A = Target.getSymA()) {
248 if (A->getSymbol().isTemporary())
254 llvm_unreachable("unhandled fixup");
255 case AVR::fixup_7_pcrel:
256 adjust::fixup_7_pcrel(Size, Fixup, Value, Ctx);
258 case AVR::fixup_13_pcrel:
259 adjust::fixup_13_pcrel(Size, Fixup, Value, Ctx);
261 case AVR::fixup_call:
262 adjust::fixup_call(Size, Fixup, Value, Ctx);
265 adjust::ldi::fixup(Size, Fixup, Value, Ctx);
267 case AVR::fixup_lo8_ldi:
268 case AVR::fixup_lo8_ldi_pm:
269 if (Kind == AVR::fixup_lo8_ldi_pm) adjust::pm(Value);
271 adjust::ldi::lo8(Size, Fixup, Value, Ctx);
273 case AVR::fixup_hi8_ldi:
274 case AVR::fixup_hi8_ldi_pm:
275 if (Kind == AVR::fixup_hi8_ldi_pm) adjust::pm(Value);
277 adjust::ldi::hi8(Size, Fixup, Value, Ctx);
279 case AVR::fixup_hh8_ldi:
280 case AVR::fixup_hh8_ldi_pm:
281 if (Kind == AVR::fixup_hh8_ldi_pm) adjust::pm(Value);
283 adjust::ldi::hh8(Size, Fixup, Value, Ctx);
285 case AVR::fixup_ms8_ldi:
286 adjust::ldi::ms8(Size, Fixup, Value, Ctx);
289 case AVR::fixup_lo8_ldi_neg:
290 case AVR::fixup_lo8_ldi_pm_neg:
291 if (Kind == AVR::fixup_lo8_ldi_pm_neg) adjust::pm(Value);
293 adjust::ldi::neg(Value);
294 adjust::ldi::lo8(Size, Fixup, Value, Ctx);
296 case AVR::fixup_hi8_ldi_neg:
297 case AVR::fixup_hi8_ldi_pm_neg:
298 if (Kind == AVR::fixup_hi8_ldi_pm_neg) adjust::pm(Value);
300 adjust::ldi::neg(Value);
301 adjust::ldi::hi8(Size, Fixup, Value, Ctx);
303 case AVR::fixup_hh8_ldi_neg:
304 case AVR::fixup_hh8_ldi_pm_neg:
305 if (Kind == AVR::fixup_hh8_ldi_pm_neg) adjust::pm(Value);
307 adjust::ldi::neg(Value);
308 adjust::ldi::hh8(Size, Fixup, Value, Ctx);
310 case AVR::fixup_ms8_ldi_neg:
311 adjust::ldi::neg(Value);
312 adjust::ldi::ms8(Size, Fixup, Value, Ctx);
315 adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
319 case AVR::fixup_6_adiw:
320 adjust::fixup_6_adiw(Fixup, Value, Ctx);
323 case AVR::fixup_port5:
324 adjust::fixup_port5(Fixup, Value, Ctx);
327 case AVR::fixup_port6:
328 adjust::fixup_port6(Fixup, Value, Ctx);
331 // Fixups which do not require adjustments.
338 llvm_unreachable("don't know how to adjust this fixup");
343 MCObjectWriter *AVRAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
344 return createAVRELFObjectWriter(OS,
345 MCELFObjectTargetWriter::getOSABI(OSType));
348 void AVRAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
349 const MCValue &Target, MutableArrayRef<char> Data,
350 uint64_t Value, bool IsPCRel) const {
351 adjustFixupValue(Fixup, Target, Value, &Asm.getContext());
353 return; // Doesn't change encoding.
355 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
357 // The number of bits in the fixup mask
358 auto NumBits = Info.TargetSize + Info.TargetOffset;
359 auto NumBytes = (NumBits / 8) + ((NumBits % 8) == 0 ? 0 : 1);
361 // Shift the value into position.
362 Value <<= Info.TargetOffset;
364 unsigned Offset = Fixup.getOffset();
365 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
367 // For each byte of the fragment that the fixup touches, mask in the
368 // bits from the fixup value.
369 for (unsigned i = 0; i < NumBytes; ++i) {
370 uint8_t mask = (((Value >> (i * 8)) & 0xff));
371 Data[Offset + i] |= mask;
375 MCFixupKindInfo const &AVRAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
376 // NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
377 // this by saying that the fixup is the size of the entire instruction.
378 const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
379 // This table *must* be in same the order of fixup_* kinds in
382 // name offset bits flags
383 {"fixup_32", 0, 32, 0},
385 {"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
386 {"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
388 {"fixup_16", 0, 16, 0},
389 {"fixup_16_pm", 0, 16, 0},
391 {"fixup_ldi", 0, 8, 0},
393 {"fixup_lo8_ldi", 0, 8, 0},
394 {"fixup_hi8_ldi", 0, 8, 0},
395 {"fixup_hh8_ldi", 0, 8, 0},
396 {"fixup_ms8_ldi", 0, 8, 0},
398 {"fixup_lo8_ldi_neg", 0, 8, 0},
399 {"fixup_hi8_ldi_neg", 0, 8, 0},
400 {"fixup_hh8_ldi_neg", 0, 8, 0},
401 {"fixup_ms8_ldi_neg", 0, 8, 0},
403 {"fixup_lo8_ldi_pm", 0, 8, 0},
404 {"fixup_hi8_ldi_pm", 0, 8, 0},
405 {"fixup_hh8_ldi_pm", 0, 8, 0},
407 {"fixup_lo8_ldi_pm_neg", 0, 8, 0},
408 {"fixup_hi8_ldi_pm_neg", 0, 8, 0},
409 {"fixup_hh8_ldi_pm_neg", 0, 8, 0},
411 {"fixup_call", 0, 22, 0},
413 {"fixup_6", 0, 16, 0}, // non-contiguous
414 {"fixup_6_adiw", 0, 6, 0},
416 {"fixup_lo8_ldi_gs", 0, 8, 0},
417 {"fixup_hi8_ldi_gs", 0, 8, 0},
419 {"fixup_8", 0, 8, 0},
420 {"fixup_8_lo8", 0, 8, 0},
421 {"fixup_8_hi8", 0, 8, 0},
422 {"fixup_8_hlo8", 0, 8, 0},
424 {"fixup_sym_diff", 0, 32, 0},
425 {"fixup_16_ldst", 0, 16, 0},
427 {"fixup_lds_sts_16", 0, 16, 0},
429 {"fixup_port6", 0, 16, 0}, // non-contiguous
430 {"fixup_port5", 3, 5, 0},
433 if (Kind < FirstTargetFixupKind)
434 return MCAsmBackend::getFixupKindInfo(Kind);
436 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
439 return Infos[Kind - FirstTargetFixupKind];
442 bool AVRAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
443 // If the count is not 2-byte aligned, we must be writing data into the text
444 // section (otherwise we have unaligned instructions, and thus have far
445 // bigger problems), so just write zeros instead.
446 assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
448 OW->WriteZeros(Count);
452 bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
453 const MCFixup &Fixup,
454 const MCValue &Target) {
455 switch ((unsigned) Fixup.getKind()) {
456 default: return false;
457 // Fixups which should always be recorded as relocations.
458 case AVR::fixup_7_pcrel:
459 case AVR::fixup_13_pcrel:
460 case AVR::fixup_call:
465 MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI,
466 const Triple &TT, StringRef CPU,
467 const llvm::MCTargetOptions &TO) {
468 return new AVRAsmBackend(TT.getOS());
471 } // end of namespace llvm