1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_AVR_FIXUP_KINDS_H
11 #define LLVM_AVR_FIXUP_KINDS_H
13 #include "llvm/MC/MCFixup.h"
18 /// The set of supported fixups.
20 /// Although most of the current fixup types reflect a unique relocation
21 /// one can have multiple fixup types for a given relocation and thus need
22 /// to be uniquely named.
24 /// \note This table *must* be in the same order of
25 /// MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]
26 /// in `AVRAsmBackend.cpp`.
28 /// A 32-bit AVR fixup.
29 fixup_32 = FirstTargetFixupKind,
31 /// A 7-bit PC-relative fixup for the family of conditional
32 /// branches which take 7-bit targets (BRNE,BRGT,etc).
34 /// A 12-bit PC-relative fixup for the family of branches
35 /// which take 12-bit targets (RJMP,RCALL,etc).
36 /// \note Although the fixup is labelled as 13 bits, it
37 /// is actually only encoded in 12. The reason for
38 /// The nonmenclature is that AVR branch targets are
39 /// rightshifted by 1, because instructions are always
40 /// aligned to 2 bytes, so the 0'th bit is always 0.
41 /// This way there is 13-bits of precision.
46 /// A 16-bit program memory address.
49 /// Replaces the 8-bit immediate with another value.
52 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
53 /// with the lower 8 bits of a 16-bit value (bits 0-7).
55 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
56 /// with the upper 8 bits of a 16-bit value (bits 8-15).
58 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
59 /// with the upper 8 bits of a 24-bit value (bits 16-23).
61 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
62 /// with the upper 8 bits of a 32-bit value (bits 24-31).
65 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
66 /// with the lower 8 bits of a negated 16-bit value (bits 0-7).
68 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
69 /// with the upper 8 bits of a negated 16-bit value (bits 8-15).
71 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
72 /// with the upper 8 bits of a negated negated 24-bit value (bits 16-23).
74 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
75 /// with the upper 8 bits of a negated negated 32-bit value (bits 24-31).
78 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
79 /// with the lower 8 bits of a 16-bit program memory address value (bits 0-7).
81 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
82 /// with the upper 8 bits of a 16-bit program memory address value (bits
85 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
86 /// with the upper 8 bits of a 24-bit program memory address value (bits
90 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
91 /// with the lower 8 bits of a negated 16-bit program memory address value
94 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
95 /// with the upper 8 bits of a negated 16-bit program memory address value
98 /// Replaces the immediate operand of a 16-bit `Rd, K` instruction
99 /// with the upper 8 bits of a negated 24-bit program memory address value
101 fixup_hh8_ldi_pm_neg,
103 /// A 22-bit fixup for the target of a `CALL k` or `JMP k` instruction.
107 /// A symbol+addr fixup for the `LDD <x>+<n>, <r>" family of instructions.
118 /// Fixup to calculate the difference between two symbols.
119 /// Is the only stateful fixup. We do not support it yet.
125 /// A 6-bit port address.
127 /// A 5-bit port address.
132 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
137 /// Adjusts the value of a branch target.
138 /// All branch targets in AVR are rightshifted by 1 to take advantage
139 /// of the fact that all instructions are aligned to addresses of size
140 /// 2, so bit 0 of an address is always 0. This gives us another bit
142 /// \param[in,out] The target to adjust.
143 template <typename T> inline void adjustBranchTarget(T &val) { val >>= 1; }
145 } // end of namespace fixups
147 } // end of namespace llvm::AVR
149 #endif // LLVM_AVR_FIXUP_KINDS_H