1 //===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AVRMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_AVR_CODE_EMITTER_H
16 #define LLVM_AVR_CODE_EMITTER_H
18 #include "AVRFixupKinds.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/Support/DataTypes.h"
23 #define GET_INSTRINFO_OPERAND_TYPES_ENUM
24 #include "AVRGenInstrInfo.inc"
34 class MCSubtargetInfo;
37 /// Writes AVR machine code to a stream.
38 class AVRMCCodeEmitter : public MCCodeEmitter {
40 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
41 : MCII(MCII), Ctx(Ctx) {}
44 /// Finishes up encoding an LD/ST instruction.
45 /// The purpose of this function is to set an bit in the instruction
46 /// which follows no logical pattern. See the implementation for details.
47 unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
48 const MCSubtargetInfo &STI) const;
50 /// Gets the encoding for a conditional branch target.
51 template <AVR::Fixups Fixup>
52 unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &STI) const;
56 /// Encodes the `PTRREGS` operand to a load or store instruction.
57 unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const;
61 /// Encodes a `register+immediate` operand for `LDD`/`STD`.
62 unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
66 /// Takes the complement of a number (~0 - val).
67 unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
71 /// Encodes an immediate value with a given fixup.
72 /// \tparam Offset The offset into the instruction for the fixup.
73 template <AVR::Fixups Fixup, unsigned Offset>
74 unsigned encodeImm(const MCInst &MI, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
78 /// Gets the encoding of the target for the `CALL k` instruction.
79 unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
83 /// TableGen'ed function to get the binary encoding for an instruction.
84 uint64_t getBinaryCodeForInstr(const MCInst &MI,
85 SmallVectorImpl<MCFixup> &Fixups,
86 const MCSubtargetInfo &STI) const;
88 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
91 /// Returns the binary encoding of operand.
93 /// If the machine operand requires relocation, the relocation is recorded
94 /// and zero is returned.
95 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
96 SmallVectorImpl<MCFixup> &Fixups,
97 const MCSubtargetInfo &STI) const;
99 void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
100 raw_ostream &OS) const;
102 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
103 SmallVectorImpl<MCFixup> &Fixups,
104 const MCSubtargetInfo &STI) const override;
106 AVRMCCodeEmitter(const AVRMCCodeEmitter &) = delete;
107 void operator=(const AVRMCCodeEmitter &) = delete;
109 const MCInstrInfo &MCII;
113 } // end namespace of llvm.
115 #endif // LLVM_AVR_CODE_EMITTER_H