1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the BPF instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "BPFInstrFormats.td"
16 // Instruction Operands and Patterns
18 // These are target-independent nodes, but have target-specific formats.
19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
21 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
22 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
23 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
24 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
27 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
28 SDTCisVT<3, OtherVT>]>;
29 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
31 def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>,
36 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
37 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
39 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
40 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
41 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
42 [SDNPHasChain, SDNPOutGlue]>;
43 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
44 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
45 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
46 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
48 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
49 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
50 def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY,
51 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
52 SDNPMayStore, SDNPMayLoad]>;
53 def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">;
54 def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
55 def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
56 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
58 def brtarget : Operand<OtherVT> {
59 let PrintMethod = "printBrTargetOperand";
61 def calltarget : Operand<i64>;
63 def u64imm : Operand<i64> {
64 let PrintMethod = "printImm64Operand";
67 def i64immSExt32 : PatLeaf<(i64 imm),
68 [{return isInt<32>(N->getSExtValue()); }]>;
69 def i32immSExt32 : PatLeaf<(i32 imm),
70 [{return isInt<32>(N->getSExtValue()); }]>;
73 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
74 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
77 def MEMri : Operand<i64> {
78 let PrintMethod = "printMemOperand";
79 let EncoderMethod = "getMemoryOpValue";
80 let DecoderMethod = "decodeMemoryOpValue";
81 let MIOperandInfo = (ops GPR, i16imm);
84 // Conditional code predicates - used for pattern matching for jump instructions
85 def BPF_CC_EQ : PatLeaf<(i64 imm),
86 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
87 def BPF_CC_NE : PatLeaf<(i64 imm),
88 [{return (N->getZExtValue() == ISD::SETNE);}]>;
89 def BPF_CC_GE : PatLeaf<(i64 imm),
90 [{return (N->getZExtValue() == ISD::SETGE);}]>;
91 def BPF_CC_GT : PatLeaf<(i64 imm),
92 [{return (N->getZExtValue() == ISD::SETGT);}]>;
93 def BPF_CC_GTU : PatLeaf<(i64 imm),
94 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
95 def BPF_CC_GEU : PatLeaf<(i64 imm),
96 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
97 def BPF_CC_LE : PatLeaf<(i64 imm),
98 [{return (N->getZExtValue() == ISD::SETLE);}]>;
99 def BPF_CC_LT : PatLeaf<(i64 imm),
100 [{return (N->getZExtValue() == ISD::SETLT);}]>;
101 def BPF_CC_LTU : PatLeaf<(i64 imm),
102 [{return (N->getZExtValue() == ISD::SETULT);}]>;
103 def BPF_CC_LEU : PatLeaf<(i64 imm),
104 [{return (N->getZExtValue() == ISD::SETULE);}]>;
106 // For arithmetic and jump instructions the 8-bit 'code'
107 // field is divided into three parts:
109 // +----------------+--------+--------------------+
110 // | 4 bits | 1 bit | 3 bits |
111 // | operation code | source | instruction class |
112 // +----------------+--------+--------------------+
114 class TYPE_ALU_JMP<bits<4> op, bits<1> srctype,
115 dag outs, dag ins, string asmstr, list<dag> pattern>
116 : InstBPF<outs, ins, asmstr, pattern> {
118 let Inst{63-60} = op;
119 let Inst{59} = srctype;
122 //For load and store instructions the 8-bit 'code' field is divided as:
124 // +--------+--------+-------------------+
125 // | 3 bits | 2 bits | 3 bits |
126 // | mode | size | instruction class |
127 // +--------+--------+-------------------+
129 class TYPE_LD_ST<bits<3> mode, bits<2> size,
130 dag outs, dag ins, string asmstr, list<dag> pattern>
131 : InstBPF<outs, ins, asmstr, pattern> {
133 let Inst{63-61} = mode;
134 let Inst{60-59} = size;
138 class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
139 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value,
141 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
142 "if $dst "#OpcodeStr#" $src goto $BrDst",
143 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
148 let Inst{55-52} = src;
149 let Inst{51-48} = dst;
150 let Inst{47-32} = BrDst;
151 let BPFClass = BPF_JMP;
154 class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
155 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
157 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
158 "if $dst "#OpcodeStr#" $imm goto $BrDst",
159 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
164 let Inst{51-48} = dst;
165 let Inst{47-32} = BrDst;
166 let Inst{31-0} = imm;
167 let BPFClass = BPF_JMP;
170 multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> {
171 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
172 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
175 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
176 // cmp+goto instructions
177 defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ>;
178 defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU>;
179 defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU>;
180 defm JNE : J<BPF_JNE, "!=", BPF_CC_NE>;
181 defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT>;
182 defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE>;
183 defm JULT : J<BPF_JLT, "<", BPF_CC_LTU>;
184 defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU>;
185 defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT>;
186 defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE>;
190 class ALU_RI<BPFOpClass Class, BPFArithOp Opc,
191 dag outs, dag ins, string asmstr, list<dag> pattern>
192 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> {
196 let Inst{51-48} = dst;
197 let Inst{31-0} = imm;
198 let BPFClass = Class;
201 class ALU_RR<BPFOpClass Class, BPFArithOp Opc,
202 dag outs, dag ins, string asmstr, list<dag> pattern>
203 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> {
207 let Inst{55-52} = src;
208 let Inst{51-48} = dst;
209 let BPFClass = Class;
212 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
213 def _rr : ALU_RR<BPF_ALU64, Opc,
215 (ins GPR:$src2, GPR:$src),
216 "$dst "#OpcodeStr#" $src",
217 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
218 def _ri : ALU_RI<BPF_ALU64, Opc,
220 (ins GPR:$src2, i64imm:$imm),
221 "$dst "#OpcodeStr#" $imm",
222 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
223 def _rr_32 : ALU_RR<BPF_ALU, Opc,
225 (ins GPR32:$src2, GPR32:$src),
226 "$dst "#OpcodeStr#" $src",
227 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
228 def _ri_32 : ALU_RI<BPF_ALU, Opc,
230 (ins GPR32:$src2, i32imm:$imm),
231 "$dst "#OpcodeStr#" $imm",
232 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
235 let Constraints = "$dst = $src2" in {
236 let isAsCheapAsAMove = 1 in {
237 defm ADD : ALU<BPF_ADD, "+=", add>;
238 defm SUB : ALU<BPF_SUB, "-=", sub>;
239 defm OR : ALU<BPF_OR, "|=", or>;
240 defm AND : ALU<BPF_AND, "&=", and>;
241 defm SLL : ALU<BPF_LSH, "<<=", shl>;
242 defm SRL : ALU<BPF_RSH, ">>=", srl>;
243 defm XOR : ALU<BPF_XOR, "^=", xor>;
244 defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
246 defm MUL : ALU<BPF_MUL, "*=", mul>;
247 defm DIV : ALU<BPF_DIV, "/=", udiv>;
250 class NEG_RR<BPFOpClass Class, BPFArithOp Opc,
251 dag outs, dag ins, string asmstr, list<dag> pattern>
252 : TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> {
255 let Inst{51-48} = dst;
256 let BPFClass = Class;
259 let Constraints = "$dst = $src", isAsCheapAsAMove = 1 in {
260 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
262 [(set GPR:$dst, (ineg i64:$src))]>;
263 def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src),
265 [(set GPR32:$dst, (ineg i32:$src))]>;
268 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
269 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
272 "$dst "#OpcodeStr#" ${imm} ll",
273 [(set GPR:$dst, (i64 imm:$imm))]> {
278 let Inst{51-48} = dst;
279 let Inst{55-52} = Pseudo;
281 let Inst{31-0} = imm{31-0};
282 let BPFClass = BPF_LD;
285 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
286 def LD_imm64 : LD_IMM64<0, "=">;
287 def MOV_rr : ALU_RR<BPF_ALU64, BPF_MOV,
292 def MOV_ri : ALU_RI<BPF_ALU64, BPF_MOV,
296 [(set GPR:$dst, (i64 i64immSExt32:$imm))]>;
297 def MOV_rr_32 : ALU_RR<BPF_ALU, BPF_MOV,
302 def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV,
306 [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>;
310 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
314 [(set i64:$dst, FIri:$addr)]> {
315 // This is a tentative instruction, and will be replaced
316 // with MOV_rr and ADD_ri in PEI phase
321 let BPFClass = BPF_LD;
325 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
327 (ins i64imm:$pseudo, u64imm:$imm),
328 "ld_pseudo\t$dst, $pseudo, $imm",
329 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
335 let Inst{51-48} = dst;
336 let Inst{55-52} = pseudo;
338 let Inst{31-0} = imm{31-0};
339 let BPFClass = BPF_LD;
342 // STORE instructions
343 class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
344 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
346 (ins GPR:$src, MEMri:$addr),
347 "*("#OpcodeStr#" *)($addr) = $src",
352 let Inst{51-48} = addr{19-16}; // base reg
353 let Inst{55-52} = src;
354 let Inst{47-32} = addr{15-0}; // offset
355 let BPFClass = BPF_STX;
358 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
359 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
361 let Predicates = [BPFNoALU32] in {
362 def STW : STOREi64<BPF_W, "u32", truncstorei32>;
363 def STH : STOREi64<BPF_H, "u16", truncstorei16>;
364 def STB : STOREi64<BPF_B, "u8", truncstorei8>;
366 def STD : STOREi64<BPF_DW, "u64", store>;
369 class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
370 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
373 "$dst = *("#OpcodeStr#" *)($addr)",
378 let Inst{51-48} = dst;
379 let Inst{55-52} = addr{19-16};
380 let Inst{47-32} = addr{15-0};
381 let BPFClass = BPF_LDX;
384 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
385 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
388 let Predicates = [BPFNoALU32] in {
389 def LDW : LOADi64<BPF_W, "u32", zextloadi32>;
390 def LDH : LOADi64<BPF_H, "u16", zextloadi16>;
391 def LDB : LOADi64<BPF_B, "u8", zextloadi8>;
394 def LDD : LOADi64<BPF_DW, "u64", load>;
396 class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern>
397 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
399 (ins brtarget:$BrDst),
400 !strconcat(OpcodeStr, " $BrDst"),
404 let Inst{47-32} = BrDst;
405 let BPFClass = BPF_JMP;
408 class CALL<string OpcodeStr>
409 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_K.Value,
411 (ins calltarget:$BrDst),
412 !strconcat(OpcodeStr, " $BrDst"),
416 let Inst{31-0} = BrDst;
417 let BPFClass = BPF_JMP;
420 class CALLX<string OpcodeStr>
421 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_X.Value,
423 (ins calltarget:$BrDst),
424 !strconcat(OpcodeStr, " $BrDst"),
428 let Inst{31-0} = BrDst;
429 let BPFClass = BPF_JMP;
433 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
434 def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>;
438 let isCall=1, hasDelaySlot=0, Uses = [R11],
439 // Potentially clobbered registers
440 Defs = [R0, R1, R2, R3, R4, R5] in {
441 def JAL : CALL<"call">;
442 def JALX : CALLX<"callx">;
445 class NOP_I<string OpcodeStr>
446 : TYPE_ALU_JMP<BPF_MOV.Value, BPF_X.Value,
449 !strconcat(OpcodeStr, "\t$imm"),
454 let BPFClass = BPF_ALU64;
457 let hasSideEffects = 0 in
458 def NOP : NOP_I<"nop">;
460 class RET<string OpcodeStr>
461 : TYPE_ALU_JMP<BPF_EXIT.Value, BPF_K.Value,
464 !strconcat(OpcodeStr, ""),
467 let BPFClass = BPF_JMP;
470 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
471 isNotDuplicable = 1 in {
472 def RET : RET<"exit">;
475 // ADJCALLSTACKDOWN/UP pseudo insns
476 let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in {
477 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
478 "#ADJCALLSTACKDOWN $amt1 $amt2",
479 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
480 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
481 "#ADJCALLSTACKUP $amt1 $amt2",
482 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
485 let usesCustomInserter = 1, isCodeGenOnly = 1 in {
486 def Select : Pseudo<(outs GPR:$dst),
487 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
488 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
490 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
491 def Select_Ri : Pseudo<(outs GPR:$dst),
492 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
493 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
495 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>;
496 def Select_64_32 : Pseudo<(outs GPR32:$dst),
497 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2),
498 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
500 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i32:$src, i32:$src2))]>;
501 def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst),
502 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2),
503 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
505 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i32:$src, i32:$src2))]>;
506 def Select_32 : Pseudo<(outs GPR32:$dst),
507 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
508 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
510 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i32:$src, i32:$src2))]>;
511 def Select_Ri_32 : Pseudo<(outs GPR32:$dst),
512 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
513 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
515 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i32:$src, i32:$src2))]>;
516 def Select_32_64 : Pseudo<(outs GPR:$dst),
517 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2),
518 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
520 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i64:$src, i64:$src2))]>;
521 def Select_Ri_32_64 : Pseudo<(outs GPR:$dst),
522 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR:$src, GPR:$src2),
523 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
525 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>;
528 // load 64-bit global addr into register
529 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
531 // 0xffffFFFF doesn't fit into simm32, optimize common case
532 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
533 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
536 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
537 def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>;
538 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
539 def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>;
542 let Predicates = [BPFNoALU32] in {
543 def : Pat<(i64 (extloadi8 ADDRri:$src)), (i64 (LDB ADDRri:$src))>;
544 def : Pat<(i64 (extloadi16 ADDRri:$src)), (i64 (LDH ADDRri:$src))>;
545 def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>;
549 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
550 : TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
552 (ins MEMri:$addr, GPR:$val),
553 "lock *("#OpcodeStr#" *)($addr) += $val",
554 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
558 let Inst{51-48} = addr{19-16}; // base reg
559 let Inst{55-52} = dst;
560 let Inst{47-32} = addr{15-0}; // offset
561 let BPFClass = BPF_STX;
564 let Constraints = "$dst = $val" in {
565 def XADD32 : XADD<BPF_W, "u32", atomic_load_add_32>;
566 def XADD64 : XADD<BPF_DW, "u64", atomic_load_add_64>;
567 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
568 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
571 // bswap16, bswap32, bswap64
572 class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern>
573 : TYPE_ALU_JMP<BPF_END.Value, SrcType.Value,
576 "$dst = "#OpcodeStr#" $src",
580 let Inst{51-48} = dst;
581 let Inst{31-0} = SizeOp;
582 let BPFClass = BPF_ALU;
586 let Constraints = "$dst = $src" in {
587 let Predicates = [BPFIsLittleEndian] in {
588 def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
589 def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
590 def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>;
592 let Predicates = [BPFIsBigEndian] in {
593 def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
594 def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
595 def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>;
599 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
600 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
601 class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
602 : TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value,
604 (ins GPR:$skb, i64imm:$imm),
605 "r0 = *("#OpcodeStr#" *)skb[$imm]",
606 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
609 let Inst{31-0} = imm;
610 let BPFClass = BPF_LD;
613 class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
614 : TYPE_LD_ST<BPF_IND.Value, SizeOp.Value,
616 (ins GPR:$skb, GPR:$val),
617 "r0 = *("#OpcodeStr#" *)skb[$val]",
618 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
621 let Inst{55-52} = val;
622 let BPFClass = BPF_LD;
626 def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>;
627 def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>;
628 def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>;
630 def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>;
631 def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>;
632 def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>;
634 let isCodeGenOnly = 1 in {
635 def MOV_32_64 : ALU_RR<BPF_ALU, BPF_MOV,
636 (outs GPR:$dst), (ins GPR32:$src),
640 def : Pat<(i64 (sext GPR32:$src)),
641 (SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
643 def : Pat<(i64 (zext GPR32:$src)),
644 (SRL_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
646 // For i64 -> i32 truncation, use the 32-bit subregister directly.
647 def : Pat<(i32 (trunc GPR:$src)),
648 (i32 (EXTRACT_SUBREG GPR:$src, sub_32))>;
650 // For i32 -> i64 anyext, we don't care about the high bits.
651 def : Pat<(i64 (anyext GPR32:$src)),
652 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
654 class STORE32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
655 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
657 (ins GPR32:$src, MEMri:$addr),
658 "*("#OpcodeStr#" *)($addr) = $src",
663 let Inst{51-48} = addr{19-16}; // base reg
664 let Inst{55-52} = src;
665 let Inst{47-32} = addr{15-0}; // offset
666 let BPFClass = BPF_STX;
669 class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
670 : STORE32<Opc, OpcodeStr, [(OpNode i32:$src, ADDRri:$addr)]>;
672 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
673 def STW32 : STOREi32<BPF_W, "u32", store>;
674 def STH32 : STOREi32<BPF_H, "u16", truncstorei16>;
675 def STB32 : STOREi32<BPF_B, "u8", truncstorei8>;
678 class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
679 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
682 "$dst = *("#OpcodeStr#" *)($addr)",
687 let Inst{51-48} = dst;
688 let Inst{55-52} = addr{19-16};
689 let Inst{47-32} = addr{15-0};
690 let BPFClass = BPF_LDX;
693 class LOADi32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
694 : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>;
696 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
697 def LDW32 : LOADi32<BPF_W, "u32", load>;
698 def LDH32 : LOADi32<BPF_H, "u16", zextloadi16>;
699 def LDB32 : LOADi32<BPF_B, "u8", zextloadi8>;
702 let Predicates = [BPFHasALU32] in {
703 def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst),
704 (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
705 def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst),
706 (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
707 def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst),
708 (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
709 def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>;
710 def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>;
711 def : Pat<(i64 (zextloadi8 ADDRri:$src)),
712 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
713 def : Pat<(i64 (zextloadi16 ADDRri:$src)),
714 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
715 def : Pat<(i64 (zextloadi32 ADDRri:$src)),
716 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
717 def : Pat<(i64 (extloadi8 ADDRri:$src)),
718 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
719 def : Pat<(i64 (extloadi16 ADDRri:$src)),
720 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
721 def : Pat<(i64 (extloadi32 ADDRri:$src)),
722 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
725 let usesCustomInserter = 1, isCodeGenOnly = 1 in {
728 (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops),
729 "#memcpy dst: $dst, src: $src, len: $len, align: $align",
730 [(BPFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>;