1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the BPF instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "BPFInstrFormats.td"
16 // Instruction Operands and Patterns
18 // These are target-independent nodes, but have target-specific formats.
19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
21 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
22 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
23 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
24 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
27 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
28 SDTCisVT<3, OtherVT>]>;
29 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
32 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
33 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
36 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
37 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
38 [SDNPHasChain, SDNPOutGlue]>;
39 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
40 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
41 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
42 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
44 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
45 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
47 def brtarget : Operand<OtherVT>;
48 def calltarget : Operand<i64>;
50 def u64imm : Operand<i64> {
51 let PrintMethod = "printImm64Operand";
54 def i64immSExt32 : PatLeaf<(i64 imm),
55 [{return isInt<32>(N->getSExtValue()); }]>;
58 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
59 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
62 def MEMri : Operand<i64> {
63 let PrintMethod = "printMemOperand";
64 let EncoderMethod = "getMemoryOpValue";
65 let DecoderMethod = "decodeMemoryOpValue";
66 let MIOperandInfo = (ops GPR, i16imm);
69 // Conditional code predicates - used for pattern matching for jump instructions
70 def BPF_CC_EQ : PatLeaf<(i64 imm),
71 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
72 def BPF_CC_NE : PatLeaf<(i64 imm),
73 [{return (N->getZExtValue() == ISD::SETNE);}]>;
74 def BPF_CC_GE : PatLeaf<(i64 imm),
75 [{return (N->getZExtValue() == ISD::SETGE);}]>;
76 def BPF_CC_GT : PatLeaf<(i64 imm),
77 [{return (N->getZExtValue() == ISD::SETGT);}]>;
78 def BPF_CC_GTU : PatLeaf<(i64 imm),
79 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
80 def BPF_CC_GEU : PatLeaf<(i64 imm),
81 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
84 class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
85 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
86 "if $dst "#OpcodeStr#" $src goto $BrDst",
87 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
95 let Inst{59} = BPFSrc;
96 let Inst{55-52} = src;
97 let Inst{51-48} = dst;
98 let Inst{47-32} = BrDst;
102 let BPFClass = 5; // BPF_JMP
105 class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
106 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
107 "if $dst "#OpcodeStr#" $imm goto $BrDst",
108 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
115 let Inst{63-60} = op;
116 let Inst{59} = BPFSrc;
117 let Inst{51-48} = dst;
118 let Inst{47-32} = BrDst;
119 let Inst{31-0} = imm;
123 let BPFClass = 5; // BPF_JMP
126 multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
127 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
128 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
131 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
132 // cmp+goto instructions
133 defm JEQ : J<0x1, "==", BPF_CC_EQ>;
134 defm JUGT : J<0x2, ">", BPF_CC_GTU>;
135 defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
136 defm JNE : J<0x5, "!=", BPF_CC_NE>;
137 defm JSGT : J<0x6, "s>", BPF_CC_GT>;
138 defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
142 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
143 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
144 "$dst "#OpcodeStr#" $imm",
145 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
151 let Inst{63-60} = op;
152 let Inst{59} = BPFSrc;
153 let Inst{51-48} = dst;
154 let Inst{31-0} = imm;
158 let BPFClass = 7; // BPF_ALU64
161 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
162 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
163 "$dst "#OpcodeStr#" $src",
164 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
170 let Inst{63-60} = op;
171 let Inst{59} = BPFSrc;
172 let Inst{55-52} = src;
173 let Inst{51-48} = dst;
177 let BPFClass = 7; // BPF_ALU64
180 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
181 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
182 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
185 let Constraints = "$dst = $src2" in {
186 let isAsCheapAsAMove = 1 in {
187 defm ADD : ALU<0x0, "+=", add>;
188 defm SUB : ALU<0x1, "-=", sub>;
189 defm OR : ALU<0x4, "|=", or>;
190 defm AND : ALU<0x5, "&=", and>;
191 defm SLL : ALU<0x6, "<<=", shl>;
192 defm SRL : ALU<0x7, ">>=", srl>;
193 defm XOR : ALU<0xa, "^=", xor>;
194 defm SRA : ALU<0xc, "s>>=", sra>;
196 defm MUL : ALU<0x2, "*=", mul>;
197 defm DIV : ALU<0x3, "/=", udiv>;
200 class MOV_RR<string OpcodeStr>
201 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
202 "$dst "#OpcodeStr#" $src",
209 let Inst{63-60} = op;
210 let Inst{59} = BPFSrc;
211 let Inst{55-52} = src;
212 let Inst{51-48} = dst;
214 let op = 0xb; // BPF_MOV
215 let BPFSrc = 1; // BPF_X
216 let BPFClass = 7; // BPF_ALU64
219 class MOV_RI<string OpcodeStr>
220 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
221 "$dst "#OpcodeStr#" $imm",
222 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
228 let Inst{63-60} = op;
229 let Inst{59} = BPFSrc;
230 let Inst{51-48} = dst;
231 let Inst{31-0} = imm;
233 let op = 0xb; // BPF_MOV
234 let BPFSrc = 0; // BPF_K
235 let BPFClass = 7; // BPF_ALU64
238 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
239 : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
240 "$dst "#OpcodeStr#" ${imm}ll",
241 [(set GPR:$dst, (i64 imm:$imm))]> {
248 let Inst{63-61} = mode;
249 let Inst{60-59} = size;
250 let Inst{51-48} = dst;
251 let Inst{55-52} = Pseudo;
253 let Inst{31-0} = imm{31-0};
255 let mode = 0; // BPF_IMM
256 let size = 3; // BPF_DW
257 let BPFClass = 0; // BPF_LD
260 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
261 def LD_imm64 : LD_IMM64<0, "=">;
262 def MOV_rr : MOV_RR<"=">;
263 def MOV_ri : MOV_RI<"=">;
267 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
269 [(set i64:$dst, FIri:$addr)]> {
270 // This is a tentative instruction, and will be replaced
271 // with MOV_rr and ADD_ri in PEI phase
283 : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
284 "ld_pseudo\t$dst, $pseudo, $imm",
285 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
293 let Inst{63-61} = mode;
294 let Inst{60-59} = size;
295 let Inst{51-48} = dst;
296 let Inst{55-52} = pseudo;
298 let Inst{31-0} = imm{31-0};
300 let mode = 0; // BPF_IMM
301 let size = 3; // BPF_DW
302 let BPFClass = 0; // BPF_LD
305 // STORE instructions
306 class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
307 : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
308 "*("#OpcodeStr#" *)($addr) = $src", Pattern> {
314 let Inst{63-61} = mode;
315 let Inst{60-59} = size;
316 let Inst{51-48} = addr{19-16}; // base reg
317 let Inst{55-52} = src;
318 let Inst{47-32} = addr{15-0}; // offset
320 let mode = 3; // BPF_MEM
322 let BPFClass = 3; // BPF_STX
325 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
326 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
328 def STW : STOREi64<0x0, "u32", truncstorei32>;
329 def STH : STOREi64<0x1, "u16", truncstorei16>;
330 def STB : STOREi64<0x2, "u8", truncstorei8>;
331 def STD : STOREi64<0x3, "u64", store>;
334 class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
335 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
336 "$dst = *("#OpcodeStr#" *)($addr)", Pattern> {
342 let Inst{63-61} = mode;
343 let Inst{60-59} = size;
344 let Inst{51-48} = dst;
345 let Inst{55-52} = addr{19-16};
346 let Inst{47-32} = addr{15-0};
348 let mode = 3; // BPF_MEM
350 let BPFClass = 1; // BPF_LDX
353 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
354 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
356 def LDW : LOADi64<0x0, "u32", zextloadi32>;
357 def LDH : LOADi64<0x1, "u16", zextloadi16>;
358 def LDB : LOADi64<0x2, "u8", zextloadi8>;
359 def LDD : LOADi64<0x3, "u64", load>;
361 class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
362 : InstBPF<(outs), (ins brtarget:$BrDst),
363 !strconcat(OpcodeStr, " $BrDst"), Pattern> {
368 let Inst{63-60} = op;
369 let Inst{59} = BPFSrc;
370 let Inst{47-32} = BrDst;
374 let BPFClass = 5; // BPF_JMP
377 class CALL<string OpcodeStr>
378 : InstBPF<(outs), (ins calltarget:$BrDst),
379 !strconcat(OpcodeStr, " $BrDst"), []> {
384 let Inst{63-60} = op;
385 let Inst{59} = BPFSrc;
386 let Inst{31-0} = BrDst;
388 let op = 8; // BPF_CALL
390 let BPFClass = 5; // BPF_JMP
394 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
395 def JMP : BRANCH<0x0, "goto", [(br bb:$BrDst)]>;
399 let isCall=1, hasDelaySlot=0, Uses = [R11],
400 // Potentially clobbered registers
401 Defs = [R0, R1, R2, R3, R4, R5] in {
402 def JAL : CALL<"call">;
405 class NOP_I<string OpcodeStr>
406 : InstBPF<(outs), (ins i32imm:$imm),
407 !strconcat(OpcodeStr, "\t$imm"), []> {
414 let Inst{63-60} = op;
415 let Inst{59} = BPFSrc;
416 let Inst{55-52} = src;
417 let Inst{51-48} = dst;
419 let op = 0xb; // BPF_MOV
420 let BPFSrc = 1; // BPF_X
421 let BPFClass = 7; // BPF_ALU64
426 let hasSideEffects = 0 in
427 def NOP : NOP_I<"nop">;
429 class RET<string OpcodeStr>
430 : InstBPF<(outs), (ins),
431 !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
434 let Inst{63-60} = op;
438 let op = 9; // BPF_EXIT
439 let BPFClass = 5; // BPF_JMP
442 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
443 isNotDuplicable = 1 in {
444 def RET : RET<"exit">;
447 // ADJCALLSTACKDOWN/UP pseudo insns
448 let Defs = [R11], Uses = [R11] in {
449 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
450 "#ADJCALLSTACKDOWN $amt1 $amt2",
451 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
452 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
453 "#ADJCALLSTACKUP $amt1 $amt2",
454 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
457 let usesCustomInserter = 1 in {
458 def Select : Pseudo<(outs GPR:$dst),
459 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
460 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
462 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
463 def Select_Ri : Pseudo<(outs GPR:$dst),
464 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
465 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
467 (BPFselectcc i64:$lhs, (i64 imm:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>;
470 // load 64-bit global addr into register
471 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
473 // 0xffffFFFF doesn't fit into simm32, optimize common case
474 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
475 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
478 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
479 def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>;
480 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
483 def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>;
484 def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
485 def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
488 class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
489 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
490 "lock *("#OpcodeStr#" *)($addr) += $val",
491 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
497 let Inst{63-61} = mode;
498 let Inst{60-59} = size;
499 let Inst{51-48} = addr{19-16}; // base reg
500 let Inst{55-52} = dst;
501 let Inst{47-32} = addr{15-0}; // offset
503 let mode = 6; // BPF_XADD
505 let BPFClass = 3; // BPF_STX
508 let Constraints = "$dst = $val" in {
509 def XADD32 : XADD<0, "u32", atomic_load_add_32>;
510 def XADD64 : XADD<3, "u64", atomic_load_add_64>;
511 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
512 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
515 // bswap16, bswap32, bswap64
516 class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
517 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
518 !strconcat(OpcodeStr, "\t$dst"),
525 let Inst{63-60} = op;
526 let Inst{59} = BPFSrc;
527 let Inst{51-48} = dst;
528 let Inst{31-0} = imm;
530 let op = 0xd; // BPF_END
531 let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
532 let BPFClass = 4; // BPF_ALU
536 let Constraints = "$dst = $src" in {
537 def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
538 def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
539 def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
542 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
543 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
544 class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
545 : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
546 "r0 = *("#OpcodeStr#" *)skb[$imm]",
547 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
552 let Inst{63-61} = mode;
553 let Inst{60-59} = size;
554 let Inst{31-0} = imm;
556 let mode = 1; // BPF_ABS
558 let BPFClass = 0; // BPF_LD
561 class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
562 : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
563 "r0 = *("#OpcodeStr#" *)skb[$val]",
564 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
569 let Inst{63-61} = mode;
570 let Inst{60-59} = size;
571 let Inst{55-52} = val;
573 let mode = 2; // BPF_IND
575 let BPFClass = 0; // BPF_LD
579 def LD_ABS_B : LOAD_ABS<2, "u8", int_bpf_load_byte>;
580 def LD_ABS_H : LOAD_ABS<1, "u16", int_bpf_load_half>;
581 def LD_ABS_W : LOAD_ABS<0, "u32", int_bpf_load_word>;
583 def LD_IND_B : LOAD_IND<2, "u8", int_bpf_load_byte>;
584 def LD_IND_H : LOAD_IND<1, "u16", int_bpf_load_half>;
585 def LD_IND_W : LOAD_IND<0, "u32", int_bpf_load_word>;