1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the BPF instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "BPFInstrFormats.td"
16 // Instruction Operands and Patterns
18 // These are target-independent nodes, but have target-specific formats.
19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
26 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27 SDTCisVT<3, OtherVT>]>;
28 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
31 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
34 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
37 [SDNPHasChain, SDNPOutGlue]>;
38 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
39 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
40 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
41 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
43 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
44 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
46 def brtarget : Operand<OtherVT>;
47 def calltarget : Operand<i64>;
49 def u64imm : Operand<i64> {
50 let PrintMethod = "printImm64Operand";
53 def i64immSExt32 : PatLeaf<(imm),
54 [{return isInt<32>(N->getSExtValue()); }]>;
57 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
58 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
61 def MEMri : Operand<i64> {
62 let PrintMethod = "printMemOperand";
63 let EncoderMethod = "getMemoryOpValue";
64 let DecoderMethod = "decodeMemoryOpValue";
65 let MIOperandInfo = (ops GPR, i16imm);
68 // Conditional code predicates - used for pattern matching for jump instructions
69 def BPF_CC_EQ : PatLeaf<(imm),
70 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
71 def BPF_CC_NE : PatLeaf<(imm),
72 [{return (N->getZExtValue() == ISD::SETNE);}]>;
73 def BPF_CC_GE : PatLeaf<(imm),
74 [{return (N->getZExtValue() == ISD::SETGE);}]>;
75 def BPF_CC_GT : PatLeaf<(imm),
76 [{return (N->getZExtValue() == ISD::SETGT);}]>;
77 def BPF_CC_GTU : PatLeaf<(imm),
78 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
79 def BPF_CC_GEU : PatLeaf<(imm),
80 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
83 class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
84 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
85 "if $dst "#OpcodeStr#" $src goto $BrDst",
86 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
94 let Inst{59} = BPFSrc;
95 let Inst{55-52} = src;
96 let Inst{51-48} = dst;
97 let Inst{47-32} = BrDst;
101 let BPFClass = 5; // BPF_JMP
104 class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
105 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
106 "if $dst "#OpcodeStr#" $imm goto $BrDst",
107 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
114 let Inst{63-60} = op;
115 let Inst{59} = BPFSrc;
116 let Inst{51-48} = dst;
117 let Inst{47-32} = BrDst;
118 let Inst{31-0} = imm;
122 let BPFClass = 5; // BPF_JMP
125 multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
126 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
127 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
130 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
131 // cmp+goto instructions
132 defm JEQ : J<0x1, "==", BPF_CC_EQ>;
133 defm JUGT : J<0x2, ">", BPF_CC_GTU>;
134 defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
135 defm JNE : J<0x5, "!=", BPF_CC_NE>;
136 defm JSGT : J<0x6, "s>", BPF_CC_GT>;
137 defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
141 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
142 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
143 "$dst "#OpcodeStr#" $imm",
144 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
150 let Inst{63-60} = op;
151 let Inst{59} = BPFSrc;
152 let Inst{51-48} = dst;
153 let Inst{31-0} = imm;
157 let BPFClass = 7; // BPF_ALU64
160 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
161 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
162 "$dst "#OpcodeStr#" $src",
163 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
169 let Inst{63-60} = op;
170 let Inst{59} = BPFSrc;
171 let Inst{55-52} = src;
172 let Inst{51-48} = dst;
176 let BPFClass = 7; // BPF_ALU64
179 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
180 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
181 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
184 let Constraints = "$dst = $src2" in {
185 let isAsCheapAsAMove = 1 in {
186 defm ADD : ALU<0x0, "+=", add>;
187 defm SUB : ALU<0x1, "-=", sub>;
188 defm OR : ALU<0x4, "|=", or>;
189 defm AND : ALU<0x5, "&=", and>;
190 defm SLL : ALU<0x6, "<<=", shl>;
191 defm SRL : ALU<0x7, ">>=", srl>;
192 defm XOR : ALU<0xa, "^=", xor>;
193 defm SRA : ALU<0xc, "s>>=", sra>;
195 defm MUL : ALU<0x2, "*=", mul>;
196 defm DIV : ALU<0x3, "/=", udiv>;
199 class MOV_RR<string OpcodeStr>
200 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
201 "$dst "#OpcodeStr#" $src",
208 let Inst{63-60} = op;
209 let Inst{59} = BPFSrc;
210 let Inst{55-52} = src;
211 let Inst{51-48} = dst;
213 let op = 0xb; // BPF_MOV
214 let BPFSrc = 1; // BPF_X
215 let BPFClass = 7; // BPF_ALU64
218 class MOV_RI<string OpcodeStr>
219 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
220 "$dst "#OpcodeStr#" $imm",
221 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
227 let Inst{63-60} = op;
228 let Inst{59} = BPFSrc;
229 let Inst{51-48} = dst;
230 let Inst{31-0} = imm;
232 let op = 0xb; // BPF_MOV
233 let BPFSrc = 0; // BPF_K
234 let BPFClass = 7; // BPF_ALU64
237 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
238 : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
239 "$dst "#OpcodeStr#" ${imm}ll",
240 [(set GPR:$dst, (i64 imm:$imm))]> {
247 let Inst{63-61} = mode;
248 let Inst{60-59} = size;
249 let Inst{51-48} = dst;
250 let Inst{55-52} = Pseudo;
252 let Inst{31-0} = imm{31-0};
254 let mode = 0; // BPF_IMM
255 let size = 3; // BPF_DW
256 let BPFClass = 0; // BPF_LD
259 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
260 def LD_imm64 : LD_IMM64<0, "=">;
261 def MOV_rr : MOV_RR<"=">;
262 def MOV_ri : MOV_RI<"=">;
266 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
268 [(set i64:$dst, FIri:$addr)]> {
269 // This is a tentative instruction, and will be replaced
270 // with MOV_rr and ADD_ri in PEI phase
282 : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
283 "ld_pseudo\t$dst, $pseudo, $imm",
284 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
292 let Inst{63-61} = mode;
293 let Inst{60-59} = size;
294 let Inst{51-48} = dst;
295 let Inst{55-52} = pseudo;
297 let Inst{31-0} = imm{31-0};
299 let mode = 0; // BPF_IMM
300 let size = 3; // BPF_DW
301 let BPFClass = 0; // BPF_LD
304 // STORE instructions
305 class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
306 : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
307 "*("#OpcodeStr#" *)($addr) = $src", Pattern> {
313 let Inst{63-61} = mode;
314 let Inst{60-59} = size;
315 let Inst{51-48} = addr{19-16}; // base reg
316 let Inst{55-52} = src;
317 let Inst{47-32} = addr{15-0}; // offset
319 let mode = 3; // BPF_MEM
321 let BPFClass = 3; // BPF_STX
324 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
325 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
327 def STW : STOREi64<0x0, "u32", truncstorei32>;
328 def STH : STOREi64<0x1, "u16", truncstorei16>;
329 def STB : STOREi64<0x2, "u8", truncstorei8>;
330 def STD : STOREi64<0x3, "u64", store>;
333 class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
334 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
335 "$dst = *("#OpcodeStr#" *)($addr)", Pattern> {
341 let Inst{63-61} = mode;
342 let Inst{60-59} = size;
343 let Inst{51-48} = dst;
344 let Inst{55-52} = addr{19-16};
345 let Inst{47-32} = addr{15-0};
347 let mode = 3; // BPF_MEM
349 let BPFClass = 1; // BPF_LDX
352 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
353 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
355 def LDW : LOADi64<0x0, "u32", zextloadi32>;
356 def LDH : LOADi64<0x1, "u16", zextloadi16>;
357 def LDB : LOADi64<0x2, "u8", zextloadi8>;
358 def LDD : LOADi64<0x3, "u64", load>;
360 class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
361 : InstBPF<(outs), (ins brtarget:$BrDst),
362 !strconcat(OpcodeStr, " $BrDst"), Pattern> {
367 let Inst{63-60} = op;
368 let Inst{59} = BPFSrc;
369 let Inst{47-32} = BrDst;
373 let BPFClass = 5; // BPF_JMP
376 class CALL<string OpcodeStr>
377 : InstBPF<(outs), (ins calltarget:$BrDst),
378 !strconcat(OpcodeStr, " $BrDst"), []> {
383 let Inst{63-60} = op;
384 let Inst{59} = BPFSrc;
385 let Inst{31-0} = BrDst;
387 let op = 8; // BPF_CALL
389 let BPFClass = 5; // BPF_JMP
393 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
394 def JMP : BRANCH<0x0, "goto", [(br bb:$BrDst)]>;
398 let isCall=1, hasDelaySlot=0, Uses = [R11],
399 // Potentially clobbered registers
400 Defs = [R0, R1, R2, R3, R4, R5] in {
401 def JAL : CALL<"call">;
404 class NOP_I<string OpcodeStr>
405 : InstBPF<(outs), (ins i32imm:$imm),
406 !strconcat(OpcodeStr, "\t$imm"), []> {
413 let Inst{63-60} = op;
414 let Inst{59} = BPFSrc;
415 let Inst{55-52} = src;
416 let Inst{51-48} = dst;
418 let op = 0xb; // BPF_MOV
419 let BPFSrc = 1; // BPF_X
420 let BPFClass = 7; // BPF_ALU64
425 let hasSideEffects = 0 in
426 def NOP : NOP_I<"nop">;
428 class RET<string OpcodeStr>
429 : InstBPF<(outs), (ins),
430 !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
433 let Inst{63-60} = op;
437 let op = 9; // BPF_EXIT
438 let BPFClass = 5; // BPF_JMP
441 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
442 isNotDuplicable = 1 in {
443 def RET : RET<"exit">;
446 // ADJCALLSTACKDOWN/UP pseudo insns
447 let Defs = [R11], Uses = [R11] in {
448 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
449 "#ADJCALLSTACKDOWN $amt",
450 [(BPFcallseq_start timm:$amt)]>;
451 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
452 "#ADJCALLSTACKUP $amt1 $amt2",
453 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
456 let usesCustomInserter = 1 in {
457 def Select : Pseudo<(outs GPR:$dst),
458 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
459 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
461 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
464 // load 64-bit global addr into register
465 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
467 // 0xffffFFFF doesn't fit into simm32, optimize common case
468 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
469 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
472 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
473 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
476 def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>;
477 def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
478 def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
481 class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
482 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
483 "lock *("#OpcodeStr#" *)($addr) += $val",
484 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
490 let Inst{63-61} = mode;
491 let Inst{60-59} = size;
492 let Inst{51-48} = addr{19-16}; // base reg
493 let Inst{55-52} = dst;
494 let Inst{47-32} = addr{15-0}; // offset
496 let mode = 6; // BPF_XADD
498 let BPFClass = 3; // BPF_STX
501 let Constraints = "$dst = $val" in {
502 def XADD32 : XADD<0, "u32", atomic_load_add_32>;
503 def XADD64 : XADD<3, "u64", atomic_load_add_64>;
504 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
505 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
508 // bswap16, bswap32, bswap64
509 class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
510 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
511 !strconcat(OpcodeStr, "\t$dst"),
518 let Inst{63-60} = op;
519 let Inst{59} = BPFSrc;
520 let Inst{51-48} = dst;
521 let Inst{31-0} = imm;
523 let op = 0xd; // BPF_END
524 let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
525 let BPFClass = 4; // BPF_ALU
529 let Constraints = "$dst = $src" in {
530 def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
531 def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
532 def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
535 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
536 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
537 class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
538 : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
539 "r0 = *("#OpcodeStr#" *)skb[$imm]",
540 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
545 let Inst{63-61} = mode;
546 let Inst{60-59} = size;
547 let Inst{31-0} = imm;
549 let mode = 1; // BPF_ABS
551 let BPFClass = 0; // BPF_LD
554 class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
555 : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
556 "r0 = *("#OpcodeStr#" *)skb[$val]",
557 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
562 let Inst{63-61} = mode;
563 let Inst{60-59} = size;
564 let Inst{55-52} = val;
566 let mode = 2; // BPF_IND
568 let BPFClass = 0; // BPF_LD
572 def LD_ABS_B : LOAD_ABS<2, "u8", int_bpf_load_byte>;
573 def LD_ABS_H : LOAD_ABS<1, "u16", int_bpf_load_half>;
574 def LD_ABS_W : LOAD_ABS<0, "u32", int_bpf_load_word>;
576 def LD_IND_B : LOAD_IND<2, "u8", int_bpf_load_byte>;
577 def LD_IND_H : LOAD_IND<1, "u16", int_bpf_load_half>;
578 def LD_IND_W : LOAD_IND<0, "u32", int_bpf_load_word>;