1 //===--- BitTracker.h -------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
13 #include "llvm/ADT/SetVector.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineOperand.h"
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
38 struct MachineEvaluator;
40 typedef SetVector<const MachineBasicBlock *> BranchTargetList;
42 typedef std::map<unsigned, RegisterCell> CellMapType;
44 BitTracker(const MachineEvaluator &E, MachineFunction &F);
48 void trace(bool On = false) { Trace = On; }
49 bool has(unsigned Reg) const;
50 const RegisterCell &lookup(unsigned Reg) const;
51 RegisterCell get(RegisterRef RR) const;
52 void put(RegisterRef RR, const RegisterCell &RC);
53 void subst(RegisterRef OldRR, RegisterRef NewRR);
54 bool reached(const MachineBasicBlock *B) const;
55 void visit(const MachineInstr &MI);
57 void print_cells(raw_ostream &OS) const;
60 void visitPHI(const MachineInstr &PI);
61 void visitNonBranch(const MachineInstr &MI);
62 void visitBranchesFrom(const MachineInstr &BI);
63 void visitUsesOf(unsigned Reg);
66 typedef std::pair<int,int> CFGEdge;
67 typedef std::set<CFGEdge> EdgeSetType;
68 typedef std::set<const MachineInstr *> InstrSetType;
69 typedef std::queue<CFGEdge> EdgeQueueType;
71 EdgeSetType EdgeExec; // Executable flow graph edges.
72 InstrSetType InstrExec; // Executable instructions.
73 EdgeQueueType FlowQ; // Work queue of CFG edges.
74 bool Trace; // Enable tracing for debugging.
76 const MachineEvaluator &ME;
78 MachineRegisterInfo &MRI;
82 // Abstraction of a reference to bit at position Pos from a register Reg.
83 struct BitTracker::BitRef {
84 BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
86 bool operator== (const BitRef &BR) const {
87 // If Reg is 0, disregard Pos.
88 return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
95 // Abstraction of a register reference in MachineOperand. It contains the
96 // register number and the subregister index.
97 struct BitTracker::RegisterRef {
98 RegisterRef(unsigned R = 0, unsigned S = 0)
100 RegisterRef(const MachineOperand &MO)
101 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
106 // Value that a single bit can take. This is outside of the context of
107 // any register, it is more of an abstraction of the two-element set of
108 // possible bit values. One extension here is the "Ref" type, which
109 // indicates that this bit takes the same value as the bit described by
111 struct BitTracker::BitValue {
113 Top, // Bit not yet defined.
116 Ref // Bit value same as the one described in RefI.
117 // Conceptually, there is no explicit "bottom" value: the lattice's
118 // bottom will be expressed as a "ref to itself", which, in the context
119 // of registers, could be read as "this value of this bit is defined by
123 // Self <= x, where "Self" is "ref to itself".
124 // This makes the value lattice different for each virtual register
125 // (even for each bit in the same virtual register), since the "bottom"
126 // for one register will be a simple "ref" for another register.
127 // Since we do not store the "Self" bit and register number, the meet
128 // operation will need to take it as a parameter.
130 // In practice there is a special case for values that are not associa-
131 // ted with any specific virtual register. An example would be a value
132 // corresponding to a bit of a physical register, or an intermediate
133 // value obtained in some computation (such as instruction evaluation).
134 // Such cases are identical to the usual Ref type, but the register
135 // number is 0. In such case the Pos field of the reference is ignored.
137 // What is worthy of notice is that in value V (that is a "ref"), as long
138 // as the RefI.Reg is not 0, it may actually be the same register as the
139 // one in which V will be contained. If the RefI.Pos refers to the posi-
140 // tion of V, then V is assumed to be "bottom" (as a "ref to itself"),
141 // otherwise V is taken to be identical to the referenced bit of the
143 // If RefI.Reg is 0, however, such a reference to the same register is
144 // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
145 // is treated as "bottom".
150 BitValue(ValueType T = Top) : Type(T) {}
151 BitValue(bool B) : Type(B ? One : Zero) {}
152 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
154 bool operator== (const BitValue &V) const {
157 if (Type == Ref && !(RefI == V.RefI))
161 bool operator!= (const BitValue &V) const {
162 return !operator==(V);
165 bool is(unsigned T) const {
166 assert(T == 0 || T == 1);
167 return T == 0 ? Type == Zero
168 : (T == 1 ? Type == One : false);
171 // The "meet" operation is the "." operation in a semilattice (L, ., T, B):
174 // (3) x.(y.z) = (x.y).z
175 // (4) x.T = x (i.e. T = "top")
176 // (5) x.B = B (i.e. B = "bottom")
178 // This "meet" function will update the value of the "*this" object with
179 // the newly calculated one, and return "true" if the value of *this has
180 // changed, and "false" otherwise.
181 // To prove that it satisfies the conditions (1)-(5), it is sufficient
182 // to show that a relation
183 // x <= y <=> x.y = x
184 // defines a partial order (i.e. that "meet" is same as "infimum").
185 bool meet(const BitValue &V, const BitRef &Self) {
186 // First, check the cases where there is nothing to be done.
187 if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This)
189 if (V.Type == Top) // This.meet(Top) = This
191 if (*this == V) // This.meet(This) = This
194 // At this point, we know that the value of "this" will change.
195 // If it is Top, it will become the same as V, otherwise it will
196 // become "bottom" (i.e. Self).
199 RefI = V.RefI; // This may be irrelevant, but copy anyway.
208 // Create a reference to the bit value V.
209 static BitValue ref(const BitValue &V);
211 static BitValue self(const BitRef &Self = BitRef());
214 return Type == Zero || Type == One;
217 operator bool() const {
218 assert(Type == Zero || Type == One);
222 friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
225 // This operation must be idempotent, i.e. ref(ref(V)) == ref(V).
226 inline BitTracker::BitValue
227 BitTracker::BitValue::ref(const BitValue &V) {
229 return BitValue(V.Type);
231 return BitValue(V.RefI.Reg, V.RefI.Pos);
235 inline BitTracker::BitValue
236 BitTracker::BitValue::self(const BitRef &Self) {
237 return BitValue(Self.Reg, Self.Pos);
240 // A sequence of bits starting from index B up to and including index E.
241 // If E < B, the mask represents two sections: [0..E] and [B..W) where
242 // W is the width of the register.
243 struct BitTracker::BitMask {
245 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
247 uint16_t first() const { return B; }
248 uint16_t last() const { return E; }
255 // Representation of a register: a list of BitValues.
256 struct BitTracker::RegisterCell {
257 RegisterCell(uint16_t Width = DefaultBitN) : Bits(Width) {}
259 uint16_t width() const {
263 const BitValue &operator[](uint16_t BitN) const {
264 assert(BitN < Bits.size());
267 BitValue &operator[](uint16_t BitN) {
268 assert(BitN < Bits.size());
272 bool meet(const RegisterCell &RC, unsigned SelfR);
273 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
274 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
275 RegisterCell &rol(uint16_t Sh); // Rotate left.
276 RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
277 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
278 uint16_t cl(bool B) const;
279 uint16_t ct(bool B) const;
281 bool operator== (const RegisterCell &RC) const;
282 bool operator!= (const RegisterCell &RC) const {
283 return !operator==(RC);
286 // Generate a "ref" cell for the corresponding register. In the resulting
287 // cell each bit will be described as being the same as the corresponding
288 // bit in register Reg (i.e. the cell is "defined" by register Reg).
289 static RegisterCell self(unsigned Reg, uint16_t Width);
290 // Generate a "top" cell of given size.
291 static RegisterCell top(uint16_t Width);
292 // Generate a cell that is a "ref" to another cell.
293 static RegisterCell ref(const RegisterCell &C);
296 // The DefaultBitN is here only to avoid frequent reallocation of the
297 // memory in the vector.
298 static const unsigned DefaultBitN = 32;
299 typedef SmallVector<BitValue, DefaultBitN> BitValueList;
302 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
305 inline bool BitTracker::has(unsigned Reg) const {
306 return Map.find(Reg) != Map.end();
309 inline const BitTracker::RegisterCell&
310 BitTracker::lookup(unsigned Reg) const {
311 CellMapType::const_iterator F = Map.find(Reg);
312 assert(F != Map.end());
316 inline BitTracker::RegisterCell
317 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) {
318 RegisterCell RC(Width);
319 for (uint16_t i = 0; i < Width; ++i)
320 RC.Bits[i] = BitValue::self(BitRef(Reg, i));
324 inline BitTracker::RegisterCell
325 BitTracker::RegisterCell::top(uint16_t Width) {
326 RegisterCell RC(Width);
327 for (uint16_t i = 0; i < Width; ++i)
328 RC.Bits[i] = BitValue(BitValue::Top);
332 inline BitTracker::RegisterCell
333 BitTracker::RegisterCell::ref(const RegisterCell &C) {
334 uint16_t W = C.width();
336 for (unsigned i = 0; i < W; ++i)
337 RC[i] = BitValue::ref(C[i]);
341 // A class to evaluate target's instructions and update the cell maps.
342 // This is used internally by the bit tracker. A target that wants to
343 // utilize this should implement the evaluation functions (noted below)
344 // in a subclass of this class.
345 struct BitTracker::MachineEvaluator {
346 MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
348 virtual ~MachineEvaluator() = default;
350 uint16_t getRegBitWidth(const RegisterRef &RR) const;
352 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
353 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
355 // A result of any operation should use refs to the source cells, not
356 // the cells directly. This function is a convenience wrapper to quickly
357 // generate a ref for a cell corresponding to a register reference.
358 RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const {
359 RegisterCell RC = getCell(RR, M);
360 return RegisterCell::ref(RC);
364 // Check if a cell is an immediate value (i.e. all bits are either 0 or 1).
365 bool isInt(const RegisterCell &A) const;
366 // Convert cell to an immediate value.
367 uint64_t toInt(const RegisterCell &A) const;
369 // Generate cell from an immediate value.
370 RegisterCell eIMM(int64_t V, uint16_t W) const;
371 RegisterCell eIMM(const ConstantInt *CI) const;
374 RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
375 RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const;
376 RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const;
377 RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const;
380 RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
381 RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
382 RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
385 RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const;
386 RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const;
387 RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const;
388 RegisterCell eNOT(const RegisterCell &A1) const;
390 // Set bit, clear bit.
391 RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
392 RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
394 // Count leading/trailing bits (zeros/ones).
395 RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const;
396 RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const;
398 // Sign/zero extension.
399 RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const;
400 RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const;
403 // XTR R,b,e: extract bits from A1 starting at bit b, ending at e-1.
404 // INS R,S,b: take R and replace bits starting from b with S.
405 RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const;
406 RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2,
409 // User-provided functions for individual targets:
411 // Return a sub-register mask that indicates which bits in Reg belong
412 // to the subregister Sub. These bits are assumed to be contiguous in
413 // the super-register, and have the same ordering in the sub-register
414 // as in the super-register. It is valid to call this function with
415 // Sub == 0, in this case, the function should return a mask that spans
416 // the entire register Reg (which is what the default implementation
418 virtual BitMask mask(unsigned Reg, unsigned Sub) const;
419 // Indicate whether a given register class should be tracked.
420 virtual bool track(const TargetRegisterClass *RC) const { return true; }
421 // Evaluate a non-branching machine instruction, given the cell map with
422 // the input values. Place the results in the Outputs map. Return "true"
423 // if evaluation succeeded, "false" otherwise.
424 virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
425 CellMapType &Outputs) const;
426 // Evaluate a branch, given the cell map with the input values. Fill out
427 // a list of all possible branch targets and indicate (through a flag)
428 // whether the branch could fall-through. Return "true" if this information
429 // has been successfully computed, "false" otherwise.
430 virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
431 BranchTargetList &Targets, bool &FallsThru) const = 0;
433 const TargetRegisterInfo &TRI;
434 MachineRegisterInfo &MRI;
437 } // end namespace llvm
439 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H