1 //===--- BitTracker.h -------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
13 #include "llvm/ADT/DenseSet.h"
14 #include "llvm/ADT/SetVector.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineOperand.h"
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
39 struct MachineEvaluator;
41 typedef SetVector<const MachineBasicBlock *> BranchTargetList;
43 typedef std::map<unsigned, RegisterCell> CellMapType;
45 BitTracker(const MachineEvaluator &E, MachineFunction &F);
49 void trace(bool On = false) { Trace = On; }
50 bool has(unsigned Reg) const;
51 const RegisterCell &lookup(unsigned Reg) const;
52 RegisterCell get(RegisterRef RR) const;
53 void put(RegisterRef RR, const RegisterCell &RC);
54 void subst(RegisterRef OldRR, RegisterRef NewRR);
55 bool reached(const MachineBasicBlock *B) const;
56 void visit(const MachineInstr &MI);
58 void print_cells(raw_ostream &OS) const;
61 void visitPHI(const MachineInstr &PI);
62 void visitNonBranch(const MachineInstr &MI);
63 void visitBranchesFrom(const MachineInstr &BI);
64 void visitUsesOf(unsigned Reg);
67 typedef std::pair<int,int> CFGEdge;
68 typedef std::set<CFGEdge> EdgeSetType;
69 typedef std::set<const MachineInstr *> InstrSetType;
70 typedef std::queue<CFGEdge> EdgeQueueType;
72 EdgeSetType EdgeExec; // Executable flow graph edges.
73 InstrSetType InstrExec; // Executable instructions.
74 EdgeQueueType FlowQ; // Work queue of CFG edges.
75 DenseSet<unsigned> ReachedBB; // Cache of reached blocks.
76 bool Trace; // Enable tracing for debugging.
78 const MachineEvaluator &ME;
80 MachineRegisterInfo &MRI;
84 // Abstraction of a reference to bit at position Pos from a register Reg.
85 struct BitTracker::BitRef {
86 BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
88 bool operator== (const BitRef &BR) const {
89 // If Reg is 0, disregard Pos.
90 return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
97 // Abstraction of a register reference in MachineOperand. It contains the
98 // register number and the subregister index.
99 struct BitTracker::RegisterRef {
100 RegisterRef(unsigned R = 0, unsigned S = 0)
102 RegisterRef(const MachineOperand &MO)
103 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
108 // Value that a single bit can take. This is outside of the context of
109 // any register, it is more of an abstraction of the two-element set of
110 // possible bit values. One extension here is the "Ref" type, which
111 // indicates that this bit takes the same value as the bit described by
113 struct BitTracker::BitValue {
115 Top, // Bit not yet defined.
118 Ref // Bit value same as the one described in RefI.
119 // Conceptually, there is no explicit "bottom" value: the lattice's
120 // bottom will be expressed as a "ref to itself", which, in the context
121 // of registers, could be read as "this value of this bit is defined by
125 // Self <= x, where "Self" is "ref to itself".
126 // This makes the value lattice different for each virtual register
127 // (even for each bit in the same virtual register), since the "bottom"
128 // for one register will be a simple "ref" for another register.
129 // Since we do not store the "Self" bit and register number, the meet
130 // operation will need to take it as a parameter.
132 // In practice there is a special case for values that are not associa-
133 // ted with any specific virtual register. An example would be a value
134 // corresponding to a bit of a physical register, or an intermediate
135 // value obtained in some computation (such as instruction evaluation).
136 // Such cases are identical to the usual Ref type, but the register
137 // number is 0. In such case the Pos field of the reference is ignored.
139 // What is worthy of notice is that in value V (that is a "ref"), as long
140 // as the RefI.Reg is not 0, it may actually be the same register as the
141 // one in which V will be contained. If the RefI.Pos refers to the posi-
142 // tion of V, then V is assumed to be "bottom" (as a "ref to itself"),
143 // otherwise V is taken to be identical to the referenced bit of the
145 // If RefI.Reg is 0, however, such a reference to the same register is
146 // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
147 // is treated as "bottom".
152 BitValue(ValueType T = Top) : Type(T) {}
153 BitValue(bool B) : Type(B ? One : Zero) {}
154 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
156 bool operator== (const BitValue &V) const {
159 if (Type == Ref && !(RefI == V.RefI))
163 bool operator!= (const BitValue &V) const {
164 return !operator==(V);
167 bool is(unsigned T) const {
168 assert(T == 0 || T == 1);
169 return T == 0 ? Type == Zero
170 : (T == 1 ? Type == One : false);
173 // The "meet" operation is the "." operation in a semilattice (L, ., T, B):
176 // (3) x.(y.z) = (x.y).z
177 // (4) x.T = x (i.e. T = "top")
178 // (5) x.B = B (i.e. B = "bottom")
180 // This "meet" function will update the value of the "*this" object with
181 // the newly calculated one, and return "true" if the value of *this has
182 // changed, and "false" otherwise.
183 // To prove that it satisfies the conditions (1)-(5), it is sufficient
184 // to show that a relation
185 // x <= y <=> x.y = x
186 // defines a partial order (i.e. that "meet" is same as "infimum").
187 bool meet(const BitValue &V, const BitRef &Self) {
188 // First, check the cases where there is nothing to be done.
189 if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This)
191 if (V.Type == Top) // This.meet(Top) = This
193 if (*this == V) // This.meet(This) = This
196 // At this point, we know that the value of "this" will change.
197 // If it is Top, it will become the same as V, otherwise it will
198 // become "bottom" (i.e. Self).
201 RefI = V.RefI; // This may be irrelevant, but copy anyway.
210 // Create a reference to the bit value V.
211 static BitValue ref(const BitValue &V);
213 static BitValue self(const BitRef &Self = BitRef());
216 return Type == Zero || Type == One;
219 operator bool() const {
220 assert(Type == Zero || Type == One);
224 friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
227 // This operation must be idempotent, i.e. ref(ref(V)) == ref(V).
228 inline BitTracker::BitValue
229 BitTracker::BitValue::ref(const BitValue &V) {
231 return BitValue(V.Type);
233 return BitValue(V.RefI.Reg, V.RefI.Pos);
237 inline BitTracker::BitValue
238 BitTracker::BitValue::self(const BitRef &Self) {
239 return BitValue(Self.Reg, Self.Pos);
242 // A sequence of bits starting from index B up to and including index E.
243 // If E < B, the mask represents two sections: [0..E] and [B..W) where
244 // W is the width of the register.
245 struct BitTracker::BitMask {
247 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
249 uint16_t first() const { return B; }
250 uint16_t last() const { return E; }
257 // Representation of a register: a list of BitValues.
258 struct BitTracker::RegisterCell {
259 RegisterCell(uint16_t Width = DefaultBitN) : Bits(Width) {}
261 uint16_t width() const {
265 const BitValue &operator[](uint16_t BitN) const {
266 assert(BitN < Bits.size());
269 BitValue &operator[](uint16_t BitN) {
270 assert(BitN < Bits.size());
274 bool meet(const RegisterCell &RC, unsigned SelfR);
275 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
276 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
277 RegisterCell &rol(uint16_t Sh); // Rotate left.
278 RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
279 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
280 uint16_t cl(bool B) const;
281 uint16_t ct(bool B) const;
283 bool operator== (const RegisterCell &RC) const;
284 bool operator!= (const RegisterCell &RC) const {
285 return !operator==(RC);
288 // Replace the ref-to-reg-0 bit values with the given register.
289 RegisterCell ®ify(unsigned R);
291 // Generate a "ref" cell for the corresponding register. In the resulting
292 // cell each bit will be described as being the same as the corresponding
293 // bit in register Reg (i.e. the cell is "defined" by register Reg).
294 static RegisterCell self(unsigned Reg, uint16_t Width);
295 // Generate a "top" cell of given size.
296 static RegisterCell top(uint16_t Width);
297 // Generate a cell that is a "ref" to another cell.
298 static RegisterCell ref(const RegisterCell &C);
301 // The DefaultBitN is here only to avoid frequent reallocation of the
302 // memory in the vector.
303 static const unsigned DefaultBitN = 32;
304 typedef SmallVector<BitValue, DefaultBitN> BitValueList;
307 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
310 inline bool BitTracker::has(unsigned Reg) const {
311 return Map.find(Reg) != Map.end();
314 inline const BitTracker::RegisterCell&
315 BitTracker::lookup(unsigned Reg) const {
316 CellMapType::const_iterator F = Map.find(Reg);
317 assert(F != Map.end());
321 inline BitTracker::RegisterCell
322 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) {
323 RegisterCell RC(Width);
324 for (uint16_t i = 0; i < Width; ++i)
325 RC.Bits[i] = BitValue::self(BitRef(Reg, i));
329 inline BitTracker::RegisterCell
330 BitTracker::RegisterCell::top(uint16_t Width) {
331 RegisterCell RC(Width);
332 for (uint16_t i = 0; i < Width; ++i)
333 RC.Bits[i] = BitValue(BitValue::Top);
337 inline BitTracker::RegisterCell
338 BitTracker::RegisterCell::ref(const RegisterCell &C) {
339 uint16_t W = C.width();
341 for (unsigned i = 0; i < W; ++i)
342 RC[i] = BitValue::ref(C[i]);
346 // A class to evaluate target's instructions and update the cell maps.
347 // This is used internally by the bit tracker. A target that wants to
348 // utilize this should implement the evaluation functions (noted below)
349 // in a subclass of this class.
350 struct BitTracker::MachineEvaluator {
351 MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
353 virtual ~MachineEvaluator() = default;
355 uint16_t getRegBitWidth(const RegisterRef &RR) const;
357 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
358 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
360 // A result of any operation should use refs to the source cells, not
361 // the cells directly. This function is a convenience wrapper to quickly
362 // generate a ref for a cell corresponding to a register reference.
363 RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const {
364 RegisterCell RC = getCell(RR, M);
365 return RegisterCell::ref(RC);
369 // Check if a cell is an immediate value (i.e. all bits are either 0 or 1).
370 bool isInt(const RegisterCell &A) const;
371 // Convert cell to an immediate value.
372 uint64_t toInt(const RegisterCell &A) const;
374 // Generate cell from an immediate value.
375 RegisterCell eIMM(int64_t V, uint16_t W) const;
376 RegisterCell eIMM(const ConstantInt *CI) const;
379 RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
380 RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const;
381 RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const;
382 RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const;
385 RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
386 RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
387 RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
390 RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const;
391 RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const;
392 RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const;
393 RegisterCell eNOT(const RegisterCell &A1) const;
395 // Set bit, clear bit.
396 RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
397 RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
399 // Count leading/trailing bits (zeros/ones).
400 RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const;
401 RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const;
403 // Sign/zero extension.
404 RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const;
405 RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const;
408 // XTR R,b,e: extract bits from A1 starting at bit b, ending at e-1.
409 // INS R,S,b: take R and replace bits starting from b with S.
410 RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const;
411 RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2,
414 // User-provided functions for individual targets:
416 // Return a sub-register mask that indicates which bits in Reg belong
417 // to the subregister Sub. These bits are assumed to be contiguous in
418 // the super-register, and have the same ordering in the sub-register
419 // as in the super-register. It is valid to call this function with
420 // Sub == 0, in this case, the function should return a mask that spans
421 // the entire register Reg (which is what the default implementation
423 virtual BitMask mask(unsigned Reg, unsigned Sub) const;
424 // Indicate whether a given register class should be tracked.
425 virtual bool track(const TargetRegisterClass *RC) const { return true; }
426 // Evaluate a non-branching machine instruction, given the cell map with
427 // the input values. Place the results in the Outputs map. Return "true"
428 // if evaluation succeeded, "false" otherwise.
429 virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
430 CellMapType &Outputs) const;
431 // Evaluate a branch, given the cell map with the input values. Fill out
432 // a list of all possible branch targets and indicate (through a flag)
433 // whether the branch could fall-through. Return "true" if this information
434 // has been successfully computed, "false" otherwise.
435 virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
436 BranchTargetList &Targets, bool &FallsThru) const = 0;
438 const TargetRegisterInfo &TRI;
439 MachineRegisterInfo &MRI;
442 } // end namespace llvm
444 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H