contrib/llvm/lib/Target/Hexagon/Hexagon.td

   1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the Hexagon target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // Target-independent interfaces which we are implementing
  16 //===----------------------------------------------------------------------===//
  17
  18 include "llvm/Target/Target.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Hexagon Subtarget features.
  22 //===----------------------------------------------------------------------===//
  23
  24 // Hexagon Architectures
  25 include "HexagonDepArch.td"
  26
  27 // Hexagon ISA Extensions
  28 def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
  29       "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
  30 def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
  31       "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
  32       [ExtensionHVX]>;
  33 def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
  34       "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
  35       [ExtensionHVX,ExtensionHVXV60]>;
  36 def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
  37       "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
  38       [ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
  39
  40 def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
  41       "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
  42 def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
  43       "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
  44
  45 def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
  46       "Support for instruction packets">;
  47 def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
  48       "Use constant-extended calls">;
  49 def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
  50       "Supports mem_noshuf feature">;
  51 def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",
  52       "Use memop instructions">;
  53 def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
  54       "Support for new-value jumps", [FeaturePackets]>;
  55 def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",
  56       "Support for new-value stores", [FeaturePackets]>;
  57 def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
  58       "Allow GP-relative addressing of global variables">;
  59 def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
  60       "Enable generation of duplex instruction">;
  61 def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
  62       "true", "Reserve register R19">;
  63
  64 //===----------------------------------------------------------------------===//
  65 // Hexagon Instruction Predicate Definitions.
  66 //===----------------------------------------------------------------------===//
  67
  68 def UseMEMOPS          : Predicate<"HST->useMemops()">;
  69 def UseHVX64B          : Predicate<"HST->useHVX64BOps()">,
  70                          AssemblerPredicate<"ExtensionHVX64B">;
  71 def UseHVX128B         : Predicate<"HST->useHVX128BOps()">,
  72                          AssemblerPredicate<"ExtensionHVX128B">;
  73 def UseHVX             : Predicate<"HST->useHVXOps()">,
  74                          AssemblerPredicate<"ExtensionHVXV60">;
  75 def UseHVXV60          : Predicate<"HST->useHVXOps()">,
  76                          AssemblerPredicate<"ExtensionHVXV60">;
  77 def UseHVXV62          : Predicate<"HST->useHVXOps()">,
  78                          AssemblerPredicate<"ExtensionHVXV62">;
  79 def UseHVXV65          : Predicate<"HST->useHVXOps()">,
  80                          AssemblerPredicate<"ExtensionHVXV65">;
  81
  82 def Hvx64:  HwMode<"+hvx-length64b">;
  83 def Hvx128: HwMode<"+hvx-length128b">;
  84
  85 //===----------------------------------------------------------------------===//
  86 // Classes used for relation maps.
  87 //===----------------------------------------------------------------------===//
  88
  89 class ImmRegShl;
  90 // ImmRegRel - Filter class used to relate instructions having reg-reg form
  91 // with their reg-imm counterparts.
  92 class ImmRegRel;
  93 // PredRel - Filter class used to relate non-predicated instructions with their
  94 // predicated forms.
  95 class PredRel;
  96 // PredNewRel - Filter class used to relate predicated instructions with their
  97 // predicate-new forms.
  98 class PredNewRel: PredRel;
  99 // NewValueRel - Filter class used to relate regular store instructions with
 100 // their new-value store form.
 101 class NewValueRel: PredNewRel;
 102 // NewValueRel - Filter class used to relate load/store instructions having
 103 // different addressing modes with each other.
 104 class AddrModeRel: NewValueRel;
 105 class PostInc_BaseImm;
 106 class IntrinsicsRel;
 107
 108 //===----------------------------------------------------------------------===//
 109 // Generate mapping table to relate non-predicate instructions with their
 110 // predicated formats - true and false.
 111 //
 112
 113 def getPredOpcode : InstrMapping {
 114   let FilterClass = "PredRel";
 115   // Instructions with the same BaseOpcode and isNVStore values form a row.
 116   let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
 117   // Instructions with the same predicate sense form a column.
 118   let ColFields = ["PredSense"];
 119   // The key column is the unpredicated instructions.
 120   let KeyCol = [""];
 121   // Value columns are PredSense=true and PredSense=false
 122   let ValueCols = [["true"], ["false"]];
 123 }
 124
 125 //===----------------------------------------------------------------------===//
 126 // Generate mapping table to relate predicate-true instructions with their
 127 // predicate-false forms
 128 //
 129 def getFalsePredOpcode : InstrMapping {
 130   let FilterClass = "PredRel";
 131   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
 132   let ColFields = ["PredSense"];
 133   let KeyCol = ["true"];
 134   let ValueCols = [["false"]];
 135 }
 136
 137 //===----------------------------------------------------------------------===//
 138 // Generate mapping table to relate predicate-false instructions with their
 139 // predicate-true forms
 140 //
 141 def getTruePredOpcode : InstrMapping {
 142   let FilterClass = "PredRel";
 143   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
 144   let ColFields = ["PredSense"];
 145   let KeyCol = ["false"];
 146   let ValueCols = [["true"]];
 147 }
 148
 149 //===----------------------------------------------------------------------===//
 150 // Generate mapping table to relate predicated instructions with their .new
 151 // format.
 152 //
 153 def getPredNewOpcode : InstrMapping {
 154   let FilterClass = "PredNewRel";
 155   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
 156   let ColFields = ["PNewValue"];
 157   let KeyCol = [""];
 158   let ValueCols = [["new"]];
 159 }
 160
 161 //===----------------------------------------------------------------------===//
 162 // Generate mapping table to relate .new predicated instructions with their old
 163 // format.
 164 //
 165 def getPredOldOpcode : InstrMapping {
 166   let FilterClass = "PredNewRel";
 167   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
 168   let ColFields = ["PNewValue"];
 169   let KeyCol = ["new"];
 170   let ValueCols = [[""]];
 171 }
 172
 173 //===----------------------------------------------------------------------===//
 174 // Generate mapping table to relate store instructions with their new-value
 175 // format.
 176 //
 177 def getNewValueOpcode : InstrMapping {
 178   let FilterClass = "NewValueRel";
 179   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
 180   let ColFields = ["NValueST"];
 181   let KeyCol = ["false"];
 182   let ValueCols = [["true"]];
 183 }
 184
 185 //===----------------------------------------------------------------------===//
 186 // Generate mapping table to relate new-value store instructions with their old
 187 // format.
 188 //
 189 def getNonNVStore : InstrMapping {
 190   let FilterClass = "NewValueRel";
 191   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
 192   let ColFields = ["NValueST"];
 193   let KeyCol = ["true"];
 194   let ValueCols = [["false"]];
 195 }
 196
 197 def changeAddrMode_abs_io: InstrMapping {
 198   let FilterClass = "AddrModeRel";
 199   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
 200                    "isFloat"];
 201   let ColFields = ["addrMode"];
 202   let KeyCol = ["Absolute"];
 203   let ValueCols = [["BaseImmOffset"]];
 204 }
 205
 206 def changeAddrMode_io_abs: InstrMapping {
 207   let FilterClass = "AddrModeRel";
 208   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
 209                    "isFloat"];
 210   let ColFields = ["addrMode"];
 211   let KeyCol = ["BaseImmOffset"];
 212   let ValueCols = [["Absolute"]];
 213 }
 214
 215 def changeAddrMode_io_rr: InstrMapping {
 216   let FilterClass = "AddrModeRel";
 217   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 218   let ColFields = ["addrMode"];
 219   let KeyCol = ["BaseImmOffset"];
 220   let ValueCols = [["BaseRegOffset"]];
 221 }
 222
 223 def changeAddrMode_rr_io: InstrMapping {
 224   let FilterClass = "AddrModeRel";
 225   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 226   let ColFields = ["addrMode"];
 227   let KeyCol = ["BaseRegOffset"];
 228   let ValueCols = [["BaseImmOffset"]];
 229 }
 230
 231 def changeAddrMode_pi_io: InstrMapping {
 232   let FilterClass = "PostInc_BaseImm";
 233   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 234   let ColFields = ["addrMode"];
 235   let KeyCol = ["PostInc"];
 236   let ValueCols = [["BaseImmOffset"]];
 237 }
 238
 239 def changeAddrMode_io_pi: InstrMapping {
 240   let FilterClass = "PostInc_BaseImm";
 241   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 242   let ColFields = ["addrMode"];
 243   let KeyCol = ["BaseImmOffset"];
 244   let ValueCols = [["PostInc"]];
 245 }
 246
 247 def changeAddrMode_rr_ur: InstrMapping {
 248   let FilterClass = "ImmRegShl";
 249   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 250   let ColFields = ["addrMode"];
 251   let KeyCol = ["BaseRegOffset"];
 252   let ValueCols = [["BaseLongOffset"]];
 253 }
 254
 255 def changeAddrMode_ur_rr : InstrMapping {
 256   let FilterClass = "ImmRegShl";
 257   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 258   let ColFields = ["addrMode"];
 259   let KeyCol = ["BaseLongOffset"];
 260   let ValueCols = [["BaseRegOffset"]];
 261 }
 262
 263 def getRegForm : InstrMapping {
 264   let FilterClass = "ImmRegRel";
 265   let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
 266   let ColFields = ["InputType"];
 267   let KeyCol = ["imm"];
 268   let ValueCols = [["reg"]];
 269 }
 270
 271 def notTakenBranchPrediction : InstrMapping {
 272   let FilterClass = "PredRel";
 273   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
 274   let ColFields = ["isBrTaken"];
 275   let KeyCol = ["true"];
 276   let ValueCols = [["false"]];
 277 }
 278
 279 def takenBranchPrediction : InstrMapping {
 280   let FilterClass = "PredRel";
 281   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
 282   let ColFields = ["isBrTaken"];
 283   let KeyCol = ["false"];
 284   let ValueCols = [["true"]];
 285 }
 286
 287 def getRealHWInstr : InstrMapping {
 288   let FilterClass = "IntrinsicsRel";
 289   let RowFields = ["BaseOpcode"];
 290   let ColFields = ["InstrType"];
 291   let KeyCol = ["Pseudo"];
 292   let ValueCols = [["Pseudo"], ["Real"]];
 293 }
 294 //===----------------------------------------------------------------------===//
 295 // Register File, Instruction Descriptions
 296 //===----------------------------------------------------------------------===//
 297 include "HexagonSchedule.td"
 298 include "HexagonRegisterInfo.td"
 299 include "HexagonOperands.td"
 300 include "HexagonDepOperands.td"
 301 include "HexagonDepITypes.td"
 302 include "HexagonInstrFormats.td"
 303 include "HexagonDepInstrFormats.td"
 304 include "HexagonDepInstrInfo.td"
 305 include "HexagonCallingConv.td"
 306 include "HexagonPseudo.td"
 307 include "HexagonPatterns.td"
 308 include "HexagonPatternsHVX.td"
 309 include "HexagonPatternsV65.td"
 310 include "HexagonDepMappings.td"
 311 include "HexagonIntrinsics.td"
 312 include "HexagonMapAsm2IntrinV62.gen.td"
 313 include "HexagonMapAsm2IntrinV65.gen.td"
 314
 315 def HexagonInstrInfo : InstrInfo;
 316
 317 //===----------------------------------------------------------------------===//
 318 // Hexagon processors supported.
 319 //===----------------------------------------------------------------------===//
 320
 321 class Proc<string Name, SchedMachineModel Model,
 322            list<SubtargetFeature> Features>
 323  : ProcessorModel<Name, Model, Features>;
 324
 325 def : Proc<"generic", HexagonModelV60,
 326            [ArchV4, ArchV5, ArchV55, ArchV60,
 327             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 328             FeaturePackets, FeatureSmallData]>;
 329 def : Proc<"hexagonv4",  HexagonModelV4,
 330            [ArchV4,
 331             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 332             FeaturePackets, FeatureSmallData]>;
 333 def : Proc<"hexagonv5",  HexagonModelV4,
 334            [ArchV4, ArchV5,
 335             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 336             FeaturePackets, FeatureSmallData]>;
 337 def : Proc<"hexagonv55", HexagonModelV55,
 338            [ArchV4, ArchV5, ArchV55,
 339             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 340             FeaturePackets, FeatureSmallData]>;
 341 def : Proc<"hexagonv60", HexagonModelV60,
 342            [ArchV4, ArchV5, ArchV55, ArchV60,
 343             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 344             FeaturePackets, FeatureSmallData]>;
 345 def : Proc<"hexagonv62", HexagonModelV62,
 346            [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62,
 347             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
 348             FeaturePackets, FeatureSmallData]>;
 349 def : Proc<"hexagonv65", HexagonModelV65,
 350            [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
 351             FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
 352             FeatureNVS, FeaturePackets, FeatureSmallData]>;
 353
 354 //===----------------------------------------------------------------------===//
 355 // Declare the target which we are implementing
 356 //===----------------------------------------------------------------------===//
 357
 358 def HexagonAsmParser : AsmParser {
 359   let ShouldEmitMatchRegisterAltName = 1;
 360   bit HasMnemonicFirst = 0;
 361 }
 362
 363 def HexagonAsmParserVariant : AsmParserVariant {
 364   int Variant = 0;
 365   string TokenizingCharacters = "#()=:.<>!+*-|^&";
 366   string BreakCharacters = "";
 367 }
 368
 369 def HexagonAsmWriter : AsmWriter {
 370   string AsmWriterClassName  = "InstPrinter";
 371   bit isMCAsmWriter = 1;
 372 }
 373
 374 def Hexagon : Target {
 375   let InstructionSet = HexagonInstrInfo;
 376   let AssemblyParsers = [HexagonAsmParser];
 377   let AssemblyParserVariants = [HexagonAsmParserVariant];
 378   let AssemblyWriters = [HexagonAsmWriter];
 379   let AllowRegisterRenaming = 1;
 380 }