1 //===--- HexagonBitTracker.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "HexagonBitTracker.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetMachine.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Argument.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
37 typedef BitTracker BT;
39 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
40 MachineRegisterInfo &mri,
41 const HexagonInstrInfo &tii,
43 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
44 // Populate the VRX map (VR to extension-type).
45 // Go over all the formal parameters of the function. If a given parameter
46 // P is sign- or zero-extended, locate the virtual register holding that
47 // parameter and create an entry in the VRX map indicating the type of ex-
48 // tension (and the source type).
49 // This is a bit complicated to do accurately, since the memory layout in-
50 // formation is necessary to precisely determine whether an aggregate para-
51 // meter will be passed in a register or in memory. What is given in MRI
52 // is the association between the physical register that is live-in (i.e.
53 // holds an argument), and the virtual register that this value will be
54 // copied into. This, by itself, is not sufficient to map back the virtual
55 // register to a formal parameter from Function (since consecutive live-ins
56 // from MRI may not correspond to consecutive formal parameters from Func-
57 // tion). To avoid the complications with in-memory arguments, only consi-
58 // der the initial sequence of formal parameters that are known to be
59 // passed via registers.
61 unsigned InVirtReg, InPhysReg = 0;
62 const Function &F = *MF.getFunction();
63 typedef Function::const_arg_iterator arg_iterator;
64 for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
66 const Argument &Arg = *I;
67 Type *ATy = Arg.getType();
69 if (ATy->isIntegerTy())
70 Width = ATy->getIntegerBitWidth();
71 else if (ATy->isPointerTy())
73 // If pointer size is not set through target data, it will default to
74 // Module::AnyPointerSize.
75 if (Width == 0 || Width > 64)
77 AttributeSet Attrs = F.getAttributes();
78 if (Attrs.hasAttribute(AttrIdx, Attribute::ByVal))
80 InPhysReg = getNextPhysReg(InPhysReg, Width);
83 InVirtReg = getVirtRegFor(InPhysReg);
86 if (Attrs.hasAttribute(AttrIdx, Attribute::SExt))
87 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
88 else if (Attrs.hasAttribute(AttrIdx, Attribute::ZExt))
89 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
93 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
94 using namespace Hexagon;
97 return MachineEvaluator::mask(Reg, 0);
98 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
99 unsigned ID = RC->getID();
100 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
101 auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
102 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
104 case DoubleRegsRegClassID:
105 case VecDblRegsRegClassID:
106 case VecDblRegs128BRegClassID:
107 return IsSubLo ? BT::BitMask(0, RW-1)
108 : BT::BitMask(RW, 2*RW-1);
113 dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
115 llvm_unreachable("Unexpected register/subregister");
121 std::vector<BT::RegisterRef> Vector;
124 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
125 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
126 const MachineOperand &MO = MI.getOperand(i);
128 Vector[i] = BT::RegisterRef(MO);
129 // For indices that don't correspond to registers, the entry will
130 // remain constructed via the default constructor.
134 size_t size() const { return Vector.size(); }
136 const BT::RegisterRef &operator[](unsigned n) const {
137 // The main purpose of this operator is to assert with bad argument.
138 assert(n < Vector.size());
143 } // end anonymous namespace
145 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
146 const CellMapType &Inputs,
147 CellMapType &Outputs) const {
148 using namespace Hexagon;
150 unsigned NumDefs = 0;
152 // Sanity verification: there should not be any defs with subregisters.
153 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
154 const MachineOperand &MO = MI.getOperand(i);
155 if (!MO.isReg() || !MO.isDef())
158 assert(MO.getSubReg() == 0);
164 unsigned Opc = MI.getOpcode();
168 // These instructions may be marked as mayLoad, but they are generating
169 // immediate values, so skip them.
174 return evaluateLoad(MI, Inputs, Outputs);
178 // Check COPY instructions that copy formal parameters into virtual
179 // registers. Such parameters can be sign- or zero-extended at the
180 // call site, and we should take advantage of this knowledge. The MRI
181 // keeps a list of pairs of live-in physical and virtual registers,
182 // which provides information about which virtual registers will hold
183 // the argument values. The function will still contain instructions
184 // defining those virtual registers, and in practice those are COPY
185 // instructions from a physical to a virtual register. In such cases,
186 // applying the argument extension to the virtual register can be seen
187 // as simply mirroring the extension that had already been applied to
188 // the physical register at the call site. If the defining instruction
189 // was not a COPY, it would not be clear how to mirror that extension
190 // on the callee's side. For that reason, only check COPY instructions
191 // for potential extensions.
193 if (evaluateFormalCopy(MI, Inputs, Outputs))
197 // Beyond this point, if any operand is a global, skip that instruction.
198 // The reason is that certain instructions that can take an immediate
199 // operand can also have a global symbol in that operand. To avoid
200 // checking what kind of operand a given instruction has individually
201 // for each instruction, do it here. Global symbols as operands gene-
202 // rally do not provide any useful information.
203 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
204 const MachineOperand &MO = MI.getOperand(i);
205 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
210 RegisterRefs Reg(MI);
211 #define op(i) MI.getOperand(i)
212 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
213 #define im(i) MI.getOperand(i).getImm()
215 // If the instruction has no register operands, skip it.
219 // Record result for register in operand 0.
220 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
222 putCell(Reg[0], Val, Outputs);
225 // Get the cell corresponding to the N-th operand.
226 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
227 uint16_t W) -> BT::RegisterCell {
228 const MachineOperand &Op = MI.getOperand(N);
230 return eIMM(Op.getImm(), W);
232 return RegisterCell::self(0, W);
233 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
236 // Extract RW low bits of the cell.
237 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
238 -> BT::RegisterCell {
239 assert(RW <= RC.width());
240 return eXTR(RC, 0, RW);
242 // Extract RW high bits of the cell.
243 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
244 -> BT::RegisterCell {
245 uint16_t W = RC.width();
247 return eXTR(RC, W-RW, W);
249 // Extract N-th halfword (counting from the least significant position).
250 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
251 -> BT::RegisterCell {
252 assert(N*16+16 <= RC.width());
253 return eXTR(RC, N*16, N*16+16);
255 // Shuffle bits (pick even/odd from cells and merge into result).
256 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
257 uint16_t BW, bool Odd) -> BT::RegisterCell {
258 uint16_t I = Odd, Ws = Rs.width();
259 assert(Ws == Rt.width());
260 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
263 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
269 // The bitwidth of the 0th operand. In most (if not all) of the
270 // instructions below, the 0th operand is the defined register.
271 // Pre-compute the bitwidth here, because it is needed in many cases
273 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
276 // Transfer immediate:
282 return rr0(eIMM(im(1), W0), Outputs);
284 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
286 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
288 int FI = op(1).getIndex();
289 int Off = op(2).getImm();
290 unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
291 unsigned L = Log2_32(A);
292 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
293 RC.fill(0, L, BT::BitValue::Zero);
294 return rr0(RC, Outputs);
297 // Transfer register:
302 return rr0(rc(1), Outputs);
305 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
307 RegisterCell PC = eXTR(rc(1), 0, PW);
308 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
309 RC.fill(PW, RW, BT::BitValue::Zero);
310 return rr0(RC, Outputs);
313 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
314 W0 = 8; // XXX Pred size
315 return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
326 uint16_t W1 = getRegBitWidth(Reg[1]);
327 assert(W0 == 64 && W1 == 32);
328 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
329 RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
330 return rr0(RC, Outputs);
334 return rr0(eADD(rc(1), rc(2)), Outputs);
336 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
337 case S4_addi_asl_ri: {
338 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
339 return rr0(RC, Outputs);
341 case S4_addi_lsr_ri: {
342 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
343 return rr0(RC, Outputs);
346 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
347 return rr0(RC, Outputs);
349 case M4_mpyri_addi: {
350 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
351 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
352 return rr0(RC, Outputs);
354 case M4_mpyrr_addi: {
355 RegisterCell M = eMLS(rc(2), rc(3));
356 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
357 return rr0(RC, Outputs);
359 case M4_mpyri_addr_u2: {
360 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
361 RegisterCell RC = eADD(rc(1), lo(M, W0));
362 return rr0(RC, Outputs);
364 case M4_mpyri_addr: {
365 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
366 RegisterCell RC = eADD(rc(1), lo(M, W0));
367 return rr0(RC, Outputs);
369 case M4_mpyrr_addr: {
370 RegisterCell M = eMLS(rc(2), rc(3));
371 RegisterCell RC = eADD(rc(1), lo(M, W0));
372 return rr0(RC, Outputs);
375 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
376 return rr0(RC, Outputs);
379 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
380 return rr0(RC, Outputs);
383 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
384 return rr0(RC, Outputs);
387 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
388 return rr0(RC, Outputs);
390 case S2_addasl_rrri: {
391 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
392 return rr0(RC, Outputs);
395 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
396 RPC.fill(0, 2, BT::BitValue::Zero);
397 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
401 return rr0(eSUB(rc(1), rc(2)), Outputs);
403 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
404 case S4_subi_asl_ri: {
405 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
406 return rr0(RC, Outputs);
408 case S4_subi_lsr_ri: {
409 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
410 return rr0(RC, Outputs);
413 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
414 return rr0(RC, Outputs);
417 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
418 return rr0(RC, Outputs);
420 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
422 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
425 RegisterCell M = eMLS(rc(1), rc(2));
426 return rr0(hi(M, W0), Outputs);
429 return rr0(eMLS(rc(1), rc(2)), Outputs);
430 case M2_dpmpyss_acc_s0:
431 return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
432 case M2_dpmpyss_nac_s0:
433 return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
435 RegisterCell M = eMLS(rc(1), rc(2));
436 return rr0(lo(M, W0), Outputs);
439 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
440 RegisterCell RC = eADD(rc(1), lo(M, W0));
441 return rr0(RC, Outputs);
444 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
445 RegisterCell RC = eSUB(rc(1), lo(M, W0));
446 return rr0(RC, Outputs);
449 RegisterCell M = eMLS(rc(2), rc(3));
450 RegisterCell RC = eADD(rc(1), lo(M, W0));
451 return rr0(RC, Outputs);
454 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
455 return rr0(lo(M, 32), Outputs);
458 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
459 return rr0(lo(M, 32), Outputs);
462 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
463 return rr0(lo(M, 32), Outputs);
466 RegisterCell M = eMLU(rc(1), rc(2));
467 return rr0(hi(M, W0), Outputs);
470 return rr0(eMLU(rc(1), rc(2)), Outputs);
471 case M2_dpmpyuu_acc_s0:
472 return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
473 case M2_dpmpyuu_nac_s0:
474 return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
480 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
483 return rr0(eAND(rc(1), rc(2)), Outputs);
486 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
487 case S4_andi_asl_ri: {
488 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
489 return rr0(RC, Outputs);
491 case S4_andi_lsr_ri: {
492 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
493 return rr0(RC, Outputs);
496 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
498 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
500 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
502 return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
504 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
507 return rr0(eORL(rc(1), rc(2)), Outputs);
510 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
511 case S4_ori_asl_ri: {
512 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
513 return rr0(RC, Outputs);
515 case S4_ori_lsr_ri: {
516 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
517 return rr0(RC, Outputs);
520 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
522 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
525 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
526 return rr0(RC, Outputs);
529 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
530 return rr0(RC, Outputs);
533 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
535 return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
538 return rr0(eXOR(rc(1), rc(2)), Outputs);
540 return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
542 return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
544 return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
546 return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
549 return rr0(eNOT(rc(1)), Outputs);
553 return rr0(eASL(rc(1), im(2)), Outputs);
555 return rr0(eASL(rc(1), 16), Outputs);
558 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
561 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
564 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
567 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
568 case S2_asl_i_r_xacc:
569 case S2_asl_i_p_xacc:
570 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
578 return rr0(eASR(rc(1), im(2)), Outputs);
580 return rr0(eASR(rc(1), 16), Outputs);
583 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
586 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
589 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
592 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
593 case S2_asr_i_r_rnd: {
594 // The input is first sign-extended to 64 bits, then the output
595 // is truncated back to 32 bits.
597 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
598 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
599 return rr0(eXTR(RC, 0, W0), Outputs);
601 case S2_asr_i_r_rnd_goodsyntax: {
604 return rr0(rc(1), Outputs);
605 // Result: S2_asr_i_r_rnd Rs, u5-1
606 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
607 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
608 return rr0(eXTR(RC, 0, W0), Outputs);
612 case S2_asr_i_svw_trun:
618 return rr0(eLSR(rc(1), im(2)), Outputs);
621 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
624 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
627 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
630 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
631 case S2_lsr_i_r_xacc:
632 case S2_lsr_i_p_xacc:
633 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
636 RegisterCell RC = rc(1);
637 RC[im(2)] = BT::BitValue::Zero;
638 return rr0(RC, Outputs);
641 RegisterCell RC = rc(1);
642 RC[im(2)] = BT::BitValue::One;
643 return rr0(RC, Outputs);
645 case S2_togglebit_i: {
646 RegisterCell RC = rc(1);
648 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
649 : RC[BX].is(1) ? BT::BitValue::Zero
650 : BT::BitValue::self();
651 return rr0(RC, Outputs);
655 uint16_t W1 = getRegBitWidth(Reg[1]);
657 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
658 const BT::BitValue Zero = BT::BitValue::Zero;
659 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
660 .fill(W1+(W1-BX), W0, Zero);
661 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
662 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
663 return rr0(RC, Outputs);
669 uint16_t Wd = im(2), Of = im(3);
672 return rr0(eIMM(0, W0), Outputs);
673 // If the width extends beyond the register size, pad the register
675 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
676 RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
677 // Ext is short, need to extend it with 0s or sign bit.
678 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
679 if (Opc == S2_extractu || Opc == S2_extractup)
680 return rr0(eZXT(RC, Wd), Outputs);
681 return rr0(eSXT(RC, Wd), Outputs);
685 uint16_t Wd = im(3), Of = im(4);
686 assert(Wd < W0 && Of < W0);
687 // If Wd+Of exceeds W0, the inserted bits are truncated.
691 return rr0(rc(1), Outputs);
692 return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
703 case V6_vcombine_128B:
705 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
709 case A2_combine_hh: {
711 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
712 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
713 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
714 // High half in the output is 0 for _ll and _lh, 1 otherwise:
715 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
716 RegisterCell R1 = rc(1);
717 RegisterCell R2 = rc(2);
718 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
719 return rr0(RC, Outputs);
723 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
724 RegisterCell R1 = rc(1);
725 RegisterCell R2 = rc(2);
726 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
728 return rr0(RC, Outputs);
731 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
732 return rr0(RC, Outputs);
735 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
736 return rr0(RC, Outputs);
739 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
740 return rr0(RC, Outputs);
743 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
744 return rr0(RC, Outputs);
748 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
749 assert(WR == 64 && WP == 8);
750 RegisterCell R1 = rc(1);
752 for (uint16_t i = 0; i < WP; ++i) {
753 const BT::BitValue &V = R1[i];
754 BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
755 RC.fill(i*8, i*8+8, F);
757 return rr0(RC, Outputs);
766 BT::BitValue PC0 = rc(1)[0];
767 RegisterCell R2 = cop(2, W0);
768 RegisterCell R3 = cop(3, W0);
769 if (PC0.is(0) || PC0.is(1))
770 return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
771 R2.meet(R3, Reg[0].Reg);
772 return rr0(R2, Outputs);
778 // Sign- and zero-extension:
781 return rr0(eSXT(rc(1), 8), Outputs);
783 return rr0(eSXT(rc(1), 16), Outputs);
785 uint16_t W1 = getRegBitWidth(Reg[1]);
786 assert(W0 == 64 && W1 == 32);
787 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
788 return rr0(RC, Outputs);
791 return rr0(eZXT(rc(1), 8), Outputs);
793 return rr0(eZXT(rc(1), 16), Outputs);
799 // Always produce a 32-bit result.
800 return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
803 return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
806 uint16_t W1 = getRegBitWidth(Reg[1]);
807 RegisterCell R1 = rc(1);
808 BT::BitValue TV = R1[W1-1];
809 if (TV.is(0) || TV.is(1))
810 return rr0(eCLB(R1, TV, 32), Outputs);
815 return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
818 return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
824 RegisterCell P1 = rc(1);
825 bool Has0 = false, All1 = true;
826 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
837 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
838 return rr0(RC, Outputs);
841 RegisterCell P1 = rc(1);
842 bool Has1 = false, All0 = true;
843 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
854 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
855 return rr0(RC, Outputs);
858 return rr0(eAND(rc(1), rc(2)), Outputs);
860 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
862 return rr0(eNOT(rc(1)), Outputs);
864 return rr0(eORL(rc(1), rc(2)), Outputs);
866 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
868 return rr0(eXOR(rc(1), rc(2)), Outputs);
870 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
872 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
874 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
876 return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
878 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
880 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
882 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
884 return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
895 BT::BitValue V = rc(1)[im(2)];
896 if (V.is(0) || V.is(1)) {
897 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
898 bool TV = (Opc == S2_tstbit_i);
899 BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
900 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
906 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
914 bool HexagonEvaluator::evaluate(const MachineInstr &BI,
915 const CellMapType &Inputs,
916 BranchTargetList &Targets,
917 bool &FallsThru) const {
918 // We need to evaluate one branch at a time. TII::analyzeBranch checks
919 // all the branches in a basic block at once, so we cannot use it.
920 unsigned Opc = BI.getOpcode();
921 bool SimpleBranch = false;
922 bool Negated = false;
924 case Hexagon::J2_jumpf:
925 case Hexagon::J2_jumpfpt:
926 case Hexagon::J2_jumpfnew:
927 case Hexagon::J2_jumpfnewpt:
929 case Hexagon::J2_jumpt:
930 case Hexagon::J2_jumptpt:
931 case Hexagon::J2_jumptnew:
932 case Hexagon::J2_jumptnewpt:
933 // Simple branch: if([!]Pn) jump ...
934 // i.e. Op0 = predicate, Op1 = branch target.
937 case Hexagon::J2_jump:
938 Targets.insert(BI.getOperand(0).getMBB());
942 // If the branch is of unknown type, assume that all successors are
950 // BI is a conditional branch if we got here.
951 RegisterRef PR = BI.getOperand(0);
952 RegisterCell PC = getCell(PR, Inputs);
953 const BT::BitValue &Test = PC[0];
955 // If the condition is neither true nor false, then it's unknown.
956 if (!Test.is(0) && !Test.is(1))
959 // "Test.is(!Negated)" means "branch condition is true".
960 if (!Test.is(!Negated)) {
961 // Condition known to be false.
966 Targets.insert(BI.getOperand(1).getMBB());
971 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
972 const CellMapType &Inputs,
973 CellMapType &Outputs) const {
974 using namespace Hexagon;
976 if (TII.isPredicated(MI))
978 assert(MI.mayLoad() && "A load that mayn't?");
979 unsigned Opc = MI.getOpcode();
990 case L2_loadalignb_pbr:
991 case L2_loadalignb_pcr:
992 case L2_loadalignb_pi:
994 case L2_loadalignh_pbr:
995 case L2_loadalignh_pcr:
996 case L2_loadalignh_pi:
998 case L2_loadbsw2_pbr:
999 case L2_loadbsw2_pci:
1000 case L2_loadbsw2_pcr:
1001 case L2_loadbsw2_pi:
1002 case L2_loadbsw4_pbr:
1003 case L2_loadbsw4_pci:
1004 case L2_loadbsw4_pcr:
1005 case L2_loadbsw4_pi:
1007 case L2_loadbzw2_pbr:
1008 case L2_loadbzw2_pci:
1009 case L2_loadbzw2_pcr:
1010 case L2_loadbzw2_pi:
1011 case L2_loadbzw4_pbr:
1012 case L2_loadbzw4_pci:
1013 case L2_loadbzw4_pcr:
1014 case L2_loadbzw4_pi:
1033 case L2_loadrub_pbr:
1034 case L2_loadrub_pci:
1035 case L2_loadrub_pcr:
1061 case L2_loadruh_pbr:
1062 case L2_loadruh_pci:
1063 case L2_loadruh_pcr:
1079 case L2_loadw_locked:
1095 case L4_loadd_locked:
1105 const MachineOperand &MD = MI.getOperand(0);
1106 assert(MD.isReg() && MD.isDef());
1107 RegisterRef RD = MD;
1109 uint16_t W = getRegBitWidth(RD);
1110 assert(W >= BitNum && BitNum > 0);
1111 RegisterCell Res(W);
1113 for (uint16_t i = 0; i < BitNum; ++i)
1114 Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1117 const BT::BitValue &Sign = Res[BitNum-1];
1118 for (uint16_t i = BitNum; i < W; ++i)
1119 Res[i] = BT::BitValue::ref(Sign);
1121 for (uint16_t i = BitNum; i < W; ++i)
1122 Res[i] = BT::BitValue::Zero;
1125 putCell(RD, Res, Outputs);
1129 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1130 const CellMapType &Inputs,
1131 CellMapType &Outputs) const {
1132 // If MI defines a formal parameter, but is not a copy (loads are handled
1133 // in evaluateLoad), then it's not clear what to do.
1134 assert(MI.isCopy());
1136 RegisterRef RD = MI.getOperand(0);
1137 RegisterRef RS = MI.getOperand(1);
1138 assert(RD.Sub == 0);
1139 if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
1141 RegExtMap::const_iterator F = VRX.find(RD.Reg);
1145 uint16_t EW = F->second.Width;
1146 // Store RD's cell into the map. This will associate the cell with a virtual
1147 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1148 // tending "self" bit values, which will have no effect, since "self" values
1149 // cannot be references to anything).
1150 putCell(RD, getCell(RS, Inputs), Outputs);
1153 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1154 if (F->second.Type == ExtType::SExt)
1155 Res = eSXT(getCell(RD, Outputs), EW);
1156 else if (F->second.Type == ExtType::ZExt)
1157 Res = eZXT(getCell(RD, Outputs), EW);
1159 putCell(RD, Res, Outputs);
1163 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1164 using namespace Hexagon;
1166 bool Is64 = DoubleRegsRegClass.contains(PReg);
1167 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1169 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1170 static const unsigned Phys64[] = { D0, D1, D2 };
1171 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1172 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1174 // Return the first parameter register of the required width.
1176 return (Width <= 32) ? Phys32[0] : Phys64[0];
1178 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1180 unsigned Idx32 = 0, Idx64 = 0;
1182 while (Idx32 < Num32) {
1183 if (Phys32[Idx32] == PReg)
1189 while (Idx64 < Num64) {
1190 if (Phys64[Idx64] == PReg)
1198 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1199 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1202 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1203 typedef MachineRegisterInfo::livein_iterator iterator;
1204 for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
1205 if (I->first == PReg)