1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "HexagonBitTracker.h"
11 #include "HexagonInstrInfo.h"
12 #include "HexagonRegisterInfo.h"
13 #include "HexagonSubtarget.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/IR/Argument.h"
21 #include "llvm/IR/Attributes.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
38 using BT = BitTracker;
40 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
41 MachineRegisterInfo &mri,
42 const HexagonInstrInfo &tii,
44 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
45 // Populate the VRX map (VR to extension-type).
46 // Go over all the formal parameters of the function. If a given parameter
47 // P is sign- or zero-extended, locate the virtual register holding that
48 // parameter and create an entry in the VRX map indicating the type of ex-
49 // tension (and the source type).
50 // This is a bit complicated to do accurately, since the memory layout in-
51 // formation is necessary to precisely determine whether an aggregate para-
52 // meter will be passed in a register or in memory. What is given in MRI
53 // is the association between the physical register that is live-in (i.e.
54 // holds an argument), and the virtual register that this value will be
55 // copied into. This, by itself, is not sufficient to map back the virtual
56 // register to a formal parameter from Function (since consecutive live-ins
57 // from MRI may not correspond to consecutive formal parameters from Func-
58 // tion). To avoid the complications with in-memory arguments, only consi-
59 // der the initial sequence of formal parameters that are known to be
60 // passed via registers.
61 unsigned InVirtReg, InPhysReg = 0;
63 for (const Argument &Arg : MF.getFunction().args()) {
64 Type *ATy = Arg.getType();
66 if (ATy->isIntegerTy())
67 Width = ATy->getIntegerBitWidth();
68 else if (ATy->isPointerTy())
70 // If pointer size is not set through target data, it will default to
71 // Module::AnyPointerSize.
72 if (Width == 0 || Width > 64)
74 if (Arg.hasAttribute(Attribute::ByVal))
76 InPhysReg = getNextPhysReg(InPhysReg, Width);
79 InVirtReg = getVirtRegFor(InPhysReg);
82 if (Arg.hasAttribute(Attribute::SExt))
83 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
84 else if (Arg.hasAttribute(Attribute::ZExt))
85 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
89 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
91 return MachineEvaluator::mask(Reg, 0);
92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
93 unsigned ID = RC.getID();
94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
98 case Hexagon::DoubleRegsRegClassID:
99 case Hexagon::HvxWRRegClassID:
100 case Hexagon::HvxVQRRegClassID:
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
107 dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
108 << TRI.getRegClassName(&RC) << '\n';
110 llvm_unreachable("Unexpected register/subregister");
113 uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
114 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
116 using namespace Hexagon;
117 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
118 if (HST.useHVXOps()) {
119 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
121 if (RC.contains(Reg))
122 return TRI.getRegSizeInBits(RC);
124 // Default treatment for other physical registers.
125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
126 return TRI.getRegSizeInBits(*RC);
129 (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
132 const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
133 const TargetRegisterClass &RC, unsigned Idx) const {
138 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
139 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
140 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
141 assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
144 switch (RC.getID()) {
145 case Hexagon::DoubleRegsRegClassID:
146 return Hexagon::IntRegsRegClass;
147 case Hexagon::HvxWRRegClassID:
148 return Hexagon::HvxVRRegClass;
149 case Hexagon::HvxVQRRegClassID:
150 return Hexagon::HvxWRRegClass;
155 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
157 llvm_unreachable("Unimplemented combination of reg class/subreg idx");
163 std::vector<BT::RegisterRef> Vector;
166 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
167 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
168 const MachineOperand &MO = MI.getOperand(i);
170 Vector[i] = BT::RegisterRef(MO);
171 // For indices that don't correspond to registers, the entry will
172 // remain constructed via the default constructor.
176 size_t size() const { return Vector.size(); }
178 const BT::RegisterRef &operator[](unsigned n) const {
179 // The main purpose of this operator is to assert with bad argument.
180 assert(n < Vector.size());
185 } // end anonymous namespace
187 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
188 const CellMapType &Inputs,
189 CellMapType &Outputs) const {
190 using namespace Hexagon;
192 unsigned NumDefs = 0;
194 // Sanity verification: there should not be any defs with subregisters.
195 for (const MachineOperand &MO : MI.operands()) {
196 if (!MO.isReg() || !MO.isDef())
199 assert(MO.getSubReg() == 0);
205 unsigned Opc = MI.getOpcode();
209 // These instructions may be marked as mayLoad, but they are generating
210 // immediate values, so skip them.
215 return evaluateLoad(MI, Inputs, Outputs);
219 // Check COPY instructions that copy formal parameters into virtual
220 // registers. Such parameters can be sign- or zero-extended at the
221 // call site, and we should take advantage of this knowledge. The MRI
222 // keeps a list of pairs of live-in physical and virtual registers,
223 // which provides information about which virtual registers will hold
224 // the argument values. The function will still contain instructions
225 // defining those virtual registers, and in practice those are COPY
226 // instructions from a physical to a virtual register. In such cases,
227 // applying the argument extension to the virtual register can be seen
228 // as simply mirroring the extension that had already been applied to
229 // the physical register at the call site. If the defining instruction
230 // was not a COPY, it would not be clear how to mirror that extension
231 // on the callee's side. For that reason, only check COPY instructions
232 // for potential extensions.
234 if (evaluateFormalCopy(MI, Inputs, Outputs))
238 // Beyond this point, if any operand is a global, skip that instruction.
239 // The reason is that certain instructions that can take an immediate
240 // operand can also have a global symbol in that operand. To avoid
241 // checking what kind of operand a given instruction has individually
242 // for each instruction, do it here. Global symbols as operands gene-
243 // rally do not provide any useful information.
244 for (const MachineOperand &MO : MI.operands()) {
245 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
250 RegisterRefs Reg(MI);
251 #define op(i) MI.getOperand(i)
252 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
253 #define im(i) MI.getOperand(i).getImm()
255 // If the instruction has no register operands, skip it.
259 // Record result for register in operand 0.
260 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
262 putCell(Reg[0], Val, Outputs);
265 // Get the cell corresponding to the N-th operand.
266 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
267 uint16_t W) -> BT::RegisterCell {
268 const MachineOperand &Op = MI.getOperand(N);
270 return eIMM(Op.getImm(), W);
272 return RegisterCell::self(0, W);
273 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
276 // Extract RW low bits of the cell.
277 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
278 -> BT::RegisterCell {
279 assert(RW <= RC.width());
280 return eXTR(RC, 0, RW);
282 // Extract RW high bits of the cell.
283 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
284 -> BT::RegisterCell {
285 uint16_t W = RC.width();
287 return eXTR(RC, W-RW, W);
289 // Extract N-th halfword (counting from the least significant position).
290 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
291 -> BT::RegisterCell {
292 assert(N*16+16 <= RC.width());
293 return eXTR(RC, N*16, N*16+16);
295 // Shuffle bits (pick even/odd from cells and merge into result).
296 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
297 uint16_t BW, bool Odd) -> BT::RegisterCell {
298 uint16_t I = Odd, Ws = Rs.width();
299 assert(Ws == Rt.width());
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
303 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
309 // The bitwidth of the 0th operand. In most (if not all) of the
310 // instructions below, the 0th operand is the defined register.
311 // Pre-compute the bitwidth here, because it is needed in many cases
313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
315 // Register id of the 0th operand. It can be 0.
316 unsigned Reg0 = Reg[0].Reg;
319 // Transfer immediate:
325 return rr0(eIMM(im(1), W0), Outputs);
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
331 int FI = op(1).getIndex();
332 int Off = op(2).getImm();
333 unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
334 unsigned L = countTrailingZeros(A);
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
336 RC.fill(0, L, BT::BitValue::Zero);
337 return rr0(RC, Outputs);
340 // Transfer register:
345 return rr0(rc(1), Outputs);
348 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
350 RegisterCell PC = eXTR(rc(1), 0, PW);
351 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
352 RC.fill(PW, RW, BT::BitValue::Zero);
353 return rr0(RC, Outputs);
357 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
358 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW);
359 RC.fill(PW, RW, BT::BitValue::Zero);
360 return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
371 uint16_t W1 = getRegBitWidth(Reg[1]);
372 assert(W0 == 64 && W1 == 32);
373 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
374 RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
375 return rr0(RC, Outputs);
379 return rr0(eADD(rc(1), rc(2)), Outputs);
381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
382 case S4_addi_asl_ri: {
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
384 return rr0(RC, Outputs);
386 case S4_addi_lsr_ri: {
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
388 return rr0(RC, Outputs);
391 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
392 return rr0(RC, Outputs);
394 case M4_mpyri_addi: {
395 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
396 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
397 return rr0(RC, Outputs);
399 case M4_mpyrr_addi: {
400 RegisterCell M = eMLS(rc(2), rc(3));
401 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
402 return rr0(RC, Outputs);
404 case M4_mpyri_addr_u2: {
405 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
406 RegisterCell RC = eADD(rc(1), lo(M, W0));
407 return rr0(RC, Outputs);
409 case M4_mpyri_addr: {
410 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
411 RegisterCell RC = eADD(rc(1), lo(M, W0));
412 return rr0(RC, Outputs);
414 case M4_mpyrr_addr: {
415 RegisterCell M = eMLS(rc(2), rc(3));
416 RegisterCell RC = eADD(rc(1), lo(M, W0));
417 return rr0(RC, Outputs);
420 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
421 return rr0(RC, Outputs);
424 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
425 return rr0(RC, Outputs);
428 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
429 return rr0(RC, Outputs);
432 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
433 return rr0(RC, Outputs);
435 case S2_addasl_rrri: {
436 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
437 return rr0(RC, Outputs);
440 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
441 RPC.fill(0, 2, BT::BitValue::Zero);
442 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
446 return rr0(eSUB(rc(1), rc(2)), Outputs);
448 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
449 case S4_subi_asl_ri: {
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
451 return rr0(RC, Outputs);
453 case S4_subi_lsr_ri: {
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
455 return rr0(RC, Outputs);
458 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
459 return rr0(RC, Outputs);
462 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
463 return rr0(RC, Outputs);
465 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
467 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
470 RegisterCell M = eMLS(rc(1), rc(2));
471 return rr0(hi(M, W0), Outputs);
474 return rr0(eMLS(rc(1), rc(2)), Outputs);
475 case M2_dpmpyss_acc_s0:
476 return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
477 case M2_dpmpyss_nac_s0:
478 return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
480 RegisterCell M = eMLS(rc(1), rc(2));
481 return rr0(lo(M, W0), Outputs);
484 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
485 RegisterCell RC = eADD(rc(1), lo(M, W0));
486 return rr0(RC, Outputs);
489 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
490 RegisterCell RC = eSUB(rc(1), lo(M, W0));
491 return rr0(RC, Outputs);
494 RegisterCell M = eMLS(rc(2), rc(3));
495 RegisterCell RC = eADD(rc(1), lo(M, W0));
496 return rr0(RC, Outputs);
499 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
500 return rr0(lo(M, 32), Outputs);
503 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
504 return rr0(lo(M, 32), Outputs);
507 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
508 return rr0(lo(M, 32), Outputs);
511 RegisterCell M = eMLU(rc(1), rc(2));
512 return rr0(hi(M, W0), Outputs);
515 return rr0(eMLU(rc(1), rc(2)), Outputs);
516 case M2_dpmpyuu_acc_s0:
517 return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
518 case M2_dpmpyuu_nac_s0:
519 return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
525 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
528 return rr0(eAND(rc(1), rc(2)), Outputs);
531 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
532 case S4_andi_asl_ri: {
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
534 return rr0(RC, Outputs);
536 case S4_andi_lsr_ri: {
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
538 return rr0(RC, Outputs);
541 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
543 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
545 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
547 return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
549 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
552 return rr0(eORL(rc(1), rc(2)), Outputs);
555 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
556 case S4_ori_asl_ri: {
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
558 return rr0(RC, Outputs);
560 case S4_ori_lsr_ri: {
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
562 return rr0(RC, Outputs);
565 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
567 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
570 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
571 return rr0(RC, Outputs);
574 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
575 return rr0(RC, Outputs);
578 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
580 return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
583 return rr0(eXOR(rc(1), rc(2)), Outputs);
585 return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
587 return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
589 return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
591 return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
594 return rr0(eNOT(rc(1)), Outputs);
598 return rr0(eASL(rc(1), im(2)), Outputs);
600 return rr0(eASL(rc(1), 16), Outputs);
603 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
606 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
609 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
612 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
613 case S2_asl_i_r_xacc:
614 case S2_asl_i_p_xacc:
615 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
623 return rr0(eASR(rc(1), im(2)), Outputs);
625 return rr0(eASR(rc(1), 16), Outputs);
628 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
631 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
634 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
637 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
638 case S2_asr_i_r_rnd: {
639 // The input is first sign-extended to 64 bits, then the output
640 // is truncated back to 32 bits.
642 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
643 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
644 return rr0(eXTR(RC, 0, W0), Outputs);
646 case S2_asr_i_r_rnd_goodsyntax: {
649 return rr0(rc(1), Outputs);
650 // Result: S2_asr_i_r_rnd Rs, u5-1
651 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
652 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
653 return rr0(eXTR(RC, 0, W0), Outputs);
657 case S2_asr_i_svw_trun:
663 return rr0(eLSR(rc(1), im(2)), Outputs);
666 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
669 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
672 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
675 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
676 case S2_lsr_i_r_xacc:
677 case S2_lsr_i_p_xacc:
678 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
681 RegisterCell RC = rc(1);
682 RC[im(2)] = BT::BitValue::Zero;
683 return rr0(RC, Outputs);
686 RegisterCell RC = rc(1);
687 RC[im(2)] = BT::BitValue::One;
688 return rr0(RC, Outputs);
690 case S2_togglebit_i: {
691 RegisterCell RC = rc(1);
693 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
694 : RC[BX].is(1) ? BT::BitValue::Zero
695 : BT::BitValue::self();
696 return rr0(RC, Outputs);
700 uint16_t W1 = getRegBitWidth(Reg[1]);
702 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
703 const BT::BitValue Zero = BT::BitValue::Zero;
704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
705 .fill(W1+(W1-BX), W0, Zero);
706 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
707 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
708 return rr0(RC, Outputs);
714 uint16_t Wd = im(2), Of = im(3);
717 return rr0(eIMM(0, W0), Outputs);
718 // If the width extends beyond the register size, pad the register
720 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
721 RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
722 // Ext is short, need to extend it with 0s or sign bit.
723 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
724 if (Opc == S2_extractu || Opc == S2_extractup)
725 return rr0(eZXT(RC, Wd), Outputs);
726 return rr0(eSXT(RC, Wd), Outputs);
730 uint16_t Wd = im(3), Of = im(4);
731 assert(Wd < W0 && Of < W0);
732 // If Wd+Of exceeds W0, the inserted bits are truncated.
736 return rr0(rc(1), Outputs);
737 return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
749 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
753 case A2_combine_hh: {
755 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
756 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
757 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
758 // High half in the output is 0 for _ll and _lh, 1 otherwise:
759 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
760 RegisterCell R1 = rc(1);
761 RegisterCell R2 = rc(2);
762 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
763 return rr0(RC, Outputs);
767 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
768 RegisterCell R1 = rc(1);
769 RegisterCell R2 = rc(2);
770 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
772 return rr0(RC, Outputs);
775 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
776 return rr0(RC, Outputs);
779 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
780 return rr0(RC, Outputs);
783 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
784 return rr0(RC, Outputs);
787 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
788 return rr0(RC, Outputs);
792 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
793 assert(WR == 64 && WP == 8);
794 RegisterCell R1 = rc(1);
796 for (uint16_t i = 0; i < WP; ++i) {
797 const BT::BitValue &V = R1[i];
798 BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
799 RC.fill(i*8, i*8+8, F);
801 return rr0(RC, Outputs);
810 BT::BitValue PC0 = rc(1)[0];
811 RegisterCell R2 = cop(2, W0);
812 RegisterCell R3 = cop(3, W0);
813 if (PC0.is(0) || PC0.is(1))
814 return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
815 R2.meet(R3, Reg[0].Reg);
816 return rr0(R2, Outputs);
822 // Sign- and zero-extension:
825 return rr0(eSXT(rc(1), 8), Outputs);
827 return rr0(eSXT(rc(1), 16), Outputs);
829 uint16_t W1 = getRegBitWidth(Reg[1]);
830 assert(W0 == 64 && W1 == 32);
831 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
832 return rr0(RC, Outputs);
835 return rr0(eZXT(rc(1), 8), Outputs);
837 return rr0(eZXT(rc(1), 16), Outputs);
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
844 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
848 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
854 // Always produce a 32-bit result.
855 return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
858 return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
861 uint16_t W1 = getRegBitWidth(Reg[1]);
862 RegisterCell R1 = rc(1);
863 BT::BitValue TV = R1[W1-1];
864 if (TV.is(0) || TV.is(1))
865 return rr0(eCLB(R1, TV, 32), Outputs);
870 return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
873 return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
879 RegisterCell P1 = rc(1);
880 bool Has0 = false, All1 = true;
881 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
892 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
893 return rr0(RC, Outputs);
896 RegisterCell P1 = rc(1);
897 bool Has1 = false, All0 = true;
898 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
909 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
910 return rr0(RC, Outputs);
913 return rr0(eAND(rc(1), rc(2)), Outputs);
915 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
917 return rr0(eNOT(rc(1)), Outputs);
919 return rr0(eORL(rc(1), rc(2)), Outputs);
921 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
923 return rr0(eXOR(rc(1), rc(2)), Outputs);
925 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
927 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
929 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
931 return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
933 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
935 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
937 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
939 return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
950 BT::BitValue V = rc(1)[im(2)];
951 if (V.is(0) || V.is(1)) {
952 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
953 bool TV = (Opc == S2_tstbit_i);
954 BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
955 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
961 // For instructions that define a single predicate registers, store
962 // the low 8 bits of the register only.
963 if (unsigned DefR = getUniqueDefVReg(MI)) {
964 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
965 BT::RegisterRef PD(DefR, 0);
966 uint16_t RW = getRegBitWidth(PD);
967 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
968 RegisterCell RC = RegisterCell::self(DefR, RW);
969 RC.fill(PW, RW, BT::BitValue::Zero);
970 putCell(PD, RC, Outputs);
974 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
982 bool HexagonEvaluator::evaluate(const MachineInstr &BI,
983 const CellMapType &Inputs,
984 BranchTargetList &Targets,
985 bool &FallsThru) const {
986 // We need to evaluate one branch at a time. TII::analyzeBranch checks
987 // all the branches in a basic block at once, so we cannot use it.
988 unsigned Opc = BI.getOpcode();
989 bool SimpleBranch = false;
990 bool Negated = false;
992 case Hexagon::J2_jumpf:
993 case Hexagon::J2_jumpfpt:
994 case Hexagon::J2_jumpfnew:
995 case Hexagon::J2_jumpfnewpt:
998 case Hexagon::J2_jumpt:
999 case Hexagon::J2_jumptpt:
1000 case Hexagon::J2_jumptnew:
1001 case Hexagon::J2_jumptnewpt:
1002 // Simple branch: if([!]Pn) jump ...
1003 // i.e. Op0 = predicate, Op1 = branch target.
1004 SimpleBranch = true;
1006 case Hexagon::J2_jump:
1007 Targets.insert(BI.getOperand(0).getMBB());
1011 // If the branch is of unknown type, assume that all successors are
1019 // BI is a conditional branch if we got here.
1020 RegisterRef PR = BI.getOperand(0);
1021 RegisterCell PC = getCell(PR, Inputs);
1022 const BT::BitValue &Test = PC[0];
1024 // If the condition is neither true nor false, then it's unknown.
1025 if (!Test.is(0) && !Test.is(1))
1028 // "Test.is(!Negated)" means "branch condition is true".
1029 if (!Test.is(!Negated)) {
1030 // Condition known to be false.
1035 Targets.insert(BI.getOperand(1).getMBB());
1040 unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1041 unsigned DefReg = 0;
1042 for (const MachineOperand &Op : MI.operands()) {
1043 if (!Op.isReg() || !Op.isDef())
1045 unsigned R = Op.getReg();
1046 if (!TargetRegisterInfo::isVirtualRegister(R))
1055 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1056 const CellMapType &Inputs,
1057 CellMapType &Outputs) const {
1058 using namespace Hexagon;
1060 if (TII.isPredicated(MI))
1062 assert(MI.mayLoad() && "A load that mayn't?");
1063 unsigned Opc = MI.getOpcode();
1074 case L2_loadalignb_pbr:
1075 case L2_loadalignb_pcr:
1076 case L2_loadalignb_pi:
1078 case L2_loadalignh_pbr:
1079 case L2_loadalignh_pcr:
1080 case L2_loadalignh_pi:
1082 case L2_loadbsw2_pbr:
1083 case L2_loadbsw2_pci:
1084 case L2_loadbsw2_pcr:
1085 case L2_loadbsw2_pi:
1086 case L2_loadbsw4_pbr:
1087 case L2_loadbsw4_pci:
1088 case L2_loadbsw4_pcr:
1089 case L2_loadbsw4_pi:
1091 case L2_loadbzw2_pbr:
1092 case L2_loadbzw2_pci:
1093 case L2_loadbzw2_pcr:
1094 case L2_loadbzw2_pi:
1095 case L2_loadbzw4_pbr:
1096 case L2_loadbzw4_pci:
1097 case L2_loadbzw4_pcr:
1098 case L2_loadbzw4_pi:
1117 case L2_loadrub_pbr:
1118 case L2_loadrub_pci:
1119 case L2_loadrub_pcr:
1145 case L2_loadruh_pbr:
1146 case L2_loadruh_pci:
1147 case L2_loadruh_pcr:
1163 case L2_loadw_locked:
1179 case L4_loadd_locked:
1189 const MachineOperand &MD = MI.getOperand(0);
1190 assert(MD.isReg() && MD.isDef());
1191 RegisterRef RD = MD;
1193 uint16_t W = getRegBitWidth(RD);
1194 assert(W >= BitNum && BitNum > 0);
1195 RegisterCell Res(W);
1197 for (uint16_t i = 0; i < BitNum; ++i)
1198 Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1201 const BT::BitValue &Sign = Res[BitNum-1];
1202 for (uint16_t i = BitNum; i < W; ++i)
1203 Res[i] = BT::BitValue::ref(Sign);
1205 for (uint16_t i = BitNum; i < W; ++i)
1206 Res[i] = BT::BitValue::Zero;
1209 putCell(RD, Res, Outputs);
1213 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1214 const CellMapType &Inputs,
1215 CellMapType &Outputs) const {
1216 // If MI defines a formal parameter, but is not a copy (loads are handled
1217 // in evaluateLoad), then it's not clear what to do.
1218 assert(MI.isCopy());
1220 RegisterRef RD = MI.getOperand(0);
1221 RegisterRef RS = MI.getOperand(1);
1222 assert(RD.Sub == 0);
1223 if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
1225 RegExtMap::const_iterator F = VRX.find(RD.Reg);
1229 uint16_t EW = F->second.Width;
1230 // Store RD's cell into the map. This will associate the cell with a virtual
1231 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1232 // tending "self" bit values, which will have no effect, since "self" values
1233 // cannot be references to anything).
1234 putCell(RD, getCell(RS, Inputs), Outputs);
1237 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1238 if (F->second.Type == ExtType::SExt)
1239 Res = eSXT(getCell(RD, Outputs), EW);
1240 else if (F->second.Type == ExtType::ZExt)
1241 Res = eZXT(getCell(RD, Outputs), EW);
1243 putCell(RD, Res, Outputs);
1247 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1248 using namespace Hexagon;
1250 bool Is64 = DoubleRegsRegClass.contains(PReg);
1251 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1253 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1254 static const unsigned Phys64[] = { D0, D1, D2 };
1255 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1256 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1258 // Return the first parameter register of the required width.
1260 return (Width <= 32) ? Phys32[0] : Phys64[0];
1262 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1264 unsigned Idx32 = 0, Idx64 = 0;
1266 while (Idx32 < Num32) {
1267 if (Phys32[Idx32] == PReg)
1273 while (Idx64 < Num64) {
1274 if (Phys64[Idx64] == PReg)
1282 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1283 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1286 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1287 for (std::pair<unsigned,unsigned> P : MRI.liveins())
1288 if (P.first == PReg)