1 //===--- HexagonBitTracker.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineRegisterInfo.h"
11 #include "llvm/IR/Module.h"
12 #include "llvm/Support/Debug.h"
13 #include "llvm/Support/raw_ostream.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonBitTracker.h"
23 typedef BitTracker BT;
25 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
26 MachineRegisterInfo &mri,
27 const HexagonInstrInfo &tii,
29 : MachineEvaluator(tri, mri), MF(mf), MFI(*mf.getFrameInfo()), TII(tii) {
30 // Populate the VRX map (VR to extension-type).
31 // Go over all the formal parameters of the function. If a given parameter
32 // P is sign- or zero-extended, locate the virtual register holding that
33 // parameter and create an entry in the VRX map indicating the type of ex-
34 // tension (and the source type).
35 // This is a bit complicated to do accurately, since the memory layout in-
36 // formation is necessary to precisely determine whether an aggregate para-
37 // meter will be passed in a register or in memory. What is given in MRI
38 // is the association between the physical register that is live-in (i.e.
39 // holds an argument), and the virtual register that this value will be
40 // copied into. This, by itself, is not sufficient to map back the virtual
41 // register to a formal parameter from Function (since consecutive live-ins
42 // from MRI may not correspond to consecutive formal parameters from Func-
43 // tion). To avoid the complications with in-memory arguments, only consi-
44 // der the initial sequence of formal parameters that are known to be
45 // passed via registers.
47 unsigned InVirtReg, InPhysReg = 0;
48 const Function &F = *MF.getFunction();
49 typedef Function::const_arg_iterator arg_iterator;
50 for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
52 const Argument &Arg = *I;
53 Type *ATy = Arg.getType();
55 if (ATy->isIntegerTy())
56 Width = ATy->getIntegerBitWidth();
57 else if (ATy->isPointerTy())
59 // If pointer size is not set through target data, it will default to
60 // Module::AnyPointerSize.
61 if (Width == 0 || Width > 64)
63 InPhysReg = getNextPhysReg(InPhysReg, Width);
66 InVirtReg = getVirtRegFor(InPhysReg);
69 AttributeSet Attrs = F.getAttributes();
70 if (Attrs.hasAttribute(AttrIdx, Attribute::SExt))
71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
72 else if (Attrs.hasAttribute(AttrIdx, Attribute::ZExt))
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
78 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
80 return MachineEvaluator::mask(Reg, 0);
81 using namespace Hexagon;
82 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
83 unsigned ID = RC->getID();
84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
86 case DoubleRegsRegClassID:
87 case VecDblRegsRegClassID:
88 case VecDblRegs128BRegClassID:
89 return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
90 : BT::BitMask(RW, 2*RW-1);
95 dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
97 llvm_unreachable("Unexpected register/subregister");
102 std::vector<BT::RegisterRef> Vector;
105 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
106 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
107 const MachineOperand &MO = MI.getOperand(i);
109 Vector[i] = BT::RegisterRef(MO);
110 // For indices that don't correspond to registers, the entry will
111 // remain constructed via the default constructor.
115 size_t size() const { return Vector.size(); }
116 const BT::RegisterRef &operator[](unsigned n) const {
117 // The main purpose of this operator is to assert with bad argument.
118 assert(n < Vector.size());
124 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
125 const CellMapType &Inputs,
126 CellMapType &Outputs) const {
127 unsigned NumDefs = 0;
129 // Sanity verification: there should not be any defs with subregisters.
130 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
131 const MachineOperand &MO = MI.getOperand(i);
132 if (!MO.isReg() || !MO.isDef())
135 assert(MO.getSubReg() == 0);
142 return evaluateLoad(MI, Inputs, Outputs);
144 // Check COPY instructions that copy formal parameters into virtual
145 // registers. Such parameters can be sign- or zero-extended at the
146 // call site, and we should take advantage of this knowledge. The MRI
147 // keeps a list of pairs of live-in physical and virtual registers,
148 // which provides information about which virtual registers will hold
149 // the argument values. The function will still contain instructions
150 // defining those virtual registers, and in practice those are COPY
151 // instructions from a physical to a virtual register. In such cases,
152 // applying the argument extension to the virtual register can be seen
153 // as simply mirroring the extension that had already been applied to
154 // the physical register at the call site. If the defining instruction
155 // was not a COPY, it would not be clear how to mirror that extension
156 // on the callee's side. For that reason, only check COPY instructions
157 // for potential extensions.
159 if (evaluateFormalCopy(MI, Inputs, Outputs))
163 // Beyond this point, if any operand is a global, skip that instruction.
164 // The reason is that certain instructions that can take an immediate
165 // operand can also have a global symbol in that operand. To avoid
166 // checking what kind of operand a given instruction has individually
167 // for each instruction, do it here. Global symbols as operands gene-
168 // rally do not provide any useful information.
169 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
170 const MachineOperand &MO = MI.getOperand(i);
171 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
176 RegisterRefs Reg(MI);
177 unsigned Opc = MI.getOpcode();
178 using namespace Hexagon;
179 #define op(i) MI.getOperand(i)
180 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
181 #define im(i) MI.getOperand(i).getImm()
183 // If the instruction has no register operands, skip it.
187 // Record result for register in operand 0.
188 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
190 putCell(Reg[0], Val, Outputs);
193 // Get the cell corresponding to the N-th operand.
194 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
195 uint16_t W) -> BT::RegisterCell {
196 const MachineOperand &Op = MI.getOperand(N);
198 return eIMM(Op.getImm(), W);
200 return RegisterCell::self(0, W);
201 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
204 // Extract RW low bits of the cell.
205 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
206 -> BT::RegisterCell {
207 assert(RW <= RC.width());
208 return eXTR(RC, 0, RW);
210 // Extract RW high bits of the cell.
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
212 -> BT::RegisterCell {
213 uint16_t W = RC.width();
215 return eXTR(RC, W-RW, W);
217 // Extract N-th halfword (counting from the least significant position).
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
219 -> BT::RegisterCell {
220 assert(N*16+16 <= RC.width());
221 return eXTR(RC, N*16, N*16+16);
223 // Shuffle bits (pick even/odd from cells and merge into result).
224 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
225 uint16_t BW, bool Odd) -> BT::RegisterCell {
226 uint16_t I = Odd, Ws = Rs.width();
227 assert(Ws == Rt.width());
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
231 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
237 // The bitwidth of the 0th operand. In most (if not all) of the
238 // instructions below, the 0th operand is the defined register.
239 // Pre-compute the bitwidth here, because it is needed in many cases
241 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
244 // Transfer immediate:
249 case CONST32_Float_Real:
250 case CONST32_Int_Real:
251 case CONST64_Float_Real:
252 case CONST64_Int_Real:
253 return rr0(eIMM(im(1), W0), Outputs);
255 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
257 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
259 int FI = op(1).getIndex();
260 int Off = op(2).getImm();
261 unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
262 unsigned L = Log2_32(A);
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
264 RC.fill(0, L, BT::BitValue::Zero);
265 return rr0(RC, Outputs);
268 // Transfer register:
273 return rr0(rc(1), Outputs);
276 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
278 RegisterCell PC = eXTR(rc(1), 0, PW);
279 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
280 RC.fill(PW, RW, BT::BitValue::Zero);
281 return rr0(RC, Outputs);
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
285 W0 = 8; // XXX Pred size
286 return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
297 uint16_t W1 = getRegBitWidth(Reg[1]);
298 assert(W0 == 64 && W1 == 32);
299 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
300 RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
301 return rr0(RC, Outputs);
305 return rr0(eADD(rc(1), rc(2)), Outputs);
307 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
308 case S4_addi_asl_ri: {
309 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
310 return rr0(RC, Outputs);
312 case S4_addi_lsr_ri: {
313 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
314 return rr0(RC, Outputs);
317 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
318 return rr0(RC, Outputs);
320 case M4_mpyri_addi: {
321 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
322 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
323 return rr0(RC, Outputs);
325 case M4_mpyrr_addi: {
326 RegisterCell M = eMLS(rc(2), rc(3));
327 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
328 return rr0(RC, Outputs);
330 case M4_mpyri_addr_u2: {
331 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
332 RegisterCell RC = eADD(rc(1), lo(M, W0));
333 return rr0(RC, Outputs);
335 case M4_mpyri_addr: {
336 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
337 RegisterCell RC = eADD(rc(1), lo(M, W0));
338 return rr0(RC, Outputs);
340 case M4_mpyrr_addr: {
341 RegisterCell M = eMLS(rc(2), rc(3));
342 RegisterCell RC = eADD(rc(1), lo(M, W0));
343 return rr0(RC, Outputs);
346 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
347 return rr0(RC, Outputs);
350 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
351 return rr0(RC, Outputs);
354 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
355 return rr0(RC, Outputs);
358 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
359 return rr0(RC, Outputs);
361 case S2_addasl_rrri: {
362 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
363 return rr0(RC, Outputs);
366 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
367 RPC.fill(0, 2, BT::BitValue::Zero);
368 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
372 return rr0(eSUB(rc(1), rc(2)), Outputs);
374 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
375 case S4_subi_asl_ri: {
376 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
377 return rr0(RC, Outputs);
379 case S4_subi_lsr_ri: {
380 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
381 return rr0(RC, Outputs);
384 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
385 return rr0(RC, Outputs);
388 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
389 return rr0(RC, Outputs);
391 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
393 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
396 RegisterCell M = eMLS(rc(1), rc(2));
397 return rr0(hi(M, W0), Outputs);
400 return rr0(eMLS(rc(1), rc(2)), Outputs);
401 case M2_dpmpyss_acc_s0:
402 return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
403 case M2_dpmpyss_nac_s0:
404 return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
406 RegisterCell M = eMLS(rc(1), rc(2));
407 return rr0(lo(M, W0), Outputs);
410 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
411 RegisterCell RC = eADD(rc(1), lo(M, W0));
412 return rr0(RC, Outputs);
415 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
416 RegisterCell RC = eSUB(rc(1), lo(M, W0));
417 return rr0(RC, Outputs);
420 RegisterCell M = eMLS(rc(2), rc(3));
421 RegisterCell RC = eADD(rc(1), lo(M, W0));
422 return rr0(RC, Outputs);
425 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
426 return rr0(lo(M, 32), Outputs);
429 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
430 return rr0(lo(M, 32), Outputs);
433 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
434 return rr0(lo(M, 32), Outputs);
437 RegisterCell M = eMLU(rc(1), rc(2));
438 return rr0(hi(M, W0), Outputs);
441 return rr0(eMLU(rc(1), rc(2)), Outputs);
442 case M2_dpmpyuu_acc_s0:
443 return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
444 case M2_dpmpyuu_nac_s0:
445 return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
451 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
454 return rr0(eAND(rc(1), rc(2)), Outputs);
457 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
458 case S4_andi_asl_ri: {
459 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
460 return rr0(RC, Outputs);
462 case S4_andi_lsr_ri: {
463 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
464 return rr0(RC, Outputs);
467 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
469 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
471 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
473 return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
475 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
478 return rr0(eORL(rc(1), rc(2)), Outputs);
481 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
482 case S4_ori_asl_ri: {
483 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
484 return rr0(RC, Outputs);
486 case S4_ori_lsr_ri: {
487 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
488 return rr0(RC, Outputs);
491 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
493 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
496 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
497 return rr0(RC, Outputs);
500 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
501 return rr0(RC, Outputs);
504 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
506 return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
509 return rr0(eXOR(rc(1), rc(2)), Outputs);
511 return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
513 return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
515 return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
517 return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
520 return rr0(eNOT(rc(1)), Outputs);
524 return rr0(eASL(rc(1), im(2)), Outputs);
526 return rr0(eASL(rc(1), 16), Outputs);
529 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
532 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
535 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
538 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
539 case S2_asl_i_r_xacc:
540 case S2_asl_i_p_xacc:
541 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
549 return rr0(eASR(rc(1), im(2)), Outputs);
551 return rr0(eASR(rc(1), 16), Outputs);
554 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
557 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
560 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
563 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
564 case S2_asr_i_r_rnd: {
565 // The input is first sign-extended to 64 bits, then the output
566 // is truncated back to 32 bits.
568 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
569 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
570 return rr0(eXTR(RC, 0, W0), Outputs);
572 case S2_asr_i_r_rnd_goodsyntax: {
575 return rr0(rc(1), Outputs);
576 // Result: S2_asr_i_r_rnd Rs, u5-1
577 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
578 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
579 return rr0(eXTR(RC, 0, W0), Outputs);
583 case S2_asr_i_svw_trun:
589 return rr0(eLSR(rc(1), im(2)), Outputs);
592 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
595 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
598 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
601 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
602 case S2_lsr_i_r_xacc:
603 case S2_lsr_i_p_xacc:
604 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
607 RegisterCell RC = rc(1);
608 RC[im(2)] = BT::BitValue::Zero;
609 return rr0(RC, Outputs);
612 RegisterCell RC = rc(1);
613 RC[im(2)] = BT::BitValue::One;
614 return rr0(RC, Outputs);
616 case S2_togglebit_i: {
617 RegisterCell RC = rc(1);
619 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
620 : RC[BX].is(1) ? BT::BitValue::Zero
621 : BT::BitValue::self();
622 return rr0(RC, Outputs);
626 uint16_t W1 = getRegBitWidth(Reg[1]);
628 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
629 const BT::BitValue Zero = BT::BitValue::Zero;
630 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
631 .fill(W1+(W1-BX), W0, Zero);
632 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
633 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
634 return rr0(RC, Outputs);
640 uint16_t Wd = im(2), Of = im(3);
643 return rr0(eIMM(0, W0), Outputs);
644 // If the width extends beyond the register size, pad the register
646 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
647 RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
648 // Ext is short, need to extend it with 0s or sign bit.
649 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
650 if (Opc == S2_extractu || Opc == S2_extractup)
651 return rr0(eZXT(RC, Wd), Outputs);
652 return rr0(eSXT(RC, Wd), Outputs);
656 uint16_t Wd = im(3), Of = im(4);
657 assert(Wd < W0 && Of < W0);
658 // If Wd+Of exceeds W0, the inserted bits are truncated.
662 return rr0(rc(1), Outputs);
663 return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
674 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
678 case A2_combine_hh: {
680 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
681 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
682 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
683 // High half in the output is 0 for _ll and _lh, 1 otherwise:
684 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
685 RegisterCell R1 = rc(1);
686 RegisterCell R2 = rc(2);
687 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
688 return rr0(RC, Outputs);
692 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
693 RegisterCell R1 = rc(1);
694 RegisterCell R2 = rc(2);
695 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
697 return rr0(RC, Outputs);
700 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
701 return rr0(RC, Outputs);
704 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
705 return rr0(RC, Outputs);
708 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
709 return rr0(RC, Outputs);
712 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
713 return rr0(RC, Outputs);
717 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
718 assert(WR == 64 && WP == 8);
719 RegisterCell R1 = rc(1);
721 for (uint16_t i = 0; i < WP; ++i) {
722 const BT::BitValue &V = R1[i];
723 BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
724 RC.fill(i*8, i*8+8, F);
726 return rr0(RC, Outputs);
735 BT::BitValue PC0 = rc(1)[0];
736 RegisterCell R2 = cop(2, W0);
737 RegisterCell R3 = cop(3, W0);
738 if (PC0.is(0) || PC0.is(1))
739 return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
740 R2.meet(R3, Reg[0].Reg);
741 return rr0(R2, Outputs);
747 // Sign- and zero-extension:
750 return rr0(eSXT(rc(1), 8), Outputs);
752 return rr0(eSXT(rc(1), 16), Outputs);
754 uint16_t W1 = getRegBitWidth(Reg[1]);
755 assert(W0 == 64 && W1 == 32);
756 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
757 return rr0(RC, Outputs);
760 return rr0(eZXT(rc(1), 8), Outputs);
762 return rr0(eZXT(rc(1), 16), Outputs);
768 // Always produce a 32-bit result.
769 return rr0(eCLB(rc(1), 0/*bit*/, 32), Outputs);
772 return rr0(eCLB(rc(1), 1/*bit*/, 32), Outputs);
775 uint16_t W1 = getRegBitWidth(Reg[1]);
776 RegisterCell R1 = rc(1);
777 BT::BitValue TV = R1[W1-1];
778 if (TV.is(0) || TV.is(1))
779 return rr0(eCLB(R1, TV, 32), Outputs);
784 return rr0(eCTB(rc(1), 0/*bit*/, 32), Outputs);
787 return rr0(eCTB(rc(1), 1/*bit*/, 32), Outputs);
793 RegisterCell P1 = rc(1);
794 bool Has0 = false, All1 = true;
795 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
806 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
807 return rr0(RC, Outputs);
810 RegisterCell P1 = rc(1);
811 bool Has1 = false, All0 = true;
812 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
823 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
824 return rr0(RC, Outputs);
827 return rr0(eAND(rc(1), rc(2)), Outputs);
829 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
831 return rr0(eNOT(rc(1)), Outputs);
833 return rr0(eORL(rc(1), rc(2)), Outputs);
835 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
837 return rr0(eXOR(rc(1), rc(2)), Outputs);
839 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
841 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
843 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
845 return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
847 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
849 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
851 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
853 return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
864 BT::BitValue V = rc(1)[im(2)];
865 if (V.is(0) || V.is(1)) {
866 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
867 bool TV = (Opc == S2_tstbit_i);
868 BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
869 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
875 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
883 bool HexagonEvaluator::evaluate(const MachineInstr &BI,
884 const CellMapType &Inputs,
885 BranchTargetList &Targets,
886 bool &FallsThru) const {
887 // We need to evaluate one branch at a time. TII::AnalyzeBranch checks
888 // all the branches in a basic block at once, so we cannot use it.
889 unsigned Opc = BI.getOpcode();
890 bool SimpleBranch = false;
891 bool Negated = false;
893 case Hexagon::J2_jumpf:
894 case Hexagon::J2_jumpfnew:
895 case Hexagon::J2_jumpfnewpt:
897 case Hexagon::J2_jumpt:
898 case Hexagon::J2_jumptnew:
899 case Hexagon::J2_jumptnewpt:
900 // Simple branch: if([!]Pn) jump ...
901 // i.e. Op0 = predicate, Op1 = branch target.
904 case Hexagon::J2_jump:
905 Targets.insert(BI.getOperand(0).getMBB());
909 // If the branch is of unknown type, assume that all successors are
917 // BI is a conditional branch if we got here.
918 RegisterRef PR = BI.getOperand(0);
919 RegisterCell PC = getCell(PR, Inputs);
920 const BT::BitValue &Test = PC[0];
922 // If the condition is neither true nor false, then it's unknown.
923 if (!Test.is(0) && !Test.is(1))
926 // "Test.is(!Negated)" means "branch condition is true".
927 if (!Test.is(!Negated)) {
928 // Condition known to be false.
933 Targets.insert(BI.getOperand(1).getMBB());
938 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
939 const CellMapType &Inputs,
940 CellMapType &Outputs) const {
941 if (TII.isPredicated(MI))
943 assert(MI.mayLoad() && "A load that mayn't?");
944 unsigned Opc = MI.getOpcode();
948 using namespace Hexagon;
956 case L2_loadalignb_pbr:
957 case L2_loadalignb_pcr:
958 case L2_loadalignb_pi:
960 case L2_loadalignh_pbr:
961 case L2_loadalignh_pcr:
962 case L2_loadalignh_pi:
964 case L2_loadbsw2_pbr:
965 case L2_loadbsw2_pci:
966 case L2_loadbsw2_pcr:
968 case L2_loadbsw4_pbr:
969 case L2_loadbsw4_pci:
970 case L2_loadbsw4_pcr:
973 case L2_loadbzw2_pbr:
974 case L2_loadbzw2_pci:
975 case L2_loadbzw2_pcr:
977 case L2_loadbzw4_pbr:
978 case L2_loadbzw4_pci:
979 case L2_loadbzw4_pcr:
1000 case L2_loadrub_pci:
1001 case L2_loadrub_pcr:
1003 case L4_loadrub_abs:
1027 case L2_loadruh_pbr:
1028 case L2_loadruh_pci:
1029 case L2_loadruh_pcr:
1032 case L4_loadruh_abs:
1045 case L2_loadw_locked:
1061 case L4_loadd_locked:
1071 const MachineOperand &MD = MI.getOperand(0);
1072 assert(MD.isReg() && MD.isDef());
1073 RegisterRef RD = MD;
1075 uint16_t W = getRegBitWidth(RD);
1076 assert(W >= BitNum && BitNum > 0);
1077 RegisterCell Res(W);
1079 for (uint16_t i = 0; i < BitNum; ++i)
1080 Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1083 const BT::BitValue &Sign = Res[BitNum-1];
1084 for (uint16_t i = BitNum; i < W; ++i)
1085 Res[i] = BT::BitValue::ref(Sign);
1087 for (uint16_t i = BitNum; i < W; ++i)
1088 Res[i] = BT::BitValue::Zero;
1091 putCell(RD, Res, Outputs);
1095 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1096 const CellMapType &Inputs,
1097 CellMapType &Outputs) const {
1098 // If MI defines a formal parameter, but is not a copy (loads are handled
1099 // in evaluateLoad), then it's not clear what to do.
1100 assert(MI.isCopy());
1102 RegisterRef RD = MI.getOperand(0);
1103 RegisterRef RS = MI.getOperand(1);
1104 assert(RD.Sub == 0);
1105 if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
1107 RegExtMap::const_iterator F = VRX.find(RD.Reg);
1111 uint16_t EW = F->second.Width;
1112 // Store RD's cell into the map. This will associate the cell with a virtual
1113 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1114 // tending "self" bit values, which will have no effect, since "self" values
1115 // cannot be references to anything).
1116 putCell(RD, getCell(RS, Inputs), Outputs);
1119 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1120 if (F->second.Type == ExtType::SExt)
1121 Res = eSXT(getCell(RD, Outputs), EW);
1122 else if (F->second.Type == ExtType::ZExt)
1123 Res = eZXT(getCell(RD, Outputs), EW);
1125 putCell(RD, Res, Outputs);
1130 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1131 using namespace Hexagon;
1132 bool Is64 = DoubleRegsRegClass.contains(PReg);
1133 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1135 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1136 static const unsigned Phys64[] = { D0, D1, D2 };
1137 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1138 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1140 // Return the first parameter register of the required width.
1142 return (Width <= 32) ? Phys32[0] : Phys64[0];
1144 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1146 unsigned Idx32 = 0, Idx64 = 0;
1148 while (Idx32 < Num32) {
1149 if (Phys32[Idx32] == PReg)
1155 while (Idx64 < Num64) {
1156 if (Phys64[Idx64] == PReg)
1164 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1165 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1169 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1170 typedef MachineRegisterInfo::livein_iterator iterator;
1171 for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
1172 if (I->first == PReg)