1 //===- HexagonCallingConv.td ----------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class CCIfArgIsVarArg<CCAction A>
11 : CCIf<"State.isVarArg() && "
12 "ValNo >= static_cast<HexagonCCState&>(State)"
13 ".getNumNamedVarArgParams()", A>;
15 def CC_HexagonStack: CallingConv<[
16 CCIfType<[i32,v2i16,v4i8],
17 CCAssignToStack<4,4>>,
18 CCIfType<[i64,v2i32,v4i16,v8i8],
22 def CC_Hexagon: CallingConv<[
24 CCPromoteToType<i32>>,
26 CCBitConvertToType<i32>>,
28 CCBitConvertToType<i64>>,
33 CCDelegateTo<CC_HexagonStack>>,
35 // Pass split values in pairs, allocate odd register if necessary.
38 CCCustom<"CC_SkipOdd">>>,
40 CCIfType<[i32,v2i16,v4i8],
41 CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>,
42 // Make sure to allocate any skipped 32-bit register, so it does not get
43 // allocated to a subsequent 32-bit value.
44 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCCustom<"CC_SkipOdd">>,
46 CCIfType<[i64,v2i32,v4i16,v8i8],
47 CCAssignToReg<[D0,D1,D2]>>,
49 CCDelegateTo<CC_HexagonStack>
52 def RetCC_Hexagon: CallingConv<[
54 CCPromoteToType<i32>>,
56 CCBitConvertToType<i32>>,
58 CCBitConvertToType<i64>>,
60 // Small structures are returned in a pair of registers, (which is
61 // always r1:0). In such case, what is returned are two i32 values
62 // without any additional information (in ArgFlags) stating that
63 // they are parts of a structure. Because of that there is no way
64 // to differentiate that situation from an attempt to return two
65 // values, so always assign R0 and R1.
67 CCAssignToReg<[R0,R1]>>,
68 CCIfType<[i32,v2i16,v4i8],
69 CCAssignToReg<[R0,R1]>>,
70 CCIfType<[i64,v2i32,v4i16,v8i8],
75 class CCIfHvx64<CCAction A>
76 : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
77 ".useHVX64BOps()", A>;
79 class CCIfHvx128<CCAction A>
80 : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
81 ".useHVX128BOps()", A>;
83 def CC_Hexagon_HVX: CallingConv<[
86 CCIfType<[v16i32,v32i16,v64i8],
87 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
89 CCIfType<[v32i32,v64i16,v128i8],
90 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
92 CCIfType<[v16i32,v32i16,v64i8],
93 CCAssignToStack<64,64>>>,
95 CCIfType<[v32i32,v64i16,v128i8],
96 CCAssignToStack<128,64>>>,
100 CCIfType<[v32i32,v64i16,v128i8],
101 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
103 CCIfType<[v64i32,v128i16,v256i8],
104 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
106 CCIfType<[v32i32,v64i16,v128i8],
107 CCAssignToStack<128,128>>>,
109 CCIfType<[v64i32,v128i16,v256i8],
110 CCAssignToStack<256,128>>>,
112 CCDelegateTo<CC_Hexagon>
115 def RetCC_Hexagon_HVX: CallingConv<[
118 CCIfType<[v16i32,v32i16,v64i8],
119 CCAssignToReg<[V0]>>>,
121 CCIfType<[v32i32,v64i16,v128i8],
122 CCAssignToReg<[W0]>>>,
126 CCIfType<[v32i32,v64i16,v128i8],
127 CCAssignToReg<[V0]>>>,
129 CCIfType<[v64i32,v128i16,v256i8],
130 CCAssignToReg<[W0]>>>,
132 CCDelegateTo<RetCC_Hexagon>