1 //===- HexagonDepInstrInfo.td ---------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Automatically generated file, please consult code owner before editing.
10 //===----------------------------------------------------------------------===//
17 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
18 let Inst{13-5} = 0b000000100;
19 let Inst{31-21} = 0b10001100100;
25 (outs DoubleRegs:$Rdd32),
26 (ins DoubleRegs:$Rss32),
27 "$Rdd32 = abs($Rss32)",
28 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
29 let Inst{13-5} = 0b000000110;
30 let Inst{31-21} = 0b10000000100;
33 def A2_abssat : HInst<
36 "$Rd32 = abs($Rs32):sat",
37 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
38 let Inst{13-5} = 0b000000101;
39 let Inst{31-21} = 0b10001100100;
47 (ins IntRegs:$Rs32, IntRegs:$Rt32),
48 "$Rd32 = add($Rs32,$Rt32)",
49 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
50 let Inst{7-5} = 0b000;
51 let Inst{13-13} = 0b0;
52 let Inst{31-21} = 0b11110011000;
55 let CextOpcode = "A2_add";
56 let InputType = "reg";
57 let BaseOpcode = "A2_add";
61 def A2_addh_h16_hh : HInst<
63 (ins IntRegs:$Rt32, IntRegs:$Rs32),
64 "$Rd32 = add($Rt32.h,$Rs32.h):<<16",
65 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
66 let Inst{7-5} = 0b011;
67 let Inst{13-13} = 0b0;
68 let Inst{31-21} = 0b11010101010;
73 def A2_addh_h16_hl : HInst<
75 (ins IntRegs:$Rt32, IntRegs:$Rs32),
76 "$Rd32 = add($Rt32.h,$Rs32.l):<<16",
77 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
78 let Inst{7-5} = 0b010;
79 let Inst{13-13} = 0b0;
80 let Inst{31-21} = 0b11010101010;
85 def A2_addh_h16_lh : HInst<
87 (ins IntRegs:$Rt32, IntRegs:$Rs32),
88 "$Rd32 = add($Rt32.l,$Rs32.h):<<16",
89 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
90 let Inst{7-5} = 0b001;
91 let Inst{13-13} = 0b0;
92 let Inst{31-21} = 0b11010101010;
97 def A2_addh_h16_ll : HInst<
99 (ins IntRegs:$Rt32, IntRegs:$Rs32),
100 "$Rd32 = add($Rt32.l,$Rs32.l):<<16",
101 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
102 let Inst{7-5} = 0b000;
103 let Inst{13-13} = 0b0;
104 let Inst{31-21} = 0b11010101010;
107 let prefersSlot3 = 1;
109 def A2_addh_h16_sat_hh : HInst<
110 (outs IntRegs:$Rd32),
111 (ins IntRegs:$Rt32, IntRegs:$Rs32),
112 "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
113 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
114 let Inst{7-5} = 0b111;
115 let Inst{13-13} = 0b0;
116 let Inst{31-21} = 0b11010101010;
119 let prefersSlot3 = 1;
120 let Defs = [USR_OVF];
122 def A2_addh_h16_sat_hl : HInst<
123 (outs IntRegs:$Rd32),
124 (ins IntRegs:$Rt32, IntRegs:$Rs32),
125 "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
126 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
127 let Inst{7-5} = 0b110;
128 let Inst{13-13} = 0b0;
129 let Inst{31-21} = 0b11010101010;
132 let prefersSlot3 = 1;
133 let Defs = [USR_OVF];
135 def A2_addh_h16_sat_lh : HInst<
136 (outs IntRegs:$Rd32),
137 (ins IntRegs:$Rt32, IntRegs:$Rs32),
138 "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
139 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
140 let Inst{7-5} = 0b101;
141 let Inst{13-13} = 0b0;
142 let Inst{31-21} = 0b11010101010;
145 let prefersSlot3 = 1;
146 let Defs = [USR_OVF];
148 def A2_addh_h16_sat_ll : HInst<
149 (outs IntRegs:$Rd32),
150 (ins IntRegs:$Rt32, IntRegs:$Rs32),
151 "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
152 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
153 let Inst{7-5} = 0b100;
154 let Inst{13-13} = 0b0;
155 let Inst{31-21} = 0b11010101010;
158 let prefersSlot3 = 1;
159 let Defs = [USR_OVF];
161 def A2_addh_l16_hl : HInst<
162 (outs IntRegs:$Rd32),
163 (ins IntRegs:$Rt32, IntRegs:$Rs32),
164 "$Rd32 = add($Rt32.l,$Rs32.h)",
165 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
166 let Inst{7-5} = 0b010;
167 let Inst{13-13} = 0b0;
168 let Inst{31-21} = 0b11010101000;
171 let prefersSlot3 = 1;
173 def A2_addh_l16_ll : HInst<
174 (outs IntRegs:$Rd32),
175 (ins IntRegs:$Rt32, IntRegs:$Rs32),
176 "$Rd32 = add($Rt32.l,$Rs32.l)",
177 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
178 let Inst{7-5} = 0b000;
179 let Inst{13-13} = 0b0;
180 let Inst{31-21} = 0b11010101000;
183 let prefersSlot3 = 1;
185 def A2_addh_l16_sat_hl : HInst<
186 (outs IntRegs:$Rd32),
187 (ins IntRegs:$Rt32, IntRegs:$Rs32),
188 "$Rd32 = add($Rt32.l,$Rs32.h):sat",
189 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
190 let Inst{7-5} = 0b110;
191 let Inst{13-13} = 0b0;
192 let Inst{31-21} = 0b11010101000;
195 let prefersSlot3 = 1;
196 let Defs = [USR_OVF];
198 def A2_addh_l16_sat_ll : HInst<
199 (outs IntRegs:$Rd32),
200 (ins IntRegs:$Rt32, IntRegs:$Rs32),
201 "$Rd32 = add($Rt32.l,$Rs32.l):sat",
202 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
203 let Inst{7-5} = 0b100;
204 let Inst{13-13} = 0b0;
205 let Inst{31-21} = 0b11010101000;
208 let prefersSlot3 = 1;
209 let Defs = [USR_OVF];
212 (outs IntRegs:$Rd32),
213 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
214 "$Rd32 = add($Rs32,#$Ii)",
215 tc_b9488031, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
216 let Inst{31-28} = 0b1011;
219 let CextOpcode = "A2_add";
220 let InputType = "imm";
221 let BaseOpcode = "A2_addi";
222 let isPredicable = 1;
224 let isExtendable = 1;
225 let opExtendable = 2;
226 let isExtentSigned = 1;
227 let opExtentBits = 16;
228 let opExtentAlign = 0;
231 (outs DoubleRegs:$Rdd32),
232 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
233 "$Rdd32 = add($Rss32,$Rtt32)",
234 tc_540fdfbc, TypeALU64>, Enc_a56825 {
235 let Inst{7-5} = 0b111;
236 let Inst{13-13} = 0b0;
237 let Inst{31-21} = 0b11010011000;
238 let isCommutable = 1;
241 def A2_addpsat : HInst<
242 (outs DoubleRegs:$Rdd32),
243 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
244 "$Rdd32 = add($Rss32,$Rtt32):sat",
245 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
246 let Inst{7-5} = 0b101;
247 let Inst{13-13} = 0b0;
248 let Inst{31-21} = 0b11010011011;
249 let prefersSlot3 = 1;
250 let Defs = [USR_OVF];
251 let isCommutable = 1;
253 def A2_addsat : HInst<
254 (outs IntRegs:$Rd32),
255 (ins IntRegs:$Rs32, IntRegs:$Rt32),
256 "$Rd32 = add($Rs32,$Rt32):sat",
257 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
258 let Inst{7-5} = 0b000;
259 let Inst{13-13} = 0b0;
260 let Inst{31-21} = 0b11110110010;
263 let prefersSlot3 = 1;
264 let Defs = [USR_OVF];
265 let InputType = "reg";
266 let isCommutable = 1;
268 def A2_addsp : HInst<
269 (outs DoubleRegs:$Rdd32),
270 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
271 "$Rdd32 = add($Rs32,$Rtt32)",
272 tc_897d1a9d, TypeALU64> {
275 def A2_addsph : HInst<
276 (outs DoubleRegs:$Rdd32),
277 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
278 "$Rdd32 = add($Rss32,$Rtt32):raw:hi",
279 tc_897d1a9d, TypeALU64>, Enc_a56825 {
280 let Inst{7-5} = 0b111;
281 let Inst{13-13} = 0b0;
282 let Inst{31-21} = 0b11010011011;
283 let prefersSlot3 = 1;
285 def A2_addspl : HInst<
286 (outs DoubleRegs:$Rdd32),
287 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
288 "$Rdd32 = add($Rss32,$Rtt32):raw:lo",
289 tc_897d1a9d, TypeALU64>, Enc_a56825 {
290 let Inst{7-5} = 0b110;
291 let Inst{13-13} = 0b0;
292 let Inst{31-21} = 0b11010011011;
293 let prefersSlot3 = 1;
296 (outs IntRegs:$Rd32),
297 (ins IntRegs:$Rs32, IntRegs:$Rt32),
298 "$Rd32 = and($Rs32,$Rt32)",
299 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
300 let Inst{7-5} = 0b000;
301 let Inst{13-13} = 0b0;
302 let Inst{31-21} = 0b11110001000;
305 let CextOpcode = "A2_and";
306 let InputType = "reg";
307 let BaseOpcode = "A2_and";
308 let isCommutable = 1;
309 let isPredicable = 1;
311 def A2_andir : HInst<
312 (outs IntRegs:$Rd32),
313 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
314 "$Rd32 = and($Rs32,#$Ii)",
315 tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
316 let Inst{31-22} = 0b0111011000;
319 let CextOpcode = "A2_and";
320 let InputType = "imm";
321 let isExtendable = 1;
322 let opExtendable = 2;
323 let isExtentSigned = 1;
324 let opExtentBits = 10;
325 let opExtentAlign = 0;
328 (outs DoubleRegs:$Rdd32),
329 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
330 "$Rdd32 = and($Rss32,$Rtt32)",
331 tc_540fdfbc, TypeALU64>, Enc_a56825 {
332 let Inst{7-5} = 0b000;
333 let Inst{13-13} = 0b0;
334 let Inst{31-21} = 0b11010011111;
335 let isCommutable = 1;
338 (outs IntRegs:$Rd32),
340 "$Rd32 = aslh($Rs32)",
341 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
342 let Inst{13-5} = 0b000000000;
343 let Inst{31-21} = 0b01110000000;
346 let BaseOpcode = "A2_aslh";
347 let isPredicable = 1;
350 (outs IntRegs:$Rd32),
352 "$Rd32 = asrh($Rs32)",
353 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
354 let Inst{13-5} = 0b000000000;
355 let Inst{31-21} = 0b01110000001;
358 let BaseOpcode = "A2_asrh";
359 let isPredicable = 1;
361 def A2_combine_hh : HInst<
362 (outs IntRegs:$Rd32),
363 (ins IntRegs:$Rt32, IntRegs:$Rs32),
364 "$Rd32 = combine($Rt32.h,$Rs32.h)",
365 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
366 let Inst{7-5} = 0b000;
367 let Inst{13-13} = 0b0;
368 let Inst{31-21} = 0b11110011100;
371 let InputType = "reg";
373 def A2_combine_hl : HInst<
374 (outs IntRegs:$Rd32),
375 (ins IntRegs:$Rt32, IntRegs:$Rs32),
376 "$Rd32 = combine($Rt32.h,$Rs32.l)",
377 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
378 let Inst{7-5} = 0b000;
379 let Inst{13-13} = 0b0;
380 let Inst{31-21} = 0b11110011101;
383 let InputType = "reg";
385 def A2_combine_lh : HInst<
386 (outs IntRegs:$Rd32),
387 (ins IntRegs:$Rt32, IntRegs:$Rs32),
388 "$Rd32 = combine($Rt32.l,$Rs32.h)",
389 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
390 let Inst{7-5} = 0b000;
391 let Inst{13-13} = 0b0;
392 let Inst{31-21} = 0b11110011110;
395 let InputType = "reg";
397 def A2_combine_ll : HInst<
398 (outs IntRegs:$Rd32),
399 (ins IntRegs:$Rt32, IntRegs:$Rs32),
400 "$Rd32 = combine($Rt32.l,$Rs32.l)",
401 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
402 let Inst{7-5} = 0b000;
403 let Inst{13-13} = 0b0;
404 let Inst{31-21} = 0b11110011111;
407 let InputType = "reg";
409 def A2_combineii : HInst<
410 (outs DoubleRegs:$Rdd32),
411 (ins s32_0Imm:$Ii, s8_0Imm:$II),
412 "$Rdd32 = combine(#$Ii,#$II)",
413 tc_b9488031, TypeALU32_2op>, Enc_18c338 {
414 let Inst{31-23} = 0b011111000;
415 let isReMaterializable = 1;
416 let isAsCheapAsAMove = 1;
418 let isExtendable = 1;
419 let opExtendable = 1;
420 let isExtentSigned = 1;
421 let opExtentBits = 8;
422 let opExtentAlign = 0;
424 def A2_combinew : HInst<
425 (outs DoubleRegs:$Rdd32),
426 (ins IntRegs:$Rs32, IntRegs:$Rt32),
427 "$Rdd32 = combine($Rs32,$Rt32)",
428 tc_b9488031, TypeALU32_3op>, Enc_be32a5, PredNewRel {
429 let Inst{7-5} = 0b000;
430 let Inst{13-13} = 0b0;
431 let Inst{31-21} = 0b11110101000;
432 let InputType = "reg";
433 let BaseOpcode = "A2_combinew";
434 let isPredicable = 1;
437 (outs IntRegs:$Rd32),
438 (ins IntRegs:$Rs32, IntRegs:$Rt32),
439 "$Rd32 = max($Rs32,$Rt32)",
440 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
441 let Inst{7-5} = 0b000;
442 let Inst{13-13} = 0b0;
443 let Inst{31-21} = 0b11010101110;
446 let prefersSlot3 = 1;
449 (outs DoubleRegs:$Rdd32),
450 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
451 "$Rdd32 = max($Rss32,$Rtt32)",
452 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
453 let Inst{7-5} = 0b100;
454 let Inst{13-13} = 0b0;
455 let Inst{31-21} = 0b11010011110;
456 let prefersSlot3 = 1;
459 (outs IntRegs:$Rd32),
460 (ins IntRegs:$Rs32, IntRegs:$Rt32),
461 "$Rd32 = maxu($Rs32,$Rt32)",
462 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
463 let Inst{7-5} = 0b100;
464 let Inst{13-13} = 0b0;
465 let Inst{31-21} = 0b11010101110;
468 let prefersSlot3 = 1;
470 def A2_maxup : HInst<
471 (outs DoubleRegs:$Rdd32),
472 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
473 "$Rdd32 = maxu($Rss32,$Rtt32)",
474 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
475 let Inst{7-5} = 0b101;
476 let Inst{13-13} = 0b0;
477 let Inst{31-21} = 0b11010011110;
478 let prefersSlot3 = 1;
481 (outs IntRegs:$Rd32),
482 (ins IntRegs:$Rt32, IntRegs:$Rs32),
483 "$Rd32 = min($Rt32,$Rs32)",
484 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
485 let Inst{7-5} = 0b000;
486 let Inst{13-13} = 0b0;
487 let Inst{31-21} = 0b11010101101;
490 let prefersSlot3 = 1;
493 (outs DoubleRegs:$Rdd32),
494 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
495 "$Rdd32 = min($Rtt32,$Rss32)",
496 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
497 let Inst{7-5} = 0b110;
498 let Inst{13-13} = 0b0;
499 let Inst{31-21} = 0b11010011101;
500 let prefersSlot3 = 1;
503 (outs IntRegs:$Rd32),
504 (ins IntRegs:$Rt32, IntRegs:$Rs32),
505 "$Rd32 = minu($Rt32,$Rs32)",
506 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
507 let Inst{7-5} = 0b100;
508 let Inst{13-13} = 0b0;
509 let Inst{31-21} = 0b11010101101;
512 let prefersSlot3 = 1;
514 def A2_minup : HInst<
515 (outs DoubleRegs:$Rdd32),
516 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
517 "$Rdd32 = minu($Rtt32,$Rss32)",
518 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
519 let Inst{7-5} = 0b111;
520 let Inst{13-13} = 0b0;
521 let Inst{31-21} = 0b11010011101;
522 let prefersSlot3 = 1;
525 (outs IntRegs:$Rd32),
527 "$Rd32 = neg($Rs32)",
528 tc_68cb12ce, TypeALU32_2op> {
532 let isCodeGenOnly = 1;
535 (outs DoubleRegs:$Rdd32),
536 (ins DoubleRegs:$Rss32),
537 "$Rdd32 = neg($Rss32)",
538 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
539 let Inst{13-5} = 0b000000101;
540 let Inst{31-21} = 0b10000000100;
542 def A2_negsat : HInst<
543 (outs IntRegs:$Rd32),
545 "$Rd32 = neg($Rs32):sat",
546 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
547 let Inst{13-5} = 0b000000110;
548 let Inst{31-21} = 0b10001100100;
551 let prefersSlot3 = 1;
552 let Defs = [USR_OVF];
558 tc_6efc556e, TypeALU32_2op>, Enc_e3b0c4 {
559 let Inst{13-0} = 0b00000000000000;
560 let Inst{31-16} = 0b0111111100000000;
563 (outs IntRegs:$Rd32),
565 "$Rd32 = not($Rs32)",
566 tc_68cb12ce, TypeALU32_2op> {
570 let isCodeGenOnly = 1;
573 (outs DoubleRegs:$Rdd32),
574 (ins DoubleRegs:$Rss32),
575 "$Rdd32 = not($Rss32)",
576 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
577 let Inst{13-5} = 0b000000100;
578 let Inst{31-21} = 0b10000000100;
581 (outs IntRegs:$Rd32),
582 (ins IntRegs:$Rs32, IntRegs:$Rt32),
583 "$Rd32 = or($Rs32,$Rt32)",
584 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
585 let Inst{7-5} = 0b000;
586 let Inst{13-13} = 0b0;
587 let Inst{31-21} = 0b11110001001;
590 let CextOpcode = "A2_or";
591 let InputType = "reg";
592 let BaseOpcode = "A2_or";
593 let isCommutable = 1;
594 let isPredicable = 1;
597 (outs IntRegs:$Rd32),
598 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
599 "$Rd32 = or($Rs32,#$Ii)",
600 tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
601 let Inst{31-22} = 0b0111011010;
604 let CextOpcode = "A2_or";
605 let InputType = "imm";
606 let isExtendable = 1;
607 let opExtendable = 2;
608 let isExtentSigned = 1;
609 let opExtentBits = 10;
610 let opExtentAlign = 0;
613 (outs DoubleRegs:$Rdd32),
614 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
615 "$Rdd32 = or($Rss32,$Rtt32)",
616 tc_540fdfbc, TypeALU64>, Enc_a56825 {
617 let Inst{7-5} = 0b010;
618 let Inst{13-13} = 0b0;
619 let Inst{31-21} = 0b11010011111;
620 let isCommutable = 1;
622 def A2_paddf : HInst<
623 (outs IntRegs:$Rd32),
624 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
625 "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
626 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
628 let Inst{13-13} = 0b0;
629 let Inst{31-21} = 0b11111011000;
630 let isPredicated = 1;
631 let isPredicatedFalse = 1;
634 let CextOpcode = "A2_add";
635 let InputType = "reg";
636 let BaseOpcode = "A2_add";
638 def A2_paddfnew : HInst<
639 (outs IntRegs:$Rd32),
640 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
641 "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
642 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
644 let Inst{13-13} = 0b1;
645 let Inst{31-21} = 0b11111011000;
646 let isPredicated = 1;
647 let isPredicatedFalse = 1;
650 let isPredicatedNew = 1;
651 let CextOpcode = "A2_add";
652 let InputType = "reg";
653 let BaseOpcode = "A2_add";
655 def A2_paddif : HInst<
656 (outs IntRegs:$Rd32),
657 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
658 "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
659 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
660 let Inst{13-13} = 0b0;
661 let Inst{31-23} = 0b011101001;
662 let isPredicated = 1;
663 let isPredicatedFalse = 1;
666 let CextOpcode = "A2_add";
667 let InputType = "imm";
668 let BaseOpcode = "A2_addi";
669 let isExtendable = 1;
670 let opExtendable = 3;
671 let isExtentSigned = 1;
672 let opExtentBits = 8;
673 let opExtentAlign = 0;
675 def A2_paddifnew : HInst<
676 (outs IntRegs:$Rd32),
677 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
678 "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
679 tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
680 let Inst{13-13} = 0b1;
681 let Inst{31-23} = 0b011101001;
682 let isPredicated = 1;
683 let isPredicatedFalse = 1;
686 let isPredicatedNew = 1;
687 let CextOpcode = "A2_add";
688 let InputType = "imm";
689 let BaseOpcode = "A2_addi";
690 let isExtendable = 1;
691 let opExtendable = 3;
692 let isExtentSigned = 1;
693 let opExtentBits = 8;
694 let opExtentAlign = 0;
696 def A2_paddit : HInst<
697 (outs IntRegs:$Rd32),
698 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
699 "if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
700 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
701 let Inst{13-13} = 0b0;
702 let Inst{31-23} = 0b011101000;
703 let isPredicated = 1;
706 let CextOpcode = "A2_add";
707 let InputType = "imm";
708 let BaseOpcode = "A2_addi";
709 let isExtendable = 1;
710 let opExtendable = 3;
711 let isExtentSigned = 1;
712 let opExtentBits = 8;
713 let opExtentAlign = 0;
715 def A2_padditnew : HInst<
716 (outs IntRegs:$Rd32),
717 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
718 "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
719 tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
720 let Inst{13-13} = 0b1;
721 let Inst{31-23} = 0b011101000;
722 let isPredicated = 1;
725 let isPredicatedNew = 1;
726 let CextOpcode = "A2_add";
727 let InputType = "imm";
728 let BaseOpcode = "A2_addi";
729 let isExtendable = 1;
730 let opExtendable = 3;
731 let isExtentSigned = 1;
732 let opExtentBits = 8;
733 let opExtentAlign = 0;
735 def A2_paddt : HInst<
736 (outs IntRegs:$Rd32),
737 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
738 "if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
739 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
741 let Inst{13-13} = 0b0;
742 let Inst{31-21} = 0b11111011000;
743 let isPredicated = 1;
746 let CextOpcode = "A2_add";
747 let InputType = "reg";
748 let BaseOpcode = "A2_add";
750 def A2_paddtnew : HInst<
751 (outs IntRegs:$Rd32),
752 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
753 "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
754 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
756 let Inst{13-13} = 0b1;
757 let Inst{31-21} = 0b11111011000;
758 let isPredicated = 1;
761 let isPredicatedNew = 1;
762 let CextOpcode = "A2_add";
763 let InputType = "reg";
764 let BaseOpcode = "A2_add";
766 def A2_pandf : HInst<
767 (outs IntRegs:$Rd32),
768 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
769 "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
770 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
772 let Inst{13-13} = 0b0;
773 let Inst{31-21} = 0b11111001000;
774 let isPredicated = 1;
775 let isPredicatedFalse = 1;
778 let BaseOpcode = "A2_and";
780 def A2_pandfnew : HInst<
781 (outs IntRegs:$Rd32),
782 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
783 "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
784 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
786 let Inst{13-13} = 0b1;
787 let Inst{31-21} = 0b11111001000;
788 let isPredicated = 1;
789 let isPredicatedFalse = 1;
792 let isPredicatedNew = 1;
793 let BaseOpcode = "A2_and";
795 def A2_pandt : HInst<
796 (outs IntRegs:$Rd32),
797 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
798 "if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
799 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
801 let Inst{13-13} = 0b0;
802 let Inst{31-21} = 0b11111001000;
803 let isPredicated = 1;
806 let BaseOpcode = "A2_and";
808 def A2_pandtnew : HInst<
809 (outs IntRegs:$Rd32),
810 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
811 "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
812 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
814 let Inst{13-13} = 0b1;
815 let Inst{31-21} = 0b11111001000;
816 let isPredicated = 1;
819 let isPredicatedNew = 1;
820 let BaseOpcode = "A2_and";
823 (outs IntRegs:$Rd32),
824 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
825 "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
826 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
828 let Inst{13-13} = 0b0;
829 let Inst{31-21} = 0b11111001001;
830 let isPredicated = 1;
831 let isPredicatedFalse = 1;
834 let BaseOpcode = "A2_or";
836 def A2_porfnew : HInst<
837 (outs IntRegs:$Rd32),
838 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
839 "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
840 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
842 let Inst{13-13} = 0b1;
843 let Inst{31-21} = 0b11111001001;
844 let isPredicated = 1;
845 let isPredicatedFalse = 1;
848 let isPredicatedNew = 1;
849 let BaseOpcode = "A2_or";
852 (outs IntRegs:$Rd32),
853 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
854 "if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
855 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
857 let Inst{13-13} = 0b0;
858 let Inst{31-21} = 0b11111001001;
859 let isPredicated = 1;
862 let BaseOpcode = "A2_or";
864 def A2_portnew : HInst<
865 (outs IntRegs:$Rd32),
866 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
867 "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
868 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
870 let Inst{13-13} = 0b1;
871 let Inst{31-21} = 0b11111001001;
872 let isPredicated = 1;
875 let isPredicatedNew = 1;
876 let BaseOpcode = "A2_or";
878 def A2_psubf : HInst<
879 (outs IntRegs:$Rd32),
880 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
881 "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
882 tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
884 let Inst{13-13} = 0b0;
885 let Inst{31-21} = 0b11111011001;
886 let isPredicated = 1;
887 let isPredicatedFalse = 1;
890 let BaseOpcode = "A2_sub";
892 def A2_psubfnew : HInst<
893 (outs IntRegs:$Rd32),
894 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
895 "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
896 tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
898 let Inst{13-13} = 0b1;
899 let Inst{31-21} = 0b11111011001;
900 let isPredicated = 1;
901 let isPredicatedFalse = 1;
904 let isPredicatedNew = 1;
905 let BaseOpcode = "A2_sub";
907 def A2_psubt : HInst<
908 (outs IntRegs:$Rd32),
909 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
910 "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
911 tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
913 let Inst{13-13} = 0b0;
914 let Inst{31-21} = 0b11111011001;
915 let isPredicated = 1;
918 let BaseOpcode = "A2_sub";
920 def A2_psubtnew : HInst<
921 (outs IntRegs:$Rd32),
922 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
923 "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
924 tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
926 let Inst{13-13} = 0b1;
927 let Inst{31-21} = 0b11111011001;
928 let isPredicated = 1;
931 let isPredicatedNew = 1;
932 let BaseOpcode = "A2_sub";
934 def A2_pxorf : HInst<
935 (outs IntRegs:$Rd32),
936 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
937 "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
938 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
940 let Inst{13-13} = 0b0;
941 let Inst{31-21} = 0b11111001011;
942 let isPredicated = 1;
943 let isPredicatedFalse = 1;
946 let BaseOpcode = "A2_xor";
948 def A2_pxorfnew : HInst<
949 (outs IntRegs:$Rd32),
950 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
951 "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
952 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
954 let Inst{13-13} = 0b1;
955 let Inst{31-21} = 0b11111001011;
956 let isPredicated = 1;
957 let isPredicatedFalse = 1;
960 let isPredicatedNew = 1;
961 let BaseOpcode = "A2_xor";
963 def A2_pxort : HInst<
964 (outs IntRegs:$Rd32),
965 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
966 "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
967 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
969 let Inst{13-13} = 0b0;
970 let Inst{31-21} = 0b11111001011;
971 let isPredicated = 1;
974 let BaseOpcode = "A2_xor";
976 def A2_pxortnew : HInst<
977 (outs IntRegs:$Rd32),
978 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
979 "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
980 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
982 let Inst{13-13} = 0b1;
983 let Inst{31-21} = 0b11111001011;
984 let isPredicated = 1;
987 let isPredicatedNew = 1;
988 let BaseOpcode = "A2_xor";
990 def A2_roundsat : HInst<
991 (outs IntRegs:$Rd32),
992 (ins DoubleRegs:$Rss32),
993 "$Rd32 = round($Rss32):sat",
994 tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
995 let Inst{13-5} = 0b000000001;
996 let Inst{31-21} = 0b10001000110;
999 let prefersSlot3 = 1;
1000 let Defs = [USR_OVF];
1003 (outs IntRegs:$Rd32),
1004 (ins DoubleRegs:$Rss32),
1005 "$Rd32 = sat($Rss32)",
1006 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
1007 let Inst{13-5} = 0b000000000;
1008 let Inst{31-21} = 0b10001000110;
1009 let hasNewValue = 1;
1011 let Defs = [USR_OVF];
1013 def A2_satb : HInst<
1014 (outs IntRegs:$Rd32),
1015 (ins IntRegs:$Rs32),
1016 "$Rd32 = satb($Rs32)",
1017 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
1018 let Inst{13-5} = 0b000000111;
1019 let Inst{31-21} = 0b10001100110;
1020 let hasNewValue = 1;
1022 let Defs = [USR_OVF];
1024 def A2_sath : HInst<
1025 (outs IntRegs:$Rd32),
1026 (ins IntRegs:$Rs32),
1027 "$Rd32 = sath($Rs32)",
1028 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
1029 let Inst{13-5} = 0b000000100;
1030 let Inst{31-21} = 0b10001100110;
1031 let hasNewValue = 1;
1033 let Defs = [USR_OVF];
1035 def A2_satub : HInst<
1036 (outs IntRegs:$Rd32),
1037 (ins IntRegs:$Rs32),
1038 "$Rd32 = satub($Rs32)",
1039 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
1040 let Inst{13-5} = 0b000000110;
1041 let Inst{31-21} = 0b10001100110;
1042 let hasNewValue = 1;
1044 let Defs = [USR_OVF];
1046 def A2_satuh : HInst<
1047 (outs IntRegs:$Rd32),
1048 (ins IntRegs:$Rs32),
1049 "$Rd32 = satuh($Rs32)",
1050 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
1051 let Inst{13-5} = 0b000000101;
1052 let Inst{31-21} = 0b10001100110;
1053 let hasNewValue = 1;
1055 let Defs = [USR_OVF];
1058 (outs IntRegs:$Rd32),
1059 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1060 "$Rd32 = sub($Rt32,$Rs32)",
1061 tc_b9488031, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1062 let Inst{7-5} = 0b000;
1063 let Inst{13-13} = 0b0;
1064 let Inst{31-21} = 0b11110011001;
1065 let hasNewValue = 1;
1067 let CextOpcode = "A2_sub";
1068 let InputType = "reg";
1069 let BaseOpcode = "A2_sub";
1070 let isPredicable = 1;
1072 def A2_subh_h16_hh : HInst<
1073 (outs IntRegs:$Rd32),
1074 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1075 "$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1076 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
1077 let Inst{7-5} = 0b011;
1078 let Inst{13-13} = 0b0;
1079 let Inst{31-21} = 0b11010101011;
1080 let hasNewValue = 1;
1082 let prefersSlot3 = 1;
1084 def A2_subh_h16_hl : HInst<
1085 (outs IntRegs:$Rd32),
1086 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1087 "$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1088 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
1089 let Inst{7-5} = 0b010;
1090 let Inst{13-13} = 0b0;
1091 let Inst{31-21} = 0b11010101011;
1092 let hasNewValue = 1;
1094 let prefersSlot3 = 1;
1096 def A2_subh_h16_lh : HInst<
1097 (outs IntRegs:$Rd32),
1098 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1099 "$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1100 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
1101 let Inst{7-5} = 0b001;
1102 let Inst{13-13} = 0b0;
1103 let Inst{31-21} = 0b11010101011;
1104 let hasNewValue = 1;
1106 let prefersSlot3 = 1;
1108 def A2_subh_h16_ll : HInst<
1109 (outs IntRegs:$Rd32),
1110 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1111 "$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1112 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
1113 let Inst{7-5} = 0b000;
1114 let Inst{13-13} = 0b0;
1115 let Inst{31-21} = 0b11010101011;
1116 let hasNewValue = 1;
1118 let prefersSlot3 = 1;
1120 def A2_subh_h16_sat_hh : HInst<
1121 (outs IntRegs:$Rd32),
1122 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1123 "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1124 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1125 let Inst{7-5} = 0b111;
1126 let Inst{13-13} = 0b0;
1127 let Inst{31-21} = 0b11010101011;
1128 let hasNewValue = 1;
1130 let prefersSlot3 = 1;
1131 let Defs = [USR_OVF];
1133 def A2_subh_h16_sat_hl : HInst<
1134 (outs IntRegs:$Rd32),
1135 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1136 "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1137 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1138 let Inst{7-5} = 0b110;
1139 let Inst{13-13} = 0b0;
1140 let Inst{31-21} = 0b11010101011;
1141 let hasNewValue = 1;
1143 let prefersSlot3 = 1;
1144 let Defs = [USR_OVF];
1146 def A2_subh_h16_sat_lh : HInst<
1147 (outs IntRegs:$Rd32),
1148 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1149 "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1150 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1151 let Inst{7-5} = 0b101;
1152 let Inst{13-13} = 0b0;
1153 let Inst{31-21} = 0b11010101011;
1154 let hasNewValue = 1;
1156 let prefersSlot3 = 1;
1157 let Defs = [USR_OVF];
1159 def A2_subh_h16_sat_ll : HInst<
1160 (outs IntRegs:$Rd32),
1161 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1162 "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1163 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1164 let Inst{7-5} = 0b100;
1165 let Inst{13-13} = 0b0;
1166 let Inst{31-21} = 0b11010101011;
1167 let hasNewValue = 1;
1169 let prefersSlot3 = 1;
1170 let Defs = [USR_OVF];
1172 def A2_subh_l16_hl : HInst<
1173 (outs IntRegs:$Rd32),
1174 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1175 "$Rd32 = sub($Rt32.l,$Rs32.h)",
1176 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
1177 let Inst{7-5} = 0b010;
1178 let Inst{13-13} = 0b0;
1179 let Inst{31-21} = 0b11010101001;
1180 let hasNewValue = 1;
1182 let prefersSlot3 = 1;
1184 def A2_subh_l16_ll : HInst<
1185 (outs IntRegs:$Rd32),
1186 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1187 "$Rd32 = sub($Rt32.l,$Rs32.l)",
1188 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
1189 let Inst{7-5} = 0b000;
1190 let Inst{13-13} = 0b0;
1191 let Inst{31-21} = 0b11010101001;
1192 let hasNewValue = 1;
1194 let prefersSlot3 = 1;
1196 def A2_subh_l16_sat_hl : HInst<
1197 (outs IntRegs:$Rd32),
1198 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1199 "$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1200 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1201 let Inst{7-5} = 0b110;
1202 let Inst{13-13} = 0b0;
1203 let Inst{31-21} = 0b11010101001;
1204 let hasNewValue = 1;
1206 let prefersSlot3 = 1;
1207 let Defs = [USR_OVF];
1209 def A2_subh_l16_sat_ll : HInst<
1210 (outs IntRegs:$Rd32),
1211 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1212 "$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1213 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
1214 let Inst{7-5} = 0b100;
1215 let Inst{13-13} = 0b0;
1216 let Inst{31-21} = 0b11010101001;
1217 let hasNewValue = 1;
1219 let prefersSlot3 = 1;
1220 let Defs = [USR_OVF];
1222 def A2_subp : HInst<
1223 (outs DoubleRegs:$Rdd32),
1224 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1225 "$Rdd32 = sub($Rtt32,$Rss32)",
1226 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
1227 let Inst{7-5} = 0b111;
1228 let Inst{13-13} = 0b0;
1229 let Inst{31-21} = 0b11010011001;
1231 def A2_subri : HInst<
1232 (outs IntRegs:$Rd32),
1233 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
1234 "$Rd32 = sub(#$Ii,$Rs32)",
1235 tc_b9488031, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1236 let Inst{31-22} = 0b0111011001;
1237 let hasNewValue = 1;
1239 let CextOpcode = "A2_sub";
1240 let InputType = "imm";
1241 let isExtendable = 1;
1242 let opExtendable = 1;
1243 let isExtentSigned = 1;
1244 let opExtentBits = 10;
1245 let opExtentAlign = 0;
1247 def A2_subsat : HInst<
1248 (outs IntRegs:$Rd32),
1249 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1250 "$Rd32 = sub($Rt32,$Rs32):sat",
1251 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
1252 let Inst{7-5} = 0b000;
1253 let Inst{13-13} = 0b0;
1254 let Inst{31-21} = 0b11110110110;
1255 let hasNewValue = 1;
1257 let prefersSlot3 = 1;
1258 let Defs = [USR_OVF];
1259 let InputType = "reg";
1261 def A2_svaddh : HInst<
1262 (outs IntRegs:$Rd32),
1263 (ins IntRegs:$Rs32, IntRegs:$Rt32),
1264 "$Rd32 = vaddh($Rs32,$Rt32)",
1265 tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
1266 let Inst{7-5} = 0b000;
1267 let Inst{13-13} = 0b0;
1268 let Inst{31-21} = 0b11110110000;
1269 let hasNewValue = 1;
1271 let InputType = "reg";
1272 let isCommutable = 1;
1274 def A2_svaddhs : HInst<
1275 (outs IntRegs:$Rd32),
1276 (ins IntRegs:$Rs32, IntRegs:$Rt32),
1277 "$Rd32 = vaddh($Rs32,$Rt32):sat",
1278 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
1279 let Inst{7-5} = 0b000;
1280 let Inst{13-13} = 0b0;
1281 let Inst{31-21} = 0b11110110001;
1282 let hasNewValue = 1;
1284 let prefersSlot3 = 1;
1285 let Defs = [USR_OVF];
1286 let InputType = "reg";
1287 let isCommutable = 1;
1289 def A2_svadduhs : HInst<
1290 (outs IntRegs:$Rd32),
1291 (ins IntRegs:$Rs32, IntRegs:$Rt32),
1292 "$Rd32 = vadduh($Rs32,$Rt32):sat",
1293 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
1294 let Inst{7-5} = 0b000;
1295 let Inst{13-13} = 0b0;
1296 let Inst{31-21} = 0b11110110011;
1297 let hasNewValue = 1;
1299 let prefersSlot3 = 1;
1300 let Defs = [USR_OVF];
1301 let InputType = "reg";
1302 let isCommutable = 1;
1304 def A2_svavgh : HInst<
1305 (outs IntRegs:$Rd32),
1306 (ins IntRegs:$Rs32, IntRegs:$Rt32),
1307 "$Rd32 = vavgh($Rs32,$Rt32)",
1308 tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
1309 let Inst{7-5} = 0b000;
1310 let Inst{13-13} = 0b0;
1311 let Inst{31-21} = 0b11110111000;
1312 let hasNewValue = 1;
1314 let InputType = "reg";
1315 let isCommutable = 1;
1317 def A2_svavghs : HInst<
1318 (outs IntRegs:$Rd32),
1319 (ins IntRegs:$Rs32, IntRegs:$Rt32),
1320 "$Rd32 = vavgh($Rs32,$Rt32):rnd",
1321 tc_8fe6b782, TypeALU32_3op>, Enc_5ab2be {
1322 let Inst{7-5} = 0b000;
1323 let Inst{13-13} = 0b0;
1324 let Inst{31-21} = 0b11110111001;
1325 let hasNewValue = 1;
1327 let InputType = "reg";
1328 let isCommutable = 1;
1330 def A2_svnavgh : HInst<
1331 (outs IntRegs:$Rd32),
1332 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1333 "$Rd32 = vnavgh($Rt32,$Rs32)",
1334 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
1335 let Inst{7-5} = 0b000;
1336 let Inst{13-13} = 0b0;
1337 let Inst{31-21} = 0b11110111011;
1338 let hasNewValue = 1;
1340 let InputType = "reg";
1342 def A2_svsubh : HInst<
1343 (outs IntRegs:$Rd32),
1344 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1345 "$Rd32 = vsubh($Rt32,$Rs32)",
1346 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
1347 let Inst{7-5} = 0b000;
1348 let Inst{13-13} = 0b0;
1349 let Inst{31-21} = 0b11110110100;
1350 let hasNewValue = 1;
1352 let InputType = "reg";
1354 def A2_svsubhs : HInst<
1355 (outs IntRegs:$Rd32),
1356 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1357 "$Rd32 = vsubh($Rt32,$Rs32):sat",
1358 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
1359 let Inst{7-5} = 0b000;
1360 let Inst{13-13} = 0b0;
1361 let Inst{31-21} = 0b11110110101;
1362 let hasNewValue = 1;
1364 let prefersSlot3 = 1;
1365 let Defs = [USR_OVF];
1366 let InputType = "reg";
1368 def A2_svsubuhs : HInst<
1369 (outs IntRegs:$Rd32),
1370 (ins IntRegs:$Rt32, IntRegs:$Rs32),
1371 "$Rd32 = vsubuh($Rt32,$Rs32):sat",
1372 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
1373 let Inst{7-5} = 0b000;
1374 let Inst{13-13} = 0b0;
1375 let Inst{31-21} = 0b11110110111;
1376 let hasNewValue = 1;
1378 let prefersSlot3 = 1;
1379 let Defs = [USR_OVF];
1380 let InputType = "reg";
1382 def A2_swiz : HInst<
1383 (outs IntRegs:$Rd32),
1384 (ins IntRegs:$Rs32),
1385 "$Rd32 = swiz($Rs32)",
1386 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
1387 let Inst{13-5} = 0b000000111;
1388 let Inst{31-21} = 0b10001100100;
1389 let hasNewValue = 1;
1392 def A2_sxtb : HInst<
1393 (outs IntRegs:$Rd32),
1394 (ins IntRegs:$Rs32),
1395 "$Rd32 = sxtb($Rs32)",
1396 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1397 let Inst{13-5} = 0b000000000;
1398 let Inst{31-21} = 0b01110000101;
1399 let hasNewValue = 1;
1401 let BaseOpcode = "A2_sxtb";
1402 let isPredicable = 1;
1404 def A2_sxth : HInst<
1405 (outs IntRegs:$Rd32),
1406 (ins IntRegs:$Rs32),
1407 "$Rd32 = sxth($Rs32)",
1408 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1409 let Inst{13-5} = 0b000000000;
1410 let Inst{31-21} = 0b01110000111;
1411 let hasNewValue = 1;
1413 let BaseOpcode = "A2_sxth";
1414 let isPredicable = 1;
1416 def A2_sxtw : HInst<
1417 (outs DoubleRegs:$Rdd32),
1418 (ins IntRegs:$Rs32),
1419 "$Rdd32 = sxtw($Rs32)",
1420 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
1421 let Inst{13-5} = 0b000000000;
1422 let Inst{31-21} = 0b10000100010;
1425 (outs IntRegs:$Rd32),
1426 (ins IntRegs:$Rs32),
1428 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1429 let Inst{13-5} = 0b000000000;
1430 let Inst{31-21} = 0b01110000011;
1431 let hasNewValue = 1;
1433 let InputType = "reg";
1434 let BaseOpcode = "A2_tfr";
1435 let isPredicable = 1;
1437 def A2_tfrcrr : HInst<
1438 (outs IntRegs:$Rd32),
1439 (ins CtrRegs:$Cs32),
1441 tc_29175780, TypeCR>, Enc_0cb018 {
1442 let Inst{13-5} = 0b000000000;
1443 let Inst{31-21} = 0b01101010000;
1444 let hasNewValue = 1;
1447 def A2_tfrf : HInst<
1448 (outs IntRegs:$Rd32),
1449 (ins PredRegs:$Pu4, IntRegs:$Rs32),
1450 "if (!$Pu4) $Rd32 = $Rs32",
1451 tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
1452 let isPredicated = 1;
1453 let isPredicatedFalse = 1;
1454 let hasNewValue = 1;
1456 let CextOpcode = "A2_tfr";
1457 let InputType = "reg";
1458 let BaseOpcode = "A2_tfr";
1460 let isCodeGenOnly = 1;
1462 def A2_tfrfnew : HInst<
1463 (outs IntRegs:$Rd32),
1464 (ins PredRegs:$Pu4, IntRegs:$Rs32),
1465 "if (!$Pu4.new) $Rd32 = $Rs32",
1466 tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
1467 let isPredicated = 1;
1468 let isPredicatedFalse = 1;
1469 let hasNewValue = 1;
1471 let isPredicatedNew = 1;
1472 let CextOpcode = "A2_tfr";
1473 let InputType = "reg";
1474 let BaseOpcode = "A2_tfr";
1476 let isCodeGenOnly = 1;
1478 def A2_tfrih : HInst<
1479 (outs IntRegs:$Rx32),
1480 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482 tc_b9488031, TypeALU32_2op>, Enc_51436c {
1483 let Inst{21-21} = 0b1;
1484 let Inst{31-24} = 0b01110010;
1485 let hasNewValue = 1;
1487 let Constraints = "$Rx32 = $Rx32in";
1489 def A2_tfril : HInst<
1490 (outs IntRegs:$Rx32),
1491 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493 tc_b9488031, TypeALU32_2op>, Enc_51436c {
1494 let Inst{21-21} = 0b1;
1495 let Inst{31-24} = 0b01110001;
1496 let hasNewValue = 1;
1498 let Constraints = "$Rx32 = $Rx32in";
1500 def A2_tfrp : HInst<
1501 (outs DoubleRegs:$Rdd32),
1502 (ins DoubleRegs:$Rss32),
1504 tc_b9488031, TypeALU32_2op>, PredNewRel {
1505 let BaseOpcode = "A2_tfrp";
1506 let isPredicable = 1;
1509 def A2_tfrpf : HInst<
1510 (outs DoubleRegs:$Rdd32),
1511 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1512 "if (!$Pu4) $Rdd32 = $Rss32",
1513 tc_b9488031, TypeALU32_2op>, PredNewRel {
1514 let isPredicated = 1;
1515 let isPredicatedFalse = 1;
1516 let BaseOpcode = "A2_tfrp";
1519 def A2_tfrpfnew : HInst<
1520 (outs DoubleRegs:$Rdd32),
1521 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1522 "if (!$Pu4.new) $Rdd32 = $Rss32",
1523 tc_5f6847a1, TypeALU32_2op>, PredNewRel {
1524 let isPredicated = 1;
1525 let isPredicatedFalse = 1;
1526 let isPredicatedNew = 1;
1527 let BaseOpcode = "A2_tfrp";
1530 def A2_tfrpi : HInst<
1531 (outs DoubleRegs:$Rdd32),
1534 tc_b9488031, TypeALU64> {
1535 let isReMaterializable = 1;
1536 let isAsCheapAsAMove = 1;
1540 def A2_tfrpt : HInst<
1541 (outs DoubleRegs:$Rdd32),
1542 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1543 "if ($Pu4) $Rdd32 = $Rss32",
1544 tc_b9488031, TypeALU32_2op>, PredNewRel {
1545 let isPredicated = 1;
1546 let BaseOpcode = "A2_tfrp";
1549 def A2_tfrptnew : HInst<
1550 (outs DoubleRegs:$Rdd32),
1551 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1552 "if ($Pu4.new) $Rdd32 = $Rss32",
1553 tc_5f6847a1, TypeALU32_2op>, PredNewRel {
1554 let isPredicated = 1;
1555 let isPredicatedNew = 1;
1556 let BaseOpcode = "A2_tfrp";
1559 def A2_tfrrcr : HInst<
1560 (outs CtrRegs:$Cd32),
1561 (ins IntRegs:$Rs32),
1563 tc_a21dc435, TypeCR>, Enc_bd811a {
1564 let Inst{13-5} = 0b000000000;
1565 let Inst{31-21} = 0b01100010001;
1566 let hasNewValue = 1;
1569 def A2_tfrsi : HInst<
1570 (outs IntRegs:$Rd32),
1573 tc_68cb12ce, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1574 let Inst{21-21} = 0b0;
1575 let Inst{31-24} = 0b01111000;
1576 let hasNewValue = 1;
1578 let CextOpcode = "A2_tfr";
1579 let InputType = "imm";
1580 let BaseOpcode = "A2_tfrsi";
1581 let isPredicable = 1;
1582 let isReMaterializable = 1;
1583 let isAsCheapAsAMove = 1;
1585 let isExtendable = 1;
1586 let opExtendable = 1;
1587 let isExtentSigned = 1;
1588 let opExtentBits = 16;
1589 let opExtentAlign = 0;
1591 def A2_tfrt : HInst<
1592 (outs IntRegs:$Rd32),
1593 (ins PredRegs:$Pu4, IntRegs:$Rs32),
1594 "if ($Pu4) $Rd32 = $Rs32",
1595 tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
1596 let isPredicated = 1;
1597 let hasNewValue = 1;
1599 let CextOpcode = "A2_tfr";
1600 let InputType = "reg";
1601 let BaseOpcode = "A2_tfr";
1603 let isCodeGenOnly = 1;
1605 def A2_tfrtnew : HInst<
1606 (outs IntRegs:$Rd32),
1607 (ins PredRegs:$Pu4, IntRegs:$Rs32),
1608 "if ($Pu4.new) $Rd32 = $Rs32",
1609 tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
1610 let isPredicated = 1;
1611 let hasNewValue = 1;
1613 let isPredicatedNew = 1;
1614 let CextOpcode = "A2_tfr";
1615 let InputType = "reg";
1616 let BaseOpcode = "A2_tfr";
1618 let isCodeGenOnly = 1;
1620 def A2_vabsh : HInst<
1621 (outs DoubleRegs:$Rdd32),
1622 (ins DoubleRegs:$Rss32),
1623 "$Rdd32 = vabsh($Rss32)",
1624 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
1625 let Inst{13-5} = 0b000000100;
1626 let Inst{31-21} = 0b10000000010;
1627 let prefersSlot3 = 1;
1629 def A2_vabshsat : HInst<
1630 (outs DoubleRegs:$Rdd32),
1631 (ins DoubleRegs:$Rss32),
1632 "$Rdd32 = vabsh($Rss32):sat",
1633 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
1634 let Inst{13-5} = 0b000000101;
1635 let Inst{31-21} = 0b10000000010;
1636 let prefersSlot3 = 1;
1637 let Defs = [USR_OVF];
1639 def A2_vabsw : HInst<
1640 (outs DoubleRegs:$Rdd32),
1641 (ins DoubleRegs:$Rss32),
1642 "$Rdd32 = vabsw($Rss32)",
1643 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
1644 let Inst{13-5} = 0b000000110;
1645 let Inst{31-21} = 0b10000000010;
1646 let prefersSlot3 = 1;
1648 def A2_vabswsat : HInst<
1649 (outs DoubleRegs:$Rdd32),
1650 (ins DoubleRegs:$Rss32),
1651 "$Rdd32 = vabsw($Rss32):sat",
1652 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
1653 let Inst{13-5} = 0b000000111;
1654 let Inst{31-21} = 0b10000000010;
1655 let prefersSlot3 = 1;
1656 let Defs = [USR_OVF];
1658 def A2_vaddb_map : HInst<
1659 (outs DoubleRegs:$Rdd32),
1660 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1661 "$Rdd32 = vaddb($Rss32,$Rtt32)",
1662 tc_540fdfbc, TypeMAPPING> {
1664 let isCodeGenOnly = 1;
1666 def A2_vaddh : HInst<
1667 (outs DoubleRegs:$Rdd32),
1668 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1669 "$Rdd32 = vaddh($Rss32,$Rtt32)",
1670 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1671 let Inst{7-5} = 0b010;
1672 let Inst{13-13} = 0b0;
1673 let Inst{31-21} = 0b11010011000;
1675 def A2_vaddhs : HInst<
1676 (outs DoubleRegs:$Rdd32),
1677 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1678 "$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1679 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
1680 let Inst{7-5} = 0b011;
1681 let Inst{13-13} = 0b0;
1682 let Inst{31-21} = 0b11010011000;
1683 let prefersSlot3 = 1;
1684 let Defs = [USR_OVF];
1686 def A2_vaddub : HInst<
1687 (outs DoubleRegs:$Rdd32),
1688 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1689 "$Rdd32 = vaddub($Rss32,$Rtt32)",
1690 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1691 let Inst{7-5} = 0b000;
1692 let Inst{13-13} = 0b0;
1693 let Inst{31-21} = 0b11010011000;
1695 def A2_vaddubs : HInst<
1696 (outs DoubleRegs:$Rdd32),
1697 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1698 "$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1699 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
1700 let Inst{7-5} = 0b001;
1701 let Inst{13-13} = 0b0;
1702 let Inst{31-21} = 0b11010011000;
1703 let prefersSlot3 = 1;
1704 let Defs = [USR_OVF];
1706 def A2_vadduhs : HInst<
1707 (outs DoubleRegs:$Rdd32),
1708 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1709 "$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1710 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
1711 let Inst{7-5} = 0b100;
1712 let Inst{13-13} = 0b0;
1713 let Inst{31-21} = 0b11010011000;
1714 let prefersSlot3 = 1;
1715 let Defs = [USR_OVF];
1717 def A2_vaddw : HInst<
1718 (outs DoubleRegs:$Rdd32),
1719 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1720 "$Rdd32 = vaddw($Rss32,$Rtt32)",
1721 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1722 let Inst{7-5} = 0b101;
1723 let Inst{13-13} = 0b0;
1724 let Inst{31-21} = 0b11010011000;
1726 def A2_vaddws : HInst<
1727 (outs DoubleRegs:$Rdd32),
1728 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1729 "$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1730 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
1731 let Inst{7-5} = 0b110;
1732 let Inst{13-13} = 0b0;
1733 let Inst{31-21} = 0b11010011000;
1734 let prefersSlot3 = 1;
1735 let Defs = [USR_OVF];
1737 def A2_vavgh : HInst<
1738 (outs DoubleRegs:$Rdd32),
1739 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1740 "$Rdd32 = vavgh($Rss32,$Rtt32)",
1741 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1742 let Inst{7-5} = 0b010;
1743 let Inst{13-13} = 0b0;
1744 let Inst{31-21} = 0b11010011010;
1746 def A2_vavghcr : HInst<
1747 (outs DoubleRegs:$Rdd32),
1748 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1749 "$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1750 tc_2b6f77c6, TypeALU64>, Enc_a56825 {
1751 let Inst{7-5} = 0b100;
1752 let Inst{13-13} = 0b0;
1753 let Inst{31-21} = 0b11010011010;
1754 let prefersSlot3 = 1;
1756 def A2_vavghr : HInst<
1757 (outs DoubleRegs:$Rdd32),
1758 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1759 "$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1760 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
1761 let Inst{7-5} = 0b011;
1762 let Inst{13-13} = 0b0;
1763 let Inst{31-21} = 0b11010011010;
1765 def A2_vavgub : HInst<
1766 (outs DoubleRegs:$Rdd32),
1767 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1768 "$Rdd32 = vavgub($Rss32,$Rtt32)",
1769 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1770 let Inst{7-5} = 0b000;
1771 let Inst{13-13} = 0b0;
1772 let Inst{31-21} = 0b11010011010;
1774 def A2_vavgubr : HInst<
1775 (outs DoubleRegs:$Rdd32),
1776 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1777 "$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1778 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
1779 let Inst{7-5} = 0b001;
1780 let Inst{13-13} = 0b0;
1781 let Inst{31-21} = 0b11010011010;
1783 def A2_vavguh : HInst<
1784 (outs DoubleRegs:$Rdd32),
1785 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1786 "$Rdd32 = vavguh($Rss32,$Rtt32)",
1787 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1788 let Inst{7-5} = 0b101;
1789 let Inst{13-13} = 0b0;
1790 let Inst{31-21} = 0b11010011010;
1792 def A2_vavguhr : HInst<
1793 (outs DoubleRegs:$Rdd32),
1794 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1795 "$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1796 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
1797 let Inst{7-5} = 0b110;
1798 let Inst{13-13} = 0b0;
1799 let Inst{31-21} = 0b11010011010;
1801 def A2_vavguw : HInst<
1802 (outs DoubleRegs:$Rdd32),
1803 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1804 "$Rdd32 = vavguw($Rss32,$Rtt32)",
1805 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1806 let Inst{7-5} = 0b011;
1807 let Inst{13-13} = 0b0;
1808 let Inst{31-21} = 0b11010011011;
1810 def A2_vavguwr : HInst<
1811 (outs DoubleRegs:$Rdd32),
1812 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1813 "$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1814 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
1815 let Inst{7-5} = 0b100;
1816 let Inst{13-13} = 0b0;
1817 let Inst{31-21} = 0b11010011011;
1819 def A2_vavgw : HInst<
1820 (outs DoubleRegs:$Rdd32),
1821 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1822 "$Rdd32 = vavgw($Rss32,$Rtt32)",
1823 tc_540fdfbc, TypeALU64>, Enc_a56825 {
1824 let Inst{7-5} = 0b000;
1825 let Inst{13-13} = 0b0;
1826 let Inst{31-21} = 0b11010011011;
1828 def A2_vavgwcr : HInst<
1829 (outs DoubleRegs:$Rdd32),
1830 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831 "$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1832 tc_2b6f77c6, TypeALU64>, Enc_a56825 {
1833 let Inst{7-5} = 0b010;
1834 let Inst{13-13} = 0b0;
1835 let Inst{31-21} = 0b11010011011;
1836 let prefersSlot3 = 1;
1838 def A2_vavgwr : HInst<
1839 (outs DoubleRegs:$Rdd32),
1840 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841 "$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1842 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
1843 let Inst{7-5} = 0b001;
1844 let Inst{13-13} = 0b0;
1845 let Inst{31-21} = 0b11010011011;
1847 def A2_vcmpbeq : HInst<
1848 (outs PredRegs:$Pd4),
1849 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1850 "$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1851 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1852 let Inst{7-2} = 0b110000;
1853 let Inst{13-13} = 0b0;
1854 let Inst{31-21} = 0b11010010000;
1856 def A2_vcmpbgtu : HInst<
1857 (outs PredRegs:$Pd4),
1858 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1859 "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1860 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1861 let Inst{7-2} = 0b111000;
1862 let Inst{13-13} = 0b0;
1863 let Inst{31-21} = 0b11010010000;
1865 def A2_vcmpheq : HInst<
1866 (outs PredRegs:$Pd4),
1867 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1868 "$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1869 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1870 let Inst{7-2} = 0b011000;
1871 let Inst{13-13} = 0b0;
1872 let Inst{31-21} = 0b11010010000;
1874 def A2_vcmphgt : HInst<
1875 (outs PredRegs:$Pd4),
1876 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1877 "$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1878 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1879 let Inst{7-2} = 0b100000;
1880 let Inst{13-13} = 0b0;
1881 let Inst{31-21} = 0b11010010000;
1883 def A2_vcmphgtu : HInst<
1884 (outs PredRegs:$Pd4),
1885 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1886 "$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1887 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1888 let Inst{7-2} = 0b101000;
1889 let Inst{13-13} = 0b0;
1890 let Inst{31-21} = 0b11010010000;
1892 def A2_vcmpweq : HInst<
1893 (outs PredRegs:$Pd4),
1894 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1895 "$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1896 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1897 let Inst{7-2} = 0b000000;
1898 let Inst{13-13} = 0b0;
1899 let Inst{31-21} = 0b11010010000;
1901 def A2_vcmpwgt : HInst<
1902 (outs PredRegs:$Pd4),
1903 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1904 "$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1905 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1906 let Inst{7-2} = 0b001000;
1907 let Inst{13-13} = 0b0;
1908 let Inst{31-21} = 0b11010010000;
1910 def A2_vcmpwgtu : HInst<
1911 (outs PredRegs:$Pd4),
1912 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1913 "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1914 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
1915 let Inst{7-2} = 0b010000;
1916 let Inst{13-13} = 0b0;
1917 let Inst{31-21} = 0b11010010000;
1919 def A2_vconj : HInst<
1920 (outs DoubleRegs:$Rdd32),
1921 (ins DoubleRegs:$Rss32),
1922 "$Rdd32 = vconj($Rss32):sat",
1923 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
1924 let Inst{13-5} = 0b000000111;
1925 let Inst{31-21} = 0b10000000100;
1926 let prefersSlot3 = 1;
1927 let Defs = [USR_OVF];
1929 def A2_vmaxb : HInst<
1930 (outs DoubleRegs:$Rdd32),
1931 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1932 "$Rdd32 = vmaxb($Rtt32,$Rss32)",
1933 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1934 let Inst{7-5} = 0b110;
1935 let Inst{13-13} = 0b0;
1936 let Inst{31-21} = 0b11010011110;
1937 let prefersSlot3 = 1;
1939 def A2_vmaxh : HInst<
1940 (outs DoubleRegs:$Rdd32),
1941 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1942 "$Rdd32 = vmaxh($Rtt32,$Rss32)",
1943 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1944 let Inst{7-5} = 0b001;
1945 let Inst{13-13} = 0b0;
1946 let Inst{31-21} = 0b11010011110;
1947 let prefersSlot3 = 1;
1949 def A2_vmaxub : HInst<
1950 (outs DoubleRegs:$Rdd32),
1951 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1952 "$Rdd32 = vmaxub($Rtt32,$Rss32)",
1953 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1954 let Inst{7-5} = 0b000;
1955 let Inst{13-13} = 0b0;
1956 let Inst{31-21} = 0b11010011110;
1957 let prefersSlot3 = 1;
1959 def A2_vmaxuh : HInst<
1960 (outs DoubleRegs:$Rdd32),
1961 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1962 "$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1963 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1964 let Inst{7-5} = 0b010;
1965 let Inst{13-13} = 0b0;
1966 let Inst{31-21} = 0b11010011110;
1967 let prefersSlot3 = 1;
1969 def A2_vmaxuw : HInst<
1970 (outs DoubleRegs:$Rdd32),
1971 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1972 "$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1973 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1974 let Inst{7-5} = 0b101;
1975 let Inst{13-13} = 0b0;
1976 let Inst{31-21} = 0b11010011101;
1977 let prefersSlot3 = 1;
1979 def A2_vmaxw : HInst<
1980 (outs DoubleRegs:$Rdd32),
1981 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1982 "$Rdd32 = vmaxw($Rtt32,$Rss32)",
1983 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1984 let Inst{7-5} = 0b011;
1985 let Inst{13-13} = 0b0;
1986 let Inst{31-21} = 0b11010011110;
1987 let prefersSlot3 = 1;
1989 def A2_vminb : HInst<
1990 (outs DoubleRegs:$Rdd32),
1991 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1992 "$Rdd32 = vminb($Rtt32,$Rss32)",
1993 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
1994 let Inst{7-5} = 0b111;
1995 let Inst{13-13} = 0b0;
1996 let Inst{31-21} = 0b11010011110;
1997 let prefersSlot3 = 1;
1999 def A2_vminh : HInst<
2000 (outs DoubleRegs:$Rdd32),
2001 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2002 "$Rdd32 = vminh($Rtt32,$Rss32)",
2003 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2004 let Inst{7-5} = 0b001;
2005 let Inst{13-13} = 0b0;
2006 let Inst{31-21} = 0b11010011101;
2007 let prefersSlot3 = 1;
2009 def A2_vminub : HInst<
2010 (outs DoubleRegs:$Rdd32),
2011 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2012 "$Rdd32 = vminub($Rtt32,$Rss32)",
2013 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2014 let Inst{7-5} = 0b000;
2015 let Inst{13-13} = 0b0;
2016 let Inst{31-21} = 0b11010011101;
2017 let prefersSlot3 = 1;
2019 def A2_vminuh : HInst<
2020 (outs DoubleRegs:$Rdd32),
2021 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2022 "$Rdd32 = vminuh($Rtt32,$Rss32)",
2023 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2024 let Inst{7-5} = 0b010;
2025 let Inst{13-13} = 0b0;
2026 let Inst{31-21} = 0b11010011101;
2027 let prefersSlot3 = 1;
2029 def A2_vminuw : HInst<
2030 (outs DoubleRegs:$Rdd32),
2031 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2032 "$Rdd32 = vminuw($Rtt32,$Rss32)",
2033 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2034 let Inst{7-5} = 0b100;
2035 let Inst{13-13} = 0b0;
2036 let Inst{31-21} = 0b11010011101;
2037 let prefersSlot3 = 1;
2039 def A2_vminw : HInst<
2040 (outs DoubleRegs:$Rdd32),
2041 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2042 "$Rdd32 = vminw($Rtt32,$Rss32)",
2043 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2044 let Inst{7-5} = 0b011;
2045 let Inst{13-13} = 0b0;
2046 let Inst{31-21} = 0b11010011101;
2047 let prefersSlot3 = 1;
2049 def A2_vnavgh : HInst<
2050 (outs DoubleRegs:$Rdd32),
2051 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2052 "$Rdd32 = vnavgh($Rtt32,$Rss32)",
2053 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2054 let Inst{7-5} = 0b000;
2055 let Inst{13-13} = 0b0;
2056 let Inst{31-21} = 0b11010011100;
2058 def A2_vnavghcr : HInst<
2059 (outs DoubleRegs:$Rdd32),
2060 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2061 "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2062 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
2063 let Inst{7-5} = 0b010;
2064 let Inst{13-13} = 0b0;
2065 let Inst{31-21} = 0b11010011100;
2066 let prefersSlot3 = 1;
2067 let Defs = [USR_OVF];
2069 def A2_vnavghr : HInst<
2070 (outs DoubleRegs:$Rdd32),
2071 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2072 "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2073 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
2074 let Inst{7-5} = 0b001;
2075 let Inst{13-13} = 0b0;
2076 let Inst{31-21} = 0b11010011100;
2077 let prefersSlot3 = 1;
2078 let Defs = [USR_OVF];
2080 def A2_vnavgw : HInst<
2081 (outs DoubleRegs:$Rdd32),
2082 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2083 "$Rdd32 = vnavgw($Rtt32,$Rss32)",
2084 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2085 let Inst{7-5} = 0b011;
2086 let Inst{13-13} = 0b0;
2087 let Inst{31-21} = 0b11010011100;
2089 def A2_vnavgwcr : HInst<
2090 (outs DoubleRegs:$Rdd32),
2091 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2092 "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2093 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
2094 let Inst{7-5} = 0b110;
2095 let Inst{13-13} = 0b0;
2096 let Inst{31-21} = 0b11010011100;
2097 let prefersSlot3 = 1;
2098 let Defs = [USR_OVF];
2100 def A2_vnavgwr : HInst<
2101 (outs DoubleRegs:$Rdd32),
2102 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2103 "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2104 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
2105 let Inst{7-5} = 0b100;
2106 let Inst{13-13} = 0b0;
2107 let Inst{31-21} = 0b11010011100;
2108 let prefersSlot3 = 1;
2109 let Defs = [USR_OVF];
2111 def A2_vraddub : HInst<
2112 (outs DoubleRegs:$Rdd32),
2113 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2114 "$Rdd32 = vraddub($Rss32,$Rtt32)",
2115 tc_8fd5f294, TypeM>, Enc_a56825 {
2116 let Inst{7-5} = 0b001;
2117 let Inst{13-13} = 0b0;
2118 let Inst{31-21} = 0b11101000010;
2119 let prefersSlot3 = 1;
2121 def A2_vraddub_acc : HInst<
2122 (outs DoubleRegs:$Rxx32),
2123 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2124 "$Rxx32 += vraddub($Rss32,$Rtt32)",
2125 tc_e913dc32, TypeM>, Enc_88c16c {
2126 let Inst{7-5} = 0b001;
2127 let Inst{13-13} = 0b0;
2128 let Inst{31-21} = 0b11101010010;
2129 let prefersSlot3 = 1;
2130 let Constraints = "$Rxx32 = $Rxx32in";
2132 def A2_vrsadub : HInst<
2133 (outs DoubleRegs:$Rdd32),
2134 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2135 "$Rdd32 = vrsadub($Rss32,$Rtt32)",
2136 tc_8fd5f294, TypeM>, Enc_a56825 {
2137 let Inst{7-5} = 0b010;
2138 let Inst{13-13} = 0b0;
2139 let Inst{31-21} = 0b11101000010;
2140 let prefersSlot3 = 1;
2142 def A2_vrsadub_acc : HInst<
2143 (outs DoubleRegs:$Rxx32),
2144 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2145 "$Rxx32 += vrsadub($Rss32,$Rtt32)",
2146 tc_e913dc32, TypeM>, Enc_88c16c {
2147 let Inst{7-5} = 0b010;
2148 let Inst{13-13} = 0b0;
2149 let Inst{31-21} = 0b11101010010;
2150 let prefersSlot3 = 1;
2151 let Constraints = "$Rxx32 = $Rxx32in";
2153 def A2_vsubb_map : HInst<
2154 (outs DoubleRegs:$Rdd32),
2155 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2156 "$Rdd32 = vsubb($Rss32,$Rtt32)",
2157 tc_540fdfbc, TypeMAPPING> {
2159 let isCodeGenOnly = 1;
2161 def A2_vsubh : HInst<
2162 (outs DoubleRegs:$Rdd32),
2163 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2164 "$Rdd32 = vsubh($Rtt32,$Rss32)",
2165 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2166 let Inst{7-5} = 0b010;
2167 let Inst{13-13} = 0b0;
2168 let Inst{31-21} = 0b11010011001;
2170 def A2_vsubhs : HInst<
2171 (outs DoubleRegs:$Rdd32),
2172 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2173 "$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2174 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2175 let Inst{7-5} = 0b011;
2176 let Inst{13-13} = 0b0;
2177 let Inst{31-21} = 0b11010011001;
2178 let prefersSlot3 = 1;
2179 let Defs = [USR_OVF];
2181 def A2_vsubub : HInst<
2182 (outs DoubleRegs:$Rdd32),
2183 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2184 "$Rdd32 = vsubub($Rtt32,$Rss32)",
2185 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2186 let Inst{7-5} = 0b000;
2187 let Inst{13-13} = 0b0;
2188 let Inst{31-21} = 0b11010011001;
2190 def A2_vsububs : HInst<
2191 (outs DoubleRegs:$Rdd32),
2192 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2193 "$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2194 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2195 let Inst{7-5} = 0b001;
2196 let Inst{13-13} = 0b0;
2197 let Inst{31-21} = 0b11010011001;
2198 let prefersSlot3 = 1;
2199 let Defs = [USR_OVF];
2201 def A2_vsubuhs : HInst<
2202 (outs DoubleRegs:$Rdd32),
2203 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2204 "$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2205 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2206 let Inst{7-5} = 0b100;
2207 let Inst{13-13} = 0b0;
2208 let Inst{31-21} = 0b11010011001;
2209 let prefersSlot3 = 1;
2210 let Defs = [USR_OVF];
2212 def A2_vsubw : HInst<
2213 (outs DoubleRegs:$Rdd32),
2214 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2215 "$Rdd32 = vsubw($Rtt32,$Rss32)",
2216 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2217 let Inst{7-5} = 0b101;
2218 let Inst{13-13} = 0b0;
2219 let Inst{31-21} = 0b11010011001;
2221 def A2_vsubws : HInst<
2222 (outs DoubleRegs:$Rdd32),
2223 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2224 "$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2225 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
2226 let Inst{7-5} = 0b110;
2227 let Inst{13-13} = 0b0;
2228 let Inst{31-21} = 0b11010011001;
2229 let prefersSlot3 = 1;
2230 let Defs = [USR_OVF];
2233 (outs IntRegs:$Rd32),
2234 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2235 "$Rd32 = xor($Rs32,$Rt32)",
2236 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2237 let Inst{7-5} = 0b000;
2238 let Inst{13-13} = 0b0;
2239 let Inst{31-21} = 0b11110001011;
2240 let hasNewValue = 1;
2242 let InputType = "reg";
2243 let BaseOpcode = "A2_xor";
2244 let isCommutable = 1;
2245 let isPredicable = 1;
2247 def A2_xorp : HInst<
2248 (outs DoubleRegs:$Rdd32),
2249 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2250 "$Rdd32 = xor($Rss32,$Rtt32)",
2251 tc_540fdfbc, TypeALU64>, Enc_a56825 {
2252 let Inst{7-5} = 0b100;
2253 let Inst{13-13} = 0b0;
2254 let Inst{31-21} = 0b11010011111;
2255 let isCommutable = 1;
2257 def A2_zxtb : HInst<
2258 (outs IntRegs:$Rd32),
2259 (ins IntRegs:$Rs32),
2260 "$Rd32 = zxtb($Rs32)",
2261 tc_b9488031, TypeALU32_2op>, PredNewRel {
2262 let hasNewValue = 1;
2264 let BaseOpcode = "A2_zxtb";
2265 let isPredicable = 1;
2267 let isCodeGenOnly = 1;
2269 def A2_zxth : HInst<
2270 (outs IntRegs:$Rd32),
2271 (ins IntRegs:$Rs32),
2272 "$Rd32 = zxth($Rs32)",
2273 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2274 let Inst{13-5} = 0b000000000;
2275 let Inst{31-21} = 0b01110000110;
2276 let hasNewValue = 1;
2278 let BaseOpcode = "A2_zxth";
2279 let isPredicable = 1;
2281 def A4_addp_c : HInst<
2282 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2283 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2284 "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2285 tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
2286 let Inst{7-7} = 0b0;
2287 let Inst{13-13} = 0b0;
2288 let Inst{31-21} = 0b11000010110;
2289 let isPredicateLate = 1;
2290 let Constraints = "$Px4 = $Px4in";
2292 def A4_andn : HInst<
2293 (outs IntRegs:$Rd32),
2294 (ins IntRegs:$Rt32, IntRegs:$Rs32),
2295 "$Rd32 = and($Rt32,~$Rs32)",
2296 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
2297 let Inst{7-5} = 0b000;
2298 let Inst{13-13} = 0b0;
2299 let Inst{31-21} = 0b11110001100;
2300 let hasNewValue = 1;
2302 let InputType = "reg";
2304 def A4_andnp : HInst<
2305 (outs DoubleRegs:$Rdd32),
2306 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2307 "$Rdd32 = and($Rtt32,~$Rss32)",
2308 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2309 let Inst{7-5} = 0b001;
2310 let Inst{13-13} = 0b0;
2311 let Inst{31-21} = 0b11010011111;
2313 def A4_bitsplit : HInst<
2314 (outs DoubleRegs:$Rdd32),
2315 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2316 "$Rdd32 = bitsplit($Rs32,$Rt32)",
2317 tc_1b9c9ee5, TypeALU64>, Enc_be32a5 {
2318 let Inst{7-5} = 0b000;
2319 let Inst{13-13} = 0b0;
2320 let Inst{31-21} = 0b11010100001;
2321 let prefersSlot3 = 1;
2323 def A4_bitspliti : HInst<
2324 (outs DoubleRegs:$Rdd32),
2325 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
2326 "$Rdd32 = bitsplit($Rs32,#$Ii)",
2327 tc_1b9c9ee5, TypeS_2op>, Enc_311abd {
2328 let Inst{7-5} = 0b100;
2329 let Inst{13-13} = 0b0;
2330 let Inst{31-21} = 0b10001000110;
2331 let prefersSlot3 = 1;
2333 def A4_boundscheck : HInst<
2334 (outs PredRegs:$Pd4),
2335 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2336 "$Pd4 = boundscheck($Rs32,$Rtt32)",
2337 tc_1e856f58, TypeALU64> {
2340 def A4_boundscheck_hi : HInst<
2341 (outs PredRegs:$Pd4),
2342 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2343 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2344 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
2345 let Inst{7-2} = 0b101000;
2346 let Inst{13-13} = 0b1;
2347 let Inst{31-21} = 0b11010010000;
2349 def A4_boundscheck_lo : HInst<
2350 (outs PredRegs:$Pd4),
2351 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2352 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2353 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
2354 let Inst{7-2} = 0b100000;
2355 let Inst{13-13} = 0b1;
2356 let Inst{31-21} = 0b11010010000;
2358 def A4_cmpbeq : HInst<
2359 (outs PredRegs:$Pd4),
2360 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2361 "$Pd4 = cmpb.eq($Rs32,$Rt32)",
2362 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2363 let Inst{7-2} = 0b110000;
2364 let Inst{13-13} = 0b0;
2365 let Inst{31-21} = 0b11000111110;
2366 let CextOpcode = "A4_cmpbeq";
2367 let InputType = "reg";
2368 let isCommutable = 1;
2371 def A4_cmpbeqi : HInst<
2372 (outs PredRegs:$Pd4),
2373 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
2374 "$Pd4 = cmpb.eq($Rs32,#$Ii)",
2375 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
2376 let Inst{4-2} = 0b000;
2377 let Inst{13-13} = 0b0;
2378 let Inst{31-21} = 0b11011101000;
2379 let CextOpcode = "A4_cmpbeq";
2380 let InputType = "imm";
2381 let isCommutable = 1;
2384 def A4_cmpbgt : HInst<
2385 (outs PredRegs:$Pd4),
2386 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2387 "$Pd4 = cmpb.gt($Rs32,$Rt32)",
2388 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2389 let Inst{7-2} = 0b010000;
2390 let Inst{13-13} = 0b0;
2391 let Inst{31-21} = 0b11000111110;
2392 let CextOpcode = "A4_cmpbgt";
2393 let InputType = "reg";
2396 def A4_cmpbgti : HInst<
2397 (outs PredRegs:$Pd4),
2398 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
2399 "$Pd4 = cmpb.gt($Rs32,#$Ii)",
2400 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
2401 let Inst{4-2} = 0b000;
2402 let Inst{13-13} = 0b0;
2403 let Inst{31-21} = 0b11011101001;
2404 let CextOpcode = "A4_cmpbgt";
2405 let InputType = "imm";
2408 def A4_cmpbgtu : HInst<
2409 (outs PredRegs:$Pd4),
2410 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2411 "$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2412 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2413 let Inst{7-2} = 0b111000;
2414 let Inst{13-13} = 0b0;
2415 let Inst{31-21} = 0b11000111110;
2416 let CextOpcode = "A4_cmpbgtu";
2417 let InputType = "reg";
2420 def A4_cmpbgtui : HInst<
2421 (outs PredRegs:$Pd4),
2422 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
2423 "$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2424 tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
2425 let Inst{4-2} = 0b000;
2426 let Inst{13-12} = 0b00;
2427 let Inst{31-21} = 0b11011101010;
2428 let CextOpcode = "A4_cmpbgtu";
2429 let InputType = "imm";
2431 let isExtendable = 1;
2432 let opExtendable = 2;
2433 let isExtentSigned = 0;
2434 let opExtentBits = 7;
2435 let opExtentAlign = 0;
2437 def A4_cmpheq : HInst<
2438 (outs PredRegs:$Pd4),
2439 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2440 "$Pd4 = cmph.eq($Rs32,$Rt32)",
2441 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2442 let Inst{7-2} = 0b011000;
2443 let Inst{13-13} = 0b0;
2444 let Inst{31-21} = 0b11000111110;
2445 let CextOpcode = "A4_cmpheq";
2446 let InputType = "reg";
2447 let isCommutable = 1;
2450 def A4_cmpheqi : HInst<
2451 (outs PredRegs:$Pd4),
2452 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
2453 "$Pd4 = cmph.eq($Rs32,#$Ii)",
2454 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
2455 let Inst{4-2} = 0b010;
2456 let Inst{13-13} = 0b0;
2457 let Inst{31-21} = 0b11011101000;
2458 let CextOpcode = "A4_cmpheq";
2459 let InputType = "imm";
2460 let isCommutable = 1;
2462 let isExtendable = 1;
2463 let opExtendable = 2;
2464 let isExtentSigned = 1;
2465 let opExtentBits = 8;
2466 let opExtentAlign = 0;
2468 def A4_cmphgt : HInst<
2469 (outs PredRegs:$Pd4),
2470 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2471 "$Pd4 = cmph.gt($Rs32,$Rt32)",
2472 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2473 let Inst{7-2} = 0b100000;
2474 let Inst{13-13} = 0b0;
2475 let Inst{31-21} = 0b11000111110;
2476 let CextOpcode = "A4_cmphgt";
2477 let InputType = "reg";
2480 def A4_cmphgti : HInst<
2481 (outs PredRegs:$Pd4),
2482 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
2483 "$Pd4 = cmph.gt($Rs32,#$Ii)",
2484 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
2485 let Inst{4-2} = 0b010;
2486 let Inst{13-13} = 0b0;
2487 let Inst{31-21} = 0b11011101001;
2488 let CextOpcode = "A4_cmphgt";
2489 let InputType = "imm";
2491 let isExtendable = 1;
2492 let opExtendable = 2;
2493 let isExtentSigned = 1;
2494 let opExtentBits = 8;
2495 let opExtentAlign = 0;
2497 def A4_cmphgtu : HInst<
2498 (outs PredRegs:$Pd4),
2499 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2500 "$Pd4 = cmph.gtu($Rs32,$Rt32)",
2501 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2502 let Inst{7-2} = 0b101000;
2503 let Inst{13-13} = 0b0;
2504 let Inst{31-21} = 0b11000111110;
2505 let CextOpcode = "A4_cmphgtu";
2506 let InputType = "reg";
2509 def A4_cmphgtui : HInst<
2510 (outs PredRegs:$Pd4),
2511 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
2512 "$Pd4 = cmph.gtu($Rs32,#$Ii)",
2513 tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
2514 let Inst{4-2} = 0b010;
2515 let Inst{13-12} = 0b00;
2516 let Inst{31-21} = 0b11011101010;
2517 let CextOpcode = "A4_cmphgtu";
2518 let InputType = "imm";
2520 let isExtendable = 1;
2521 let opExtendable = 2;
2522 let isExtentSigned = 0;
2523 let opExtentBits = 7;
2524 let opExtentAlign = 0;
2526 def A4_combineii : HInst<
2527 (outs DoubleRegs:$Rdd32),
2528 (ins s8_0Imm:$Ii, u32_0Imm:$II),
2529 "$Rdd32 = combine(#$Ii,#$II)",
2530 tc_b9488031, TypeALU32_2op>, Enc_f0cca7 {
2531 let Inst{31-21} = 0b01111100100;
2532 let isExtendable = 1;
2533 let opExtendable = 2;
2534 let isExtentSigned = 0;
2535 let opExtentBits = 6;
2536 let opExtentAlign = 0;
2538 def A4_combineir : HInst<
2539 (outs DoubleRegs:$Rdd32),
2540 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
2541 "$Rdd32 = combine(#$Ii,$Rs32)",
2542 tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
2543 let Inst{13-13} = 0b1;
2544 let Inst{31-21} = 0b01110011001;
2545 let isExtendable = 1;
2546 let opExtendable = 1;
2547 let isExtentSigned = 1;
2548 let opExtentBits = 8;
2549 let opExtentAlign = 0;
2551 def A4_combineri : HInst<
2552 (outs DoubleRegs:$Rdd32),
2553 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
2554 "$Rdd32 = combine($Rs32,#$Ii)",
2555 tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
2556 let Inst{13-13} = 0b1;
2557 let Inst{31-21} = 0b01110011000;
2558 let isExtendable = 1;
2559 let opExtendable = 2;
2560 let isExtentSigned = 1;
2561 let opExtentBits = 8;
2562 let opExtentAlign = 0;
2564 def A4_cround_ri : HInst<
2565 (outs IntRegs:$Rd32),
2566 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
2567 "$Rd32 = cround($Rs32,#$Ii)",
2568 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
2569 let Inst{7-5} = 0b000;
2570 let Inst{13-13} = 0b0;
2571 let Inst{31-21} = 0b10001100111;
2572 let hasNewValue = 1;
2574 let prefersSlot3 = 1;
2576 def A4_cround_rr : HInst<
2577 (outs IntRegs:$Rd32),
2578 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2579 "$Rd32 = cround($Rs32,$Rt32)",
2580 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
2581 let Inst{7-5} = 0b000;
2582 let Inst{13-13} = 0b0;
2583 let Inst{31-21} = 0b11000110110;
2584 let hasNewValue = 1;
2586 let prefersSlot3 = 1;
2592 tc_452f85af, TypeEXTENDER>, Enc_2b518f {
2593 let Inst{31-28} = 0b0000;
2595 def A4_modwrapu : HInst<
2596 (outs IntRegs:$Rd32),
2597 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2598 "$Rd32 = modwrap($Rs32,$Rt32)",
2599 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
2600 let Inst{7-5} = 0b111;
2601 let Inst{13-13} = 0b0;
2602 let Inst{31-21} = 0b11010011111;
2603 let hasNewValue = 1;
2605 let prefersSlot3 = 1;
2608 (outs IntRegs:$Rd32),
2609 (ins IntRegs:$Rt32, IntRegs:$Rs32),
2610 "$Rd32 = or($Rt32,~$Rs32)",
2611 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
2612 let Inst{7-5} = 0b000;
2613 let Inst{13-13} = 0b0;
2614 let Inst{31-21} = 0b11110001101;
2615 let hasNewValue = 1;
2617 let InputType = "reg";
2619 def A4_ornp : HInst<
2620 (outs DoubleRegs:$Rdd32),
2621 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2622 "$Rdd32 = or($Rtt32,~$Rss32)",
2623 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
2624 let Inst{7-5} = 0b011;
2625 let Inst{13-13} = 0b0;
2626 let Inst{31-21} = 0b11010011111;
2628 def A4_paslhf : HInst<
2629 (outs IntRegs:$Rd32),
2630 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2631 "if (!$Pu4) $Rd32 = aslh($Rs32)",
2632 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2633 let Inst{7-5} = 0b000;
2634 let Inst{13-10} = 0b1010;
2635 let Inst{31-21} = 0b01110000000;
2636 let isPredicated = 1;
2637 let isPredicatedFalse = 1;
2638 let hasNewValue = 1;
2640 let BaseOpcode = "A2_aslh";
2642 def A4_paslhfnew : HInst<
2643 (outs IntRegs:$Rd32),
2644 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2645 "if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2646 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2647 let Inst{7-5} = 0b000;
2648 let Inst{13-10} = 0b1011;
2649 let Inst{31-21} = 0b01110000000;
2650 let isPredicated = 1;
2651 let isPredicatedFalse = 1;
2652 let hasNewValue = 1;
2654 let isPredicatedNew = 1;
2655 let BaseOpcode = "A2_aslh";
2657 def A4_paslht : HInst<
2658 (outs IntRegs:$Rd32),
2659 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2660 "if ($Pu4) $Rd32 = aslh($Rs32)",
2661 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2662 let Inst{7-5} = 0b000;
2663 let Inst{13-10} = 0b1000;
2664 let Inst{31-21} = 0b01110000000;
2665 let isPredicated = 1;
2666 let hasNewValue = 1;
2668 let BaseOpcode = "A2_aslh";
2670 def A4_paslhtnew : HInst<
2671 (outs IntRegs:$Rd32),
2672 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2673 "if ($Pu4.new) $Rd32 = aslh($Rs32)",
2674 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675 let Inst{7-5} = 0b000;
2676 let Inst{13-10} = 0b1001;
2677 let Inst{31-21} = 0b01110000000;
2678 let isPredicated = 1;
2679 let hasNewValue = 1;
2681 let isPredicatedNew = 1;
2682 let BaseOpcode = "A2_aslh";
2684 def A4_pasrhf : HInst<
2685 (outs IntRegs:$Rd32),
2686 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2687 "if (!$Pu4) $Rd32 = asrh($Rs32)",
2688 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2689 let Inst{7-5} = 0b000;
2690 let Inst{13-10} = 0b1010;
2691 let Inst{31-21} = 0b01110000001;
2692 let isPredicated = 1;
2693 let isPredicatedFalse = 1;
2694 let hasNewValue = 1;
2696 let BaseOpcode = "A2_asrh";
2698 def A4_pasrhfnew : HInst<
2699 (outs IntRegs:$Rd32),
2700 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2701 "if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2702 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2703 let Inst{7-5} = 0b000;
2704 let Inst{13-10} = 0b1011;
2705 let Inst{31-21} = 0b01110000001;
2706 let isPredicated = 1;
2707 let isPredicatedFalse = 1;
2708 let hasNewValue = 1;
2710 let isPredicatedNew = 1;
2711 let BaseOpcode = "A2_asrh";
2713 def A4_pasrht : HInst<
2714 (outs IntRegs:$Rd32),
2715 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2716 "if ($Pu4) $Rd32 = asrh($Rs32)",
2717 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2718 let Inst{7-5} = 0b000;
2719 let Inst{13-10} = 0b1000;
2720 let Inst{31-21} = 0b01110000001;
2721 let isPredicated = 1;
2722 let hasNewValue = 1;
2724 let BaseOpcode = "A2_asrh";
2726 def A4_pasrhtnew : HInst<
2727 (outs IntRegs:$Rd32),
2728 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2729 "if ($Pu4.new) $Rd32 = asrh($Rs32)",
2730 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731 let Inst{7-5} = 0b000;
2732 let Inst{13-10} = 0b1001;
2733 let Inst{31-21} = 0b01110000001;
2734 let isPredicated = 1;
2735 let hasNewValue = 1;
2737 let isPredicatedNew = 1;
2738 let BaseOpcode = "A2_asrh";
2740 def A4_psxtbf : HInst<
2741 (outs IntRegs:$Rd32),
2742 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2743 "if (!$Pu4) $Rd32 = sxtb($Rs32)",
2744 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2745 let Inst{7-5} = 0b000;
2746 let Inst{13-10} = 0b1010;
2747 let Inst{31-21} = 0b01110000101;
2748 let isPredicated = 1;
2749 let isPredicatedFalse = 1;
2750 let hasNewValue = 1;
2752 let BaseOpcode = "A2_sxtb";
2754 def A4_psxtbfnew : HInst<
2755 (outs IntRegs:$Rd32),
2756 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2757 "if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2758 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2759 let Inst{7-5} = 0b000;
2760 let Inst{13-10} = 0b1011;
2761 let Inst{31-21} = 0b01110000101;
2762 let isPredicated = 1;
2763 let isPredicatedFalse = 1;
2764 let hasNewValue = 1;
2766 let isPredicatedNew = 1;
2767 let BaseOpcode = "A2_sxtb";
2769 def A4_psxtbt : HInst<
2770 (outs IntRegs:$Rd32),
2771 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2772 "if ($Pu4) $Rd32 = sxtb($Rs32)",
2773 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2774 let Inst{7-5} = 0b000;
2775 let Inst{13-10} = 0b1000;
2776 let Inst{31-21} = 0b01110000101;
2777 let isPredicated = 1;
2778 let hasNewValue = 1;
2780 let BaseOpcode = "A2_sxtb";
2782 def A4_psxtbtnew : HInst<
2783 (outs IntRegs:$Rd32),
2784 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2785 "if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2786 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787 let Inst{7-5} = 0b000;
2788 let Inst{13-10} = 0b1001;
2789 let Inst{31-21} = 0b01110000101;
2790 let isPredicated = 1;
2791 let hasNewValue = 1;
2793 let isPredicatedNew = 1;
2794 let BaseOpcode = "A2_sxtb";
2796 def A4_psxthf : HInst<
2797 (outs IntRegs:$Rd32),
2798 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2799 "if (!$Pu4) $Rd32 = sxth($Rs32)",
2800 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2801 let Inst{7-5} = 0b000;
2802 let Inst{13-10} = 0b1010;
2803 let Inst{31-21} = 0b01110000111;
2804 let isPredicated = 1;
2805 let isPredicatedFalse = 1;
2806 let hasNewValue = 1;
2808 let BaseOpcode = "A2_sxth";
2810 def A4_psxthfnew : HInst<
2811 (outs IntRegs:$Rd32),
2812 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2813 "if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2814 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2815 let Inst{7-5} = 0b000;
2816 let Inst{13-10} = 0b1011;
2817 let Inst{31-21} = 0b01110000111;
2818 let isPredicated = 1;
2819 let isPredicatedFalse = 1;
2820 let hasNewValue = 1;
2822 let isPredicatedNew = 1;
2823 let BaseOpcode = "A2_sxth";
2825 def A4_psxtht : HInst<
2826 (outs IntRegs:$Rd32),
2827 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2828 "if ($Pu4) $Rd32 = sxth($Rs32)",
2829 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2830 let Inst{7-5} = 0b000;
2831 let Inst{13-10} = 0b1000;
2832 let Inst{31-21} = 0b01110000111;
2833 let isPredicated = 1;
2834 let hasNewValue = 1;
2836 let BaseOpcode = "A2_sxth";
2838 def A4_psxthtnew : HInst<
2839 (outs IntRegs:$Rd32),
2840 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2841 "if ($Pu4.new) $Rd32 = sxth($Rs32)",
2842 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843 let Inst{7-5} = 0b000;
2844 let Inst{13-10} = 0b1001;
2845 let Inst{31-21} = 0b01110000111;
2846 let isPredicated = 1;
2847 let hasNewValue = 1;
2849 let isPredicatedNew = 1;
2850 let BaseOpcode = "A2_sxth";
2852 def A4_pzxtbf : HInst<
2853 (outs IntRegs:$Rd32),
2854 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2855 "if (!$Pu4) $Rd32 = zxtb($Rs32)",
2856 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2857 let Inst{7-5} = 0b000;
2858 let Inst{13-10} = 0b1010;
2859 let Inst{31-21} = 0b01110000100;
2860 let isPredicated = 1;
2861 let isPredicatedFalse = 1;
2862 let hasNewValue = 1;
2864 let BaseOpcode = "A2_zxtb";
2866 def A4_pzxtbfnew : HInst<
2867 (outs IntRegs:$Rd32),
2868 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2869 "if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2870 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2871 let Inst{7-5} = 0b000;
2872 let Inst{13-10} = 0b1011;
2873 let Inst{31-21} = 0b01110000100;
2874 let isPredicated = 1;
2875 let isPredicatedFalse = 1;
2876 let hasNewValue = 1;
2878 let isPredicatedNew = 1;
2879 let BaseOpcode = "A2_zxtb";
2881 def A4_pzxtbt : HInst<
2882 (outs IntRegs:$Rd32),
2883 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2884 "if ($Pu4) $Rd32 = zxtb($Rs32)",
2885 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2886 let Inst{7-5} = 0b000;
2887 let Inst{13-10} = 0b1000;
2888 let Inst{31-21} = 0b01110000100;
2889 let isPredicated = 1;
2890 let hasNewValue = 1;
2892 let BaseOpcode = "A2_zxtb";
2894 def A4_pzxtbtnew : HInst<
2895 (outs IntRegs:$Rd32),
2896 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2897 "if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2898 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899 let Inst{7-5} = 0b000;
2900 let Inst{13-10} = 0b1001;
2901 let Inst{31-21} = 0b01110000100;
2902 let isPredicated = 1;
2903 let hasNewValue = 1;
2905 let isPredicatedNew = 1;
2906 let BaseOpcode = "A2_zxtb";
2908 def A4_pzxthf : HInst<
2909 (outs IntRegs:$Rd32),
2910 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2911 "if (!$Pu4) $Rd32 = zxth($Rs32)",
2912 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2913 let Inst{7-5} = 0b000;
2914 let Inst{13-10} = 0b1010;
2915 let Inst{31-21} = 0b01110000110;
2916 let isPredicated = 1;
2917 let isPredicatedFalse = 1;
2918 let hasNewValue = 1;
2920 let BaseOpcode = "A2_zxth";
2922 def A4_pzxthfnew : HInst<
2923 (outs IntRegs:$Rd32),
2924 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2925 "if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2926 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2927 let Inst{7-5} = 0b000;
2928 let Inst{13-10} = 0b1011;
2929 let Inst{31-21} = 0b01110000110;
2930 let isPredicated = 1;
2931 let isPredicatedFalse = 1;
2932 let hasNewValue = 1;
2934 let isPredicatedNew = 1;
2935 let BaseOpcode = "A2_zxth";
2937 def A4_pzxtht : HInst<
2938 (outs IntRegs:$Rd32),
2939 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2940 "if ($Pu4) $Rd32 = zxth($Rs32)",
2941 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2942 let Inst{7-5} = 0b000;
2943 let Inst{13-10} = 0b1000;
2944 let Inst{31-21} = 0b01110000110;
2945 let isPredicated = 1;
2946 let hasNewValue = 1;
2948 let BaseOpcode = "A2_zxth";
2950 def A4_pzxthtnew : HInst<
2951 (outs IntRegs:$Rd32),
2952 (ins PredRegs:$Pu4, IntRegs:$Rs32),
2953 "if ($Pu4.new) $Rd32 = zxth($Rs32)",
2954 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955 let Inst{7-5} = 0b000;
2956 let Inst{13-10} = 0b1001;
2957 let Inst{31-21} = 0b01110000110;
2958 let isPredicated = 1;
2959 let hasNewValue = 1;
2961 let isPredicatedNew = 1;
2962 let BaseOpcode = "A2_zxth";
2964 def A4_rcmpeq : HInst<
2965 (outs IntRegs:$Rd32),
2966 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2967 "$Rd32 = cmp.eq($Rs32,$Rt32)",
2968 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2969 let Inst{7-5} = 0b000;
2970 let Inst{13-13} = 0b0;
2971 let Inst{31-21} = 0b11110011010;
2972 let hasNewValue = 1;
2974 let CextOpcode = "A4_rcmpeq";
2975 let InputType = "reg";
2976 let isCommutable = 1;
2978 def A4_rcmpeqi : HInst<
2979 (outs IntRegs:$Rd32),
2980 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
2981 "$Rd32 = cmp.eq($Rs32,#$Ii)",
2982 tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2983 let Inst{13-13} = 0b1;
2984 let Inst{31-21} = 0b01110011010;
2985 let hasNewValue = 1;
2987 let CextOpcode = "A4_rcmpeqi";
2988 let InputType = "imm";
2989 let isExtendable = 1;
2990 let opExtendable = 2;
2991 let isExtentSigned = 1;
2992 let opExtentBits = 8;
2993 let opExtentAlign = 0;
2995 def A4_rcmpneq : HInst<
2996 (outs IntRegs:$Rd32),
2997 (ins IntRegs:$Rs32, IntRegs:$Rt32),
2998 "$Rd32 = !cmp.eq($Rs32,$Rt32)",
2999 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3000 let Inst{7-5} = 0b000;
3001 let Inst{13-13} = 0b0;
3002 let Inst{31-21} = 0b11110011011;
3003 let hasNewValue = 1;
3005 let CextOpcode = "A4_rcmpneq";
3006 let InputType = "reg";
3007 let isCommutable = 1;
3009 def A4_rcmpneqi : HInst<
3010 (outs IntRegs:$Rd32),
3011 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
3012 "$Rd32 = !cmp.eq($Rs32,#$Ii)",
3013 tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3014 let Inst{13-13} = 0b1;
3015 let Inst{31-21} = 0b01110011011;
3016 let hasNewValue = 1;
3018 let CextOpcode = "A4_rcmpeqi";
3019 let InputType = "imm";
3020 let isExtendable = 1;
3021 let opExtendable = 2;
3022 let isExtentSigned = 1;
3023 let opExtentBits = 8;
3024 let opExtentAlign = 0;
3026 def A4_round_ri : HInst<
3027 (outs IntRegs:$Rd32),
3028 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
3029 "$Rd32 = round($Rs32,#$Ii)",
3030 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
3031 let Inst{7-5} = 0b100;
3032 let Inst{13-13} = 0b0;
3033 let Inst{31-21} = 0b10001100111;
3034 let hasNewValue = 1;
3036 let prefersSlot3 = 1;
3038 def A4_round_ri_sat : HInst<
3039 (outs IntRegs:$Rd32),
3040 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
3041 "$Rd32 = round($Rs32,#$Ii):sat",
3042 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
3043 let Inst{7-5} = 0b110;
3044 let Inst{13-13} = 0b0;
3045 let Inst{31-21} = 0b10001100111;
3046 let hasNewValue = 1;
3048 let prefersSlot3 = 1;
3049 let Defs = [USR_OVF];
3051 def A4_round_rr : HInst<
3052 (outs IntRegs:$Rd32),
3053 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3054 "$Rd32 = round($Rs32,$Rt32)",
3055 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
3056 let Inst{7-5} = 0b100;
3057 let Inst{13-13} = 0b0;
3058 let Inst{31-21} = 0b11000110110;
3059 let hasNewValue = 1;
3061 let prefersSlot3 = 1;
3063 def A4_round_rr_sat : HInst<
3064 (outs IntRegs:$Rd32),
3065 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3066 "$Rd32 = round($Rs32,$Rt32):sat",
3067 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
3068 let Inst{7-5} = 0b110;
3069 let Inst{13-13} = 0b0;
3070 let Inst{31-21} = 0b11000110110;
3071 let hasNewValue = 1;
3073 let prefersSlot3 = 1;
3074 let Defs = [USR_OVF];
3076 def A4_subp_c : HInst<
3077 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3078 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3079 "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3080 tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
3081 let Inst{7-7} = 0b0;
3082 let Inst{13-13} = 0b0;
3083 let Inst{31-21} = 0b11000010111;
3084 let isPredicateLate = 1;
3085 let Constraints = "$Px4 = $Px4in";
3087 def A4_tfrcpp : HInst<
3088 (outs DoubleRegs:$Rdd32),
3089 (ins CtrRegs64:$Css32),
3091 tc_29175780, TypeCR>, Enc_667b39 {
3092 let Inst{13-5} = 0b000000000;
3093 let Inst{31-21} = 0b01101000000;
3095 def A4_tfrpcp : HInst<
3096 (outs CtrRegs64:$Cdd32),
3097 (ins DoubleRegs:$Rss32),
3099 tc_a21dc435, TypeCR>, Enc_0ed752 {
3100 let Inst{13-5} = 0b000000000;
3101 let Inst{31-21} = 0b01100011001;
3103 def A4_tlbmatch : HInst<
3104 (outs PredRegs:$Pd4),
3105 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3106 "$Pd4 = tlbmatch($Rss32,$Rt32)",
3107 tc_04c9decc, TypeALU64>, Enc_03833b {
3108 let Inst{7-2} = 0b011000;
3109 let Inst{13-13} = 0b1;
3110 let Inst{31-21} = 0b11010010000;
3111 let isPredicateLate = 1;
3113 def A4_vcmpbeq_any : HInst<
3114 (outs PredRegs:$Pd4),
3115 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3116 "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3117 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
3118 let Inst{7-2} = 0b000000;
3119 let Inst{13-13} = 0b1;
3120 let Inst{31-21} = 0b11010010000;
3122 def A4_vcmpbeqi : HInst<
3123 (outs PredRegs:$Pd4),
3124 (ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3125 "$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3126 tc_7a830544, TypeALU64>, Enc_0d8adb {
3127 let Inst{4-2} = 0b000;
3128 let Inst{13-13} = 0b0;
3129 let Inst{31-21} = 0b11011100000;
3131 def A4_vcmpbgt : HInst<
3132 (outs PredRegs:$Pd4),
3133 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3134 "$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3135 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
3136 let Inst{7-2} = 0b010000;
3137 let Inst{13-13} = 0b1;
3138 let Inst{31-21} = 0b11010010000;
3140 def A4_vcmpbgti : HInst<
3141 (outs PredRegs:$Pd4),
3142 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3143 "$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3144 tc_7a830544, TypeALU64>, Enc_0d8adb {
3145 let Inst{4-2} = 0b000;
3146 let Inst{13-13} = 0b0;
3147 let Inst{31-21} = 0b11011100001;
3149 def A4_vcmpbgtui : HInst<
3150 (outs PredRegs:$Pd4),
3151 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3152 "$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3153 tc_7a830544, TypeALU64>, Enc_3680c2 {
3154 let Inst{4-2} = 0b000;
3155 let Inst{13-12} = 0b00;
3156 let Inst{31-21} = 0b11011100010;
3158 def A4_vcmpheqi : HInst<
3159 (outs PredRegs:$Pd4),
3160 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3161 "$Pd4 = vcmph.eq($Rss32,#$Ii)",
3162 tc_7a830544, TypeALU64>, Enc_0d8adb {
3163 let Inst{4-2} = 0b010;
3164 let Inst{13-13} = 0b0;
3165 let Inst{31-21} = 0b11011100000;
3167 def A4_vcmphgti : HInst<
3168 (outs PredRegs:$Pd4),
3169 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3170 "$Pd4 = vcmph.gt($Rss32,#$Ii)",
3171 tc_7a830544, TypeALU64>, Enc_0d8adb {
3172 let Inst{4-2} = 0b010;
3173 let Inst{13-13} = 0b0;
3174 let Inst{31-21} = 0b11011100001;
3176 def A4_vcmphgtui : HInst<
3177 (outs PredRegs:$Pd4),
3178 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3179 "$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3180 tc_7a830544, TypeALU64>, Enc_3680c2 {
3181 let Inst{4-2} = 0b010;
3182 let Inst{13-12} = 0b00;
3183 let Inst{31-21} = 0b11011100010;
3185 def A4_vcmpweqi : HInst<
3186 (outs PredRegs:$Pd4),
3187 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3188 "$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3189 tc_7a830544, TypeALU64>, Enc_0d8adb {
3190 let Inst{4-2} = 0b100;
3191 let Inst{13-13} = 0b0;
3192 let Inst{31-21} = 0b11011100000;
3194 def A4_vcmpwgti : HInst<
3195 (outs PredRegs:$Pd4),
3196 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3197 "$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3198 tc_7a830544, TypeALU64>, Enc_0d8adb {
3199 let Inst{4-2} = 0b100;
3200 let Inst{13-13} = 0b0;
3201 let Inst{31-21} = 0b11011100001;
3203 def A4_vcmpwgtui : HInst<
3204 (outs PredRegs:$Pd4),
3205 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3206 "$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3207 tc_7a830544, TypeALU64>, Enc_3680c2 {
3208 let Inst{4-2} = 0b100;
3209 let Inst{13-12} = 0b00;
3210 let Inst{31-21} = 0b11011100010;
3212 def A4_vrmaxh : HInst<
3213 (outs DoubleRegs:$Rxx32),
3214 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3215 "$Rxx32 = vrmaxh($Rss32,$Ru32)",
3216 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3217 let Inst{7-5} = 0b001;
3218 let Inst{13-13} = 0b0;
3219 let Inst{31-21} = 0b11001011001;
3220 let prefersSlot3 = 1;
3221 let Constraints = "$Rxx32 = $Rxx32in";
3223 def A4_vrmaxuh : HInst<
3224 (outs DoubleRegs:$Rxx32),
3225 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3226 "$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3227 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3228 let Inst{7-5} = 0b001;
3229 let Inst{13-13} = 0b1;
3230 let Inst{31-21} = 0b11001011001;
3231 let prefersSlot3 = 1;
3232 let Constraints = "$Rxx32 = $Rxx32in";
3234 def A4_vrmaxuw : HInst<
3235 (outs DoubleRegs:$Rxx32),
3236 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3237 "$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3238 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3239 let Inst{7-5} = 0b010;
3240 let Inst{13-13} = 0b1;
3241 let Inst{31-21} = 0b11001011001;
3242 let prefersSlot3 = 1;
3243 let Constraints = "$Rxx32 = $Rxx32in";
3245 def A4_vrmaxw : HInst<
3246 (outs DoubleRegs:$Rxx32),
3247 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3248 "$Rxx32 = vrmaxw($Rss32,$Ru32)",
3249 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3250 let Inst{7-5} = 0b010;
3251 let Inst{13-13} = 0b0;
3252 let Inst{31-21} = 0b11001011001;
3253 let prefersSlot3 = 1;
3254 let Constraints = "$Rxx32 = $Rxx32in";
3256 def A4_vrminh : HInst<
3257 (outs DoubleRegs:$Rxx32),
3258 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3259 "$Rxx32 = vrminh($Rss32,$Ru32)",
3260 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3261 let Inst{7-5} = 0b101;
3262 let Inst{13-13} = 0b0;
3263 let Inst{31-21} = 0b11001011001;
3264 let prefersSlot3 = 1;
3265 let Constraints = "$Rxx32 = $Rxx32in";
3267 def A4_vrminuh : HInst<
3268 (outs DoubleRegs:$Rxx32),
3269 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3270 "$Rxx32 = vrminuh($Rss32,$Ru32)",
3271 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3272 let Inst{7-5} = 0b101;
3273 let Inst{13-13} = 0b1;
3274 let Inst{31-21} = 0b11001011001;
3275 let prefersSlot3 = 1;
3276 let Constraints = "$Rxx32 = $Rxx32in";
3278 def A4_vrminuw : HInst<
3279 (outs DoubleRegs:$Rxx32),
3280 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3281 "$Rxx32 = vrminuw($Rss32,$Ru32)",
3282 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3283 let Inst{7-5} = 0b110;
3284 let Inst{13-13} = 0b1;
3285 let Inst{31-21} = 0b11001011001;
3286 let prefersSlot3 = 1;
3287 let Constraints = "$Rxx32 = $Rxx32in";
3289 def A4_vrminw : HInst<
3290 (outs DoubleRegs:$Rxx32),
3291 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3292 "$Rxx32 = vrminw($Rss32,$Ru32)",
3293 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
3294 let Inst{7-5} = 0b110;
3295 let Inst{13-13} = 0b0;
3296 let Inst{31-21} = 0b11001011001;
3297 let prefersSlot3 = 1;
3298 let Constraints = "$Rxx32 = $Rxx32in";
3301 (outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3302 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3303 "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3304 tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55T]> {
3305 let Inst{7-7} = 0b0;
3306 let Inst{13-13} = 0b0;
3307 let Inst{31-21} = 0b11101010101;
3308 let isPredicateLate = 1;
3309 let prefersSlot3 = 1;
3310 let Defs = [USR_OVF];
3311 let Constraints = "$Rxx32 = $Rxx32in";
3313 def A5_vaddhubs : HInst<
3314 (outs IntRegs:$Rd32),
3315 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316 "$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3317 tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> {
3318 let Inst{7-5} = 0b001;
3319 let Inst{13-13} = 0b0;
3320 let Inst{31-21} = 0b11000001010;
3321 let hasNewValue = 1;
3323 let prefersSlot3 = 1;
3324 let Defs = [USR_OVF];
3326 def A6_vcmpbeq_notany : HInst<
3327 (outs PredRegs:$Pd4),
3328 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329 "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3330 tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65T]> {
3331 let Inst{7-2} = 0b001000;
3332 let Inst{13-13} = 0b1;
3333 let Inst{31-21} = 0b11010010000;
3335 def A6_vminub_RdP : HInst<
3336 (outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3337 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3338 "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3339 tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> {
3340 let Inst{7-7} = 0b0;
3341 let Inst{13-13} = 0b0;
3342 let Inst{31-21} = 0b11101010111;
3343 let isPredicateLate = 1;
3344 let prefersSlot3 = 1;
3346 def C2_all8 : HInst<
3347 (outs PredRegs:$Pd4),
3348 (ins PredRegs:$Ps4),
3349 "$Pd4 = all8($Ps4)",
3350 tc_f2704b9a, TypeCR>, Enc_65d691 {
3351 let Inst{13-2} = 0b000000000000;
3352 let Inst{31-18} = 0b01101011101000;
3355 (outs PredRegs:$Pd4),
3356 (ins PredRegs:$Pt4, PredRegs:$Ps4),
3357 "$Pd4 = and($Pt4,$Ps4)",
3358 tc_53bc8a6a, TypeCR>, Enc_454a26 {
3359 let Inst{7-2} = 0b000000;
3360 let Inst{13-10} = 0b0000;
3361 let Inst{31-18} = 0b01101011000000;
3363 def C2_andn : HInst<
3364 (outs PredRegs:$Pd4),
3365 (ins PredRegs:$Pt4, PredRegs:$Ps4),
3366 "$Pd4 = and($Pt4,!$Ps4)",
3367 tc_53bc8a6a, TypeCR>, Enc_454a26 {
3368 let Inst{7-2} = 0b000000;
3369 let Inst{13-10} = 0b0000;
3370 let Inst{31-18} = 0b01101011011000;
3372 def C2_any8 : HInst<
3373 (outs PredRegs:$Pd4),
3374 (ins PredRegs:$Ps4),
3375 "$Pd4 = any8($Ps4)",
3376 tc_f2704b9a, TypeCR>, Enc_65d691 {
3377 let Inst{13-2} = 0b000000000000;
3378 let Inst{31-18} = 0b01101011100000;
3380 def C2_bitsclr : HInst<
3381 (outs PredRegs:$Pd4),
3382 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3383 "$Pd4 = bitsclr($Rs32,$Rt32)",
3384 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
3385 let Inst{7-2} = 0b000000;
3386 let Inst{13-13} = 0b0;
3387 let Inst{31-21} = 0b11000111100;
3389 def C2_bitsclri : HInst<
3390 (outs PredRegs:$Pd4),
3391 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
3392 "$Pd4 = bitsclr($Rs32,#$Ii)",
3393 tc_7a830544, TypeS_2op>, Enc_5d6c34 {
3394 let Inst{7-2} = 0b000000;
3395 let Inst{31-21} = 0b10000101100;
3397 def C2_bitsset : HInst<
3398 (outs PredRegs:$Pd4),
3399 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3400 "$Pd4 = bitsset($Rs32,$Rt32)",
3401 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
3402 let Inst{7-2} = 0b000000;
3403 let Inst{13-13} = 0b0;
3404 let Inst{31-21} = 0b11000111010;
3406 def C2_ccombinewf : HInst<
3407 (outs DoubleRegs:$Rdd32),
3408 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3409 "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3410 tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3411 let Inst{7-7} = 0b1;
3412 let Inst{13-13} = 0b0;
3413 let Inst{31-21} = 0b11111101000;
3414 let isPredicated = 1;
3415 let isPredicatedFalse = 1;
3416 let BaseOpcode = "A2_combinew";
3418 def C2_ccombinewnewf : HInst<
3419 (outs DoubleRegs:$Rdd32),
3420 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3421 "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3422 tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3423 let Inst{7-7} = 0b1;
3424 let Inst{13-13} = 0b1;
3425 let Inst{31-21} = 0b11111101000;
3426 let isPredicated = 1;
3427 let isPredicatedFalse = 1;
3428 let isPredicatedNew = 1;
3429 let BaseOpcode = "A2_combinew";
3431 def C2_ccombinewnewt : HInst<
3432 (outs DoubleRegs:$Rdd32),
3433 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3434 "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3435 tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3436 let Inst{7-7} = 0b0;
3437 let Inst{13-13} = 0b1;
3438 let Inst{31-21} = 0b11111101000;
3439 let isPredicated = 1;
3440 let isPredicatedNew = 1;
3441 let BaseOpcode = "A2_combinew";
3443 def C2_ccombinewt : HInst<
3444 (outs DoubleRegs:$Rdd32),
3445 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3446 "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3447 tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3448 let Inst{7-7} = 0b0;
3449 let Inst{13-13} = 0b0;
3450 let Inst{31-21} = 0b11111101000;
3451 let isPredicated = 1;
3452 let BaseOpcode = "A2_combinew";
3454 def C2_cmoveif : HInst<
3455 (outs IntRegs:$Rd32),
3456 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
3457 "if (!$Pu4) $Rd32 = #$Ii",
3458 tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3459 let Inst{13-13} = 0b0;
3460 let Inst{20-20} = 0b0;
3461 let Inst{31-23} = 0b011111101;
3462 let isPredicated = 1;
3463 let isPredicatedFalse = 1;
3464 let hasNewValue = 1;
3466 let CextOpcode = "A2_tfr";
3467 let InputType = "imm";
3468 let BaseOpcode = "A2_tfrsi";
3470 let isExtendable = 1;
3471 let opExtendable = 2;
3472 let isExtentSigned = 1;
3473 let opExtentBits = 12;
3474 let opExtentAlign = 0;
3476 def C2_cmoveit : HInst<
3477 (outs IntRegs:$Rd32),
3478 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
3479 "if ($Pu4) $Rd32 = #$Ii",
3480 tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3481 let Inst{13-13} = 0b0;
3482 let Inst{20-20} = 0b0;
3483 let Inst{31-23} = 0b011111100;
3484 let isPredicated = 1;
3485 let hasNewValue = 1;
3487 let CextOpcode = "A2_tfr";
3488 let InputType = "imm";
3489 let BaseOpcode = "A2_tfrsi";
3491 let isExtendable = 1;
3492 let opExtendable = 2;
3493 let isExtentSigned = 1;
3494 let opExtentBits = 12;
3495 let opExtentAlign = 0;
3497 def C2_cmovenewif : HInst<
3498 (outs IntRegs:$Rd32),
3499 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
3500 "if (!$Pu4.new) $Rd32 = #$Ii",
3501 tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3502 let Inst{13-13} = 0b1;
3503 let Inst{20-20} = 0b0;
3504 let Inst{31-23} = 0b011111101;
3505 let isPredicated = 1;
3506 let isPredicatedFalse = 1;
3507 let hasNewValue = 1;
3509 let isPredicatedNew = 1;
3510 let CextOpcode = "A2_tfr";
3511 let InputType = "imm";
3512 let BaseOpcode = "A2_tfrsi";
3514 let isExtendable = 1;
3515 let opExtendable = 2;
3516 let isExtentSigned = 1;
3517 let opExtentBits = 12;
3518 let opExtentAlign = 0;
3520 def C2_cmovenewit : HInst<
3521 (outs IntRegs:$Rd32),
3522 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
3523 "if ($Pu4.new) $Rd32 = #$Ii",
3524 tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3525 let Inst{13-13} = 0b1;
3526 let Inst{20-20} = 0b0;
3527 let Inst{31-23} = 0b011111100;
3528 let isPredicated = 1;
3529 let hasNewValue = 1;
3531 let isPredicatedNew = 1;
3532 let CextOpcode = "A2_tfr";
3533 let InputType = "imm";
3534 let BaseOpcode = "A2_tfrsi";
3536 let isExtendable = 1;
3537 let opExtendable = 2;
3538 let isExtentSigned = 1;
3539 let opExtentBits = 12;
3540 let opExtentAlign = 0;
3542 def C2_cmpeq : HInst<
3543 (outs PredRegs:$Pd4),
3544 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3545 "$Pd4 = cmp.eq($Rs32,$Rt32)",
3546 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3547 let Inst{7-2} = 0b000000;
3548 let Inst{13-13} = 0b0;
3549 let Inst{31-21} = 0b11110010000;
3550 let CextOpcode = "C2_cmpeq";
3551 let InputType = "reg";
3552 let isCommutable = 1;
3555 def C2_cmpeqi : HInst<
3556 (outs PredRegs:$Pd4),
3557 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
3558 "$Pd4 = cmp.eq($Rs32,#$Ii)",
3559 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3560 let Inst{4-2} = 0b000;
3561 let Inst{31-22} = 0b0111010100;
3562 let CextOpcode = "C2_cmpeq";
3563 let InputType = "imm";
3565 let isExtendable = 1;
3566 let opExtendable = 2;
3567 let isExtentSigned = 1;
3568 let opExtentBits = 10;
3569 let opExtentAlign = 0;
3571 def C2_cmpeqp : HInst<
3572 (outs PredRegs:$Pd4),
3573 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3574 "$Pd4 = cmp.eq($Rss32,$Rtt32)",
3575 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
3576 let Inst{7-2} = 0b000000;
3577 let Inst{13-13} = 0b0;
3578 let Inst{31-21} = 0b11010010100;
3579 let isCommutable = 1;
3582 def C2_cmpgei : HInst<
3583 (outs PredRegs:$Pd4),
3584 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
3585 "$Pd4 = cmp.ge($Rs32,#$Ii)",
3586 tc_6ebb4a12, TypeALU32_2op> {
3590 def C2_cmpgeui : HInst<
3591 (outs PredRegs:$Pd4),
3592 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
3593 "$Pd4 = cmp.geu($Rs32,#$Ii)",
3594 tc_6ebb4a12, TypeALU32_2op> {
3598 def C2_cmpgt : HInst<
3599 (outs PredRegs:$Pd4),
3600 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3601 "$Pd4 = cmp.gt($Rs32,$Rt32)",
3602 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3603 let Inst{7-2} = 0b000000;
3604 let Inst{13-13} = 0b0;
3605 let Inst{31-21} = 0b11110010010;
3606 let CextOpcode = "C2_cmpgt";
3607 let InputType = "reg";
3610 def C2_cmpgti : HInst<
3611 (outs PredRegs:$Pd4),
3612 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
3613 "$Pd4 = cmp.gt($Rs32,#$Ii)",
3614 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3615 let Inst{4-2} = 0b000;
3616 let Inst{31-22} = 0b0111010101;
3617 let CextOpcode = "C2_cmpgt";
3618 let InputType = "imm";
3620 let isExtendable = 1;
3621 let opExtendable = 2;
3622 let isExtentSigned = 1;
3623 let opExtentBits = 10;
3624 let opExtentAlign = 0;
3626 def C2_cmpgtp : HInst<
3627 (outs PredRegs:$Pd4),
3628 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3629 "$Pd4 = cmp.gt($Rss32,$Rtt32)",
3630 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
3631 let Inst{7-2} = 0b010000;
3632 let Inst{13-13} = 0b0;
3633 let Inst{31-21} = 0b11010010100;
3636 def C2_cmpgtu : HInst<
3637 (outs PredRegs:$Pd4),
3638 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3639 "$Pd4 = cmp.gtu($Rs32,$Rt32)",
3640 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3641 let Inst{7-2} = 0b000000;
3642 let Inst{13-13} = 0b0;
3643 let Inst{31-21} = 0b11110010011;
3644 let CextOpcode = "C2_cmpgtu";
3645 let InputType = "reg";
3648 def C2_cmpgtui : HInst<
3649 (outs PredRegs:$Pd4),
3650 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
3651 "$Pd4 = cmp.gtu($Rs32,#$Ii)",
3652 tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3653 let Inst{4-2} = 0b000;
3654 let Inst{31-21} = 0b01110101100;
3655 let CextOpcode = "C2_cmpgtu";
3656 let InputType = "imm";
3658 let isExtendable = 1;
3659 let opExtendable = 2;
3660 let isExtentSigned = 0;
3661 let opExtentBits = 9;
3662 let opExtentAlign = 0;
3664 def C2_cmpgtup : HInst<
3665 (outs PredRegs:$Pd4),
3666 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3667 "$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3668 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
3669 let Inst{7-2} = 0b100000;
3670 let Inst{13-13} = 0b0;
3671 let Inst{31-21} = 0b11010010100;
3674 def C2_cmplt : HInst<
3675 (outs PredRegs:$Pd4),
3676 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3677 "$Pd4 = cmp.lt($Rs32,$Rt32)",
3678 tc_6ebb4a12, TypeALU32_3op> {
3681 let isCodeGenOnly = 1;
3683 def C2_cmpltu : HInst<
3684 (outs PredRegs:$Pd4),
3685 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3686 "$Pd4 = cmp.ltu($Rs32,$Rt32)",
3687 tc_6ebb4a12, TypeALU32_3op> {
3690 let isCodeGenOnly = 1;
3692 def C2_mask : HInst<
3693 (outs DoubleRegs:$Rdd32),
3694 (ins PredRegs:$Pt4),
3695 "$Rdd32 = mask($Pt4)",
3696 tc_cde8b071, TypeS_2op>, Enc_78e566 {
3697 let Inst{7-5} = 0b000;
3698 let Inst{13-10} = 0b0000;
3699 let Inst{31-16} = 0b1000011000000000;
3702 (outs IntRegs:$Rd32),
3703 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3704 "$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3705 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54 {
3706 let Inst{7-7} = 0b0;
3707 let Inst{13-13} = 0b0;
3708 let Inst{31-21} = 0b11110100000;
3709 let hasNewValue = 1;
3711 let InputType = "reg";
3713 def C2_muxii : HInst<
3714 (outs IntRegs:$Rd32),
3715 (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3716 "$Rd32 = mux($Pu4,#$Ii,#$II)",
3717 tc_d6bf0472, TypeALU32_2op>, Enc_830e5d {
3718 let Inst{31-25} = 0b0111101;
3719 let hasNewValue = 1;
3721 let isExtendable = 1;
3722 let opExtendable = 2;
3723 let isExtentSigned = 1;
3724 let opExtentBits = 8;
3725 let opExtentAlign = 0;
3727 def C2_muxir : HInst<
3728 (outs IntRegs:$Rd32),
3729 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3730 "$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3731 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
3732 let Inst{13-13} = 0b0;
3733 let Inst{31-23} = 0b011100110;
3734 let hasNewValue = 1;
3736 let InputType = "imm";
3737 let isExtendable = 1;
3738 let opExtendable = 3;
3739 let isExtentSigned = 1;
3740 let opExtentBits = 8;
3741 let opExtentAlign = 0;
3743 def C2_muxri : HInst<
3744 (outs IntRegs:$Rd32),
3745 (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3746 "$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3747 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
3748 let Inst{13-13} = 0b0;
3749 let Inst{31-23} = 0b011100111;
3750 let hasNewValue = 1;
3752 let InputType = "imm";
3753 let isExtendable = 1;
3754 let opExtendable = 2;
3755 let isExtentSigned = 1;
3756 let opExtentBits = 8;
3757 let opExtentAlign = 0;
3760 (outs PredRegs:$Pd4),
3761 (ins PredRegs:$Ps4),
3763 tc_f2704b9a, TypeCR>, Enc_65d691 {
3764 let Inst{13-2} = 0b000000000000;
3765 let Inst{31-18} = 0b01101011110000;
3768 (outs PredRegs:$Pd4),
3769 (ins PredRegs:$Pt4, PredRegs:$Ps4),
3770 "$Pd4 = or($Pt4,$Ps4)",
3771 tc_53bc8a6a, TypeCR>, Enc_454a26 {
3772 let Inst{7-2} = 0b000000;
3773 let Inst{13-10} = 0b0000;
3774 let Inst{31-18} = 0b01101011001000;
3777 (outs PredRegs:$Pd4),
3778 (ins PredRegs:$Pt4, PredRegs:$Ps4),
3779 "$Pd4 = or($Pt4,!$Ps4)",
3780 tc_53bc8a6a, TypeCR>, Enc_454a26 {
3781 let Inst{7-2} = 0b000000;
3782 let Inst{13-10} = 0b0000;
3783 let Inst{31-18} = 0b01101011111000;
3785 def C2_pxfer_map : HInst<
3786 (outs PredRegs:$Pd4),
3787 (ins PredRegs:$Ps4),
3789 tc_53bc8a6a, TypeMAPPING> {
3791 let isCodeGenOnly = 1;
3793 def C2_tfrpr : HInst<
3794 (outs IntRegs:$Rd32),
3795 (ins PredRegs:$Ps4),
3797 tc_cde8b071, TypeS_2op>, Enc_f5e933 {
3798 let Inst{13-5} = 0b000000000;
3799 let Inst{31-18} = 0b10001001010000;
3800 let hasNewValue = 1;
3803 def C2_tfrrp : HInst<
3804 (outs PredRegs:$Pd4),
3805 (ins IntRegs:$Rs32),
3807 tc_351fed2d, TypeS_2op>, Enc_48b75f {
3808 let Inst{13-2} = 0b000000000000;
3809 let Inst{31-21} = 0b10000101010;
3811 def C2_vitpack : HInst<
3812 (outs IntRegs:$Rd32),
3813 (ins PredRegs:$Ps4, PredRegs:$Pt4),
3814 "$Rd32 = vitpack($Ps4,$Pt4)",
3815 tc_1b9c9ee5, TypeS_2op>, Enc_527412 {
3816 let Inst{7-5} = 0b000;
3817 let Inst{13-10} = 0b0000;
3818 let Inst{31-18} = 0b10001001000000;
3819 let hasNewValue = 1;
3821 let prefersSlot3 = 1;
3823 def C2_vmux : HInst<
3824 (outs DoubleRegs:$Rdd32),
3825 (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3826 "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3827 tc_f8eeed7a, TypeALU64>, Enc_329361 {
3828 let Inst{7-7} = 0b0;
3829 let Inst{13-13} = 0b0;
3830 let Inst{31-21} = 0b11010001000;
3833 (outs PredRegs:$Pd4),
3834 (ins PredRegs:$Ps4, PredRegs:$Pt4),
3835 "$Pd4 = xor($Ps4,$Pt4)",
3836 tc_53bc8a6a, TypeCR>, Enc_284ebb {
3837 let Inst{7-2} = 0b000000;
3838 let Inst{13-10} = 0b0000;
3839 let Inst{31-18} = 0b01101011010000;
3841 def C4_addipc : HInst<
3842 (outs IntRegs:$Rd32),
3844 "$Rd32 = add(pc,#$Ii)",
3845 tc_b9c4623f, TypeCR>, Enc_607661 {
3846 let Inst{6-5} = 0b00;
3847 let Inst{13-13} = 0b0;
3848 let Inst{31-16} = 0b0110101001001001;
3849 let hasNewValue = 1;
3851 let isExtendable = 1;
3852 let opExtendable = 1;
3853 let isExtentSigned = 0;
3854 let opExtentBits = 6;
3855 let opExtentAlign = 0;
3857 def C4_and_and : HInst<
3858 (outs PredRegs:$Pd4),
3859 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3860 "$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3861 tc_481e5e5c, TypeCR>, Enc_9ac432 {
3862 let Inst{5-2} = 0b0000;
3863 let Inst{13-10} = 0b0000;
3864 let Inst{31-18} = 0b01101011000100;
3866 def C4_and_andn : HInst<
3867 (outs PredRegs:$Pd4),
3868 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3869 "$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3870 tc_481e5e5c, TypeCR>, Enc_9ac432 {
3871 let Inst{5-2} = 0b0000;
3872 let Inst{13-10} = 0b0000;
3873 let Inst{31-18} = 0b01101011100100;
3875 def C4_and_or : HInst<
3876 (outs PredRegs:$Pd4),
3877 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3878 "$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3879 tc_481e5e5c, TypeCR>, Enc_9ac432 {
3880 let Inst{5-2} = 0b0000;
3881 let Inst{13-10} = 0b0000;
3882 let Inst{31-18} = 0b01101011001100;
3884 def C4_and_orn : HInst<
3885 (outs PredRegs:$Pd4),
3886 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3887 "$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3888 tc_481e5e5c, TypeCR>, Enc_9ac432 {
3889 let Inst{5-2} = 0b0000;
3890 let Inst{13-10} = 0b0000;
3891 let Inst{31-18} = 0b01101011101100;
3893 def C4_cmplte : HInst<
3894 (outs PredRegs:$Pd4),
3895 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3896 "$Pd4 = !cmp.gt($Rs32,$Rt32)",
3897 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3898 let Inst{7-2} = 0b000100;
3899 let Inst{13-13} = 0b0;
3900 let Inst{31-21} = 0b11110010010;
3901 let CextOpcode = "C4_cmplte";
3902 let InputType = "reg";
3905 def C4_cmpltei : HInst<
3906 (outs PredRegs:$Pd4),
3907 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
3908 "$Pd4 = !cmp.gt($Rs32,#$Ii)",
3909 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3910 let Inst{4-2} = 0b100;
3911 let Inst{31-22} = 0b0111010101;
3912 let CextOpcode = "C4_cmplte";
3913 let InputType = "imm";
3915 let isExtendable = 1;
3916 let opExtendable = 2;
3917 let isExtentSigned = 1;
3918 let opExtentBits = 10;
3919 let opExtentAlign = 0;
3921 def C4_cmplteu : HInst<
3922 (outs PredRegs:$Pd4),
3923 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3924 "$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3925 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3926 let Inst{7-2} = 0b000100;
3927 let Inst{13-13} = 0b0;
3928 let Inst{31-21} = 0b11110010011;
3929 let CextOpcode = "C4_cmplteu";
3930 let InputType = "reg";
3933 def C4_cmplteui : HInst<
3934 (outs PredRegs:$Pd4),
3935 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
3936 "$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3937 tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3938 let Inst{4-2} = 0b100;
3939 let Inst{31-21} = 0b01110101100;
3940 let CextOpcode = "C4_cmplteu";
3941 let InputType = "imm";
3943 let isExtendable = 1;
3944 let opExtendable = 2;
3945 let isExtentSigned = 0;
3946 let opExtentBits = 9;
3947 let opExtentAlign = 0;
3949 def C4_cmpneq : HInst<
3950 (outs PredRegs:$Pd4),
3951 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3952 "$Pd4 = !cmp.eq($Rs32,$Rt32)",
3953 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3954 let Inst{7-2} = 0b000100;
3955 let Inst{13-13} = 0b0;
3956 let Inst{31-21} = 0b11110010000;
3957 let CextOpcode = "C4_cmpneq";
3958 let InputType = "reg";
3959 let isCommutable = 1;
3962 def C4_cmpneqi : HInst<
3963 (outs PredRegs:$Pd4),
3964 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
3965 "$Pd4 = !cmp.eq($Rs32,#$Ii)",
3966 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3967 let Inst{4-2} = 0b100;
3968 let Inst{31-22} = 0b0111010100;
3969 let CextOpcode = "C4_cmpneq";
3970 let InputType = "imm";
3972 let isExtendable = 1;
3973 let opExtendable = 2;
3974 let isExtentSigned = 1;
3975 let opExtentBits = 10;
3976 let opExtentAlign = 0;
3978 def C4_fastcorner9 : HInst<
3979 (outs PredRegs:$Pd4),
3980 (ins PredRegs:$Ps4, PredRegs:$Pt4),
3981 "$Pd4 = fastcorner9($Ps4,$Pt4)",
3982 tc_53bc8a6a, TypeCR>, Enc_284ebb {
3983 let Inst{7-2} = 0b100100;
3984 let Inst{13-10} = 0b1000;
3985 let Inst{31-18} = 0b01101011000000;
3987 def C4_fastcorner9_not : HInst<
3988 (outs PredRegs:$Pd4),
3989 (ins PredRegs:$Ps4, PredRegs:$Pt4),
3990 "$Pd4 = !fastcorner9($Ps4,$Pt4)",
3991 tc_53bc8a6a, TypeCR>, Enc_284ebb {
3992 let Inst{7-2} = 0b100100;
3993 let Inst{13-10} = 0b1000;
3994 let Inst{31-18} = 0b01101011000100;
3996 def C4_nbitsclr : HInst<
3997 (outs PredRegs:$Pd4),
3998 (ins IntRegs:$Rs32, IntRegs:$Rt32),
3999 "$Pd4 = !bitsclr($Rs32,$Rt32)",
4000 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
4001 let Inst{7-2} = 0b000000;
4002 let Inst{13-13} = 0b0;
4003 let Inst{31-21} = 0b11000111101;
4005 def C4_nbitsclri : HInst<
4006 (outs PredRegs:$Pd4),
4007 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
4008 "$Pd4 = !bitsclr($Rs32,#$Ii)",
4009 tc_7a830544, TypeS_2op>, Enc_5d6c34 {
4010 let Inst{7-2} = 0b000000;
4011 let Inst{31-21} = 0b10000101101;
4013 def C4_nbitsset : HInst<
4014 (outs PredRegs:$Pd4),
4015 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4016 "$Pd4 = !bitsset($Rs32,$Rt32)",
4017 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
4018 let Inst{7-2} = 0b000000;
4019 let Inst{13-13} = 0b0;
4020 let Inst{31-21} = 0b11000111011;
4022 def C4_or_and : HInst<
4023 (outs PredRegs:$Pd4),
4024 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4025 "$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4026 tc_481e5e5c, TypeCR>, Enc_9ac432 {
4027 let Inst{5-2} = 0b0000;
4028 let Inst{13-10} = 0b0000;
4029 let Inst{31-18} = 0b01101011010100;
4031 def C4_or_andn : HInst<
4032 (outs PredRegs:$Pd4),
4033 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4034 "$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4035 tc_481e5e5c, TypeCR>, Enc_9ac432 {
4036 let Inst{5-2} = 0b0000;
4037 let Inst{13-10} = 0b0000;
4038 let Inst{31-18} = 0b01101011110100;
4040 def C4_or_or : HInst<
4041 (outs PredRegs:$Pd4),
4042 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4043 "$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4044 tc_481e5e5c, TypeCR>, Enc_9ac432 {
4045 let Inst{5-2} = 0b0000;
4046 let Inst{13-10} = 0b0000;
4047 let Inst{31-18} = 0b01101011011100;
4049 def C4_or_orn : HInst<
4050 (outs PredRegs:$Pd4),
4051 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4052 "$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4053 tc_481e5e5c, TypeCR>, Enc_9ac432 {
4054 let Inst{5-2} = 0b0000;
4055 let Inst{13-10} = 0b0000;
4056 let Inst{31-18} = 0b01101011111100;
4058 def F2_conv_d2df : HInst<
4059 (outs DoubleRegs:$Rdd32),
4060 (ins DoubleRegs:$Rss32),
4061 "$Rdd32 = convert_d2df($Rss32)",
4062 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4063 let Inst{13-5} = 0b000000011;
4064 let Inst{31-21} = 0b10000000111;
4068 def F2_conv_d2sf : HInst<
4069 (outs IntRegs:$Rd32),
4070 (ins DoubleRegs:$Rss32),
4071 "$Rd32 = convert_d2sf($Rss32)",
4072 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4073 let Inst{13-5} = 0b000000001;
4074 let Inst{31-21} = 0b10001000010;
4075 let hasNewValue = 1;
4080 def F2_conv_df2d : HInst<
4081 (outs DoubleRegs:$Rdd32),
4082 (ins DoubleRegs:$Rss32),
4083 "$Rdd32 = convert_df2d($Rss32)",
4084 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4085 let Inst{13-5} = 0b000000000;
4086 let Inst{31-21} = 0b10000000111;
4090 def F2_conv_df2d_chop : HInst<
4091 (outs DoubleRegs:$Rdd32),
4092 (ins DoubleRegs:$Rss32),
4093 "$Rdd32 = convert_df2d($Rss32):chop",
4094 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4095 let Inst{13-5} = 0b000000110;
4096 let Inst{31-21} = 0b10000000111;
4100 def F2_conv_df2sf : HInst<
4101 (outs IntRegs:$Rd32),
4102 (ins DoubleRegs:$Rss32),
4103 "$Rd32 = convert_df2sf($Rss32)",
4104 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4105 let Inst{13-5} = 0b000000001;
4106 let Inst{31-21} = 0b10001000000;
4107 let hasNewValue = 1;
4112 def F2_conv_df2ud : HInst<
4113 (outs DoubleRegs:$Rdd32),
4114 (ins DoubleRegs:$Rss32),
4115 "$Rdd32 = convert_df2ud($Rss32)",
4116 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4117 let Inst{13-5} = 0b000000001;
4118 let Inst{31-21} = 0b10000000111;
4122 def F2_conv_df2ud_chop : HInst<
4123 (outs DoubleRegs:$Rdd32),
4124 (ins DoubleRegs:$Rss32),
4125 "$Rdd32 = convert_df2ud($Rss32):chop",
4126 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4127 let Inst{13-5} = 0b000000111;
4128 let Inst{31-21} = 0b10000000111;
4132 def F2_conv_df2uw : HInst<
4133 (outs IntRegs:$Rd32),
4134 (ins DoubleRegs:$Rss32),
4135 "$Rd32 = convert_df2uw($Rss32)",
4136 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4137 let Inst{13-5} = 0b000000001;
4138 let Inst{31-21} = 0b10001000011;
4139 let hasNewValue = 1;
4144 def F2_conv_df2uw_chop : HInst<
4145 (outs IntRegs:$Rd32),
4146 (ins DoubleRegs:$Rss32),
4147 "$Rd32 = convert_df2uw($Rss32):chop",
4148 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4149 let Inst{13-5} = 0b000000001;
4150 let Inst{31-21} = 0b10001000101;
4151 let hasNewValue = 1;
4156 def F2_conv_df2w : HInst<
4157 (outs IntRegs:$Rd32),
4158 (ins DoubleRegs:$Rss32),
4159 "$Rd32 = convert_df2w($Rss32)",
4160 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4161 let Inst{13-5} = 0b000000001;
4162 let Inst{31-21} = 0b10001000100;
4163 let hasNewValue = 1;
4168 def F2_conv_df2w_chop : HInst<
4169 (outs IntRegs:$Rd32),
4170 (ins DoubleRegs:$Rss32),
4171 "$Rd32 = convert_df2w($Rss32):chop",
4172 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4173 let Inst{13-5} = 0b000000001;
4174 let Inst{31-21} = 0b10001000111;
4175 let hasNewValue = 1;
4180 def F2_conv_sf2d : HInst<
4181 (outs DoubleRegs:$Rdd32),
4182 (ins IntRegs:$Rs32),
4183 "$Rdd32 = convert_sf2d($Rs32)",
4184 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4185 let Inst{13-5} = 0b000000100;
4186 let Inst{31-21} = 0b10000100100;
4190 def F2_conv_sf2d_chop : HInst<
4191 (outs DoubleRegs:$Rdd32),
4192 (ins IntRegs:$Rs32),
4193 "$Rdd32 = convert_sf2d($Rs32):chop",
4194 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4195 let Inst{13-5} = 0b000000110;
4196 let Inst{31-21} = 0b10000100100;
4200 def F2_conv_sf2df : HInst<
4201 (outs DoubleRegs:$Rdd32),
4202 (ins IntRegs:$Rs32),
4203 "$Rdd32 = convert_sf2df($Rs32)",
4204 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4205 let Inst{13-5} = 0b000000000;
4206 let Inst{31-21} = 0b10000100100;
4210 def F2_conv_sf2ud : HInst<
4211 (outs DoubleRegs:$Rdd32),
4212 (ins IntRegs:$Rs32),
4213 "$Rdd32 = convert_sf2ud($Rs32)",
4214 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4215 let Inst{13-5} = 0b000000011;
4216 let Inst{31-21} = 0b10000100100;
4220 def F2_conv_sf2ud_chop : HInst<
4221 (outs DoubleRegs:$Rdd32),
4222 (ins IntRegs:$Rs32),
4223 "$Rdd32 = convert_sf2ud($Rs32):chop",
4224 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4225 let Inst{13-5} = 0b000000101;
4226 let Inst{31-21} = 0b10000100100;
4230 def F2_conv_sf2uw : HInst<
4231 (outs IntRegs:$Rd32),
4232 (ins IntRegs:$Rs32),
4233 "$Rd32 = convert_sf2uw($Rs32)",
4234 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4235 let Inst{13-5} = 0b000000000;
4236 let Inst{31-21} = 0b10001011011;
4237 let hasNewValue = 1;
4242 def F2_conv_sf2uw_chop : HInst<
4243 (outs IntRegs:$Rd32),
4244 (ins IntRegs:$Rs32),
4245 "$Rd32 = convert_sf2uw($Rs32):chop",
4246 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4247 let Inst{13-5} = 0b000000001;
4248 let Inst{31-21} = 0b10001011011;
4249 let hasNewValue = 1;
4254 def F2_conv_sf2w : HInst<
4255 (outs IntRegs:$Rd32),
4256 (ins IntRegs:$Rs32),
4257 "$Rd32 = convert_sf2w($Rs32)",
4258 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4259 let Inst{13-5} = 0b000000000;
4260 let Inst{31-21} = 0b10001011100;
4261 let hasNewValue = 1;
4266 def F2_conv_sf2w_chop : HInst<
4267 (outs IntRegs:$Rd32),
4268 (ins IntRegs:$Rs32),
4269 "$Rd32 = convert_sf2w($Rs32):chop",
4270 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4271 let Inst{13-5} = 0b000000001;
4272 let Inst{31-21} = 0b10001011100;
4273 let hasNewValue = 1;
4278 def F2_conv_ud2df : HInst<
4279 (outs DoubleRegs:$Rdd32),
4280 (ins DoubleRegs:$Rss32),
4281 "$Rdd32 = convert_ud2df($Rss32)",
4282 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
4283 let Inst{13-5} = 0b000000010;
4284 let Inst{31-21} = 0b10000000111;
4288 def F2_conv_ud2sf : HInst<
4289 (outs IntRegs:$Rd32),
4290 (ins DoubleRegs:$Rss32),
4291 "$Rd32 = convert_ud2sf($Rss32)",
4292 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
4293 let Inst{13-5} = 0b000000001;
4294 let Inst{31-21} = 0b10001000001;
4295 let hasNewValue = 1;
4300 def F2_conv_uw2df : HInst<
4301 (outs DoubleRegs:$Rdd32),
4302 (ins IntRegs:$Rs32),
4303 "$Rdd32 = convert_uw2df($Rs32)",
4304 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4305 let Inst{13-5} = 0b000000001;
4306 let Inst{31-21} = 0b10000100100;
4310 def F2_conv_uw2sf : HInst<
4311 (outs IntRegs:$Rd32),
4312 (ins IntRegs:$Rs32),
4313 "$Rd32 = convert_uw2sf($Rs32)",
4314 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4315 let Inst{13-5} = 0b000000000;
4316 let Inst{31-21} = 0b10001011001;
4317 let hasNewValue = 1;
4322 def F2_conv_w2df : HInst<
4323 (outs DoubleRegs:$Rdd32),
4324 (ins IntRegs:$Rs32),
4325 "$Rdd32 = convert_w2df($Rs32)",
4326 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
4327 let Inst{13-5} = 0b000000010;
4328 let Inst{31-21} = 0b10000100100;
4332 def F2_conv_w2sf : HInst<
4333 (outs IntRegs:$Rd32),
4334 (ins IntRegs:$Rs32),
4335 "$Rd32 = convert_w2sf($Rs32)",
4336 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4337 let Inst{13-5} = 0b000000000;
4338 let Inst{31-21} = 0b10001011010;
4339 let hasNewValue = 1;
4344 def F2_dfclass : HInst<
4345 (outs PredRegs:$Pd4),
4346 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4347 "$Pd4 = dfclass($Rss32,#$Ii)",
4348 tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> {
4349 let Inst{4-2} = 0b100;
4350 let Inst{13-10} = 0b0000;
4351 let Inst{31-21} = 0b11011100100;
4355 def F2_dfcmpeq : HInst<
4356 (outs PredRegs:$Pd4),
4357 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4358 "$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4359 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
4360 let Inst{7-2} = 0b000000;
4361 let Inst{13-13} = 0b0;
4362 let Inst{31-21} = 0b11010010111;
4367 def F2_dfcmpge : HInst<
4368 (outs PredRegs:$Pd4),
4369 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4370 "$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4371 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
4372 let Inst{7-2} = 0b010000;
4373 let Inst{13-13} = 0b0;
4374 let Inst{31-21} = 0b11010010111;
4379 def F2_dfcmpgt : HInst<
4380 (outs PredRegs:$Pd4),
4381 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4382 "$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4383 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
4384 let Inst{7-2} = 0b001000;
4385 let Inst{13-13} = 0b0;
4386 let Inst{31-21} = 0b11010010111;
4391 def F2_dfcmpuo : HInst<
4392 (outs PredRegs:$Pd4),
4393 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4394 "$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4395 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
4396 let Inst{7-2} = 0b011000;
4397 let Inst{13-13} = 0b0;
4398 let Inst{31-21} = 0b11010010111;
4403 def F2_dfimm_n : HInst<
4404 (outs DoubleRegs:$Rdd32),
4406 "$Rdd32 = dfmake(#$Ii):neg",
4407 tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
4408 let Inst{20-16} = 0b00000;
4409 let Inst{31-22} = 0b1101100101;
4410 let prefersSlot3 = 1;
4412 def F2_dfimm_p : HInst<
4413 (outs DoubleRegs:$Rdd32),
4415 "$Rdd32 = dfmake(#$Ii):pos",
4416 tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
4417 let Inst{20-16} = 0b00000;
4418 let Inst{31-22} = 0b1101100100;
4419 let prefersSlot3 = 1;
4421 def F2_sfadd : HInst<
4422 (outs IntRegs:$Rd32),
4423 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4424 "$Rd32 = sfadd($Rs32,$Rt32)",
4425 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4426 let Inst{7-5} = 0b000;
4427 let Inst{13-13} = 0b0;
4428 let Inst{31-21} = 0b11101011000;
4429 let hasNewValue = 1;
4433 let isCommutable = 1;
4435 def F2_sfclass : HInst<
4436 (outs PredRegs:$Pd4),
4437 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
4438 "$Pd4 = sfclass($Rs32,#$Ii)",
4439 tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> {
4440 let Inst{7-2} = 0b000000;
4441 let Inst{13-13} = 0b0;
4442 let Inst{31-21} = 0b10000101111;
4446 def F2_sfcmpeq : HInst<
4447 (outs PredRegs:$Pd4),
4448 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4449 "$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4450 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
4451 let Inst{7-2} = 0b011000;
4452 let Inst{13-13} = 0b0;
4453 let Inst{31-21} = 0b11000111111;
4458 def F2_sfcmpge : HInst<
4459 (outs PredRegs:$Pd4),
4460 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4461 "$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4462 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
4463 let Inst{7-2} = 0b000000;
4464 let Inst{13-13} = 0b0;
4465 let Inst{31-21} = 0b11000111111;
4470 def F2_sfcmpgt : HInst<
4471 (outs PredRegs:$Pd4),
4472 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4473 "$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4474 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
4475 let Inst{7-2} = 0b100000;
4476 let Inst{13-13} = 0b0;
4477 let Inst{31-21} = 0b11000111111;
4482 def F2_sfcmpuo : HInst<
4483 (outs PredRegs:$Pd4),
4484 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4485 "$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4486 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
4487 let Inst{7-2} = 0b001000;
4488 let Inst{13-13} = 0b0;
4489 let Inst{31-21} = 0b11000111111;
4494 def F2_sffixupd : HInst<
4495 (outs IntRegs:$Rd32),
4496 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4497 "$Rd32 = sffixupd($Rs32,$Rt32)",
4498 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4499 let Inst{7-5} = 0b001;
4500 let Inst{13-13} = 0b0;
4501 let Inst{31-21} = 0b11101011110;
4502 let hasNewValue = 1;
4506 def F2_sffixupn : HInst<
4507 (outs IntRegs:$Rd32),
4508 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4509 "$Rd32 = sffixupn($Rs32,$Rt32)",
4510 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4511 let Inst{7-5} = 0b000;
4512 let Inst{13-13} = 0b0;
4513 let Inst{31-21} = 0b11101011110;
4514 let hasNewValue = 1;
4518 def F2_sffixupr : HInst<
4519 (outs IntRegs:$Rd32),
4520 (ins IntRegs:$Rs32),
4521 "$Rd32 = sffixupr($Rs32)",
4522 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
4523 let Inst{13-5} = 0b000000000;
4524 let Inst{31-21} = 0b10001011101;
4525 let hasNewValue = 1;
4529 def F2_sffma : HInst<
4530 (outs IntRegs:$Rx32),
4531 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4532 "$Rx32 += sfmpy($Rs32,$Rt32)",
4533 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
4534 let Inst{7-5} = 0b100;
4535 let Inst{13-13} = 0b0;
4536 let Inst{31-21} = 0b11101111000;
4537 let hasNewValue = 1;
4541 let Constraints = "$Rx32 = $Rx32in";
4543 def F2_sffma_lib : HInst<
4544 (outs IntRegs:$Rx32),
4545 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4546 "$Rx32 += sfmpy($Rs32,$Rt32):lib",
4547 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
4548 let Inst{7-5} = 0b110;
4549 let Inst{13-13} = 0b0;
4550 let Inst{31-21} = 0b11101111000;
4551 let hasNewValue = 1;
4555 let Constraints = "$Rx32 = $Rx32in";
4557 def F2_sffma_sc : HInst<
4558 (outs IntRegs:$Rx32),
4559 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4560 "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4561 tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5T]> {
4562 let Inst{7-7} = 0b1;
4563 let Inst{13-13} = 0b0;
4564 let Inst{31-21} = 0b11101111011;
4565 let hasNewValue = 1;
4569 let Constraints = "$Rx32 = $Rx32in";
4571 def F2_sffms : HInst<
4572 (outs IntRegs:$Rx32),
4573 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4574 "$Rx32 -= sfmpy($Rs32,$Rt32)",
4575 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
4576 let Inst{7-5} = 0b101;
4577 let Inst{13-13} = 0b0;
4578 let Inst{31-21} = 0b11101111000;
4579 let hasNewValue = 1;
4583 let Constraints = "$Rx32 = $Rx32in";
4585 def F2_sffms_lib : HInst<
4586 (outs IntRegs:$Rx32),
4587 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4588 "$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4589 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
4590 let Inst{7-5} = 0b111;
4591 let Inst{13-13} = 0b0;
4592 let Inst{31-21} = 0b11101111000;
4593 let hasNewValue = 1;
4597 let Constraints = "$Rx32 = $Rx32in";
4599 def F2_sfimm_n : HInst<
4600 (outs IntRegs:$Rd32),
4602 "$Rd32 = sfmake(#$Ii):neg",
4603 tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
4604 let Inst{20-16} = 0b00000;
4605 let Inst{31-22} = 0b1101011001;
4606 let hasNewValue = 1;
4608 let prefersSlot3 = 1;
4610 def F2_sfimm_p : HInst<
4611 (outs IntRegs:$Rd32),
4613 "$Rd32 = sfmake(#$Ii):pos",
4614 tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
4615 let Inst{20-16} = 0b00000;
4616 let Inst{31-22} = 0b1101011000;
4617 let hasNewValue = 1;
4619 let prefersSlot3 = 1;
4621 def F2_sfinvsqrta : HInst<
4622 (outs IntRegs:$Rd32, PredRegs:$Pe4),
4623 (ins IntRegs:$Rs32),
4624 "$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4625 tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5T]> {
4626 let Inst{13-7} = 0b0000000;
4627 let Inst{31-21} = 0b10001011111;
4628 let hasNewValue = 1;
4631 let isPredicateLate = 1;
4633 def F2_sfmax : HInst<
4634 (outs IntRegs:$Rd32),
4635 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4636 "$Rd32 = sfmax($Rs32,$Rt32)",
4637 tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4638 let Inst{7-5} = 0b000;
4639 let Inst{13-13} = 0b0;
4640 let Inst{31-21} = 0b11101011100;
4641 let hasNewValue = 1;
4644 let prefersSlot3 = 1;
4647 def F2_sfmin : HInst<
4648 (outs IntRegs:$Rd32),
4649 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4650 "$Rd32 = sfmin($Rs32,$Rt32)",
4651 tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4652 let Inst{7-5} = 0b001;
4653 let Inst{13-13} = 0b0;
4654 let Inst{31-21} = 0b11101011100;
4655 let hasNewValue = 1;
4658 let prefersSlot3 = 1;
4661 def F2_sfmpy : HInst<
4662 (outs IntRegs:$Rd32),
4663 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4664 "$Rd32 = sfmpy($Rs32,$Rt32)",
4665 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4666 let Inst{7-5} = 0b000;
4667 let Inst{13-13} = 0b0;
4668 let Inst{31-21} = 0b11101011010;
4669 let hasNewValue = 1;
4673 let isCommutable = 1;
4675 def F2_sfrecipa : HInst<
4676 (outs IntRegs:$Rd32, PredRegs:$Pe4),
4677 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4678 "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4679 tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5T]> {
4680 let Inst{7-7} = 0b1;
4681 let Inst{13-13} = 0b0;
4682 let Inst{31-21} = 0b11101011111;
4683 let hasNewValue = 1;
4686 let isPredicateLate = 1;
4688 def F2_sfsub : HInst<
4689 (outs IntRegs:$Rd32),
4690 (ins IntRegs:$Rs32, IntRegs:$Rt32),
4691 "$Rd32 = sfsub($Rs32,$Rt32)",
4692 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
4693 let Inst{7-5} = 0b001;
4694 let Inst{13-13} = 0b0;
4695 let Inst{31-21} = 0b11101011000;
4696 let hasNewValue = 1;
4701 def J2_call : HInst<
4705 tc_a27582fa, TypeJ>, Enc_81ac1d, PredRel {
4706 let Inst{0-0} = 0b0;
4707 let Inst{31-25} = 0b0101101;
4709 let prefersSlot3 = 1;
4713 let Defs = [PC, R31];
4714 let BaseOpcode = "J2_call";
4715 let isPredicable = 1;
4716 let hasSideEffects = 1;
4717 let isExtendable = 1;
4718 let opExtendable = 0;
4719 let isExtentSigned = 1;
4720 let opExtentBits = 24;
4721 let opExtentAlign = 2;
4723 def J2_callf : HInst<
4725 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
4726 "if (!$Pu4) call $Ii",
4727 tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
4728 let Inst{0-0} = 0b0;
4729 let Inst{12-10} = 0b000;
4730 let Inst{21-21} = 0b1;
4731 let Inst{31-24} = 0b01011101;
4732 let isPredicated = 1;
4733 let isPredicatedFalse = 1;
4735 let prefersSlot3 = 1;
4740 let Defs = [PC, R31];
4741 let BaseOpcode = "J2_call";
4742 let hasSideEffects = 1;
4743 let isTaken = Inst{12};
4744 let isExtendable = 1;
4745 let opExtendable = 1;
4746 let isExtentSigned = 1;
4747 let opExtentBits = 17;
4748 let opExtentAlign = 2;
4750 def J2_callr : HInst<
4752 (ins IntRegs:$Rs32),
4754 tc_15411484, TypeJ>, Enc_ecbcc8 {
4755 let Inst{13-0} = 0b00000000000000;
4756 let Inst{31-21} = 0b01010000101;
4758 let prefersSlot3 = 1;
4761 let Defs = [PC, R31];
4762 let hasSideEffects = 1;
4764 def J2_callrf : HInst<
4766 (ins PredRegs:$Pu4, IntRegs:$Rs32),
4767 "if (!$Pu4) callr $Rs32",
4768 tc_10b97e27, TypeJ>, Enc_88d4d9 {
4769 let Inst{7-0} = 0b00000000;
4770 let Inst{13-10} = 0b0000;
4771 let Inst{31-21} = 0b01010001001;
4772 let isPredicated = 1;
4773 let isPredicatedFalse = 1;
4775 let prefersSlot3 = 1;
4778 let Defs = [PC, R31];
4779 let hasSideEffects = 1;
4780 let isTaken = Inst{12};
4782 def J2_callrt : HInst<
4784 (ins PredRegs:$Pu4, IntRegs:$Rs32),
4785 "if ($Pu4) callr $Rs32",
4786 tc_10b97e27, TypeJ>, Enc_88d4d9 {
4787 let Inst{7-0} = 0b00000000;
4788 let Inst{13-10} = 0b0000;
4789 let Inst{31-21} = 0b01010001000;
4790 let isPredicated = 1;
4792 let prefersSlot3 = 1;
4795 let Defs = [PC, R31];
4796 let hasSideEffects = 1;
4797 let isTaken = Inst{12};
4799 def J2_callt : HInst<
4801 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
4802 "if ($Pu4) call $Ii",
4803 tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
4804 let Inst{0-0} = 0b0;
4805 let Inst{12-10} = 0b000;
4806 let Inst{21-21} = 0b0;
4807 let Inst{31-24} = 0b01011101;
4808 let isPredicated = 1;
4810 let prefersSlot3 = 1;
4815 let Defs = [PC, R31];
4816 let BaseOpcode = "J2_call";
4817 let hasSideEffects = 1;
4818 let isTaken = Inst{12};
4819 let isExtendable = 1;
4820 let opExtendable = 1;
4821 let isExtentSigned = 1;
4822 let opExtentBits = 17;
4823 let opExtentAlign = 2;
4825 def J2_endloop0 : HInst<
4829 tc_52d7bbea, TypeJ> {
4830 let Uses = [LC0, SA0];
4831 let Defs = [LC0, P3, PC, USR];
4833 let isTerminator = 1;
4836 def J2_endloop01 : HInst<
4840 tc_52d7bbea, TypeJ> {
4841 let Uses = [LC0, LC1, SA0, SA1];
4842 let Defs = [LC0, LC1, P3, PC, USR];
4845 def J2_endloop1 : HInst<
4849 tc_52d7bbea, TypeJ> {
4850 let Uses = [LC1, SA1];
4851 let Defs = [LC1, PC];
4853 let isTerminator = 1;
4856 def J2_jump : HInst<
4860 tc_3669266a, TypeJ>, Enc_81ac1d, PredNewRel {
4861 let Inst{0-0} = 0b0;
4862 let Inst{31-25} = 0b0101100;
4863 let isTerminator = 1;
4868 let InputType = "imm";
4869 let BaseOpcode = "J2_jump";
4871 let isPredicable = 1;
4872 let isExtendable = 1;
4873 let opExtendable = 0;
4874 let isExtentSigned = 1;
4875 let opExtentBits = 24;
4876 let opExtentAlign = 2;
4878 def J2_jumpf : HInst<
4880 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
4881 "if (!$Pu4) jump:nt $Ii",
4882 tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
4883 let Inst{0-0} = 0b0;
4884 let Inst{12-10} = 0b000;
4885 let Inst{21-21} = 0b1;
4886 let Inst{31-24} = 0b01011100;
4887 let isPredicated = 1;
4888 let isPredicatedFalse = 1;
4889 let isTerminator = 1;
4895 let InputType = "imm";
4896 let BaseOpcode = "J2_jump";
4897 let isTaken = Inst{12};
4898 let isExtendable = 1;
4899 let opExtendable = 1;
4900 let isExtentSigned = 1;
4901 let opExtentBits = 17;
4902 let opExtentAlign = 2;
4904 def J2_jumpf_nopred_map : HInst<
4906 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
4907 "if (!$Pu4) jump $Ii",
4908 tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> {
4910 let isCodeGenOnly = 1;
4912 def J2_jumpfnew : HInst<
4914 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
4915 "if (!$Pu4.new) jump:nt $Ii",
4916 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
4917 let Inst{0-0} = 0b0;
4918 let Inst{12-10} = 0b010;
4919 let Inst{21-21} = 0b1;
4920 let Inst{31-24} = 0b01011100;
4921 let isPredicated = 1;
4922 let isPredicatedFalse = 1;
4923 let isTerminator = 1;
4925 let isPredicatedNew = 1;
4930 let InputType = "imm";
4931 let BaseOpcode = "J2_jump";
4932 let isTaken = Inst{12};
4933 let isExtendable = 1;
4934 let opExtendable = 1;
4935 let isExtentSigned = 1;
4936 let opExtentBits = 17;
4937 let opExtentAlign = 2;
4939 def J2_jumpfnewpt : HInst<
4941 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
4942 "if (!$Pu4.new) jump:t $Ii",
4943 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
4944 let Inst{0-0} = 0b0;
4945 let Inst{12-10} = 0b110;
4946 let Inst{21-21} = 0b1;
4947 let Inst{31-24} = 0b01011100;
4948 let isPredicated = 1;
4949 let isPredicatedFalse = 1;
4950 let isTerminator = 1;
4952 let isPredicatedNew = 1;
4957 let InputType = "imm";
4958 let BaseOpcode = "J2_jump";
4959 let isTaken = Inst{12};
4960 let isExtendable = 1;
4961 let opExtendable = 1;
4962 let isExtentSigned = 1;
4963 let opExtentBits = 17;
4964 let opExtentAlign = 2;
4966 def J2_jumpfpt : HInst<
4968 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
4969 "if (!$Pu4) jump:t $Ii",
4970 tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
4971 let Inst{0-0} = 0b0;
4972 let Inst{12-10} = 0b100;
4973 let Inst{21-21} = 0b1;
4974 let Inst{31-24} = 0b01011100;
4975 let isPredicated = 1;
4976 let isPredicatedFalse = 1;
4977 let isTerminator = 1;
4983 let InputType = "imm";
4984 let BaseOpcode = "J2_jump";
4985 let isTaken = Inst{12};
4986 let isExtendable = 1;
4987 let opExtendable = 1;
4988 let isExtentSigned = 1;
4989 let opExtentBits = 17;
4990 let opExtentAlign = 2;
4992 def J2_jumpr : HInst<
4994 (ins IntRegs:$Rs32),
4996 tc_9faf76ae, TypeJ>, Enc_ecbcc8, PredNewRel {
4997 let Inst{13-0} = 0b00000000000000;
4998 let Inst{31-21} = 0b01010010100;
4999 let isTerminator = 1;
5000 let isIndirectBranch = 1;
5004 let InputType = "reg";
5005 let BaseOpcode = "J2_jumpr";
5007 let isPredicable = 1;
5009 def J2_jumprf : HInst<
5011 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5012 "if (!$Pu4) jumpr:nt $Rs32",
5013 tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
5014 let Inst{7-0} = 0b00000000;
5015 let Inst{13-10} = 0b0000;
5016 let Inst{31-21} = 0b01010011011;
5017 let isPredicated = 1;
5018 let isPredicatedFalse = 1;
5019 let isTerminator = 1;
5020 let isIndirectBranch = 1;
5024 let InputType = "reg";
5025 let BaseOpcode = "J2_jumpr";
5026 let isTaken = Inst{12};
5028 def J2_jumprf_nopred_map : HInst<
5030 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5031 "if (!$Pu4) jumpr $Rs32",
5032 tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> {
5034 let isCodeGenOnly = 1;
5036 def J2_jumprfnew : HInst<
5038 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5039 "if (!$Pu4.new) jumpr:nt $Rs32",
5040 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
5041 let Inst{7-0} = 0b00000000;
5042 let Inst{13-10} = 0b0010;
5043 let Inst{31-21} = 0b01010011011;
5044 let isPredicated = 1;
5045 let isPredicatedFalse = 1;
5046 let isTerminator = 1;
5047 let isIndirectBranch = 1;
5049 let isPredicatedNew = 1;
5052 let InputType = "reg";
5053 let BaseOpcode = "J2_jumpr";
5054 let isTaken = Inst{12};
5056 def J2_jumprfnewpt : HInst<
5058 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5059 "if (!$Pu4.new) jumpr:t $Rs32",
5060 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
5061 let Inst{7-0} = 0b00000000;
5062 let Inst{13-10} = 0b0110;
5063 let Inst{31-21} = 0b01010011011;
5064 let isPredicated = 1;
5065 let isPredicatedFalse = 1;
5066 let isTerminator = 1;
5067 let isIndirectBranch = 1;
5069 let isPredicatedNew = 1;
5072 let InputType = "reg";
5073 let BaseOpcode = "J2_jumpr";
5074 let isTaken = Inst{12};
5076 def J2_jumprfpt : HInst<
5078 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5079 "if (!$Pu4) jumpr:t $Rs32",
5080 tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
5081 let Inst{7-0} = 0b00000000;
5082 let Inst{13-10} = 0b0100;
5083 let Inst{31-21} = 0b01010011011;
5084 let isPredicated = 1;
5085 let isPredicatedFalse = 1;
5086 let isTerminator = 1;
5087 let isIndirectBranch = 1;
5091 let InputType = "reg";
5092 let BaseOpcode = "J2_jumpr";
5093 let isTaken = Inst{12};
5095 def J2_jumprgtez : HInst<
5097 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5098 "if ($Rs32>=#0) jump:nt $Ii",
5099 tc_73043bf4, TypeCR>, Enc_0fa531 {
5100 let Inst{0-0} = 0b0;
5101 let Inst{12-12} = 0b0;
5102 let Inst{31-22} = 0b0110000101;
5103 let isPredicated = 1;
5104 let isTerminator = 1;
5106 let isPredicatedNew = 1;
5111 let isTaken = Inst{12};
5113 def J2_jumprgtezpt : HInst<
5115 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5116 "if ($Rs32>=#0) jump:t $Ii",
5117 tc_73043bf4, TypeCR>, Enc_0fa531 {
5118 let Inst{0-0} = 0b0;
5119 let Inst{12-12} = 0b1;
5120 let Inst{31-22} = 0b0110000101;
5121 let isPredicated = 1;
5122 let isTerminator = 1;
5124 let isPredicatedNew = 1;
5129 let isTaken = Inst{12};
5131 def J2_jumprltez : HInst<
5133 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5134 "if ($Rs32<=#0) jump:nt $Ii",
5135 tc_73043bf4, TypeCR>, Enc_0fa531 {
5136 let Inst{0-0} = 0b0;
5137 let Inst{12-12} = 0b0;
5138 let Inst{31-22} = 0b0110000111;
5139 let isPredicated = 1;
5140 let isTerminator = 1;
5142 let isPredicatedNew = 1;
5147 let isTaken = Inst{12};
5149 def J2_jumprltezpt : HInst<
5151 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5152 "if ($Rs32<=#0) jump:t $Ii",
5153 tc_73043bf4, TypeCR>, Enc_0fa531 {
5154 let Inst{0-0} = 0b0;
5155 let Inst{12-12} = 0b1;
5156 let Inst{31-22} = 0b0110000111;
5157 let isPredicated = 1;
5158 let isTerminator = 1;
5160 let isPredicatedNew = 1;
5165 let isTaken = Inst{12};
5167 def J2_jumprnz : HInst<
5169 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5170 "if ($Rs32==#0) jump:nt $Ii",
5171 tc_73043bf4, TypeCR>, Enc_0fa531 {
5172 let Inst{0-0} = 0b0;
5173 let Inst{12-12} = 0b0;
5174 let Inst{31-22} = 0b0110000110;
5175 let isPredicated = 1;
5176 let isTerminator = 1;
5178 let isPredicatedNew = 1;
5183 let isTaken = Inst{12};
5185 def J2_jumprnzpt : HInst<
5187 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5188 "if ($Rs32==#0) jump:t $Ii",
5189 tc_73043bf4, TypeCR>, Enc_0fa531 {
5190 let Inst{0-0} = 0b0;
5191 let Inst{12-12} = 0b1;
5192 let Inst{31-22} = 0b0110000110;
5193 let isPredicated = 1;
5194 let isTerminator = 1;
5196 let isPredicatedNew = 1;
5201 let isTaken = Inst{12};
5203 def J2_jumprt : HInst<
5205 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5206 "if ($Pu4) jumpr:nt $Rs32",
5207 tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
5208 let Inst{7-0} = 0b00000000;
5209 let Inst{13-10} = 0b0000;
5210 let Inst{31-21} = 0b01010011010;
5211 let isPredicated = 1;
5212 let isTerminator = 1;
5213 let isIndirectBranch = 1;
5217 let InputType = "reg";
5218 let BaseOpcode = "J2_jumpr";
5219 let isTaken = Inst{12};
5221 def J2_jumprt_nopred_map : HInst<
5223 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5224 "if ($Pu4) jumpr $Rs32",
5225 tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> {
5227 let isCodeGenOnly = 1;
5229 def J2_jumprtnew : HInst<
5231 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5232 "if ($Pu4.new) jumpr:nt $Rs32",
5233 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
5234 let Inst{7-0} = 0b00000000;
5235 let Inst{13-10} = 0b0010;
5236 let Inst{31-21} = 0b01010011010;
5237 let isPredicated = 1;
5238 let isTerminator = 1;
5239 let isIndirectBranch = 1;
5241 let isPredicatedNew = 1;
5244 let InputType = "reg";
5245 let BaseOpcode = "J2_jumpr";
5246 let isTaken = Inst{12};
5248 def J2_jumprtnewpt : HInst<
5250 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5251 "if ($Pu4.new) jumpr:t $Rs32",
5252 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
5253 let Inst{7-0} = 0b00000000;
5254 let Inst{13-10} = 0b0110;
5255 let Inst{31-21} = 0b01010011010;
5256 let isPredicated = 1;
5257 let isTerminator = 1;
5258 let isIndirectBranch = 1;
5260 let isPredicatedNew = 1;
5263 let InputType = "reg";
5264 let BaseOpcode = "J2_jumpr";
5265 let isTaken = Inst{12};
5267 def J2_jumprtpt : HInst<
5269 (ins PredRegs:$Pu4, IntRegs:$Rs32),
5270 "if ($Pu4) jumpr:t $Rs32",
5271 tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
5272 let Inst{7-0} = 0b00000000;
5273 let Inst{13-10} = 0b0100;
5274 let Inst{31-21} = 0b01010011010;
5275 let isPredicated = 1;
5276 let isTerminator = 1;
5277 let isIndirectBranch = 1;
5281 let InputType = "reg";
5282 let BaseOpcode = "J2_jumpr";
5283 let isTaken = Inst{12};
5285 def J2_jumprz : HInst<
5287 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5288 "if ($Rs32!=#0) jump:nt $Ii",
5289 tc_73043bf4, TypeCR>, Enc_0fa531 {
5290 let Inst{0-0} = 0b0;
5291 let Inst{12-12} = 0b0;
5292 let Inst{31-22} = 0b0110000100;
5293 let isPredicated = 1;
5294 let isTerminator = 1;
5296 let isPredicatedNew = 1;
5301 let isTaken = Inst{12};
5303 def J2_jumprzpt : HInst<
5305 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
5306 "if ($Rs32!=#0) jump:t $Ii",
5307 tc_73043bf4, TypeCR>, Enc_0fa531 {
5308 let Inst{0-0} = 0b0;
5309 let Inst{12-12} = 0b1;
5310 let Inst{31-22} = 0b0110000100;
5311 let isPredicated = 1;
5312 let isTerminator = 1;
5314 let isPredicatedNew = 1;
5319 let isTaken = Inst{12};
5321 def J2_jumpt : HInst<
5323 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
5324 "if ($Pu4) jump:nt $Ii",
5325 tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
5326 let Inst{0-0} = 0b0;
5327 let Inst{12-10} = 0b000;
5328 let Inst{21-21} = 0b0;
5329 let Inst{31-24} = 0b01011100;
5330 let isPredicated = 1;
5331 let isTerminator = 1;
5337 let InputType = "imm";
5338 let BaseOpcode = "J2_jump";
5339 let isTaken = Inst{12};
5340 let isExtendable = 1;
5341 let opExtendable = 1;
5342 let isExtentSigned = 1;
5343 let opExtentBits = 17;
5344 let opExtentAlign = 2;
5346 def J2_jumpt_nopred_map : HInst<
5348 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
5349 "if ($Pu4) jump $Ii",
5350 tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> {
5352 let isCodeGenOnly = 1;
5354 def J2_jumptnew : HInst<
5356 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
5357 "if ($Pu4.new) jump:nt $Ii",
5358 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
5359 let Inst{0-0} = 0b0;
5360 let Inst{12-10} = 0b010;
5361 let Inst{21-21} = 0b0;
5362 let Inst{31-24} = 0b01011100;
5363 let isPredicated = 1;
5364 let isTerminator = 1;
5366 let isPredicatedNew = 1;
5371 let InputType = "imm";
5372 let BaseOpcode = "J2_jump";
5373 let isTaken = Inst{12};
5374 let isExtendable = 1;
5375 let opExtendable = 1;
5376 let isExtentSigned = 1;
5377 let opExtentBits = 17;
5378 let opExtentAlign = 2;
5380 def J2_jumptnewpt : HInst<
5382 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
5383 "if ($Pu4.new) jump:t $Ii",
5384 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
5385 let Inst{0-0} = 0b0;
5386 let Inst{12-10} = 0b110;
5387 let Inst{21-21} = 0b0;
5388 let Inst{31-24} = 0b01011100;
5389 let isPredicated = 1;
5390 let isTerminator = 1;
5392 let isPredicatedNew = 1;
5397 let InputType = "imm";
5398 let BaseOpcode = "J2_jump";
5399 let isTaken = Inst{12};
5400 let isExtendable = 1;
5401 let opExtendable = 1;
5402 let isExtentSigned = 1;
5403 let opExtentBits = 17;
5404 let opExtentAlign = 2;
5406 def J2_jumptpt : HInst<
5408 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
5409 "if ($Pu4) jump:t $Ii",
5410 tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
5411 let Inst{0-0} = 0b0;
5412 let Inst{12-10} = 0b100;
5413 let Inst{21-21} = 0b0;
5414 let Inst{31-24} = 0b01011100;
5415 let isPredicated = 1;
5416 let isTerminator = 1;
5422 let InputType = "imm";
5423 let BaseOpcode = "J2_jump";
5424 let isTaken = Inst{12};
5425 let isExtendable = 1;
5426 let opExtendable = 1;
5427 let isExtentSigned = 1;
5428 let opExtentBits = 17;
5429 let opExtentAlign = 2;
5431 def J2_loop0i : HInst<
5433 (ins b30_2Imm:$Ii, u10_0Imm:$II),
5435 tc_cf59f215, TypeCR>, Enc_4dc228 {
5436 let Inst{2-2} = 0b0;
5437 let Inst{13-13} = 0b0;
5438 let Inst{31-21} = 0b01101001000;
5441 let Defs = [LC0, SA0, USR];
5442 let isExtendable = 1;
5443 let opExtendable = 0;
5444 let isExtentSigned = 1;
5445 let opExtentBits = 9;
5446 let opExtentAlign = 2;
5448 def J2_loop0r : HInst<
5450 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
5452 tc_7934b9df, TypeCR>, Enc_864a5a {
5453 let Inst{2-0} = 0b000;
5454 let Inst{7-5} = 0b000;
5455 let Inst{13-13} = 0b0;
5456 let Inst{31-21} = 0b01100000000;
5459 let Defs = [LC0, SA0, USR];
5460 let isExtendable = 1;
5461 let opExtendable = 0;
5462 let isExtentSigned = 1;
5463 let opExtentBits = 9;
5464 let opExtentAlign = 2;
5466 def J2_loop1i : HInst<
5468 (ins b30_2Imm:$Ii, u10_0Imm:$II),
5470 tc_cf59f215, TypeCR>, Enc_4dc228 {
5471 let Inst{2-2} = 0b0;
5472 let Inst{13-13} = 0b0;
5473 let Inst{31-21} = 0b01101001001;
5476 let Defs = [LC1, SA1];
5477 let isExtendable = 1;
5478 let opExtendable = 0;
5479 let isExtentSigned = 1;
5480 let opExtentBits = 9;
5481 let opExtentAlign = 2;
5483 def J2_loop1r : HInst<
5485 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
5487 tc_7934b9df, TypeCR>, Enc_864a5a {
5488 let Inst{2-0} = 0b000;
5489 let Inst{7-5} = 0b000;
5490 let Inst{13-13} = 0b0;
5491 let Inst{31-21} = 0b01100000001;
5494 let Defs = [LC1, SA1];
5495 let isExtendable = 1;
5496 let opExtendable = 0;
5497 let isExtentSigned = 1;
5498 let opExtentBits = 9;
5499 let opExtentAlign = 2;
5501 def J2_pause : HInst<
5505 tc_681a2300, TypeJ>, Enc_a51a9a {
5506 let Inst{1-0} = 0b00;
5507 let Inst{7-5} = 0b000;
5508 let Inst{13-13} = 0b0;
5509 let Inst{31-16} = 0b0101010001000000;
5512 def J2_ploop1si : HInst<
5514 (ins b30_2Imm:$Ii, u10_0Imm:$II),
5515 "p3 = sp1loop0($Ii,#$II)",
5516 tc_c5e2426d, TypeCR>, Enc_4dc228 {
5517 let Inst{2-2} = 0b0;
5518 let Inst{13-13} = 0b0;
5519 let Inst{31-21} = 0b01101001101;
5520 let isPredicateLate = 1;
5523 let Defs = [LC0, P3, SA0, USR];
5524 let isExtendable = 1;
5525 let opExtendable = 0;
5526 let isExtentSigned = 1;
5527 let opExtentBits = 9;
5528 let opExtentAlign = 2;
5530 def J2_ploop1sr : HInst<
5532 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
5533 "p3 = sp1loop0($Ii,$Rs32)",
5534 tc_4f7cd700, TypeCR>, Enc_864a5a {
5535 let Inst{2-0} = 0b000;
5536 let Inst{7-5} = 0b000;
5537 let Inst{13-13} = 0b0;
5538 let Inst{31-21} = 0b01100000101;
5539 let isPredicateLate = 1;
5542 let Defs = [LC0, P3, SA0, USR];
5543 let isExtendable = 1;
5544 let opExtendable = 0;
5545 let isExtentSigned = 1;
5546 let opExtentBits = 9;
5547 let opExtentAlign = 2;
5549 def J2_ploop2si : HInst<
5551 (ins b30_2Imm:$Ii, u10_0Imm:$II),
5552 "p3 = sp2loop0($Ii,#$II)",
5553 tc_c5e2426d, TypeCR>, Enc_4dc228 {
5554 let Inst{2-2} = 0b0;
5555 let Inst{13-13} = 0b0;
5556 let Inst{31-21} = 0b01101001110;
5557 let isPredicateLate = 1;
5560 let Defs = [LC0, P3, SA0, USR];
5561 let isExtendable = 1;
5562 let opExtendable = 0;
5563 let isExtentSigned = 1;
5564 let opExtentBits = 9;
5565 let opExtentAlign = 2;
5567 def J2_ploop2sr : HInst<
5569 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
5570 "p3 = sp2loop0($Ii,$Rs32)",
5571 tc_4f7cd700, TypeCR>, Enc_864a5a {
5572 let Inst{2-0} = 0b000;
5573 let Inst{7-5} = 0b000;
5574 let Inst{13-13} = 0b0;
5575 let Inst{31-21} = 0b01100000110;
5576 let isPredicateLate = 1;
5579 let Defs = [LC0, P3, SA0, USR];
5580 let isExtendable = 1;
5581 let opExtendable = 0;
5582 let isExtentSigned = 1;
5583 let opExtentBits = 9;
5584 let opExtentAlign = 2;
5586 def J2_ploop3si : HInst<
5588 (ins b30_2Imm:$Ii, u10_0Imm:$II),
5589 "p3 = sp3loop0($Ii,#$II)",
5590 tc_c5e2426d, TypeCR>, Enc_4dc228 {
5591 let Inst{2-2} = 0b0;
5592 let Inst{13-13} = 0b0;
5593 let Inst{31-21} = 0b01101001111;
5594 let isPredicateLate = 1;
5597 let Defs = [LC0, P3, SA0, USR];
5598 let isExtendable = 1;
5599 let opExtendable = 0;
5600 let isExtentSigned = 1;
5601 let opExtentBits = 9;
5602 let opExtentAlign = 2;
5604 def J2_ploop3sr : HInst<
5606 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
5607 "p3 = sp3loop0($Ii,$Rs32)",
5608 tc_4f7cd700, TypeCR>, Enc_864a5a {
5609 let Inst{2-0} = 0b000;
5610 let Inst{7-5} = 0b000;
5611 let Inst{13-13} = 0b0;
5612 let Inst{31-21} = 0b01100000111;
5613 let isPredicateLate = 1;
5616 let Defs = [LC0, P3, SA0, USR];
5617 let isExtendable = 1;
5618 let opExtendable = 0;
5619 let isExtentSigned = 1;
5620 let opExtentBits = 9;
5621 let opExtentAlign = 2;
5623 def J2_trap0 : HInst<
5627 tc_14cd4cfa, TypeJ>, Enc_a51a9a {
5628 let Inst{1-0} = 0b00;
5629 let Inst{7-5} = 0b000;
5630 let Inst{13-13} = 0b0;
5631 let Inst{31-16} = 0b0101010000000000;
5634 def J4_cmpeq_f_jumpnv_nt : HInst<
5636 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5637 "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5638 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
5639 let Inst{0-0} = 0b0;
5640 let Inst{13-13} = 0b0;
5641 let Inst{19-19} = 0b0;
5642 let Inst{31-22} = 0b0010000001;
5643 let isPredicated = 1;
5644 let isPredicatedFalse = 1;
5645 let isTerminator = 1;
5649 let isRestrictNoSlot1Store = 1;
5651 let BaseOpcode = "J4_cmpeqr";
5652 let isTaken = Inst{13};
5653 let isExtendable = 1;
5654 let opExtendable = 2;
5655 let isExtentSigned = 1;
5656 let opExtentBits = 11;
5657 let opExtentAlign = 2;
5660 def J4_cmpeq_f_jumpnv_t : HInst<
5662 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5663 "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5664 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
5665 let Inst{0-0} = 0b0;
5666 let Inst{13-13} = 0b1;
5667 let Inst{19-19} = 0b0;
5668 let Inst{31-22} = 0b0010000001;
5669 let isPredicated = 1;
5670 let isPredicatedFalse = 1;
5671 let isTerminator = 1;
5675 let isRestrictNoSlot1Store = 1;
5677 let BaseOpcode = "J4_cmpeqr";
5678 let isTaken = Inst{13};
5679 let isExtendable = 1;
5680 let opExtendable = 2;
5681 let isExtentSigned = 1;
5682 let opExtentBits = 11;
5683 let opExtentAlign = 2;
5686 def J4_cmpeq_fp0_jump_nt : HInst<
5688 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5689 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5690 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5691 let Inst{0-0} = 0b0;
5692 let Inst{13-12} = 0b00;
5693 let Inst{31-22} = 0b0001010001;
5694 let isPredicated = 1;
5695 let isPredicatedFalse = 1;
5696 let isTerminator = 1;
5698 let isPredicatedNew = 1;
5703 let Defs = [P0, PC];
5704 let BaseOpcode = "J4_cmpeqp0";
5705 let isTaken = Inst{13};
5706 let isExtendable = 1;
5707 let opExtendable = 2;
5708 let isExtentSigned = 1;
5709 let opExtentBits = 11;
5710 let opExtentAlign = 2;
5712 def J4_cmpeq_fp0_jump_t : HInst<
5714 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5715 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5716 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5717 let Inst{0-0} = 0b0;
5718 let Inst{13-12} = 0b10;
5719 let Inst{31-22} = 0b0001010001;
5720 let isPredicated = 1;
5721 let isPredicatedFalse = 1;
5722 let isTerminator = 1;
5724 let isPredicatedNew = 1;
5729 let Defs = [P0, PC];
5730 let BaseOpcode = "J4_cmpeqp0";
5731 let isTaken = Inst{13};
5732 let isExtendable = 1;
5733 let opExtendable = 2;
5734 let isExtentSigned = 1;
5735 let opExtentBits = 11;
5736 let opExtentAlign = 2;
5738 def J4_cmpeq_fp1_jump_nt : HInst<
5740 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5741 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5742 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5743 let Inst{0-0} = 0b0;
5744 let Inst{13-12} = 0b01;
5745 let Inst{31-22} = 0b0001010001;
5746 let isPredicated = 1;
5747 let isPredicatedFalse = 1;
5748 let isTerminator = 1;
5750 let isPredicatedNew = 1;
5755 let Defs = [P1, PC];
5756 let BaseOpcode = "J4_cmpeqp1";
5757 let isTaken = Inst{13};
5758 let isExtendable = 1;
5759 let opExtendable = 2;
5760 let isExtentSigned = 1;
5761 let opExtentBits = 11;
5762 let opExtentAlign = 2;
5764 def J4_cmpeq_fp1_jump_t : HInst<
5766 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5767 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
5768 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5769 let Inst{0-0} = 0b0;
5770 let Inst{13-12} = 0b11;
5771 let Inst{31-22} = 0b0001010001;
5772 let isPredicated = 1;
5773 let isPredicatedFalse = 1;
5774 let isTerminator = 1;
5776 let isPredicatedNew = 1;
5781 let Defs = [P1, PC];
5782 let BaseOpcode = "J4_cmpeqp1";
5783 let isTaken = Inst{13};
5784 let isExtendable = 1;
5785 let opExtendable = 2;
5786 let isExtentSigned = 1;
5787 let opExtentBits = 11;
5788 let opExtentAlign = 2;
5790 def J4_cmpeq_t_jumpnv_nt : HInst<
5792 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5793 "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5794 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
5795 let Inst{0-0} = 0b0;
5796 let Inst{13-13} = 0b0;
5797 let Inst{19-19} = 0b0;
5798 let Inst{31-22} = 0b0010000000;
5799 let isPredicated = 1;
5800 let isTerminator = 1;
5804 let isRestrictNoSlot1Store = 1;
5806 let BaseOpcode = "J4_cmpeqr";
5807 let isTaken = Inst{13};
5808 let isExtendable = 1;
5809 let opExtendable = 2;
5810 let isExtentSigned = 1;
5811 let opExtentBits = 11;
5812 let opExtentAlign = 2;
5815 def J4_cmpeq_t_jumpnv_t : HInst<
5817 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5818 "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5819 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
5820 let Inst{0-0} = 0b0;
5821 let Inst{13-13} = 0b1;
5822 let Inst{19-19} = 0b0;
5823 let Inst{31-22} = 0b0010000000;
5824 let isPredicated = 1;
5825 let isTerminator = 1;
5829 let isRestrictNoSlot1Store = 1;
5831 let BaseOpcode = "J4_cmpeqr";
5832 let isTaken = Inst{13};
5833 let isExtendable = 1;
5834 let opExtendable = 2;
5835 let isExtentSigned = 1;
5836 let opExtentBits = 11;
5837 let opExtentAlign = 2;
5840 def J4_cmpeq_tp0_jump_nt : HInst<
5842 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5843 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
5844 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5845 let Inst{0-0} = 0b0;
5846 let Inst{13-12} = 0b00;
5847 let Inst{31-22} = 0b0001010000;
5848 let isPredicated = 1;
5849 let isTerminator = 1;
5851 let isPredicatedNew = 1;
5856 let Defs = [P0, PC];
5857 let BaseOpcode = "J4_cmpeqp0";
5858 let isTaken = Inst{13};
5859 let isExtendable = 1;
5860 let opExtendable = 2;
5861 let isExtentSigned = 1;
5862 let opExtentBits = 11;
5863 let opExtentAlign = 2;
5865 def J4_cmpeq_tp0_jump_t : HInst<
5867 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5868 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
5869 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5870 let Inst{0-0} = 0b0;
5871 let Inst{13-12} = 0b10;
5872 let Inst{31-22} = 0b0001010000;
5873 let isPredicated = 1;
5874 let isTerminator = 1;
5876 let isPredicatedNew = 1;
5881 let Defs = [P0, PC];
5882 let BaseOpcode = "J4_cmpeqp0";
5883 let isTaken = Inst{13};
5884 let isExtendable = 1;
5885 let opExtendable = 2;
5886 let isExtentSigned = 1;
5887 let opExtentBits = 11;
5888 let opExtentAlign = 2;
5890 def J4_cmpeq_tp1_jump_nt : HInst<
5892 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5893 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
5894 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5895 let Inst{0-0} = 0b0;
5896 let Inst{13-12} = 0b01;
5897 let Inst{31-22} = 0b0001010000;
5898 let isPredicated = 1;
5899 let isTerminator = 1;
5901 let isPredicatedNew = 1;
5906 let Defs = [P1, PC];
5907 let BaseOpcode = "J4_cmpeqp1";
5908 let isTaken = Inst{13};
5909 let isExtendable = 1;
5910 let opExtendable = 2;
5911 let isExtentSigned = 1;
5912 let opExtentBits = 11;
5913 let opExtentAlign = 2;
5915 def J4_cmpeq_tp1_jump_t : HInst<
5917 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5918 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
5919 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
5920 let Inst{0-0} = 0b0;
5921 let Inst{13-12} = 0b11;
5922 let Inst{31-22} = 0b0001010000;
5923 let isPredicated = 1;
5924 let isTerminator = 1;
5926 let isPredicatedNew = 1;
5931 let Defs = [P1, PC];
5932 let BaseOpcode = "J4_cmpeqp1";
5933 let isTaken = Inst{13};
5934 let isExtendable = 1;
5935 let opExtendable = 2;
5936 let isExtentSigned = 1;
5937 let opExtentBits = 11;
5938 let opExtentAlign = 2;
5940 def J4_cmpeqi_f_jumpnv_nt : HInst<
5942 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
5943 "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
5944 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
5945 let Inst{0-0} = 0b0;
5946 let Inst{13-13} = 0b0;
5947 let Inst{19-19} = 0b0;
5948 let Inst{31-22} = 0b0010010001;
5949 let isPredicated = 1;
5950 let isPredicatedFalse = 1;
5951 let isTerminator = 1;
5955 let isRestrictNoSlot1Store = 1;
5957 let BaseOpcode = "J4_cmpeqi";
5958 let isTaken = Inst{13};
5959 let isExtendable = 1;
5960 let opExtendable = 2;
5961 let isExtentSigned = 1;
5962 let opExtentBits = 11;
5963 let opExtentAlign = 2;
5966 def J4_cmpeqi_f_jumpnv_t : HInst<
5968 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
5969 "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
5970 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
5971 let Inst{0-0} = 0b0;
5972 let Inst{13-13} = 0b1;
5973 let Inst{19-19} = 0b0;
5974 let Inst{31-22} = 0b0010010001;
5975 let isPredicated = 1;
5976 let isPredicatedFalse = 1;
5977 let isTerminator = 1;
5981 let isRestrictNoSlot1Store = 1;
5983 let BaseOpcode = "J4_cmpeqi";
5984 let isTaken = Inst{13};
5985 let isExtendable = 1;
5986 let opExtendable = 2;
5987 let isExtentSigned = 1;
5988 let opExtentBits = 11;
5989 let opExtentAlign = 2;
5992 def J4_cmpeqi_fp0_jump_nt : HInst<
5994 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
5995 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
5996 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
5997 let Inst{0-0} = 0b0;
5998 let Inst{13-13} = 0b0;
5999 let Inst{31-22} = 0b0001000001;
6000 let isPredicated = 1;
6001 let isPredicatedFalse = 1;
6002 let isTerminator = 1;
6004 let isPredicatedNew = 1;
6009 let Defs = [P0, PC];
6010 let BaseOpcode = "J4_cmpeqip0";
6011 let isTaken = Inst{13};
6012 let isExtendable = 1;
6013 let opExtendable = 2;
6014 let isExtentSigned = 1;
6015 let opExtentBits = 11;
6016 let opExtentAlign = 2;
6018 def J4_cmpeqi_fp0_jump_t : HInst<
6020 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6021 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6022 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6023 let Inst{0-0} = 0b0;
6024 let Inst{13-13} = 0b1;
6025 let Inst{31-22} = 0b0001000001;
6026 let isPredicated = 1;
6027 let isPredicatedFalse = 1;
6028 let isTerminator = 1;
6030 let isPredicatedNew = 1;
6035 let Defs = [P0, PC];
6036 let BaseOpcode = "J4_cmpeqip0";
6037 let isTaken = Inst{13};
6038 let isExtendable = 1;
6039 let opExtendable = 2;
6040 let isExtentSigned = 1;
6041 let opExtentBits = 11;
6042 let opExtentAlign = 2;
6044 def J4_cmpeqi_fp1_jump_nt : HInst<
6046 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6047 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6048 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6049 let Inst{0-0} = 0b0;
6050 let Inst{13-13} = 0b0;
6051 let Inst{31-22} = 0b0001001001;
6052 let isPredicated = 1;
6053 let isPredicatedFalse = 1;
6054 let isTerminator = 1;
6056 let isPredicatedNew = 1;
6061 let Defs = [P1, PC];
6062 let BaseOpcode = "J4_cmpeqip1";
6063 let isTaken = Inst{13};
6064 let isExtendable = 1;
6065 let opExtendable = 2;
6066 let isExtentSigned = 1;
6067 let opExtentBits = 11;
6068 let opExtentAlign = 2;
6070 def J4_cmpeqi_fp1_jump_t : HInst<
6072 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6073 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6074 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6075 let Inst{0-0} = 0b0;
6076 let Inst{13-13} = 0b1;
6077 let Inst{31-22} = 0b0001001001;
6078 let isPredicated = 1;
6079 let isPredicatedFalse = 1;
6080 let isTerminator = 1;
6082 let isPredicatedNew = 1;
6087 let Defs = [P1, PC];
6088 let BaseOpcode = "J4_cmpeqip1";
6089 let isTaken = Inst{13};
6090 let isExtendable = 1;
6091 let opExtendable = 2;
6092 let isExtentSigned = 1;
6093 let opExtentBits = 11;
6094 let opExtentAlign = 2;
6096 def J4_cmpeqi_t_jumpnv_nt : HInst<
6098 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6099 "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6100 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
6101 let Inst{0-0} = 0b0;
6102 let Inst{13-13} = 0b0;
6103 let Inst{19-19} = 0b0;
6104 let Inst{31-22} = 0b0010010000;
6105 let isPredicated = 1;
6106 let isTerminator = 1;
6110 let isRestrictNoSlot1Store = 1;
6112 let BaseOpcode = "J4_cmpeqi";
6113 let isTaken = Inst{13};
6114 let isExtendable = 1;
6115 let opExtendable = 2;
6116 let isExtentSigned = 1;
6117 let opExtentBits = 11;
6118 let opExtentAlign = 2;
6121 def J4_cmpeqi_t_jumpnv_t : HInst<
6123 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6124 "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6125 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
6126 let Inst{0-0} = 0b0;
6127 let Inst{13-13} = 0b1;
6128 let Inst{19-19} = 0b0;
6129 let Inst{31-22} = 0b0010010000;
6130 let isPredicated = 1;
6131 let isTerminator = 1;
6135 let isRestrictNoSlot1Store = 1;
6137 let BaseOpcode = "J4_cmpeqi";
6138 let isTaken = Inst{13};
6139 let isExtendable = 1;
6140 let opExtendable = 2;
6141 let isExtentSigned = 1;
6142 let opExtentBits = 11;
6143 let opExtentAlign = 2;
6146 def J4_cmpeqi_tp0_jump_nt : HInst<
6148 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6149 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6150 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6151 let Inst{0-0} = 0b0;
6152 let Inst{13-13} = 0b0;
6153 let Inst{31-22} = 0b0001000000;
6154 let isPredicated = 1;
6155 let isTerminator = 1;
6157 let isPredicatedNew = 1;
6162 let Defs = [P0, PC];
6163 let BaseOpcode = "J4_cmpeqip0";
6164 let isTaken = Inst{13};
6165 let isExtendable = 1;
6166 let opExtendable = 2;
6167 let isExtentSigned = 1;
6168 let opExtentBits = 11;
6169 let opExtentAlign = 2;
6171 def J4_cmpeqi_tp0_jump_t : HInst<
6173 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6174 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6175 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6176 let Inst{0-0} = 0b0;
6177 let Inst{13-13} = 0b1;
6178 let Inst{31-22} = 0b0001000000;
6179 let isPredicated = 1;
6180 let isTerminator = 1;
6182 let isPredicatedNew = 1;
6187 let Defs = [P0, PC];
6188 let BaseOpcode = "J4_cmpeqip0";
6189 let isTaken = Inst{13};
6190 let isExtendable = 1;
6191 let opExtendable = 2;
6192 let isExtentSigned = 1;
6193 let opExtentBits = 11;
6194 let opExtentAlign = 2;
6196 def J4_cmpeqi_tp1_jump_nt : HInst<
6198 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6199 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6200 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6201 let Inst{0-0} = 0b0;
6202 let Inst{13-13} = 0b0;
6203 let Inst{31-22} = 0b0001001000;
6204 let isPredicated = 1;
6205 let isTerminator = 1;
6207 let isPredicatedNew = 1;
6212 let Defs = [P1, PC];
6213 let BaseOpcode = "J4_cmpeqip1";
6214 let isTaken = Inst{13};
6215 let isExtendable = 1;
6216 let opExtendable = 2;
6217 let isExtentSigned = 1;
6218 let opExtentBits = 11;
6219 let opExtentAlign = 2;
6221 def J4_cmpeqi_tp1_jump_t : HInst<
6223 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6224 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6225 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6226 let Inst{0-0} = 0b0;
6227 let Inst{13-13} = 0b1;
6228 let Inst{31-22} = 0b0001001000;
6229 let isPredicated = 1;
6230 let isTerminator = 1;
6232 let isPredicatedNew = 1;
6237 let Defs = [P1, PC];
6238 let BaseOpcode = "J4_cmpeqip1";
6239 let isTaken = Inst{13};
6240 let isExtendable = 1;
6241 let opExtendable = 2;
6242 let isExtentSigned = 1;
6243 let opExtentBits = 11;
6244 let opExtentAlign = 2;
6246 def J4_cmpeqn1_f_jumpnv_nt : HInst<
6248 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6249 "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6250 tc_bde7aaf4, TypeNCJ>, Enc_e90a15, PredRel {
6251 let Inst{0-0} = 0b0;
6252 let Inst{13-8} = 0b000000;
6253 let Inst{19-19} = 0b0;
6254 let Inst{31-22} = 0b0010011001;
6255 let isPredicated = 1;
6256 let isPredicatedFalse = 1;
6257 let isTerminator = 1;
6261 let isRestrictNoSlot1Store = 1;
6263 let BaseOpcode = "J4_cmpeqn1r";
6264 let isTaken = Inst{13};
6265 let isExtendable = 1;
6266 let opExtendable = 2;
6267 let isExtentSigned = 1;
6268 let opExtentBits = 11;
6269 let opExtentAlign = 2;
6272 def J4_cmpeqn1_f_jumpnv_t : HInst<
6274 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6275 "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6276 tc_bde7aaf4, TypeNCJ>, Enc_5a18b3, PredRel {
6277 let Inst{0-0} = 0b0;
6278 let Inst{13-8} = 0b100000;
6279 let Inst{19-19} = 0b0;
6280 let Inst{31-22} = 0b0010011001;
6281 let isPredicated = 1;
6282 let isPredicatedFalse = 1;
6283 let isTerminator = 1;
6287 let isRestrictNoSlot1Store = 1;
6289 let BaseOpcode = "J4_cmpeqn1r";
6290 let isTaken = Inst{13};
6291 let isExtendable = 1;
6292 let opExtendable = 2;
6293 let isExtentSigned = 1;
6294 let opExtentBits = 11;
6295 let opExtentAlign = 2;
6298 def J4_cmpeqn1_fp0_jump_nt : HInst<
6300 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6301 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6302 tc_99be14ca, TypeCJ>, Enc_1de724, PredRel {
6303 let Inst{0-0} = 0b0;
6304 let Inst{13-8} = 0b000000;
6305 let Inst{31-22} = 0b0001000111;
6306 let isPredicated = 1;
6307 let isPredicatedFalse = 1;
6308 let isTerminator = 1;
6310 let isPredicatedNew = 1;
6315 let Defs = [P0, PC];
6316 let BaseOpcode = "J4_cmpeqn1p0";
6317 let isTaken = Inst{13};
6318 let isExtendable = 1;
6319 let opExtendable = 2;
6320 let isExtentSigned = 1;
6321 let opExtentBits = 11;
6322 let opExtentAlign = 2;
6324 def J4_cmpeqn1_fp0_jump_t : HInst<
6326 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6327 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6328 tc_99be14ca, TypeCJ>, Enc_14640c, PredRel {
6329 let Inst{0-0} = 0b0;
6330 let Inst{13-8} = 0b100000;
6331 let Inst{31-22} = 0b0001000111;
6332 let isPredicated = 1;
6333 let isPredicatedFalse = 1;
6334 let isTerminator = 1;
6336 let isPredicatedNew = 1;
6341 let Defs = [P0, PC];
6342 let BaseOpcode = "J4_cmpeqn1p0";
6343 let isTaken = Inst{13};
6344 let isExtendable = 1;
6345 let opExtendable = 2;
6346 let isExtentSigned = 1;
6347 let opExtentBits = 11;
6348 let opExtentAlign = 2;
6350 def J4_cmpeqn1_fp1_jump_nt : HInst<
6352 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6353 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6354 tc_99be14ca, TypeCJ>, Enc_668704, PredRel {
6355 let Inst{0-0} = 0b0;
6356 let Inst{13-8} = 0b000000;
6357 let Inst{31-22} = 0b0001001111;
6358 let isPredicated = 1;
6359 let isPredicatedFalse = 1;
6360 let isTerminator = 1;
6362 let isPredicatedNew = 1;
6367 let Defs = [P1, PC];
6368 let BaseOpcode = "J4_cmpeqn1p1";
6369 let isTaken = Inst{13};
6370 let isExtendable = 1;
6371 let opExtendable = 2;
6372 let isExtentSigned = 1;
6373 let opExtentBits = 11;
6374 let opExtentAlign = 2;
6376 def J4_cmpeqn1_fp1_jump_t : HInst<
6378 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6379 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6380 tc_99be14ca, TypeCJ>, Enc_800e04, PredRel {
6381 let Inst{0-0} = 0b0;
6382 let Inst{13-8} = 0b100000;
6383 let Inst{31-22} = 0b0001001111;
6384 let isPredicated = 1;
6385 let isPredicatedFalse = 1;
6386 let isTerminator = 1;
6388 let isPredicatedNew = 1;
6393 let Defs = [P1, PC];
6394 let BaseOpcode = "J4_cmpeqn1p1";
6395 let isTaken = Inst{13};
6396 let isExtendable = 1;
6397 let opExtendable = 2;
6398 let isExtentSigned = 1;
6399 let opExtentBits = 11;
6400 let opExtentAlign = 2;
6402 def J4_cmpeqn1_t_jumpnv_nt : HInst<
6404 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6405 "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6406 tc_bde7aaf4, TypeNCJ>, Enc_4aca3a, PredRel {
6407 let Inst{0-0} = 0b0;
6408 let Inst{13-8} = 0b000000;
6409 let Inst{19-19} = 0b0;
6410 let Inst{31-22} = 0b0010011000;
6411 let isPredicated = 1;
6412 let isTerminator = 1;
6416 let isRestrictNoSlot1Store = 1;
6418 let BaseOpcode = "J4_cmpeqn1r";
6419 let isTaken = Inst{13};
6420 let isExtendable = 1;
6421 let opExtendable = 2;
6422 let isExtentSigned = 1;
6423 let opExtentBits = 11;
6424 let opExtentAlign = 2;
6427 def J4_cmpeqn1_t_jumpnv_t : HInst<
6429 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6430 "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6431 tc_bde7aaf4, TypeNCJ>, Enc_f7ea77, PredRel {
6432 let Inst{0-0} = 0b0;
6433 let Inst{13-8} = 0b100000;
6434 let Inst{19-19} = 0b0;
6435 let Inst{31-22} = 0b0010011000;
6436 let isPredicated = 1;
6437 let isTerminator = 1;
6441 let isRestrictNoSlot1Store = 1;
6443 let BaseOpcode = "J4_cmpeqn1r";
6444 let isTaken = Inst{13};
6445 let isExtendable = 1;
6446 let opExtendable = 2;
6447 let isExtentSigned = 1;
6448 let opExtentBits = 11;
6449 let opExtentAlign = 2;
6452 def J4_cmpeqn1_tp0_jump_nt : HInst<
6454 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6455 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6456 tc_99be14ca, TypeCJ>, Enc_405228, PredRel {
6457 let Inst{0-0} = 0b0;
6458 let Inst{13-8} = 0b000000;
6459 let Inst{31-22} = 0b0001000110;
6460 let isPredicated = 1;
6461 let isTerminator = 1;
6463 let isPredicatedNew = 1;
6468 let Defs = [P0, PC];
6469 let BaseOpcode = "J4_cmpeqn1p0";
6470 let isTaken = Inst{13};
6471 let isExtendable = 1;
6472 let opExtendable = 2;
6473 let isExtentSigned = 1;
6474 let opExtentBits = 11;
6475 let opExtentAlign = 2;
6477 def J4_cmpeqn1_tp0_jump_t : HInst<
6479 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6480 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6481 tc_99be14ca, TypeCJ>, Enc_3a2484, PredRel {
6482 let Inst{0-0} = 0b0;
6483 let Inst{13-8} = 0b100000;
6484 let Inst{31-22} = 0b0001000110;
6485 let isPredicated = 1;
6486 let isTerminator = 1;
6488 let isPredicatedNew = 1;
6493 let Defs = [P0, PC];
6494 let BaseOpcode = "J4_cmpeqn1p0";
6495 let isTaken = Inst{13};
6496 let isExtendable = 1;
6497 let opExtendable = 2;
6498 let isExtentSigned = 1;
6499 let opExtentBits = 11;
6500 let opExtentAlign = 2;
6502 def J4_cmpeqn1_tp1_jump_nt : HInst<
6504 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6505 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6506 tc_99be14ca, TypeCJ>, Enc_736575, PredRel {
6507 let Inst{0-0} = 0b0;
6508 let Inst{13-8} = 0b000000;
6509 let Inst{31-22} = 0b0001001110;
6510 let isPredicated = 1;
6511 let isTerminator = 1;
6513 let isPredicatedNew = 1;
6518 let Defs = [P1, PC];
6519 let BaseOpcode = "J4_cmpeqn1p1";
6520 let isTaken = Inst{13};
6521 let isExtendable = 1;
6522 let opExtendable = 2;
6523 let isExtentSigned = 1;
6524 let opExtentBits = 11;
6525 let opExtentAlign = 2;
6527 def J4_cmpeqn1_tp1_jump_t : HInst<
6529 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6530 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6531 tc_99be14ca, TypeCJ>, Enc_8e583a, PredRel {
6532 let Inst{0-0} = 0b0;
6533 let Inst{13-8} = 0b100000;
6534 let Inst{31-22} = 0b0001001110;
6535 let isPredicated = 1;
6536 let isTerminator = 1;
6538 let isPredicatedNew = 1;
6543 let Defs = [P1, PC];
6544 let BaseOpcode = "J4_cmpeqn1p1";
6545 let isTaken = Inst{13};
6546 let isExtendable = 1;
6547 let opExtendable = 2;
6548 let isExtentSigned = 1;
6549 let opExtentBits = 11;
6550 let opExtentAlign = 2;
6552 def J4_cmpgt_f_jumpnv_nt : HInst<
6554 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6555 "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6556 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
6557 let Inst{0-0} = 0b0;
6558 let Inst{13-13} = 0b0;
6559 let Inst{19-19} = 0b0;
6560 let Inst{31-22} = 0b0010000011;
6561 let isPredicated = 1;
6562 let isPredicatedFalse = 1;
6563 let isTerminator = 1;
6567 let isRestrictNoSlot1Store = 1;
6569 let BaseOpcode = "J4_cmpgtr";
6570 let isTaken = Inst{13};
6571 let isExtendable = 1;
6572 let opExtendable = 2;
6573 let isExtentSigned = 1;
6574 let opExtentBits = 11;
6575 let opExtentAlign = 2;
6578 def J4_cmpgt_f_jumpnv_t : HInst<
6580 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6581 "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6582 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
6583 let Inst{0-0} = 0b0;
6584 let Inst{13-13} = 0b1;
6585 let Inst{19-19} = 0b0;
6586 let Inst{31-22} = 0b0010000011;
6587 let isPredicated = 1;
6588 let isPredicatedFalse = 1;
6589 let isTerminator = 1;
6593 let isRestrictNoSlot1Store = 1;
6595 let BaseOpcode = "J4_cmpgtr";
6596 let isTaken = Inst{13};
6597 let isExtendable = 1;
6598 let opExtendable = 2;
6599 let isExtentSigned = 1;
6600 let opExtentBits = 11;
6601 let opExtentAlign = 2;
6604 def J4_cmpgt_fp0_jump_nt : HInst<
6606 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6607 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6608 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6609 let Inst{0-0} = 0b0;
6610 let Inst{13-12} = 0b00;
6611 let Inst{31-22} = 0b0001010011;
6612 let isPredicated = 1;
6613 let isPredicatedFalse = 1;
6614 let isTerminator = 1;
6616 let isPredicatedNew = 1;
6621 let Defs = [P0, PC];
6622 let BaseOpcode = "J4_cmpgtp0";
6623 let isTaken = Inst{13};
6624 let isExtendable = 1;
6625 let opExtendable = 2;
6626 let isExtentSigned = 1;
6627 let opExtentBits = 11;
6628 let opExtentAlign = 2;
6630 def J4_cmpgt_fp0_jump_t : HInst<
6632 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6633 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6634 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6635 let Inst{0-0} = 0b0;
6636 let Inst{13-12} = 0b10;
6637 let Inst{31-22} = 0b0001010011;
6638 let isPredicated = 1;
6639 let isPredicatedFalse = 1;
6640 let isTerminator = 1;
6642 let isPredicatedNew = 1;
6647 let Defs = [P0, PC];
6648 let BaseOpcode = "J4_cmpgtp0";
6649 let isTaken = Inst{13};
6650 let isExtendable = 1;
6651 let opExtendable = 2;
6652 let isExtentSigned = 1;
6653 let opExtentBits = 11;
6654 let opExtentAlign = 2;
6656 def J4_cmpgt_fp1_jump_nt : HInst<
6658 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6659 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6660 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6661 let Inst{0-0} = 0b0;
6662 let Inst{13-12} = 0b01;
6663 let Inst{31-22} = 0b0001010011;
6664 let isPredicated = 1;
6665 let isPredicatedFalse = 1;
6666 let isTerminator = 1;
6668 let isPredicatedNew = 1;
6673 let Defs = [P1, PC];
6674 let BaseOpcode = "J4_cmpgtp1";
6675 let isTaken = Inst{13};
6676 let isExtendable = 1;
6677 let opExtendable = 2;
6678 let isExtentSigned = 1;
6679 let opExtentBits = 11;
6680 let opExtentAlign = 2;
6682 def J4_cmpgt_fp1_jump_t : HInst<
6684 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6685 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6686 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6687 let Inst{0-0} = 0b0;
6688 let Inst{13-12} = 0b11;
6689 let Inst{31-22} = 0b0001010011;
6690 let isPredicated = 1;
6691 let isPredicatedFalse = 1;
6692 let isTerminator = 1;
6694 let isPredicatedNew = 1;
6699 let Defs = [P1, PC];
6700 let BaseOpcode = "J4_cmpgtp1";
6701 let isTaken = Inst{13};
6702 let isExtendable = 1;
6703 let opExtendable = 2;
6704 let isExtentSigned = 1;
6705 let opExtentBits = 11;
6706 let opExtentAlign = 2;
6708 def J4_cmpgt_t_jumpnv_nt : HInst<
6710 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6711 "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6712 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
6713 let Inst{0-0} = 0b0;
6714 let Inst{13-13} = 0b0;
6715 let Inst{19-19} = 0b0;
6716 let Inst{31-22} = 0b0010000010;
6717 let isPredicated = 1;
6718 let isTerminator = 1;
6722 let isRestrictNoSlot1Store = 1;
6724 let BaseOpcode = "J4_cmpgtr";
6725 let isTaken = Inst{13};
6726 let isExtendable = 1;
6727 let opExtendable = 2;
6728 let isExtentSigned = 1;
6729 let opExtentBits = 11;
6730 let opExtentAlign = 2;
6733 def J4_cmpgt_t_jumpnv_t : HInst<
6735 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6736 "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6737 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
6738 let Inst{0-0} = 0b0;
6739 let Inst{13-13} = 0b1;
6740 let Inst{19-19} = 0b0;
6741 let Inst{31-22} = 0b0010000010;
6742 let isPredicated = 1;
6743 let isTerminator = 1;
6747 let isRestrictNoSlot1Store = 1;
6749 let BaseOpcode = "J4_cmpgtr";
6750 let isTaken = Inst{13};
6751 let isExtendable = 1;
6752 let opExtendable = 2;
6753 let isExtentSigned = 1;
6754 let opExtentBits = 11;
6755 let opExtentAlign = 2;
6758 def J4_cmpgt_tp0_jump_nt : HInst<
6760 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6761 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6762 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6763 let Inst{0-0} = 0b0;
6764 let Inst{13-12} = 0b00;
6765 let Inst{31-22} = 0b0001010010;
6766 let isPredicated = 1;
6767 let isTerminator = 1;
6769 let isPredicatedNew = 1;
6774 let Defs = [P0, PC];
6775 let BaseOpcode = "J4_cmpgtp0";
6776 let isTaken = Inst{13};
6777 let isExtendable = 1;
6778 let opExtendable = 2;
6779 let isExtentSigned = 1;
6780 let opExtentBits = 11;
6781 let opExtentAlign = 2;
6783 def J4_cmpgt_tp0_jump_t : HInst<
6785 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6786 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6787 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6788 let Inst{0-0} = 0b0;
6789 let Inst{13-12} = 0b10;
6790 let Inst{31-22} = 0b0001010010;
6791 let isPredicated = 1;
6792 let isTerminator = 1;
6794 let isPredicatedNew = 1;
6799 let Defs = [P0, PC];
6800 let BaseOpcode = "J4_cmpgtp0";
6801 let isTaken = Inst{13};
6802 let isExtendable = 1;
6803 let opExtendable = 2;
6804 let isExtentSigned = 1;
6805 let opExtentBits = 11;
6806 let opExtentAlign = 2;
6808 def J4_cmpgt_tp1_jump_nt : HInst<
6810 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6811 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6812 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6813 let Inst{0-0} = 0b0;
6814 let Inst{13-12} = 0b01;
6815 let Inst{31-22} = 0b0001010010;
6816 let isPredicated = 1;
6817 let isTerminator = 1;
6819 let isPredicatedNew = 1;
6824 let Defs = [P1, PC];
6825 let BaseOpcode = "J4_cmpgtp1";
6826 let isTaken = Inst{13};
6827 let isExtendable = 1;
6828 let opExtendable = 2;
6829 let isExtentSigned = 1;
6830 let opExtentBits = 11;
6831 let opExtentAlign = 2;
6833 def J4_cmpgt_tp1_jump_t : HInst<
6835 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6836 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6837 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
6838 let Inst{0-0} = 0b0;
6839 let Inst{13-12} = 0b11;
6840 let Inst{31-22} = 0b0001010010;
6841 let isPredicated = 1;
6842 let isTerminator = 1;
6844 let isPredicatedNew = 1;
6849 let Defs = [P1, PC];
6850 let BaseOpcode = "J4_cmpgtp1";
6851 let isTaken = Inst{13};
6852 let isExtendable = 1;
6853 let opExtendable = 2;
6854 let isExtentSigned = 1;
6855 let opExtentBits = 11;
6856 let opExtentAlign = 2;
6858 def J4_cmpgti_f_jumpnv_nt : HInst<
6860 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6861 "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
6862 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
6863 let Inst{0-0} = 0b0;
6864 let Inst{13-13} = 0b0;
6865 let Inst{19-19} = 0b0;
6866 let Inst{31-22} = 0b0010010011;
6867 let isPredicated = 1;
6868 let isPredicatedFalse = 1;
6869 let isTerminator = 1;
6873 let isRestrictNoSlot1Store = 1;
6875 let BaseOpcode = "J4_cmpgtir";
6876 let isTaken = Inst{13};
6877 let isExtendable = 1;
6878 let opExtendable = 2;
6879 let isExtentSigned = 1;
6880 let opExtentBits = 11;
6881 let opExtentAlign = 2;
6884 def J4_cmpgti_f_jumpnv_t : HInst<
6886 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6887 "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
6888 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
6889 let Inst{0-0} = 0b0;
6890 let Inst{13-13} = 0b1;
6891 let Inst{19-19} = 0b0;
6892 let Inst{31-22} = 0b0010010011;
6893 let isPredicated = 1;
6894 let isPredicatedFalse = 1;
6895 let isTerminator = 1;
6899 let isRestrictNoSlot1Store = 1;
6901 let BaseOpcode = "J4_cmpgtir";
6902 let isTaken = Inst{13};
6903 let isExtendable = 1;
6904 let opExtendable = 2;
6905 let isExtentSigned = 1;
6906 let opExtentBits = 11;
6907 let opExtentAlign = 2;
6910 def J4_cmpgti_fp0_jump_nt : HInst<
6912 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6913 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6914 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6915 let Inst{0-0} = 0b0;
6916 let Inst{13-13} = 0b0;
6917 let Inst{31-22} = 0b0001000011;
6918 let isPredicated = 1;
6919 let isPredicatedFalse = 1;
6920 let isTerminator = 1;
6922 let isPredicatedNew = 1;
6927 let Defs = [P0, PC];
6928 let BaseOpcode = "J4_cmpgtip0";
6929 let isTaken = Inst{13};
6930 let isExtendable = 1;
6931 let opExtendable = 2;
6932 let isExtentSigned = 1;
6933 let opExtentBits = 11;
6934 let opExtentAlign = 2;
6936 def J4_cmpgti_fp0_jump_t : HInst<
6938 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6939 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
6940 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6941 let Inst{0-0} = 0b0;
6942 let Inst{13-13} = 0b1;
6943 let Inst{31-22} = 0b0001000011;
6944 let isPredicated = 1;
6945 let isPredicatedFalse = 1;
6946 let isTerminator = 1;
6948 let isPredicatedNew = 1;
6953 let Defs = [P0, PC];
6954 let BaseOpcode = "J4_cmpgtip0";
6955 let isTaken = Inst{13};
6956 let isExtendable = 1;
6957 let opExtendable = 2;
6958 let isExtentSigned = 1;
6959 let opExtentBits = 11;
6960 let opExtentAlign = 2;
6962 def J4_cmpgti_fp1_jump_nt : HInst<
6964 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6965 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6966 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6967 let Inst{0-0} = 0b0;
6968 let Inst{13-13} = 0b0;
6969 let Inst{31-22} = 0b0001001011;
6970 let isPredicated = 1;
6971 let isPredicatedFalse = 1;
6972 let isTerminator = 1;
6974 let isPredicatedNew = 1;
6979 let Defs = [P1, PC];
6980 let BaseOpcode = "J4_cmpgtip1";
6981 let isTaken = Inst{13};
6982 let isExtendable = 1;
6983 let opExtendable = 2;
6984 let isExtentSigned = 1;
6985 let opExtentBits = 11;
6986 let opExtentAlign = 2;
6988 def J4_cmpgti_fp1_jump_t : HInst<
6990 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6991 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
6992 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
6993 let Inst{0-0} = 0b0;
6994 let Inst{13-13} = 0b1;
6995 let Inst{31-22} = 0b0001001011;
6996 let isPredicated = 1;
6997 let isPredicatedFalse = 1;
6998 let isTerminator = 1;
7000 let isPredicatedNew = 1;
7005 let Defs = [P1, PC];
7006 let BaseOpcode = "J4_cmpgtip1";
7007 let isTaken = Inst{13};
7008 let isExtendable = 1;
7009 let opExtendable = 2;
7010 let isExtentSigned = 1;
7011 let opExtentBits = 11;
7012 let opExtentAlign = 2;
7014 def J4_cmpgti_t_jumpnv_nt : HInst<
7016 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7017 "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7018 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7019 let Inst{0-0} = 0b0;
7020 let Inst{13-13} = 0b0;
7021 let Inst{19-19} = 0b0;
7022 let Inst{31-22} = 0b0010010010;
7023 let isPredicated = 1;
7024 let isTerminator = 1;
7028 let isRestrictNoSlot1Store = 1;
7030 let BaseOpcode = "J4_cmpgtir";
7031 let isTaken = Inst{13};
7032 let isExtendable = 1;
7033 let opExtendable = 2;
7034 let isExtentSigned = 1;
7035 let opExtentBits = 11;
7036 let opExtentAlign = 2;
7039 def J4_cmpgti_t_jumpnv_t : HInst<
7041 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7042 "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7043 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7044 let Inst{0-0} = 0b0;
7045 let Inst{13-13} = 0b1;
7046 let Inst{19-19} = 0b0;
7047 let Inst{31-22} = 0b0010010010;
7048 let isPredicated = 1;
7049 let isTerminator = 1;
7053 let isRestrictNoSlot1Store = 1;
7055 let BaseOpcode = "J4_cmpgtir";
7056 let isTaken = Inst{13};
7057 let isExtendable = 1;
7058 let opExtendable = 2;
7059 let isExtentSigned = 1;
7060 let opExtentBits = 11;
7061 let opExtentAlign = 2;
7064 def J4_cmpgti_tp0_jump_nt : HInst<
7066 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7067 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7068 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7069 let Inst{0-0} = 0b0;
7070 let Inst{13-13} = 0b0;
7071 let Inst{31-22} = 0b0001000010;
7072 let isPredicated = 1;
7073 let isTerminator = 1;
7075 let isPredicatedNew = 1;
7080 let Defs = [P0, PC];
7081 let BaseOpcode = "J4_cmpgtip0";
7082 let isTaken = Inst{13};
7083 let isExtendable = 1;
7084 let opExtendable = 2;
7085 let isExtentSigned = 1;
7086 let opExtentBits = 11;
7087 let opExtentAlign = 2;
7089 def J4_cmpgti_tp0_jump_t : HInst<
7091 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7092 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7093 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7094 let Inst{0-0} = 0b0;
7095 let Inst{13-13} = 0b1;
7096 let Inst{31-22} = 0b0001000010;
7097 let isPredicated = 1;
7098 let isTerminator = 1;
7100 let isPredicatedNew = 1;
7105 let Defs = [P0, PC];
7106 let BaseOpcode = "J4_cmpgtip0";
7107 let isTaken = Inst{13};
7108 let isExtendable = 1;
7109 let opExtendable = 2;
7110 let isExtentSigned = 1;
7111 let opExtentBits = 11;
7112 let opExtentAlign = 2;
7114 def J4_cmpgti_tp1_jump_nt : HInst<
7116 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7117 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7118 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7119 let Inst{0-0} = 0b0;
7120 let Inst{13-13} = 0b0;
7121 let Inst{31-22} = 0b0001001010;
7122 let isPredicated = 1;
7123 let isTerminator = 1;
7125 let isPredicatedNew = 1;
7130 let Defs = [P1, PC];
7131 let BaseOpcode = "J4_cmpgtip1";
7132 let isTaken = Inst{13};
7133 let isExtendable = 1;
7134 let opExtendable = 2;
7135 let isExtentSigned = 1;
7136 let opExtentBits = 11;
7137 let opExtentAlign = 2;
7139 def J4_cmpgti_tp1_jump_t : HInst<
7141 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7142 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7143 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7144 let Inst{0-0} = 0b0;
7145 let Inst{13-13} = 0b1;
7146 let Inst{31-22} = 0b0001001010;
7147 let isPredicated = 1;
7148 let isTerminator = 1;
7150 let isPredicatedNew = 1;
7155 let Defs = [P1, PC];
7156 let BaseOpcode = "J4_cmpgtip1";
7157 let isTaken = Inst{13};
7158 let isExtendable = 1;
7159 let opExtendable = 2;
7160 let isExtentSigned = 1;
7161 let opExtentBits = 11;
7162 let opExtentAlign = 2;
7164 def J4_cmpgtn1_f_jumpnv_nt : HInst<
7166 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7167 "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7168 tc_bde7aaf4, TypeNCJ>, Enc_3694bd, PredRel {
7169 let Inst{0-0} = 0b0;
7170 let Inst{13-8} = 0b000000;
7171 let Inst{19-19} = 0b0;
7172 let Inst{31-22} = 0b0010011011;
7173 let isPredicated = 1;
7174 let isPredicatedFalse = 1;
7175 let isTerminator = 1;
7179 let isRestrictNoSlot1Store = 1;
7181 let BaseOpcode = "J4_cmpgtn1r";
7182 let isTaken = Inst{13};
7183 let isExtendable = 1;
7184 let opExtendable = 2;
7185 let isExtentSigned = 1;
7186 let opExtentBits = 11;
7187 let opExtentAlign = 2;
7190 def J4_cmpgtn1_f_jumpnv_t : HInst<
7192 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7193 "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7194 tc_bde7aaf4, TypeNCJ>, Enc_a6853f, PredRel {
7195 let Inst{0-0} = 0b0;
7196 let Inst{13-8} = 0b100000;
7197 let Inst{19-19} = 0b0;
7198 let Inst{31-22} = 0b0010011011;
7199 let isPredicated = 1;
7200 let isPredicatedFalse = 1;
7201 let isTerminator = 1;
7205 let isRestrictNoSlot1Store = 1;
7207 let BaseOpcode = "J4_cmpgtn1r";
7208 let isTaken = Inst{13};
7209 let isExtendable = 1;
7210 let opExtendable = 2;
7211 let isExtentSigned = 1;
7212 let opExtentBits = 11;
7213 let opExtentAlign = 2;
7216 def J4_cmpgtn1_fp0_jump_nt : HInst<
7218 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7219 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7220 tc_99be14ca, TypeCJ>, Enc_a42857, PredRel {
7221 let Inst{0-0} = 0b0;
7222 let Inst{13-8} = 0b000001;
7223 let Inst{31-22} = 0b0001000111;
7224 let isPredicated = 1;
7225 let isPredicatedFalse = 1;
7226 let isTerminator = 1;
7228 let isPredicatedNew = 1;
7233 let Defs = [P0, PC];
7234 let BaseOpcode = "J4_cmpgtn1p0";
7235 let isTaken = Inst{13};
7236 let isExtendable = 1;
7237 let opExtendable = 2;
7238 let isExtentSigned = 1;
7239 let opExtentBits = 11;
7240 let opExtentAlign = 2;
7242 def J4_cmpgtn1_fp0_jump_t : HInst<
7244 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7245 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7246 tc_99be14ca, TypeCJ>, Enc_f6fe0b, PredRel {
7247 let Inst{0-0} = 0b0;
7248 let Inst{13-8} = 0b100001;
7249 let Inst{31-22} = 0b0001000111;
7250 let isPredicated = 1;
7251 let isPredicatedFalse = 1;
7252 let isTerminator = 1;
7254 let isPredicatedNew = 1;
7259 let Defs = [P0, PC];
7260 let BaseOpcode = "J4_cmpgtn1p0";
7261 let isTaken = Inst{13};
7262 let isExtendable = 1;
7263 let opExtendable = 2;
7264 let isExtentSigned = 1;
7265 let opExtentBits = 11;
7266 let opExtentAlign = 2;
7268 def J4_cmpgtn1_fp1_jump_nt : HInst<
7270 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7271 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7272 tc_99be14ca, TypeCJ>, Enc_3e3989, PredRel {
7273 let Inst{0-0} = 0b0;
7274 let Inst{13-8} = 0b000001;
7275 let Inst{31-22} = 0b0001001111;
7276 let isPredicated = 1;
7277 let isPredicatedFalse = 1;
7278 let isTerminator = 1;
7280 let isPredicatedNew = 1;
7285 let Defs = [P1, PC];
7286 let BaseOpcode = "J4_cmpgtn1p1";
7287 let isTaken = Inst{13};
7288 let isExtendable = 1;
7289 let opExtendable = 2;
7290 let isExtentSigned = 1;
7291 let opExtentBits = 11;
7292 let opExtentAlign = 2;
7294 def J4_cmpgtn1_fp1_jump_t : HInst<
7296 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7297 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7298 tc_99be14ca, TypeCJ>, Enc_b909d2, PredRel {
7299 let Inst{0-0} = 0b0;
7300 let Inst{13-8} = 0b100001;
7301 let Inst{31-22} = 0b0001001111;
7302 let isPredicated = 1;
7303 let isPredicatedFalse = 1;
7304 let isTerminator = 1;
7306 let isPredicatedNew = 1;
7311 let Defs = [P1, PC];
7312 let BaseOpcode = "J4_cmpgtn1p1";
7313 let isTaken = Inst{13};
7314 let isExtendable = 1;
7315 let opExtendable = 2;
7316 let isExtentSigned = 1;
7317 let opExtentBits = 11;
7318 let opExtentAlign = 2;
7320 def J4_cmpgtn1_t_jumpnv_nt : HInst<
7322 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7323 "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7324 tc_bde7aaf4, TypeNCJ>, Enc_f82302, PredRel {
7325 let Inst{0-0} = 0b0;
7326 let Inst{13-8} = 0b000000;
7327 let Inst{19-19} = 0b0;
7328 let Inst{31-22} = 0b0010011010;
7329 let isPredicated = 1;
7330 let isTerminator = 1;
7334 let isRestrictNoSlot1Store = 1;
7336 let BaseOpcode = "J4_cmpgtn1r";
7337 let isTaken = Inst{13};
7338 let isExtendable = 1;
7339 let opExtendable = 2;
7340 let isExtentSigned = 1;
7341 let opExtentBits = 11;
7342 let opExtentAlign = 2;
7345 def J4_cmpgtn1_t_jumpnv_t : HInst<
7347 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7348 "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7349 tc_bde7aaf4, TypeNCJ>, Enc_6413b6, PredRel {
7350 let Inst{0-0} = 0b0;
7351 let Inst{13-8} = 0b100000;
7352 let Inst{19-19} = 0b0;
7353 let Inst{31-22} = 0b0010011010;
7354 let isPredicated = 1;
7355 let isTerminator = 1;
7359 let isRestrictNoSlot1Store = 1;
7361 let BaseOpcode = "J4_cmpgtn1r";
7362 let isTaken = Inst{13};
7363 let isExtendable = 1;
7364 let opExtendable = 2;
7365 let isExtentSigned = 1;
7366 let opExtentBits = 11;
7367 let opExtentAlign = 2;
7370 def J4_cmpgtn1_tp0_jump_nt : HInst<
7372 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7373 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7374 tc_99be14ca, TypeCJ>, Enc_b78edd, PredRel {
7375 let Inst{0-0} = 0b0;
7376 let Inst{13-8} = 0b000001;
7377 let Inst{31-22} = 0b0001000110;
7378 let isPredicated = 1;
7379 let isTerminator = 1;
7381 let isPredicatedNew = 1;
7386 let Defs = [P0, PC];
7387 let BaseOpcode = "J4_cmpgtn1p0";
7388 let isTaken = Inst{13};
7389 let isExtendable = 1;
7390 let opExtendable = 2;
7391 let isExtentSigned = 1;
7392 let opExtentBits = 11;
7393 let opExtentAlign = 2;
7395 def J4_cmpgtn1_tp0_jump_t : HInst<
7397 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7398 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7399 tc_99be14ca, TypeCJ>, Enc_041d7b, PredRel {
7400 let Inst{0-0} = 0b0;
7401 let Inst{13-8} = 0b100001;
7402 let Inst{31-22} = 0b0001000110;
7403 let isPredicated = 1;
7404 let isTerminator = 1;
7406 let isPredicatedNew = 1;
7411 let Defs = [P0, PC];
7412 let BaseOpcode = "J4_cmpgtn1p0";
7413 let isTaken = Inst{13};
7414 let isExtendable = 1;
7415 let opExtendable = 2;
7416 let isExtentSigned = 1;
7417 let opExtentBits = 11;
7418 let opExtentAlign = 2;
7420 def J4_cmpgtn1_tp1_jump_nt : HInst<
7422 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7423 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7424 tc_99be14ca, TypeCJ>, Enc_b1e1fb, PredRel {
7425 let Inst{0-0} = 0b0;
7426 let Inst{13-8} = 0b000001;
7427 let Inst{31-22} = 0b0001001110;
7428 let isPredicated = 1;
7429 let isTerminator = 1;
7431 let isPredicatedNew = 1;
7436 let Defs = [P1, PC];
7437 let BaseOpcode = "J4_cmpgtn1p1";
7438 let isTaken = Inst{13};
7439 let isExtendable = 1;
7440 let opExtendable = 2;
7441 let isExtentSigned = 1;
7442 let opExtentBits = 11;
7443 let opExtentAlign = 2;
7445 def J4_cmpgtn1_tp1_jump_t : HInst<
7447 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7448 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7449 tc_99be14ca, TypeCJ>, Enc_178717, PredRel {
7450 let Inst{0-0} = 0b0;
7451 let Inst{13-8} = 0b100001;
7452 let Inst{31-22} = 0b0001001110;
7453 let isPredicated = 1;
7454 let isTerminator = 1;
7456 let isPredicatedNew = 1;
7461 let Defs = [P1, PC];
7462 let BaseOpcode = "J4_cmpgtn1p1";
7463 let isTaken = Inst{13};
7464 let isExtendable = 1;
7465 let opExtendable = 2;
7466 let isExtentSigned = 1;
7467 let opExtentBits = 11;
7468 let opExtentAlign = 2;
7470 def J4_cmpgtu_f_jumpnv_nt : HInst<
7472 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7473 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7474 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
7475 let Inst{0-0} = 0b0;
7476 let Inst{13-13} = 0b0;
7477 let Inst{19-19} = 0b0;
7478 let Inst{31-22} = 0b0010000101;
7479 let isPredicated = 1;
7480 let isPredicatedFalse = 1;
7481 let isTerminator = 1;
7485 let isRestrictNoSlot1Store = 1;
7487 let BaseOpcode = "J4_cmpgtur";
7488 let isTaken = Inst{13};
7489 let isExtendable = 1;
7490 let opExtendable = 2;
7491 let isExtentSigned = 1;
7492 let opExtentBits = 11;
7493 let opExtentAlign = 2;
7496 def J4_cmpgtu_f_jumpnv_t : HInst<
7498 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7499 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7500 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
7501 let Inst{0-0} = 0b0;
7502 let Inst{13-13} = 0b1;
7503 let Inst{19-19} = 0b0;
7504 let Inst{31-22} = 0b0010000101;
7505 let isPredicated = 1;
7506 let isPredicatedFalse = 1;
7507 let isTerminator = 1;
7511 let isRestrictNoSlot1Store = 1;
7513 let BaseOpcode = "J4_cmpgtur";
7514 let isTaken = Inst{13};
7515 let isExtendable = 1;
7516 let opExtendable = 2;
7517 let isExtentSigned = 1;
7518 let opExtentBits = 11;
7519 let opExtentAlign = 2;
7522 def J4_cmpgtu_fp0_jump_nt : HInst<
7524 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7525 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7526 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7527 let Inst{0-0} = 0b0;
7528 let Inst{13-12} = 0b00;
7529 let Inst{31-22} = 0b0001010101;
7530 let isPredicated = 1;
7531 let isPredicatedFalse = 1;
7532 let isTerminator = 1;
7534 let isPredicatedNew = 1;
7539 let Defs = [P0, PC];
7540 let BaseOpcode = "J4_cmpgtup0";
7541 let isTaken = Inst{13};
7542 let isExtendable = 1;
7543 let opExtendable = 2;
7544 let isExtentSigned = 1;
7545 let opExtentBits = 11;
7546 let opExtentAlign = 2;
7548 def J4_cmpgtu_fp0_jump_t : HInst<
7550 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7551 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7552 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7553 let Inst{0-0} = 0b0;
7554 let Inst{13-12} = 0b10;
7555 let Inst{31-22} = 0b0001010101;
7556 let isPredicated = 1;
7557 let isPredicatedFalse = 1;
7558 let isTerminator = 1;
7560 let isPredicatedNew = 1;
7565 let Defs = [P0, PC];
7566 let BaseOpcode = "J4_cmpgtup0";
7567 let isTaken = Inst{13};
7568 let isExtendable = 1;
7569 let opExtendable = 2;
7570 let isExtentSigned = 1;
7571 let opExtentBits = 11;
7572 let opExtentAlign = 2;
7574 def J4_cmpgtu_fp1_jump_nt : HInst<
7576 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7577 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7578 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7579 let Inst{0-0} = 0b0;
7580 let Inst{13-12} = 0b01;
7581 let Inst{31-22} = 0b0001010101;
7582 let isPredicated = 1;
7583 let isPredicatedFalse = 1;
7584 let isTerminator = 1;
7586 let isPredicatedNew = 1;
7591 let Defs = [P1, PC];
7592 let BaseOpcode = "J4_cmpgtup1";
7593 let isTaken = Inst{13};
7594 let isExtendable = 1;
7595 let opExtendable = 2;
7596 let isExtentSigned = 1;
7597 let opExtentBits = 11;
7598 let opExtentAlign = 2;
7600 def J4_cmpgtu_fp1_jump_t : HInst<
7602 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7603 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7604 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7605 let Inst{0-0} = 0b0;
7606 let Inst{13-12} = 0b11;
7607 let Inst{31-22} = 0b0001010101;
7608 let isPredicated = 1;
7609 let isPredicatedFalse = 1;
7610 let isTerminator = 1;
7612 let isPredicatedNew = 1;
7617 let Defs = [P1, PC];
7618 let BaseOpcode = "J4_cmpgtup1";
7619 let isTaken = Inst{13};
7620 let isExtendable = 1;
7621 let opExtendable = 2;
7622 let isExtentSigned = 1;
7623 let opExtentBits = 11;
7624 let opExtentAlign = 2;
7626 def J4_cmpgtu_t_jumpnv_nt : HInst<
7628 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7629 "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7630 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
7631 let Inst{0-0} = 0b0;
7632 let Inst{13-13} = 0b0;
7633 let Inst{19-19} = 0b0;
7634 let Inst{31-22} = 0b0010000100;
7635 let isPredicated = 1;
7636 let isTerminator = 1;
7640 let isRestrictNoSlot1Store = 1;
7642 let BaseOpcode = "J4_cmpgtur";
7643 let isTaken = Inst{13};
7644 let isExtendable = 1;
7645 let opExtendable = 2;
7646 let isExtentSigned = 1;
7647 let opExtentBits = 11;
7648 let opExtentAlign = 2;
7651 def J4_cmpgtu_t_jumpnv_t : HInst<
7653 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7654 "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7655 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
7656 let Inst{0-0} = 0b0;
7657 let Inst{13-13} = 0b1;
7658 let Inst{19-19} = 0b0;
7659 let Inst{31-22} = 0b0010000100;
7660 let isPredicated = 1;
7661 let isTerminator = 1;
7665 let isRestrictNoSlot1Store = 1;
7667 let BaseOpcode = "J4_cmpgtur";
7668 let isTaken = Inst{13};
7669 let isExtendable = 1;
7670 let opExtendable = 2;
7671 let isExtentSigned = 1;
7672 let opExtentBits = 11;
7673 let opExtentAlign = 2;
7676 def J4_cmpgtu_tp0_jump_nt : HInst<
7678 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7679 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7680 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7681 let Inst{0-0} = 0b0;
7682 let Inst{13-12} = 0b00;
7683 let Inst{31-22} = 0b0001010100;
7684 let isPredicated = 1;
7685 let isTerminator = 1;
7687 let isPredicatedNew = 1;
7692 let Defs = [P0, PC];
7693 let BaseOpcode = "J4_cmpgtup0";
7694 let isTaken = Inst{13};
7695 let isExtendable = 1;
7696 let opExtendable = 2;
7697 let isExtentSigned = 1;
7698 let opExtentBits = 11;
7699 let opExtentAlign = 2;
7701 def J4_cmpgtu_tp0_jump_t : HInst<
7703 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7704 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7705 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7706 let Inst{0-0} = 0b0;
7707 let Inst{13-12} = 0b10;
7708 let Inst{31-22} = 0b0001010100;
7709 let isPredicated = 1;
7710 let isTerminator = 1;
7712 let isPredicatedNew = 1;
7717 let Defs = [P0, PC];
7718 let BaseOpcode = "J4_cmpgtup0";
7719 let isTaken = Inst{13};
7720 let isExtendable = 1;
7721 let opExtendable = 2;
7722 let isExtentSigned = 1;
7723 let opExtentBits = 11;
7724 let opExtentAlign = 2;
7726 def J4_cmpgtu_tp1_jump_nt : HInst<
7728 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7729 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7730 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7731 let Inst{0-0} = 0b0;
7732 let Inst{13-12} = 0b01;
7733 let Inst{31-22} = 0b0001010100;
7734 let isPredicated = 1;
7735 let isTerminator = 1;
7737 let isPredicatedNew = 1;
7742 let Defs = [P1, PC];
7743 let BaseOpcode = "J4_cmpgtup1";
7744 let isTaken = Inst{13};
7745 let isExtendable = 1;
7746 let opExtendable = 2;
7747 let isExtentSigned = 1;
7748 let opExtentBits = 11;
7749 let opExtentAlign = 2;
7751 def J4_cmpgtu_tp1_jump_t : HInst<
7753 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7754 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7755 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
7756 let Inst{0-0} = 0b0;
7757 let Inst{13-12} = 0b11;
7758 let Inst{31-22} = 0b0001010100;
7759 let isPredicated = 1;
7760 let isTerminator = 1;
7762 let isPredicatedNew = 1;
7767 let Defs = [P1, PC];
7768 let BaseOpcode = "J4_cmpgtup1";
7769 let isTaken = Inst{13};
7770 let isExtendable = 1;
7771 let opExtendable = 2;
7772 let isExtentSigned = 1;
7773 let opExtentBits = 11;
7774 let opExtentAlign = 2;
7776 def J4_cmpgtui_f_jumpnv_nt : HInst<
7778 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7779 "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7780 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7781 let Inst{0-0} = 0b0;
7782 let Inst{13-13} = 0b0;
7783 let Inst{19-19} = 0b0;
7784 let Inst{31-22} = 0b0010010101;
7785 let isPredicated = 1;
7786 let isPredicatedFalse = 1;
7787 let isTerminator = 1;
7791 let isRestrictNoSlot1Store = 1;
7793 let BaseOpcode = "J4_cmpgtuir";
7794 let isTaken = Inst{13};
7795 let isExtendable = 1;
7796 let opExtendable = 2;
7797 let isExtentSigned = 1;
7798 let opExtentBits = 11;
7799 let opExtentAlign = 2;
7802 def J4_cmpgtui_f_jumpnv_t : HInst<
7804 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7805 "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
7806 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7807 let Inst{0-0} = 0b0;
7808 let Inst{13-13} = 0b1;
7809 let Inst{19-19} = 0b0;
7810 let Inst{31-22} = 0b0010010101;
7811 let isPredicated = 1;
7812 let isPredicatedFalse = 1;
7813 let isTerminator = 1;
7817 let isRestrictNoSlot1Store = 1;
7819 let BaseOpcode = "J4_cmpgtuir";
7820 let isTaken = Inst{13};
7821 let isExtendable = 1;
7822 let opExtendable = 2;
7823 let isExtentSigned = 1;
7824 let opExtentBits = 11;
7825 let opExtentAlign = 2;
7828 def J4_cmpgtui_fp0_jump_nt : HInst<
7830 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7831 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7832 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7833 let Inst{0-0} = 0b0;
7834 let Inst{13-13} = 0b0;
7835 let Inst{31-22} = 0b0001000101;
7836 let isPredicated = 1;
7837 let isPredicatedFalse = 1;
7838 let isTerminator = 1;
7840 let isPredicatedNew = 1;
7845 let Defs = [P0, PC];
7846 let BaseOpcode = "J4_cmpgtuip0";
7847 let isTaken = Inst{13};
7848 let isExtendable = 1;
7849 let opExtendable = 2;
7850 let isExtentSigned = 1;
7851 let opExtentBits = 11;
7852 let opExtentAlign = 2;
7854 def J4_cmpgtui_fp0_jump_t : HInst<
7856 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7857 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
7858 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7859 let Inst{0-0} = 0b0;
7860 let Inst{13-13} = 0b1;
7861 let Inst{31-22} = 0b0001000101;
7862 let isPredicated = 1;
7863 let isPredicatedFalse = 1;
7864 let isTerminator = 1;
7866 let isPredicatedNew = 1;
7871 let Defs = [P0, PC];
7872 let BaseOpcode = "J4_cmpgtuip0";
7873 let isTaken = Inst{13};
7874 let isExtendable = 1;
7875 let opExtendable = 2;
7876 let isExtentSigned = 1;
7877 let opExtentBits = 11;
7878 let opExtentAlign = 2;
7880 def J4_cmpgtui_fp1_jump_nt : HInst<
7882 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7883 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7884 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7885 let Inst{0-0} = 0b0;
7886 let Inst{13-13} = 0b0;
7887 let Inst{31-22} = 0b0001001101;
7888 let isPredicated = 1;
7889 let isPredicatedFalse = 1;
7890 let isTerminator = 1;
7892 let isPredicatedNew = 1;
7897 let Defs = [P1, PC];
7898 let BaseOpcode = "J4_cmpgtuip1";
7899 let isTaken = Inst{13};
7900 let isExtendable = 1;
7901 let opExtendable = 2;
7902 let isExtentSigned = 1;
7903 let opExtentBits = 11;
7904 let opExtentAlign = 2;
7906 def J4_cmpgtui_fp1_jump_t : HInst<
7908 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7909 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
7910 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7911 let Inst{0-0} = 0b0;
7912 let Inst{13-13} = 0b1;
7913 let Inst{31-22} = 0b0001001101;
7914 let isPredicated = 1;
7915 let isPredicatedFalse = 1;
7916 let isTerminator = 1;
7918 let isPredicatedNew = 1;
7923 let Defs = [P1, PC];
7924 let BaseOpcode = "J4_cmpgtuip1";
7925 let isTaken = Inst{13};
7926 let isExtendable = 1;
7927 let opExtendable = 2;
7928 let isExtentSigned = 1;
7929 let opExtentBits = 11;
7930 let opExtentAlign = 2;
7932 def J4_cmpgtui_t_jumpnv_nt : HInst<
7934 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7935 "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7936 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7937 let Inst{0-0} = 0b0;
7938 let Inst{13-13} = 0b0;
7939 let Inst{19-19} = 0b0;
7940 let Inst{31-22} = 0b0010010100;
7941 let isPredicated = 1;
7942 let isTerminator = 1;
7946 let isRestrictNoSlot1Store = 1;
7948 let BaseOpcode = "J4_cmpgtuir";
7949 let isTaken = Inst{13};
7950 let isExtendable = 1;
7951 let opExtendable = 2;
7952 let isExtentSigned = 1;
7953 let opExtentBits = 11;
7954 let opExtentAlign = 2;
7957 def J4_cmpgtui_t_jumpnv_t : HInst<
7959 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7960 "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
7961 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
7962 let Inst{0-0} = 0b0;
7963 let Inst{13-13} = 0b1;
7964 let Inst{19-19} = 0b0;
7965 let Inst{31-22} = 0b0010010100;
7966 let isPredicated = 1;
7967 let isTerminator = 1;
7971 let isRestrictNoSlot1Store = 1;
7973 let BaseOpcode = "J4_cmpgtuir";
7974 let isTaken = Inst{13};
7975 let isExtendable = 1;
7976 let opExtendable = 2;
7977 let isExtentSigned = 1;
7978 let opExtentBits = 11;
7979 let opExtentAlign = 2;
7982 def J4_cmpgtui_tp0_jump_nt : HInst<
7984 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7985 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
7986 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
7987 let Inst{0-0} = 0b0;
7988 let Inst{13-13} = 0b0;
7989 let Inst{31-22} = 0b0001000100;
7990 let isPredicated = 1;
7991 let isTerminator = 1;
7993 let isPredicatedNew = 1;
7998 let Defs = [P0, PC];
7999 let BaseOpcode = "J4_cmpgtuip0";
8000 let isTaken = Inst{13};
8001 let isExtendable = 1;
8002 let opExtendable = 2;
8003 let isExtentSigned = 1;
8004 let opExtentBits = 11;
8005 let opExtentAlign = 2;
8007 def J4_cmpgtui_tp0_jump_t : HInst<
8009 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8010 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8011 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
8012 let Inst{0-0} = 0b0;
8013 let Inst{13-13} = 0b1;
8014 let Inst{31-22} = 0b0001000100;
8015 let isPredicated = 1;
8016 let isTerminator = 1;
8018 let isPredicatedNew = 1;
8023 let Defs = [P0, PC];
8024 let BaseOpcode = "J4_cmpgtuip0";
8025 let isTaken = Inst{13};
8026 let isExtendable = 1;
8027 let opExtendable = 2;
8028 let isExtentSigned = 1;
8029 let opExtentBits = 11;
8030 let opExtentAlign = 2;
8032 def J4_cmpgtui_tp1_jump_nt : HInst<
8034 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8035 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8036 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
8037 let Inst{0-0} = 0b0;
8038 let Inst{13-13} = 0b0;
8039 let Inst{31-22} = 0b0001001100;
8040 let isPredicated = 1;
8041 let isTerminator = 1;
8043 let isPredicatedNew = 1;
8048 let Defs = [P1, PC];
8049 let BaseOpcode = "J4_cmpgtuip1";
8050 let isTaken = Inst{13};
8051 let isExtendable = 1;
8052 let opExtendable = 2;
8053 let isExtentSigned = 1;
8054 let opExtentBits = 11;
8055 let opExtentAlign = 2;
8057 def J4_cmpgtui_tp1_jump_t : HInst<
8059 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8060 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8061 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
8062 let Inst{0-0} = 0b0;
8063 let Inst{13-13} = 0b1;
8064 let Inst{31-22} = 0b0001001100;
8065 let isPredicated = 1;
8066 let isTerminator = 1;
8068 let isPredicatedNew = 1;
8073 let Defs = [P1, PC];
8074 let BaseOpcode = "J4_cmpgtuip1";
8075 let isTaken = Inst{13};
8076 let isExtendable = 1;
8077 let opExtendable = 2;
8078 let isExtentSigned = 1;
8079 let opExtentBits = 11;
8080 let opExtentAlign = 2;
8082 def J4_cmplt_f_jumpnv_nt : HInst<
8084 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8085 "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8086 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8087 let Inst{0-0} = 0b0;
8088 let Inst{13-13} = 0b0;
8089 let Inst{19-19} = 0b0;
8090 let Inst{31-22} = 0b0010000111;
8091 let isPredicated = 1;
8092 let isPredicatedFalse = 1;
8093 let isTerminator = 1;
8097 let isRestrictNoSlot1Store = 1;
8099 let BaseOpcode = "J4_cmpltr";
8100 let isTaken = Inst{13};
8101 let isExtendable = 1;
8102 let opExtendable = 2;
8103 let isExtentSigned = 1;
8104 let opExtentBits = 11;
8105 let opExtentAlign = 2;
8108 def J4_cmplt_f_jumpnv_t : HInst<
8110 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8111 "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8112 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8113 let Inst{0-0} = 0b0;
8114 let Inst{13-13} = 0b1;
8115 let Inst{19-19} = 0b0;
8116 let Inst{31-22} = 0b0010000111;
8117 let isPredicated = 1;
8118 let isPredicatedFalse = 1;
8119 let isTerminator = 1;
8123 let isRestrictNoSlot1Store = 1;
8125 let BaseOpcode = "J4_cmpltr";
8126 let isTaken = Inst{13};
8127 let isExtendable = 1;
8128 let opExtendable = 2;
8129 let isExtentSigned = 1;
8130 let opExtentBits = 11;
8131 let opExtentAlign = 2;
8134 def J4_cmplt_t_jumpnv_nt : HInst<
8136 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8137 "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8138 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8139 let Inst{0-0} = 0b0;
8140 let Inst{13-13} = 0b0;
8141 let Inst{19-19} = 0b0;
8142 let Inst{31-22} = 0b0010000110;
8143 let isPredicated = 1;
8144 let isTerminator = 1;
8148 let isRestrictNoSlot1Store = 1;
8150 let BaseOpcode = "J4_cmpltr";
8151 let isTaken = Inst{13};
8152 let isExtendable = 1;
8153 let opExtendable = 2;
8154 let isExtentSigned = 1;
8155 let opExtentBits = 11;
8156 let opExtentAlign = 2;
8159 def J4_cmplt_t_jumpnv_t : HInst<
8161 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8162 "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8163 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8164 let Inst{0-0} = 0b0;
8165 let Inst{13-13} = 0b1;
8166 let Inst{19-19} = 0b0;
8167 let Inst{31-22} = 0b0010000110;
8168 let isPredicated = 1;
8169 let isTerminator = 1;
8173 let isRestrictNoSlot1Store = 1;
8175 let BaseOpcode = "J4_cmpltr";
8176 let isTaken = Inst{13};
8177 let isExtendable = 1;
8178 let opExtendable = 2;
8179 let isExtentSigned = 1;
8180 let opExtentBits = 11;
8181 let opExtentAlign = 2;
8184 def J4_cmpltu_f_jumpnv_nt : HInst<
8186 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8187 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8188 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8189 let Inst{0-0} = 0b0;
8190 let Inst{13-13} = 0b0;
8191 let Inst{19-19} = 0b0;
8192 let Inst{31-22} = 0b0010001001;
8193 let isPredicated = 1;
8194 let isPredicatedFalse = 1;
8195 let isTerminator = 1;
8199 let isRestrictNoSlot1Store = 1;
8201 let BaseOpcode = "J4_cmpltur";
8202 let isTaken = Inst{13};
8203 let isExtendable = 1;
8204 let opExtendable = 2;
8205 let isExtentSigned = 1;
8206 let opExtentBits = 11;
8207 let opExtentAlign = 2;
8210 def J4_cmpltu_f_jumpnv_t : HInst<
8212 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8213 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8214 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8215 let Inst{0-0} = 0b0;
8216 let Inst{13-13} = 0b1;
8217 let Inst{19-19} = 0b0;
8218 let Inst{31-22} = 0b0010001001;
8219 let isPredicated = 1;
8220 let isPredicatedFalse = 1;
8221 let isTerminator = 1;
8225 let isRestrictNoSlot1Store = 1;
8227 let BaseOpcode = "J4_cmpltur";
8228 let isTaken = Inst{13};
8229 let isExtendable = 1;
8230 let opExtendable = 2;
8231 let isExtentSigned = 1;
8232 let opExtentBits = 11;
8233 let opExtentAlign = 2;
8236 def J4_cmpltu_t_jumpnv_nt : HInst<
8238 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8239 "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8240 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8241 let Inst{0-0} = 0b0;
8242 let Inst{13-13} = 0b0;
8243 let Inst{19-19} = 0b0;
8244 let Inst{31-22} = 0b0010001000;
8245 let isPredicated = 1;
8246 let isTerminator = 1;
8250 let isRestrictNoSlot1Store = 1;
8252 let BaseOpcode = "J4_cmpltur";
8253 let isTaken = Inst{13};
8254 let isExtendable = 1;
8255 let opExtendable = 2;
8256 let isExtentSigned = 1;
8257 let opExtentBits = 11;
8258 let opExtentAlign = 2;
8261 def J4_cmpltu_t_jumpnv_t : HInst<
8263 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8264 "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8265 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
8266 let Inst{0-0} = 0b0;
8267 let Inst{13-13} = 0b1;
8268 let Inst{19-19} = 0b0;
8269 let Inst{31-22} = 0b0010001000;
8270 let isPredicated = 1;
8271 let isTerminator = 1;
8275 let isRestrictNoSlot1Store = 1;
8277 let BaseOpcode = "J4_cmpltur";
8278 let isTaken = Inst{13};
8279 let isExtendable = 1;
8280 let opExtendable = 2;
8281 let isExtentSigned = 1;
8282 let opExtentBits = 11;
8283 let opExtentAlign = 2;
8286 def J4_hintjumpr : HInst<
8288 (ins IntRegs:$Rs32),
8290 tc_9faf76ae, TypeJ>, Enc_ecbcc8 {
8291 let Inst{13-0} = 0b00000000000000;
8292 let Inst{31-21} = 0b01010010101;
8293 let isTerminator = 1;
8294 let isIndirectBranch = 1;
8298 def J4_jumpseti : HInst<
8299 (outs GeneralSubRegs:$Rd16),
8300 (ins u6_0Imm:$II, b30_2Imm:$Ii),
8301 "$Rd16 = #$II ; jump $Ii",
8302 tc_49eb22c8, TypeCJ>, Enc_9e4c3f {
8303 let Inst{0-0} = 0b0;
8304 let Inst{31-22} = 0b0001011000;
8305 let hasNewValue = 1;
8307 let isTerminator = 1;
8312 let isExtendable = 1;
8313 let opExtendable = 2;
8314 let isExtentSigned = 1;
8315 let opExtentBits = 11;
8316 let opExtentAlign = 2;
8318 def J4_jumpsetr : HInst<
8319 (outs GeneralSubRegs:$Rd16),
8320 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8321 "$Rd16 = $Rs16 ; jump $Ii",
8322 tc_49eb22c8, TypeCJ>, Enc_66bce1 {
8323 let Inst{0-0} = 0b0;
8324 let Inst{13-12} = 0b00;
8325 let Inst{31-22} = 0b0001011100;
8326 let hasNewValue = 1;
8328 let isTerminator = 1;
8333 let isExtendable = 1;
8334 let opExtendable = 2;
8335 let isExtentSigned = 1;
8336 let opExtentBits = 11;
8337 let opExtentAlign = 2;
8339 def J4_tstbit0_f_jumpnv_nt : HInst<
8341 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
8342 "if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8343 tc_746baa8e, TypeNCJ>, Enc_69d63b {
8344 let Inst{0-0} = 0b0;
8345 let Inst{13-8} = 0b000000;
8346 let Inst{19-19} = 0b0;
8347 let Inst{31-22} = 0b0010010111;
8348 let isPredicated = 1;
8349 let isPredicatedFalse = 1;
8350 let isTerminator = 1;
8354 let isRestrictNoSlot1Store = 1;
8356 let isTaken = Inst{13};
8357 let isExtendable = 1;
8358 let opExtendable = 1;
8359 let isExtentSigned = 1;
8360 let opExtentBits = 11;
8361 let opExtentAlign = 2;
8364 def J4_tstbit0_f_jumpnv_t : HInst<
8366 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
8367 "if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8368 tc_746baa8e, TypeNCJ>, Enc_69d63b {
8369 let Inst{0-0} = 0b0;
8370 let Inst{13-8} = 0b100000;
8371 let Inst{19-19} = 0b0;
8372 let Inst{31-22} = 0b0010010111;
8373 let isPredicated = 1;
8374 let isPredicatedFalse = 1;
8375 let isTerminator = 1;
8379 let isRestrictNoSlot1Store = 1;
8381 let isTaken = Inst{13};
8382 let isExtendable = 1;
8383 let opExtendable = 1;
8384 let isExtentSigned = 1;
8385 let opExtentBits = 11;
8386 let opExtentAlign = 2;
8389 def J4_tstbit0_fp0_jump_nt : HInst<
8391 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8392 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8393 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8394 let Inst{0-0} = 0b0;
8395 let Inst{13-8} = 0b000011;
8396 let Inst{31-22} = 0b0001000111;
8397 let isPredicated = 1;
8398 let isPredicatedFalse = 1;
8399 let isTerminator = 1;
8401 let isPredicatedNew = 1;
8406 let Defs = [P0, PC];
8407 let isTaken = Inst{13};
8408 let isExtendable = 1;
8409 let opExtendable = 1;
8410 let isExtentSigned = 1;
8411 let opExtentBits = 11;
8412 let opExtentAlign = 2;
8414 def J4_tstbit0_fp0_jump_t : HInst<
8416 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8417 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8418 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8419 let Inst{0-0} = 0b0;
8420 let Inst{13-8} = 0b100011;
8421 let Inst{31-22} = 0b0001000111;
8422 let isPredicated = 1;
8423 let isPredicatedFalse = 1;
8424 let isTerminator = 1;
8426 let isPredicatedNew = 1;
8431 let Defs = [P0, PC];
8432 let isTaken = Inst{13};
8433 let isExtendable = 1;
8434 let opExtendable = 1;
8435 let isExtentSigned = 1;
8436 let opExtentBits = 11;
8437 let opExtentAlign = 2;
8439 def J4_tstbit0_fp1_jump_nt : HInst<
8441 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8442 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8443 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8444 let Inst{0-0} = 0b0;
8445 let Inst{13-8} = 0b000011;
8446 let Inst{31-22} = 0b0001001111;
8447 let isPredicated = 1;
8448 let isPredicatedFalse = 1;
8449 let isTerminator = 1;
8451 let isPredicatedNew = 1;
8456 let Defs = [P1, PC];
8457 let isTaken = Inst{13};
8458 let isExtendable = 1;
8459 let opExtendable = 1;
8460 let isExtentSigned = 1;
8461 let opExtentBits = 11;
8462 let opExtentAlign = 2;
8464 def J4_tstbit0_fp1_jump_t : HInst<
8466 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8467 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8468 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8469 let Inst{0-0} = 0b0;
8470 let Inst{13-8} = 0b100011;
8471 let Inst{31-22} = 0b0001001111;
8472 let isPredicated = 1;
8473 let isPredicatedFalse = 1;
8474 let isTerminator = 1;
8476 let isPredicatedNew = 1;
8481 let Defs = [P1, PC];
8482 let isTaken = Inst{13};
8483 let isExtendable = 1;
8484 let opExtendable = 1;
8485 let isExtentSigned = 1;
8486 let opExtentBits = 11;
8487 let opExtentAlign = 2;
8489 def J4_tstbit0_t_jumpnv_nt : HInst<
8491 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
8492 "if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8493 tc_746baa8e, TypeNCJ>, Enc_69d63b {
8494 let Inst{0-0} = 0b0;
8495 let Inst{13-8} = 0b000000;
8496 let Inst{19-19} = 0b0;
8497 let Inst{31-22} = 0b0010010110;
8498 let isPredicated = 1;
8499 let isTerminator = 1;
8503 let isRestrictNoSlot1Store = 1;
8505 let isTaken = Inst{13};
8506 let isExtendable = 1;
8507 let opExtendable = 1;
8508 let isExtentSigned = 1;
8509 let opExtentBits = 11;
8510 let opExtentAlign = 2;
8513 def J4_tstbit0_t_jumpnv_t : HInst<
8515 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
8516 "if (tstbit($Ns8.new,#0)) jump:t $Ii",
8517 tc_746baa8e, TypeNCJ>, Enc_69d63b {
8518 let Inst{0-0} = 0b0;
8519 let Inst{13-8} = 0b100000;
8520 let Inst{19-19} = 0b0;
8521 let Inst{31-22} = 0b0010010110;
8522 let isPredicated = 1;
8523 let isTerminator = 1;
8527 let isRestrictNoSlot1Store = 1;
8529 let isTaken = Inst{13};
8530 let isExtendable = 1;
8531 let opExtendable = 1;
8532 let isExtentSigned = 1;
8533 let opExtentBits = 11;
8534 let opExtentAlign = 2;
8537 def J4_tstbit0_tp0_jump_nt : HInst<
8539 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8540 "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8541 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8542 let Inst{0-0} = 0b0;
8543 let Inst{13-8} = 0b000011;
8544 let Inst{31-22} = 0b0001000110;
8545 let isPredicated = 1;
8546 let isTerminator = 1;
8548 let isPredicatedNew = 1;
8553 let Defs = [P0, PC];
8554 let isTaken = Inst{13};
8555 let isExtendable = 1;
8556 let opExtendable = 1;
8557 let isExtentSigned = 1;
8558 let opExtentBits = 11;
8559 let opExtentAlign = 2;
8561 def J4_tstbit0_tp0_jump_t : HInst<
8563 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8564 "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8565 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8566 let Inst{0-0} = 0b0;
8567 let Inst{13-8} = 0b100011;
8568 let Inst{31-22} = 0b0001000110;
8569 let isPredicated = 1;
8570 let isTerminator = 1;
8572 let isPredicatedNew = 1;
8577 let Defs = [P0, PC];
8578 let isTaken = Inst{13};
8579 let isExtendable = 1;
8580 let opExtendable = 1;
8581 let isExtentSigned = 1;
8582 let opExtentBits = 11;
8583 let opExtentAlign = 2;
8585 def J4_tstbit0_tp1_jump_nt : HInst<
8587 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8588 "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8589 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8590 let Inst{0-0} = 0b0;
8591 let Inst{13-8} = 0b000011;
8592 let Inst{31-22} = 0b0001001110;
8593 let isPredicated = 1;
8594 let isTerminator = 1;
8596 let isPredicatedNew = 1;
8601 let Defs = [P1, PC];
8602 let isTaken = Inst{13};
8603 let isExtendable = 1;
8604 let opExtendable = 1;
8605 let isExtentSigned = 1;
8606 let opExtentBits = 11;
8607 let opExtentAlign = 2;
8609 def J4_tstbit0_tp1_jump_t : HInst<
8611 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8612 "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8613 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
8614 let Inst{0-0} = 0b0;
8615 let Inst{13-8} = 0b100011;
8616 let Inst{31-22} = 0b0001001110;
8617 let isPredicated = 1;
8618 let isTerminator = 1;
8620 let isPredicatedNew = 1;
8625 let Defs = [P1, PC];
8626 let isTaken = Inst{13};
8627 let isExtendable = 1;
8628 let opExtendable = 1;
8629 let isExtentSigned = 1;
8630 let opExtentBits = 11;
8631 let opExtentAlign = 2;
8633 def L2_deallocframe : HInst<
8634 (outs DoubleRegs:$Rdd32),
8635 (ins IntRegs:$Rs32),
8636 "$Rdd32 = deallocframe($Rs32):raw",
8637 tc_d1090e34, TypeLD>, Enc_3a3d62 {
8638 let Inst{13-5} = 0b000000000;
8639 let Inst{31-21} = 0b10010000000;
8640 let accessSize = DoubleWordAccess;
8642 let Uses = [FRAMEKEY];
8645 def L2_loadalignb_io : HInst<
8646 (outs DoubleRegs:$Ryy32),
8647 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8648 "$Ryy32 = memb_fifo($Rs32+#$Ii)",
8649 tc_ef52ed71, TypeLD>, Enc_a27588 {
8650 let Inst{24-21} = 0b0100;
8651 let Inst{31-27} = 0b10010;
8652 let addrMode = BaseImmOffset;
8653 let accessSize = ByteAccess;
8655 let isExtendable = 1;
8656 let opExtendable = 3;
8657 let isExtentSigned = 1;
8658 let opExtentBits = 11;
8659 let opExtentAlign = 0;
8660 let Constraints = "$Ryy32 = $Ryy32in";
8662 def L2_loadalignb_pbr : HInst<
8663 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8664 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8665 "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8666 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8667 let Inst{12-5} = 0b00000000;
8668 let Inst{31-21} = 0b10011110100;
8669 let accessSize = ByteAccess;
8671 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8673 def L2_loadalignb_pci : HInst<
8674 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8675 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8676 "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8677 tc_03220ffa, TypeLD>, Enc_74aef2 {
8678 let Inst{12-9} = 0b0000;
8679 let Inst{31-21} = 0b10011000100;
8680 let addrMode = PostInc;
8681 let accessSize = ByteAccess;
8684 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8686 def L2_loadalignb_pcr : HInst<
8687 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8688 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8689 "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8690 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8691 let Inst{12-5} = 0b00010000;
8692 let Inst{31-21} = 0b10011000100;
8693 let addrMode = PostInc;
8694 let accessSize = ByteAccess;
8697 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8699 def L2_loadalignb_pi : HInst<
8700 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8701 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8702 "$Ryy32 = memb_fifo($Rx32++#$Ii)",
8703 tc_bad2bcaf, TypeLD>, Enc_6b197f {
8704 let Inst{13-9} = 0b00000;
8705 let Inst{31-21} = 0b10011010100;
8706 let addrMode = PostInc;
8707 let accessSize = ByteAccess;
8709 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8711 def L2_loadalignb_pr : HInst<
8712 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8713 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8714 "$Ryy32 = memb_fifo($Rx32++$Mu2)",
8715 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8716 let Inst{12-5} = 0b00000000;
8717 let Inst{31-21} = 0b10011100100;
8718 let addrMode = PostInc;
8719 let accessSize = ByteAccess;
8721 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8723 def L2_loadalignb_zomap : HInst<
8724 (outs DoubleRegs:$Ryy32),
8725 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8726 "$Ryy32 = memb_fifo($Rs32)",
8727 tc_ef52ed71, TypeMAPPING> {
8729 let isCodeGenOnly = 1;
8730 let Constraints = "$Ryy32 = $Ryy32in";
8732 def L2_loadalignh_io : HInst<
8733 (outs DoubleRegs:$Ryy32),
8734 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8735 "$Ryy32 = memh_fifo($Rs32+#$Ii)",
8736 tc_ef52ed71, TypeLD>, Enc_5cd7e9 {
8737 let Inst{24-21} = 0b0010;
8738 let Inst{31-27} = 0b10010;
8739 let addrMode = BaseImmOffset;
8740 let accessSize = HalfWordAccess;
8742 let isExtendable = 1;
8743 let opExtendable = 3;
8744 let isExtentSigned = 1;
8745 let opExtentBits = 12;
8746 let opExtentAlign = 1;
8747 let Constraints = "$Ryy32 = $Ryy32in";
8749 def L2_loadalignh_pbr : HInst<
8750 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8751 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8752 "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8753 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8754 let Inst{12-5} = 0b00000000;
8755 let Inst{31-21} = 0b10011110010;
8756 let accessSize = HalfWordAccess;
8758 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8760 def L2_loadalignh_pci : HInst<
8761 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8762 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8763 "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
8764 tc_03220ffa, TypeLD>, Enc_9e2e1c {
8765 let Inst{12-9} = 0b0000;
8766 let Inst{31-21} = 0b10011000010;
8767 let addrMode = PostInc;
8768 let accessSize = HalfWordAccess;
8771 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8773 def L2_loadalignh_pcr : HInst<
8774 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8775 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8776 "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
8777 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8778 let Inst{12-5} = 0b00010000;
8779 let Inst{31-21} = 0b10011000010;
8780 let addrMode = PostInc;
8781 let accessSize = HalfWordAccess;
8784 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8786 def L2_loadalignh_pi : HInst<
8787 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8788 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
8789 "$Ryy32 = memh_fifo($Rx32++#$Ii)",
8790 tc_bad2bcaf, TypeLD>, Enc_bd1cbc {
8791 let Inst{13-9} = 0b00000;
8792 let Inst{31-21} = 0b10011010010;
8793 let addrMode = PostInc;
8794 let accessSize = HalfWordAccess;
8796 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8798 def L2_loadalignh_pr : HInst<
8799 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8800 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8801 "$Ryy32 = memh_fifo($Rx32++$Mu2)",
8802 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
8803 let Inst{12-5} = 0b00000000;
8804 let Inst{31-21} = 0b10011100010;
8805 let addrMode = PostInc;
8806 let accessSize = HalfWordAccess;
8808 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8810 def L2_loadalignh_zomap : HInst<
8811 (outs DoubleRegs:$Ryy32),
8812 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8813 "$Ryy32 = memh_fifo($Rs32)",
8814 tc_ef52ed71, TypeMAPPING> {
8816 let isCodeGenOnly = 1;
8817 let Constraints = "$Ryy32 = $Ryy32in";
8819 def L2_loadbsw2_io : HInst<
8820 (outs IntRegs:$Rd32),
8821 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
8822 "$Rd32 = membh($Rs32+#$Ii)",
8823 tc_7f881c76, TypeLD>, Enc_de0214 {
8824 let Inst{24-21} = 0b0001;
8825 let Inst{31-27} = 0b10010;
8826 let hasNewValue = 1;
8828 let addrMode = BaseImmOffset;
8829 let accessSize = HalfWordAccess;
8831 let isExtendable = 1;
8832 let opExtendable = 2;
8833 let isExtentSigned = 1;
8834 let opExtentBits = 12;
8835 let opExtentAlign = 1;
8837 def L2_loadbsw2_pbr : HInst<
8838 (outs IntRegs:$Rd32, IntRegs:$Rx32),
8839 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8840 "$Rd32 = membh($Rx32++$Mu2:brev)",
8841 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
8842 let Inst{12-5} = 0b00000000;
8843 let Inst{31-21} = 0b10011110001;
8844 let hasNewValue = 1;
8846 let accessSize = HalfWordAccess;
8848 let Constraints = "$Rx32 = $Rx32in";
8850 def L2_loadbsw2_pci : HInst<
8851 (outs IntRegs:$Rd32, IntRegs:$Rx32),
8852 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8853 "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
8854 tc_4403ca65, TypeLD>, Enc_e83554 {
8855 let Inst{12-9} = 0b0000;
8856 let Inst{31-21} = 0b10011000001;
8857 let hasNewValue = 1;
8859 let addrMode = PostInc;
8860 let accessSize = HalfWordAccess;
8863 let Constraints = "$Rx32 = $Rx32in";
8865 def L2_loadbsw2_pcr : HInst<
8866 (outs IntRegs:$Rd32, IntRegs:$Rx32),
8867 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8868 "$Rd32 = membh($Rx32++I:circ($Mu2))",
8869 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
8870 let Inst{12-5} = 0b00010000;
8871 let Inst{31-21} = 0b10011000001;
8872 let hasNewValue = 1;
8874 let addrMode = PostInc;
8875 let accessSize = HalfWordAccess;
8878 let Constraints = "$Rx32 = $Rx32in";
8880 def L2_loadbsw2_pi : HInst<
8881 (outs IntRegs:$Rd32, IntRegs:$Rx32),
8882 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
8883 "$Rd32 = membh($Rx32++#$Ii)",
8884 tc_2fc0c436, TypeLD>, Enc_152467 {
8885 let Inst{13-9} = 0b00000;
8886 let Inst{31-21} = 0b10011010001;
8887 let hasNewValue = 1;
8889 let addrMode = PostInc;
8890 let accessSize = HalfWordAccess;
8892 let Constraints = "$Rx32 = $Rx32in";
8894 def L2_loadbsw2_pr : HInst<
8895 (outs IntRegs:$Rd32, IntRegs:$Rx32),
8896 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8897 "$Rd32 = membh($Rx32++$Mu2)",
8898 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
8899 let Inst{12-5} = 0b00000000;
8900 let Inst{31-21} = 0b10011100001;
8901 let hasNewValue = 1;
8903 let addrMode = PostInc;
8904 let accessSize = HalfWordAccess;
8906 let Constraints = "$Rx32 = $Rx32in";
8908 def L2_loadbsw2_zomap : HInst<
8909 (outs IntRegs:$Rd32),
8910 (ins IntRegs:$Rs32),
8911 "$Rd32 = membh($Rs32)",
8912 tc_7f881c76, TypeMAPPING> {
8913 let hasNewValue = 1;
8916 let isCodeGenOnly = 1;
8918 def L2_loadbsw4_io : HInst<
8919 (outs DoubleRegs:$Rdd32),
8920 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
8921 "$Rdd32 = membh($Rs32+#$Ii)",
8922 tc_7f881c76, TypeLD>, Enc_2d7491 {
8923 let Inst{24-21} = 0b0111;
8924 let Inst{31-27} = 0b10010;
8925 let addrMode = BaseImmOffset;
8926 let accessSize = WordAccess;
8928 let isExtendable = 1;
8929 let opExtendable = 2;
8930 let isExtentSigned = 1;
8931 let opExtentBits = 13;
8932 let opExtentAlign = 2;
8934 def L2_loadbsw4_pbr : HInst<
8935 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
8936 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8937 "$Rdd32 = membh($Rx32++$Mu2:brev)",
8938 tc_2fc0c436, TypeLD>, Enc_7eee72 {
8939 let Inst{12-5} = 0b00000000;
8940 let Inst{31-21} = 0b10011110111;
8941 let accessSize = WordAccess;
8943 let Constraints = "$Rx32 = $Rx32in";
8945 def L2_loadbsw4_pci : HInst<
8946 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
8947 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
8948 "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
8949 tc_4403ca65, TypeLD>, Enc_70b24b {
8950 let Inst{12-9} = 0b0000;
8951 let Inst{31-21} = 0b10011000111;
8952 let addrMode = PostInc;
8953 let accessSize = WordAccess;
8956 let Constraints = "$Rx32 = $Rx32in";
8958 def L2_loadbsw4_pcr : HInst<
8959 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
8960 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8961 "$Rdd32 = membh($Rx32++I:circ($Mu2))",
8962 tc_2fc0c436, TypeLD>, Enc_7eee72 {
8963 let Inst{12-5} = 0b00010000;
8964 let Inst{31-21} = 0b10011000111;
8965 let addrMode = PostInc;
8966 let accessSize = WordAccess;
8969 let Constraints = "$Rx32 = $Rx32in";
8971 def L2_loadbsw4_pi : HInst<
8972 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
8973 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
8974 "$Rdd32 = membh($Rx32++#$Ii)",
8975 tc_2fc0c436, TypeLD>, Enc_71f1b4 {
8976 let Inst{13-9} = 0b00000;
8977 let Inst{31-21} = 0b10011010111;
8978 let addrMode = PostInc;
8979 let accessSize = WordAccess;
8981 let Constraints = "$Rx32 = $Rx32in";
8983 def L2_loadbsw4_pr : HInst<
8984 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
8985 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
8986 "$Rdd32 = membh($Rx32++$Mu2)",
8987 tc_2fc0c436, TypeLD>, Enc_7eee72 {
8988 let Inst{12-5} = 0b00000000;
8989 let Inst{31-21} = 0b10011100111;
8990 let addrMode = PostInc;
8991 let accessSize = WordAccess;
8993 let Constraints = "$Rx32 = $Rx32in";
8995 def L2_loadbsw4_zomap : HInst<
8996 (outs DoubleRegs:$Rdd32),
8997 (ins IntRegs:$Rs32),
8998 "$Rdd32 = membh($Rs32)",
8999 tc_7f881c76, TypeMAPPING> {
9001 let isCodeGenOnly = 1;
9003 def L2_loadbzw2_io : HInst<
9004 (outs IntRegs:$Rd32),
9005 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
9006 "$Rd32 = memubh($Rs32+#$Ii)",
9007 tc_7f881c76, TypeLD>, Enc_de0214 {
9008 let Inst{24-21} = 0b0011;
9009 let Inst{31-27} = 0b10010;
9010 let hasNewValue = 1;
9012 let addrMode = BaseImmOffset;
9013 let accessSize = HalfWordAccess;
9015 let isExtendable = 1;
9016 let opExtendable = 2;
9017 let isExtentSigned = 1;
9018 let opExtentBits = 12;
9019 let opExtentAlign = 1;
9021 def L2_loadbzw2_pbr : HInst<
9022 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9023 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9024 "$Rd32 = memubh($Rx32++$Mu2:brev)",
9025 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9026 let Inst{12-5} = 0b00000000;
9027 let Inst{31-21} = 0b10011110011;
9028 let hasNewValue = 1;
9030 let accessSize = HalfWordAccess;
9032 let Constraints = "$Rx32 = $Rx32in";
9034 def L2_loadbzw2_pci : HInst<
9035 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9036 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9037 "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9038 tc_4403ca65, TypeLD>, Enc_e83554 {
9039 let Inst{12-9} = 0b0000;
9040 let Inst{31-21} = 0b10011000011;
9041 let hasNewValue = 1;
9043 let addrMode = PostInc;
9044 let accessSize = HalfWordAccess;
9047 let Constraints = "$Rx32 = $Rx32in";
9049 def L2_loadbzw2_pcr : HInst<
9050 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9051 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9052 "$Rd32 = memubh($Rx32++I:circ($Mu2))",
9053 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9054 let Inst{12-5} = 0b00010000;
9055 let Inst{31-21} = 0b10011000011;
9056 let hasNewValue = 1;
9058 let addrMode = PostInc;
9059 let accessSize = HalfWordAccess;
9062 let Constraints = "$Rx32 = $Rx32in";
9064 def L2_loadbzw2_pi : HInst<
9065 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9066 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9067 "$Rd32 = memubh($Rx32++#$Ii)",
9068 tc_2fc0c436, TypeLD>, Enc_152467 {
9069 let Inst{13-9} = 0b00000;
9070 let Inst{31-21} = 0b10011010011;
9071 let hasNewValue = 1;
9073 let addrMode = PostInc;
9074 let accessSize = HalfWordAccess;
9076 let Constraints = "$Rx32 = $Rx32in";
9078 def L2_loadbzw2_pr : HInst<
9079 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9080 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9081 "$Rd32 = memubh($Rx32++$Mu2)",
9082 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9083 let Inst{12-5} = 0b00000000;
9084 let Inst{31-21} = 0b10011100011;
9085 let hasNewValue = 1;
9087 let addrMode = PostInc;
9088 let accessSize = HalfWordAccess;
9090 let Constraints = "$Rx32 = $Rx32in";
9092 def L2_loadbzw2_zomap : HInst<
9093 (outs IntRegs:$Rd32),
9094 (ins IntRegs:$Rs32),
9095 "$Rd32 = memubh($Rs32)",
9096 tc_7f881c76, TypeMAPPING> {
9097 let hasNewValue = 1;
9100 let isCodeGenOnly = 1;
9102 def L2_loadbzw4_io : HInst<
9103 (outs DoubleRegs:$Rdd32),
9104 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
9105 "$Rdd32 = memubh($Rs32+#$Ii)",
9106 tc_7f881c76, TypeLD>, Enc_2d7491 {
9107 let Inst{24-21} = 0b0101;
9108 let Inst{31-27} = 0b10010;
9109 let addrMode = BaseImmOffset;
9110 let accessSize = WordAccess;
9112 let isExtendable = 1;
9113 let opExtendable = 2;
9114 let isExtentSigned = 1;
9115 let opExtentBits = 13;
9116 let opExtentAlign = 2;
9118 def L2_loadbzw4_pbr : HInst<
9119 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9120 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9121 "$Rdd32 = memubh($Rx32++$Mu2:brev)",
9122 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9123 let Inst{12-5} = 0b00000000;
9124 let Inst{31-21} = 0b10011110101;
9125 let accessSize = WordAccess;
9127 let Constraints = "$Rx32 = $Rx32in";
9129 def L2_loadbzw4_pci : HInst<
9130 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9131 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9132 "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9133 tc_4403ca65, TypeLD>, Enc_70b24b {
9134 let Inst{12-9} = 0b0000;
9135 let Inst{31-21} = 0b10011000101;
9136 let addrMode = PostInc;
9137 let accessSize = WordAccess;
9140 let Constraints = "$Rx32 = $Rx32in";
9142 def L2_loadbzw4_pcr : HInst<
9143 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9144 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9145 "$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9146 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9147 let Inst{12-5} = 0b00010000;
9148 let Inst{31-21} = 0b10011000101;
9149 let addrMode = PostInc;
9150 let accessSize = WordAccess;
9153 let Constraints = "$Rx32 = $Rx32in";
9155 def L2_loadbzw4_pi : HInst<
9156 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9157 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9158 "$Rdd32 = memubh($Rx32++#$Ii)",
9159 tc_2fc0c436, TypeLD>, Enc_71f1b4 {
9160 let Inst{13-9} = 0b00000;
9161 let Inst{31-21} = 0b10011010101;
9162 let addrMode = PostInc;
9163 let accessSize = WordAccess;
9165 let Constraints = "$Rx32 = $Rx32in";
9167 def L2_loadbzw4_pr : HInst<
9168 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9169 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9170 "$Rdd32 = memubh($Rx32++$Mu2)",
9171 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9172 let Inst{12-5} = 0b00000000;
9173 let Inst{31-21} = 0b10011100101;
9174 let addrMode = PostInc;
9175 let accessSize = WordAccess;
9177 let Constraints = "$Rx32 = $Rx32in";
9179 def L2_loadbzw4_zomap : HInst<
9180 (outs DoubleRegs:$Rdd32),
9181 (ins IntRegs:$Rs32),
9182 "$Rdd32 = memubh($Rs32)",
9183 tc_7f881c76, TypeMAPPING> {
9185 let isCodeGenOnly = 1;
9187 def L2_loadrb_io : HInst<
9188 (outs IntRegs:$Rd32),
9189 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
9190 "$Rd32 = memb($Rs32+#$Ii)",
9191 tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9192 let Inst{24-21} = 0b1000;
9193 let Inst{31-27} = 0b10010;
9194 let hasNewValue = 1;
9196 let addrMode = BaseImmOffset;
9197 let accessSize = ByteAccess;
9199 let CextOpcode = "L2_loadrb";
9200 let BaseOpcode = "L2_loadrb_io";
9201 let isPredicable = 1;
9202 let isExtendable = 1;
9203 let opExtendable = 2;
9204 let isExtentSigned = 1;
9205 let opExtentBits = 11;
9206 let opExtentAlign = 0;
9208 def L2_loadrb_pbr : HInst<
9209 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9210 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9211 "$Rd32 = memb($Rx32++$Mu2:brev)",
9212 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9213 let Inst{12-5} = 0b00000000;
9214 let Inst{31-21} = 0b10011111000;
9215 let hasNewValue = 1;
9217 let accessSize = ByteAccess;
9219 let Constraints = "$Rx32 = $Rx32in";
9221 def L2_loadrb_pci : HInst<
9222 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9223 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9224 "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9225 tc_4403ca65, TypeLD>, Enc_e0a47a {
9226 let Inst{12-9} = 0b0000;
9227 let Inst{31-21} = 0b10011001000;
9228 let hasNewValue = 1;
9230 let addrMode = PostInc;
9231 let accessSize = ByteAccess;
9234 let Constraints = "$Rx32 = $Rx32in";
9236 def L2_loadrb_pcr : HInst<
9237 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9238 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9239 "$Rd32 = memb($Rx32++I:circ($Mu2))",
9240 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9241 let Inst{12-5} = 0b00010000;
9242 let Inst{31-21} = 0b10011001000;
9243 let hasNewValue = 1;
9245 let addrMode = PostInc;
9246 let accessSize = ByteAccess;
9249 let Constraints = "$Rx32 = $Rx32in";
9251 def L2_loadrb_pi : HInst<
9252 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9253 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9254 "$Rd32 = memb($Rx32++#$Ii)",
9255 tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9256 let Inst{13-9} = 0b00000;
9257 let Inst{31-21} = 0b10011011000;
9258 let hasNewValue = 1;
9260 let addrMode = PostInc;
9261 let accessSize = ByteAccess;
9263 let CextOpcode = "L2_loadrb";
9264 let BaseOpcode = "L2_loadrb_pi";
9265 let isPredicable = 1;
9266 let Constraints = "$Rx32 = $Rx32in";
9268 def L2_loadrb_pr : HInst<
9269 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9270 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9271 "$Rd32 = memb($Rx32++$Mu2)",
9272 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9273 let Inst{12-5} = 0b00000000;
9274 let Inst{31-21} = 0b10011101000;
9275 let hasNewValue = 1;
9277 let addrMode = PostInc;
9278 let accessSize = ByteAccess;
9280 let Constraints = "$Rx32 = $Rx32in";
9282 def L2_loadrb_zomap : HInst<
9283 (outs IntRegs:$Rd32),
9284 (ins IntRegs:$Rs32),
9285 "$Rd32 = memb($Rs32)",
9286 tc_7f881c76, TypeMAPPING> {
9287 let hasNewValue = 1;
9290 let isCodeGenOnly = 1;
9292 def L2_loadrbgp : HInst<
9293 (outs IntRegs:$Rd32),
9295 "$Rd32 = memb(gp+#$Ii)",
9296 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9297 let Inst{24-21} = 0b1000;
9298 let Inst{31-27} = 0b01001;
9299 let hasNewValue = 1;
9301 let accessSize = ByteAccess;
9304 let BaseOpcode = "L4_loadrb_abs";
9305 let isPredicable = 1;
9306 let opExtendable = 1;
9307 let isExtentSigned = 0;
9308 let opExtentBits = 16;
9309 let opExtentAlign = 0;
9311 def L2_loadrd_io : HInst<
9312 (outs DoubleRegs:$Rdd32),
9313 (ins IntRegs:$Rs32, s29_3Imm:$Ii),
9314 "$Rdd32 = memd($Rs32+#$Ii)",
9315 tc_7f881c76, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9316 let Inst{24-21} = 0b1110;
9317 let Inst{31-27} = 0b10010;
9318 let addrMode = BaseImmOffset;
9319 let accessSize = DoubleWordAccess;
9321 let CextOpcode = "L2_loadrd";
9322 let BaseOpcode = "L2_loadrd_io";
9323 let isPredicable = 1;
9324 let isExtendable = 1;
9325 let opExtendable = 2;
9326 let isExtentSigned = 1;
9327 let opExtentBits = 14;
9328 let opExtentAlign = 3;
9330 def L2_loadrd_pbr : HInst<
9331 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9332 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9333 "$Rdd32 = memd($Rx32++$Mu2:brev)",
9334 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9335 let Inst{12-5} = 0b00000000;
9336 let Inst{31-21} = 0b10011111110;
9337 let accessSize = DoubleWordAccess;
9339 let Constraints = "$Rx32 = $Rx32in";
9341 def L2_loadrd_pci : HInst<
9342 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9343 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9344 "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9345 tc_4403ca65, TypeLD>, Enc_b05839 {
9346 let Inst{12-9} = 0b0000;
9347 let Inst{31-21} = 0b10011001110;
9348 let addrMode = PostInc;
9349 let accessSize = DoubleWordAccess;
9352 let Constraints = "$Rx32 = $Rx32in";
9354 def L2_loadrd_pcr : HInst<
9355 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9356 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9357 "$Rdd32 = memd($Rx32++I:circ($Mu2))",
9358 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9359 let Inst{12-5} = 0b00010000;
9360 let Inst{31-21} = 0b10011001110;
9361 let addrMode = PostInc;
9362 let accessSize = DoubleWordAccess;
9365 let Constraints = "$Rx32 = $Rx32in";
9367 def L2_loadrd_pi : HInst<
9368 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9369 (ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9370 "$Rdd32 = memd($Rx32++#$Ii)",
9371 tc_2fc0c436, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9372 let Inst{13-9} = 0b00000;
9373 let Inst{31-21} = 0b10011011110;
9374 let addrMode = PostInc;
9375 let accessSize = DoubleWordAccess;
9377 let CextOpcode = "L2_loadrd";
9378 let BaseOpcode = "L2_loadrd_pi";
9379 let isPredicable = 1;
9380 let Constraints = "$Rx32 = $Rx32in";
9382 def L2_loadrd_pr : HInst<
9383 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9384 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9385 "$Rdd32 = memd($Rx32++$Mu2)",
9386 tc_2fc0c436, TypeLD>, Enc_7eee72 {
9387 let Inst{12-5} = 0b00000000;
9388 let Inst{31-21} = 0b10011101110;
9389 let addrMode = PostInc;
9390 let accessSize = DoubleWordAccess;
9392 let Constraints = "$Rx32 = $Rx32in";
9394 def L2_loadrd_zomap : HInst<
9395 (outs DoubleRegs:$Rdd32),
9396 (ins IntRegs:$Rs32),
9397 "$Rdd32 = memd($Rs32)",
9398 tc_7f881c76, TypeMAPPING> {
9400 let isCodeGenOnly = 1;
9402 def L2_loadrdgp : HInst<
9403 (outs DoubleRegs:$Rdd32),
9405 "$Rdd32 = memd(gp+#$Ii)",
9406 tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
9407 let Inst{24-21} = 0b1110;
9408 let Inst{31-27} = 0b01001;
9409 let accessSize = DoubleWordAccess;
9412 let BaseOpcode = "L4_loadrd_abs";
9413 let isPredicable = 1;
9414 let opExtendable = 1;
9415 let isExtentSigned = 0;
9416 let opExtentBits = 19;
9417 let opExtentAlign = 3;
9419 def L2_loadrh_io : HInst<
9420 (outs IntRegs:$Rd32),
9421 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
9422 "$Rd32 = memh($Rs32+#$Ii)",
9423 tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9424 let Inst{24-21} = 0b1010;
9425 let Inst{31-27} = 0b10010;
9426 let hasNewValue = 1;
9428 let addrMode = BaseImmOffset;
9429 let accessSize = HalfWordAccess;
9431 let CextOpcode = "L2_loadrh";
9432 let BaseOpcode = "L2_loadrh_io";
9433 let isPredicable = 1;
9434 let isExtendable = 1;
9435 let opExtendable = 2;
9436 let isExtentSigned = 1;
9437 let opExtentBits = 12;
9438 let opExtentAlign = 1;
9440 def L2_loadrh_pbr : HInst<
9441 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9442 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9443 "$Rd32 = memh($Rx32++$Mu2:brev)",
9444 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9445 let Inst{12-5} = 0b00000000;
9446 let Inst{31-21} = 0b10011111010;
9447 let hasNewValue = 1;
9449 let accessSize = HalfWordAccess;
9451 let Constraints = "$Rx32 = $Rx32in";
9453 def L2_loadrh_pci : HInst<
9454 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9455 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9456 "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9457 tc_4403ca65, TypeLD>, Enc_e83554 {
9458 let Inst{12-9} = 0b0000;
9459 let Inst{31-21} = 0b10011001010;
9460 let hasNewValue = 1;
9462 let addrMode = PostInc;
9463 let accessSize = HalfWordAccess;
9466 let Constraints = "$Rx32 = $Rx32in";
9468 def L2_loadrh_pcr : HInst<
9469 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9470 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9471 "$Rd32 = memh($Rx32++I:circ($Mu2))",
9472 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9473 let Inst{12-5} = 0b00010000;
9474 let Inst{31-21} = 0b10011001010;
9475 let hasNewValue = 1;
9477 let addrMode = PostInc;
9478 let accessSize = HalfWordAccess;
9481 let Constraints = "$Rx32 = $Rx32in";
9483 def L2_loadrh_pi : HInst<
9484 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9485 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9486 "$Rd32 = memh($Rx32++#$Ii)",
9487 tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9488 let Inst{13-9} = 0b00000;
9489 let Inst{31-21} = 0b10011011010;
9490 let hasNewValue = 1;
9492 let addrMode = PostInc;
9493 let accessSize = HalfWordAccess;
9495 let CextOpcode = "L2_loadrh";
9496 let BaseOpcode = "L2_loadrh_pi";
9497 let isPredicable = 1;
9498 let Constraints = "$Rx32 = $Rx32in";
9500 def L2_loadrh_pr : HInst<
9501 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9502 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9503 "$Rd32 = memh($Rx32++$Mu2)",
9504 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9505 let Inst{12-5} = 0b00000000;
9506 let Inst{31-21} = 0b10011101010;
9507 let hasNewValue = 1;
9509 let addrMode = PostInc;
9510 let accessSize = HalfWordAccess;
9512 let Constraints = "$Rx32 = $Rx32in";
9514 def L2_loadrh_zomap : HInst<
9515 (outs IntRegs:$Rd32),
9516 (ins IntRegs:$Rs32),
9517 "$Rd32 = memh($Rs32)",
9518 tc_7f881c76, TypeMAPPING> {
9519 let hasNewValue = 1;
9522 let isCodeGenOnly = 1;
9524 def L2_loadrhgp : HInst<
9525 (outs IntRegs:$Rd32),
9527 "$Rd32 = memh(gp+#$Ii)",
9528 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9529 let Inst{24-21} = 0b1010;
9530 let Inst{31-27} = 0b01001;
9531 let hasNewValue = 1;
9533 let accessSize = HalfWordAccess;
9536 let BaseOpcode = "L4_loadrh_abs";
9537 let isPredicable = 1;
9538 let opExtendable = 1;
9539 let isExtentSigned = 0;
9540 let opExtentBits = 17;
9541 let opExtentAlign = 1;
9543 def L2_loadri_io : HInst<
9544 (outs IntRegs:$Rd32),
9545 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
9546 "$Rd32 = memw($Rs32+#$Ii)",
9547 tc_7f881c76, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9548 let Inst{24-21} = 0b1100;
9549 let Inst{31-27} = 0b10010;
9550 let hasNewValue = 1;
9552 let addrMode = BaseImmOffset;
9553 let accessSize = WordAccess;
9555 let CextOpcode = "L2_loadri";
9556 let BaseOpcode = "L2_loadri_io";
9557 let isPredicable = 1;
9558 let isExtendable = 1;
9559 let opExtendable = 2;
9560 let isExtentSigned = 1;
9561 let opExtentBits = 13;
9562 let opExtentAlign = 2;
9564 def L2_loadri_pbr : HInst<
9565 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9566 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9567 "$Rd32 = memw($Rx32++$Mu2:brev)",
9568 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9569 let Inst{12-5} = 0b00000000;
9570 let Inst{31-21} = 0b10011111100;
9571 let hasNewValue = 1;
9573 let accessSize = WordAccess;
9575 let Constraints = "$Rx32 = $Rx32in";
9577 def L2_loadri_pci : HInst<
9578 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9579 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9580 "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9581 tc_4403ca65, TypeLD>, Enc_27fd0e {
9582 let Inst{12-9} = 0b0000;
9583 let Inst{31-21} = 0b10011001100;
9584 let hasNewValue = 1;
9586 let addrMode = PostInc;
9587 let accessSize = WordAccess;
9590 let Constraints = "$Rx32 = $Rx32in";
9592 def L2_loadri_pcr : HInst<
9593 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9594 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9595 "$Rd32 = memw($Rx32++I:circ($Mu2))",
9596 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9597 let Inst{12-5} = 0b00010000;
9598 let Inst{31-21} = 0b10011001100;
9599 let hasNewValue = 1;
9601 let addrMode = PostInc;
9602 let accessSize = WordAccess;
9605 let Constraints = "$Rx32 = $Rx32in";
9607 def L2_loadri_pi : HInst<
9608 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9609 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9610 "$Rd32 = memw($Rx32++#$Ii)",
9611 tc_2fc0c436, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9612 let Inst{13-9} = 0b00000;
9613 let Inst{31-21} = 0b10011011100;
9614 let hasNewValue = 1;
9616 let addrMode = PostInc;
9617 let accessSize = WordAccess;
9619 let CextOpcode = "L2_loadri";
9620 let BaseOpcode = "L2_loadri_pi";
9621 let isPredicable = 1;
9622 let Constraints = "$Rx32 = $Rx32in";
9624 def L2_loadri_pr : HInst<
9625 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9626 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9627 "$Rd32 = memw($Rx32++$Mu2)",
9628 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9629 let Inst{12-5} = 0b00000000;
9630 let Inst{31-21} = 0b10011101100;
9631 let hasNewValue = 1;
9633 let addrMode = PostInc;
9634 let accessSize = WordAccess;
9636 let Constraints = "$Rx32 = $Rx32in";
9638 def L2_loadri_zomap : HInst<
9639 (outs IntRegs:$Rd32),
9640 (ins IntRegs:$Rs32),
9641 "$Rd32 = memw($Rs32)",
9642 tc_7f881c76, TypeMAPPING> {
9643 let hasNewValue = 1;
9646 let isCodeGenOnly = 1;
9648 def L2_loadrigp : HInst<
9649 (outs IntRegs:$Rd32),
9651 "$Rd32 = memw(gp+#$Ii)",
9652 tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9653 let Inst{24-21} = 0b1100;
9654 let Inst{31-27} = 0b01001;
9655 let hasNewValue = 1;
9657 let accessSize = WordAccess;
9660 let BaseOpcode = "L4_loadri_abs";
9661 let isPredicable = 1;
9662 let opExtendable = 1;
9663 let isExtentSigned = 0;
9664 let opExtentBits = 18;
9665 let opExtentAlign = 2;
9667 def L2_loadrub_io : HInst<
9668 (outs IntRegs:$Rd32),
9669 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
9670 "$Rd32 = memub($Rs32+#$Ii)",
9671 tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9672 let Inst{24-21} = 0b1001;
9673 let Inst{31-27} = 0b10010;
9674 let hasNewValue = 1;
9676 let addrMode = BaseImmOffset;
9677 let accessSize = ByteAccess;
9679 let CextOpcode = "L2_loadrub";
9680 let BaseOpcode = "L2_loadrub_io";
9681 let isPredicable = 1;
9682 let isExtendable = 1;
9683 let opExtendable = 2;
9684 let isExtentSigned = 1;
9685 let opExtentBits = 11;
9686 let opExtentAlign = 0;
9688 def L2_loadrub_pbr : HInst<
9689 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9690 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9691 "$Rd32 = memub($Rx32++$Mu2:brev)",
9692 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9693 let Inst{12-5} = 0b00000000;
9694 let Inst{31-21} = 0b10011111001;
9695 let hasNewValue = 1;
9697 let accessSize = ByteAccess;
9699 let Constraints = "$Rx32 = $Rx32in";
9701 def L2_loadrub_pci : HInst<
9702 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9703 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9704 "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9705 tc_4403ca65, TypeLD>, Enc_e0a47a {
9706 let Inst{12-9} = 0b0000;
9707 let Inst{31-21} = 0b10011001001;
9708 let hasNewValue = 1;
9710 let addrMode = PostInc;
9711 let accessSize = ByteAccess;
9714 let Constraints = "$Rx32 = $Rx32in";
9716 def L2_loadrub_pcr : HInst<
9717 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9718 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9719 "$Rd32 = memub($Rx32++I:circ($Mu2))",
9720 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9721 let Inst{12-5} = 0b00010000;
9722 let Inst{31-21} = 0b10011001001;
9723 let hasNewValue = 1;
9725 let addrMode = PostInc;
9726 let accessSize = ByteAccess;
9729 let Constraints = "$Rx32 = $Rx32in";
9731 def L2_loadrub_pi : HInst<
9732 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9733 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9734 "$Rd32 = memub($Rx32++#$Ii)",
9735 tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9736 let Inst{13-9} = 0b00000;
9737 let Inst{31-21} = 0b10011011001;
9738 let hasNewValue = 1;
9740 let addrMode = PostInc;
9741 let accessSize = ByteAccess;
9743 let CextOpcode = "L2_loadrub";
9744 let BaseOpcode = "L2_loadrub_pi";
9745 let isPredicable = 1;
9746 let Constraints = "$Rx32 = $Rx32in";
9748 def L2_loadrub_pr : HInst<
9749 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9750 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9751 "$Rd32 = memub($Rx32++$Mu2)",
9752 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9753 let Inst{12-5} = 0b00000000;
9754 let Inst{31-21} = 0b10011101001;
9755 let hasNewValue = 1;
9757 let addrMode = PostInc;
9758 let accessSize = ByteAccess;
9760 let Constraints = "$Rx32 = $Rx32in";
9762 def L2_loadrub_zomap : HInst<
9763 (outs IntRegs:$Rd32),
9764 (ins IntRegs:$Rs32),
9765 "$Rd32 = memub($Rs32)",
9766 tc_7f881c76, TypeMAPPING> {
9767 let hasNewValue = 1;
9770 let isCodeGenOnly = 1;
9772 def L2_loadrubgp : HInst<
9773 (outs IntRegs:$Rd32),
9775 "$Rd32 = memub(gp+#$Ii)",
9776 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9777 let Inst{24-21} = 0b1001;
9778 let Inst{31-27} = 0b01001;
9779 let hasNewValue = 1;
9781 let accessSize = ByteAccess;
9784 let BaseOpcode = "L4_loadrub_abs";
9785 let isPredicable = 1;
9786 let opExtendable = 1;
9787 let isExtentSigned = 0;
9788 let opExtentBits = 16;
9789 let opExtentAlign = 0;
9791 def L2_loadruh_io : HInst<
9792 (outs IntRegs:$Rd32),
9793 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
9794 "$Rd32 = memuh($Rs32+#$Ii)",
9795 tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9796 let Inst{24-21} = 0b1011;
9797 let Inst{31-27} = 0b10010;
9798 let hasNewValue = 1;
9800 let addrMode = BaseImmOffset;
9801 let accessSize = HalfWordAccess;
9803 let CextOpcode = "L2_loadruh";
9804 let BaseOpcode = "L2_loadruh_io";
9805 let isPredicable = 1;
9806 let isExtendable = 1;
9807 let opExtendable = 2;
9808 let isExtentSigned = 1;
9809 let opExtentBits = 12;
9810 let opExtentAlign = 1;
9812 def L2_loadruh_pbr : HInst<
9813 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9814 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9815 "$Rd32 = memuh($Rx32++$Mu2:brev)",
9816 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9817 let Inst{12-5} = 0b00000000;
9818 let Inst{31-21} = 0b10011111011;
9819 let hasNewValue = 1;
9821 let accessSize = HalfWordAccess;
9823 let Constraints = "$Rx32 = $Rx32in";
9825 def L2_loadruh_pci : HInst<
9826 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9827 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9828 "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
9829 tc_4403ca65, TypeLD>, Enc_e83554 {
9830 let Inst{12-9} = 0b0000;
9831 let Inst{31-21} = 0b10011001011;
9832 let hasNewValue = 1;
9834 let addrMode = PostInc;
9835 let accessSize = HalfWordAccess;
9838 let Constraints = "$Rx32 = $Rx32in";
9840 def L2_loadruh_pcr : HInst<
9841 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9842 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9843 "$Rd32 = memuh($Rx32++I:circ($Mu2))",
9844 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9845 let Inst{12-5} = 0b00010000;
9846 let Inst{31-21} = 0b10011001011;
9847 let hasNewValue = 1;
9849 let addrMode = PostInc;
9850 let accessSize = HalfWordAccess;
9853 let Constraints = "$Rx32 = $Rx32in";
9855 def L2_loadruh_pi : HInst<
9856 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9857 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9858 "$Rd32 = memuh($Rx32++#$Ii)",
9859 tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9860 let Inst{13-9} = 0b00000;
9861 let Inst{31-21} = 0b10011011011;
9862 let hasNewValue = 1;
9864 let addrMode = PostInc;
9865 let accessSize = HalfWordAccess;
9867 let CextOpcode = "L2_loadruh";
9868 let BaseOpcode = "L2_loadruh_pi";
9869 let isPredicable = 1;
9870 let Constraints = "$Rx32 = $Rx32in";
9872 def L2_loadruh_pr : HInst<
9873 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9874 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
9875 "$Rd32 = memuh($Rx32++$Mu2)",
9876 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
9877 let Inst{12-5} = 0b00000000;
9878 let Inst{31-21} = 0b10011101011;
9879 let hasNewValue = 1;
9881 let addrMode = PostInc;
9882 let accessSize = HalfWordAccess;
9884 let Constraints = "$Rx32 = $Rx32in";
9886 def L2_loadruh_zomap : HInst<
9887 (outs IntRegs:$Rd32),
9888 (ins IntRegs:$Rs32),
9889 "$Rd32 = memuh($Rs32)",
9890 tc_7f881c76, TypeMAPPING> {
9891 let hasNewValue = 1;
9894 let isCodeGenOnly = 1;
9896 def L2_loadruhgp : HInst<
9897 (outs IntRegs:$Rd32),
9899 "$Rd32 = memuh(gp+#$Ii)",
9900 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9901 let Inst{24-21} = 0b1011;
9902 let Inst{31-27} = 0b01001;
9903 let hasNewValue = 1;
9905 let accessSize = HalfWordAccess;
9908 let BaseOpcode = "L4_loadruh_abs";
9909 let isPredicable = 1;
9910 let opExtendable = 1;
9911 let isExtentSigned = 0;
9912 let opExtentBits = 17;
9913 let opExtentAlign = 1;
9915 def L2_loadw_locked : HInst<
9916 (outs IntRegs:$Rd32),
9917 (ins IntRegs:$Rs32),
9918 "$Rd32 = memw_locked($Rs32)",
9919 tc_6aa5711a, TypeLD>, Enc_5e2823 {
9920 let Inst{13-5} = 0b000000000;
9921 let Inst{31-21} = 0b10010010000;
9922 let hasNewValue = 1;
9924 let accessSize = WordAccess;
9928 def L2_ploadrbf_io : HInst<
9929 (outs IntRegs:$Rd32),
9930 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
9931 "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
9932 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
9933 let Inst{13-13} = 0b0;
9934 let Inst{31-21} = 0b01000101000;
9935 let isPredicated = 1;
9936 let isPredicatedFalse = 1;
9937 let hasNewValue = 1;
9939 let addrMode = BaseImmOffset;
9940 let accessSize = ByteAccess;
9942 let CextOpcode = "L2_loadrb";
9943 let BaseOpcode = "L2_loadrb_io";
9944 let isExtendable = 1;
9945 let opExtendable = 3;
9946 let isExtentSigned = 0;
9947 let opExtentBits = 6;
9948 let opExtentAlign = 0;
9950 def L2_ploadrbf_pi : HInst<
9951 (outs IntRegs:$Rd32, IntRegs:$Rx32),
9952 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
9953 "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
9954 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
9955 let Inst{13-11} = 0b101;
9956 let Inst{31-21} = 0b10011011000;
9957 let isPredicated = 1;
9958 let isPredicatedFalse = 1;
9959 let hasNewValue = 1;
9961 let addrMode = PostInc;
9962 let accessSize = ByteAccess;
9964 let BaseOpcode = "L2_loadrb_pi";
9965 let Constraints = "$Rx32 = $Rx32in";
9967 def L2_ploadrbf_zomap : HInst<
9968 (outs IntRegs:$Rd32),
9969 (ins PredRegs:$Pt4, IntRegs:$Rs32),
9970 "if (!$Pt4) $Rd32 = memb($Rs32)",
9971 tc_ef52ed71, TypeMAPPING> {
9972 let hasNewValue = 1;
9975 let isCodeGenOnly = 1;
9977 def L2_ploadrbfnew_io : HInst<
9978 (outs IntRegs:$Rd32),
9979 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
9980 "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
9981 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
9982 let Inst{13-13} = 0b0;
9983 let Inst{31-21} = 0b01000111000;
9984 let isPredicated = 1;
9985 let isPredicatedFalse = 1;
9986 let hasNewValue = 1;
9988 let addrMode = BaseImmOffset;
9989 let accessSize = ByteAccess;
9990 let isPredicatedNew = 1;
9992 let CextOpcode = "L2_loadrb";
9993 let BaseOpcode = "L2_loadrb_io";
9994 let isExtendable = 1;
9995 let opExtendable = 3;
9996 let isExtentSigned = 0;
9997 let opExtentBits = 6;
9998 let opExtentAlign = 0;
10000 def L2_ploadrbfnew_pi : HInst<
10001 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10002 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10003 "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10004 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
10005 let Inst{13-11} = 0b111;
10006 let Inst{31-21} = 0b10011011000;
10007 let isPredicated = 1;
10008 let isPredicatedFalse = 1;
10009 let hasNewValue = 1;
10010 let opNewValue = 0;
10011 let addrMode = PostInc;
10012 let accessSize = ByteAccess;
10013 let isPredicatedNew = 1;
10015 let BaseOpcode = "L2_loadrb_pi";
10016 let Constraints = "$Rx32 = $Rx32in";
10018 def L2_ploadrbfnew_zomap : HInst<
10019 (outs IntRegs:$Rd32),
10020 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10021 "if (!$Pt4.new) $Rd32 = memb($Rs32)",
10022 tc_2fc0c436, TypeMAPPING> {
10023 let hasNewValue = 1;
10024 let opNewValue = 0;
10026 let isCodeGenOnly = 1;
10028 def L2_ploadrbt_io : HInst<
10029 (outs IntRegs:$Rd32),
10030 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10031 "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10032 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10033 let Inst{13-13} = 0b0;
10034 let Inst{31-21} = 0b01000001000;
10035 let isPredicated = 1;
10036 let hasNewValue = 1;
10037 let opNewValue = 0;
10038 let addrMode = BaseImmOffset;
10039 let accessSize = ByteAccess;
10041 let CextOpcode = "L2_loadrb";
10042 let BaseOpcode = "L2_loadrb_io";
10043 let isExtendable = 1;
10044 let opExtendable = 3;
10045 let isExtentSigned = 0;
10046 let opExtentBits = 6;
10047 let opExtentAlign = 0;
10049 def L2_ploadrbt_pi : HInst<
10050 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10051 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10052 "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10053 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
10054 let Inst{13-11} = 0b100;
10055 let Inst{31-21} = 0b10011011000;
10056 let isPredicated = 1;
10057 let hasNewValue = 1;
10058 let opNewValue = 0;
10059 let addrMode = PostInc;
10060 let accessSize = ByteAccess;
10062 let BaseOpcode = "L2_loadrb_pi";
10063 let Constraints = "$Rx32 = $Rx32in";
10065 def L2_ploadrbt_zomap : HInst<
10066 (outs IntRegs:$Rd32),
10067 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10068 "if ($Pt4) $Rd32 = memb($Rs32)",
10069 tc_ef52ed71, TypeMAPPING> {
10070 let hasNewValue = 1;
10071 let opNewValue = 0;
10073 let isCodeGenOnly = 1;
10075 def L2_ploadrbtnew_io : HInst<
10076 (outs IntRegs:$Rd32),
10077 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10078 "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10079 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10080 let Inst{13-13} = 0b0;
10081 let Inst{31-21} = 0b01000011000;
10082 let isPredicated = 1;
10083 let hasNewValue = 1;
10084 let opNewValue = 0;
10085 let addrMode = BaseImmOffset;
10086 let accessSize = ByteAccess;
10087 let isPredicatedNew = 1;
10089 let CextOpcode = "L2_loadrb";
10090 let BaseOpcode = "L2_loadrb_io";
10091 let isExtendable = 1;
10092 let opExtendable = 3;
10093 let isExtentSigned = 0;
10094 let opExtentBits = 6;
10095 let opExtentAlign = 0;
10097 def L2_ploadrbtnew_pi : HInst<
10098 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10099 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10100 "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10101 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
10102 let Inst{13-11} = 0b110;
10103 let Inst{31-21} = 0b10011011000;
10104 let isPredicated = 1;
10105 let hasNewValue = 1;
10106 let opNewValue = 0;
10107 let addrMode = PostInc;
10108 let accessSize = ByteAccess;
10109 let isPredicatedNew = 1;
10111 let BaseOpcode = "L2_loadrb_pi";
10112 let Constraints = "$Rx32 = $Rx32in";
10114 def L2_ploadrbtnew_zomap : HInst<
10115 (outs IntRegs:$Rd32),
10116 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10117 "if ($Pt4.new) $Rd32 = memb($Rs32)",
10118 tc_2fc0c436, TypeMAPPING> {
10119 let hasNewValue = 1;
10120 let opNewValue = 0;
10122 let isCodeGenOnly = 1;
10124 def L2_ploadrdf_io : HInst<
10125 (outs DoubleRegs:$Rdd32),
10126 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10127 "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10128 tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10129 let Inst{13-13} = 0b0;
10130 let Inst{31-21} = 0b01000101110;
10131 let isPredicated = 1;
10132 let isPredicatedFalse = 1;
10133 let addrMode = BaseImmOffset;
10134 let accessSize = DoubleWordAccess;
10136 let CextOpcode = "L2_loadrd";
10137 let BaseOpcode = "L2_loadrd_io";
10138 let isExtendable = 1;
10139 let opExtendable = 3;
10140 let isExtentSigned = 0;
10141 let opExtentBits = 9;
10142 let opExtentAlign = 3;
10144 def L2_ploadrdf_pi : HInst<
10145 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10146 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10147 "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10148 tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
10149 let Inst{13-11} = 0b101;
10150 let Inst{31-21} = 0b10011011110;
10151 let isPredicated = 1;
10152 let isPredicatedFalse = 1;
10153 let addrMode = PostInc;
10154 let accessSize = DoubleWordAccess;
10156 let BaseOpcode = "L2_loadrd_pi";
10157 let Constraints = "$Rx32 = $Rx32in";
10159 def L2_ploadrdf_zomap : HInst<
10160 (outs DoubleRegs:$Rdd32),
10161 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10162 "if (!$Pt4) $Rdd32 = memd($Rs32)",
10163 tc_ef52ed71, TypeMAPPING> {
10165 let isCodeGenOnly = 1;
10167 def L2_ploadrdfnew_io : HInst<
10168 (outs DoubleRegs:$Rdd32),
10169 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10170 "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10171 tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10172 let Inst{13-13} = 0b0;
10173 let Inst{31-21} = 0b01000111110;
10174 let isPredicated = 1;
10175 let isPredicatedFalse = 1;
10176 let addrMode = BaseImmOffset;
10177 let accessSize = DoubleWordAccess;
10178 let isPredicatedNew = 1;
10180 let CextOpcode = "L2_loadrd";
10181 let BaseOpcode = "L2_loadrd_io";
10182 let isExtendable = 1;
10183 let opExtendable = 3;
10184 let isExtentSigned = 0;
10185 let opExtentBits = 9;
10186 let opExtentAlign = 3;
10188 def L2_ploadrdfnew_pi : HInst<
10189 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10190 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10191 "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10192 tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
10193 let Inst{13-11} = 0b111;
10194 let Inst{31-21} = 0b10011011110;
10195 let isPredicated = 1;
10196 let isPredicatedFalse = 1;
10197 let addrMode = PostInc;
10198 let accessSize = DoubleWordAccess;
10199 let isPredicatedNew = 1;
10201 let BaseOpcode = "L2_loadrd_pi";
10202 let Constraints = "$Rx32 = $Rx32in";
10204 def L2_ploadrdfnew_zomap : HInst<
10205 (outs DoubleRegs:$Rdd32),
10206 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10207 "if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10208 tc_2fc0c436, TypeMAPPING> {
10210 let isCodeGenOnly = 1;
10212 def L2_ploadrdt_io : HInst<
10213 (outs DoubleRegs:$Rdd32),
10214 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10215 "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10216 tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10217 let Inst{13-13} = 0b0;
10218 let Inst{31-21} = 0b01000001110;
10219 let isPredicated = 1;
10220 let addrMode = BaseImmOffset;
10221 let accessSize = DoubleWordAccess;
10223 let CextOpcode = "L2_loadrd";
10224 let BaseOpcode = "L2_loadrd_io";
10225 let isExtendable = 1;
10226 let opExtendable = 3;
10227 let isExtentSigned = 0;
10228 let opExtentBits = 9;
10229 let opExtentAlign = 3;
10231 def L2_ploadrdt_pi : HInst<
10232 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10233 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10234 "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10235 tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
10236 let Inst{13-11} = 0b100;
10237 let Inst{31-21} = 0b10011011110;
10238 let isPredicated = 1;
10239 let addrMode = PostInc;
10240 let accessSize = DoubleWordAccess;
10242 let BaseOpcode = "L2_loadrd_pi";
10243 let Constraints = "$Rx32 = $Rx32in";
10245 def L2_ploadrdt_zomap : HInst<
10246 (outs DoubleRegs:$Rdd32),
10247 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10248 "if ($Pt4) $Rdd32 = memd($Rs32)",
10249 tc_ef52ed71, TypeMAPPING> {
10251 let isCodeGenOnly = 1;
10253 def L2_ploadrdtnew_io : HInst<
10254 (outs DoubleRegs:$Rdd32),
10255 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10256 "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10257 tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10258 let Inst{13-13} = 0b0;
10259 let Inst{31-21} = 0b01000011110;
10260 let isPredicated = 1;
10261 let addrMode = BaseImmOffset;
10262 let accessSize = DoubleWordAccess;
10263 let isPredicatedNew = 1;
10265 let CextOpcode = "L2_loadrd";
10266 let BaseOpcode = "L2_loadrd_io";
10267 let isExtendable = 1;
10268 let opExtendable = 3;
10269 let isExtentSigned = 0;
10270 let opExtentBits = 9;
10271 let opExtentAlign = 3;
10273 def L2_ploadrdtnew_pi : HInst<
10274 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10275 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10276 "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10277 tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
10278 let Inst{13-11} = 0b110;
10279 let Inst{31-21} = 0b10011011110;
10280 let isPredicated = 1;
10281 let addrMode = PostInc;
10282 let accessSize = DoubleWordAccess;
10283 let isPredicatedNew = 1;
10285 let BaseOpcode = "L2_loadrd_pi";
10286 let Constraints = "$Rx32 = $Rx32in";
10288 def L2_ploadrdtnew_zomap : HInst<
10289 (outs DoubleRegs:$Rdd32),
10290 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10291 "if ($Pt4.new) $Rdd32 = memd($Rs32)",
10292 tc_2fc0c436, TypeMAPPING> {
10294 let isCodeGenOnly = 1;
10296 def L2_ploadrhf_io : HInst<
10297 (outs IntRegs:$Rd32),
10298 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10299 "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10300 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10301 let Inst{13-13} = 0b0;
10302 let Inst{31-21} = 0b01000101010;
10303 let isPredicated = 1;
10304 let isPredicatedFalse = 1;
10305 let hasNewValue = 1;
10306 let opNewValue = 0;
10307 let addrMode = BaseImmOffset;
10308 let accessSize = HalfWordAccess;
10310 let CextOpcode = "L2_loadrh";
10311 let BaseOpcode = "L2_loadrh_io";
10312 let isExtendable = 1;
10313 let opExtendable = 3;
10314 let isExtentSigned = 0;
10315 let opExtentBits = 7;
10316 let opExtentAlign = 1;
10318 def L2_ploadrhf_pi : HInst<
10319 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10320 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10321 "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10322 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
10323 let Inst{13-11} = 0b101;
10324 let Inst{31-21} = 0b10011011010;
10325 let isPredicated = 1;
10326 let isPredicatedFalse = 1;
10327 let hasNewValue = 1;
10328 let opNewValue = 0;
10329 let addrMode = PostInc;
10330 let accessSize = HalfWordAccess;
10332 let BaseOpcode = "L2_loadrh_pi";
10333 let Constraints = "$Rx32 = $Rx32in";
10335 def L2_ploadrhf_zomap : HInst<
10336 (outs IntRegs:$Rd32),
10337 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10338 "if (!$Pt4) $Rd32 = memh($Rs32)",
10339 tc_ef52ed71, TypeMAPPING> {
10340 let hasNewValue = 1;
10341 let opNewValue = 0;
10343 let isCodeGenOnly = 1;
10345 def L2_ploadrhfnew_io : HInst<
10346 (outs IntRegs:$Rd32),
10347 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10348 "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10349 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10350 let Inst{13-13} = 0b0;
10351 let Inst{31-21} = 0b01000111010;
10352 let isPredicated = 1;
10353 let isPredicatedFalse = 1;
10354 let hasNewValue = 1;
10355 let opNewValue = 0;
10356 let addrMode = BaseImmOffset;
10357 let accessSize = HalfWordAccess;
10358 let isPredicatedNew = 1;
10360 let CextOpcode = "L2_loadrh";
10361 let BaseOpcode = "L2_loadrh_io";
10362 let isExtendable = 1;
10363 let opExtendable = 3;
10364 let isExtentSigned = 0;
10365 let opExtentBits = 7;
10366 let opExtentAlign = 1;
10368 def L2_ploadrhfnew_pi : HInst<
10369 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10370 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10371 "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10372 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
10373 let Inst{13-11} = 0b111;
10374 let Inst{31-21} = 0b10011011010;
10375 let isPredicated = 1;
10376 let isPredicatedFalse = 1;
10377 let hasNewValue = 1;
10378 let opNewValue = 0;
10379 let addrMode = PostInc;
10380 let accessSize = HalfWordAccess;
10381 let isPredicatedNew = 1;
10383 let BaseOpcode = "L2_loadrh_pi";
10384 let Constraints = "$Rx32 = $Rx32in";
10386 def L2_ploadrhfnew_zomap : HInst<
10387 (outs IntRegs:$Rd32),
10388 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10389 "if (!$Pt4.new) $Rd32 = memh($Rs32)",
10390 tc_2fc0c436, TypeMAPPING> {
10391 let hasNewValue = 1;
10392 let opNewValue = 0;
10394 let isCodeGenOnly = 1;
10396 def L2_ploadrht_io : HInst<
10397 (outs IntRegs:$Rd32),
10398 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10399 "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10400 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10401 let Inst{13-13} = 0b0;
10402 let Inst{31-21} = 0b01000001010;
10403 let isPredicated = 1;
10404 let hasNewValue = 1;
10405 let opNewValue = 0;
10406 let addrMode = BaseImmOffset;
10407 let accessSize = HalfWordAccess;
10409 let CextOpcode = "L2_loadrh";
10410 let BaseOpcode = "L2_loadrh_io";
10411 let isExtendable = 1;
10412 let opExtendable = 3;
10413 let isExtentSigned = 0;
10414 let opExtentBits = 7;
10415 let opExtentAlign = 1;
10417 def L2_ploadrht_pi : HInst<
10418 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10419 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10420 "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10421 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
10422 let Inst{13-11} = 0b100;
10423 let Inst{31-21} = 0b10011011010;
10424 let isPredicated = 1;
10425 let hasNewValue = 1;
10426 let opNewValue = 0;
10427 let addrMode = PostInc;
10428 let accessSize = HalfWordAccess;
10430 let BaseOpcode = "L2_loadrh_pi";
10431 let Constraints = "$Rx32 = $Rx32in";
10433 def L2_ploadrht_zomap : HInst<
10434 (outs IntRegs:$Rd32),
10435 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10436 "if ($Pt4) $Rd32 = memh($Rs32)",
10437 tc_ef52ed71, TypeMAPPING> {
10438 let hasNewValue = 1;
10439 let opNewValue = 0;
10441 let isCodeGenOnly = 1;
10443 def L2_ploadrhtnew_io : HInst<
10444 (outs IntRegs:$Rd32),
10445 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10446 "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10447 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10448 let Inst{13-13} = 0b0;
10449 let Inst{31-21} = 0b01000011010;
10450 let isPredicated = 1;
10451 let hasNewValue = 1;
10452 let opNewValue = 0;
10453 let addrMode = BaseImmOffset;
10454 let accessSize = HalfWordAccess;
10455 let isPredicatedNew = 1;
10457 let CextOpcode = "L2_loadrh";
10458 let BaseOpcode = "L2_loadrh_io";
10459 let isExtendable = 1;
10460 let opExtendable = 3;
10461 let isExtentSigned = 0;
10462 let opExtentBits = 7;
10463 let opExtentAlign = 1;
10465 def L2_ploadrhtnew_pi : HInst<
10466 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10467 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10468 "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10469 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
10470 let Inst{13-11} = 0b110;
10471 let Inst{31-21} = 0b10011011010;
10472 let isPredicated = 1;
10473 let hasNewValue = 1;
10474 let opNewValue = 0;
10475 let addrMode = PostInc;
10476 let accessSize = HalfWordAccess;
10477 let isPredicatedNew = 1;
10479 let BaseOpcode = "L2_loadrh_pi";
10480 let Constraints = "$Rx32 = $Rx32in";
10482 def L2_ploadrhtnew_zomap : HInst<
10483 (outs IntRegs:$Rd32),
10484 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10485 "if ($Pt4.new) $Rd32 = memh($Rs32)",
10486 tc_2fc0c436, TypeMAPPING> {
10487 let hasNewValue = 1;
10488 let opNewValue = 0;
10490 let isCodeGenOnly = 1;
10492 def L2_ploadrif_io : HInst<
10493 (outs IntRegs:$Rd32),
10494 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10495 "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10496 tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10497 let Inst{13-13} = 0b0;
10498 let Inst{31-21} = 0b01000101100;
10499 let isPredicated = 1;
10500 let isPredicatedFalse = 1;
10501 let hasNewValue = 1;
10502 let opNewValue = 0;
10503 let addrMode = BaseImmOffset;
10504 let accessSize = WordAccess;
10506 let CextOpcode = "L2_loadri";
10507 let BaseOpcode = "L2_loadri_io";
10508 let isExtendable = 1;
10509 let opExtendable = 3;
10510 let isExtentSigned = 0;
10511 let opExtentBits = 8;
10512 let opExtentAlign = 2;
10514 def L2_ploadrif_pi : HInst<
10515 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10516 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10517 "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10518 tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
10519 let Inst{13-11} = 0b101;
10520 let Inst{31-21} = 0b10011011100;
10521 let isPredicated = 1;
10522 let isPredicatedFalse = 1;
10523 let hasNewValue = 1;
10524 let opNewValue = 0;
10525 let addrMode = PostInc;
10526 let accessSize = WordAccess;
10528 let BaseOpcode = "L2_loadri_pi";
10529 let Constraints = "$Rx32 = $Rx32in";
10531 def L2_ploadrif_zomap : HInst<
10532 (outs IntRegs:$Rd32),
10533 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10534 "if (!$Pt4) $Rd32 = memw($Rs32)",
10535 tc_ef52ed71, TypeMAPPING> {
10536 let hasNewValue = 1;
10537 let opNewValue = 0;
10539 let isCodeGenOnly = 1;
10541 def L2_ploadrifnew_io : HInst<
10542 (outs IntRegs:$Rd32),
10543 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10544 "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10545 tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10546 let Inst{13-13} = 0b0;
10547 let Inst{31-21} = 0b01000111100;
10548 let isPredicated = 1;
10549 let isPredicatedFalse = 1;
10550 let hasNewValue = 1;
10551 let opNewValue = 0;
10552 let addrMode = BaseImmOffset;
10553 let accessSize = WordAccess;
10554 let isPredicatedNew = 1;
10556 let CextOpcode = "L2_loadri";
10557 let BaseOpcode = "L2_loadri_io";
10558 let isExtendable = 1;
10559 let opExtendable = 3;
10560 let isExtentSigned = 0;
10561 let opExtentBits = 8;
10562 let opExtentAlign = 2;
10564 def L2_ploadrifnew_pi : HInst<
10565 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10566 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10567 "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10568 tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
10569 let Inst{13-11} = 0b111;
10570 let Inst{31-21} = 0b10011011100;
10571 let isPredicated = 1;
10572 let isPredicatedFalse = 1;
10573 let hasNewValue = 1;
10574 let opNewValue = 0;
10575 let addrMode = PostInc;
10576 let accessSize = WordAccess;
10577 let isPredicatedNew = 1;
10579 let BaseOpcode = "L2_loadri_pi";
10580 let Constraints = "$Rx32 = $Rx32in";
10582 def L2_ploadrifnew_zomap : HInst<
10583 (outs IntRegs:$Rd32),
10584 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10585 "if (!$Pt4.new) $Rd32 = memw($Rs32)",
10586 tc_2fc0c436, TypeMAPPING> {
10587 let hasNewValue = 1;
10588 let opNewValue = 0;
10590 let isCodeGenOnly = 1;
10592 def L2_ploadrit_io : HInst<
10593 (outs IntRegs:$Rd32),
10594 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10595 "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10596 tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10597 let Inst{13-13} = 0b0;
10598 let Inst{31-21} = 0b01000001100;
10599 let isPredicated = 1;
10600 let hasNewValue = 1;
10601 let opNewValue = 0;
10602 let addrMode = BaseImmOffset;
10603 let accessSize = WordAccess;
10605 let CextOpcode = "L2_loadri";
10606 let BaseOpcode = "L2_loadri_io";
10607 let isExtendable = 1;
10608 let opExtendable = 3;
10609 let isExtentSigned = 0;
10610 let opExtentBits = 8;
10611 let opExtentAlign = 2;
10613 def L2_ploadrit_pi : HInst<
10614 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10615 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10616 "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10617 tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
10618 let Inst{13-11} = 0b100;
10619 let Inst{31-21} = 0b10011011100;
10620 let isPredicated = 1;
10621 let hasNewValue = 1;
10622 let opNewValue = 0;
10623 let addrMode = PostInc;
10624 let accessSize = WordAccess;
10626 let BaseOpcode = "L2_loadri_pi";
10627 let Constraints = "$Rx32 = $Rx32in";
10629 def L2_ploadrit_zomap : HInst<
10630 (outs IntRegs:$Rd32),
10631 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10632 "if ($Pt4) $Rd32 = memw($Rs32)",
10633 tc_ef52ed71, TypeMAPPING> {
10634 let hasNewValue = 1;
10635 let opNewValue = 0;
10637 let isCodeGenOnly = 1;
10639 def L2_ploadritnew_io : HInst<
10640 (outs IntRegs:$Rd32),
10641 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10642 "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10643 tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10644 let Inst{13-13} = 0b0;
10645 let Inst{31-21} = 0b01000011100;
10646 let isPredicated = 1;
10647 let hasNewValue = 1;
10648 let opNewValue = 0;
10649 let addrMode = BaseImmOffset;
10650 let accessSize = WordAccess;
10651 let isPredicatedNew = 1;
10653 let CextOpcode = "L2_loadri";
10654 let BaseOpcode = "L2_loadri_io";
10655 let isExtendable = 1;
10656 let opExtendable = 3;
10657 let isExtentSigned = 0;
10658 let opExtentBits = 8;
10659 let opExtentAlign = 2;
10661 def L2_ploadritnew_pi : HInst<
10662 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10663 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10664 "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10665 tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
10666 let Inst{13-11} = 0b110;
10667 let Inst{31-21} = 0b10011011100;
10668 let isPredicated = 1;
10669 let hasNewValue = 1;
10670 let opNewValue = 0;
10671 let addrMode = PostInc;
10672 let accessSize = WordAccess;
10673 let isPredicatedNew = 1;
10675 let BaseOpcode = "L2_loadri_pi";
10676 let Constraints = "$Rx32 = $Rx32in";
10678 def L2_ploadritnew_zomap : HInst<
10679 (outs IntRegs:$Rd32),
10680 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10681 "if ($Pt4.new) $Rd32 = memw($Rs32)",
10682 tc_2fc0c436, TypeMAPPING> {
10683 let hasNewValue = 1;
10684 let opNewValue = 0;
10686 let isCodeGenOnly = 1;
10688 def L2_ploadrubf_io : HInst<
10689 (outs IntRegs:$Rd32),
10690 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10691 "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10692 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10693 let Inst{13-13} = 0b0;
10694 let Inst{31-21} = 0b01000101001;
10695 let isPredicated = 1;
10696 let isPredicatedFalse = 1;
10697 let hasNewValue = 1;
10698 let opNewValue = 0;
10699 let addrMode = BaseImmOffset;
10700 let accessSize = ByteAccess;
10702 let CextOpcode = "L2_loadrub";
10703 let BaseOpcode = "L2_loadrub_io";
10704 let isExtendable = 1;
10705 let opExtendable = 3;
10706 let isExtentSigned = 0;
10707 let opExtentBits = 6;
10708 let opExtentAlign = 0;
10710 def L2_ploadrubf_pi : HInst<
10711 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10712 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10713 "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10714 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
10715 let Inst{13-11} = 0b101;
10716 let Inst{31-21} = 0b10011011001;
10717 let isPredicated = 1;
10718 let isPredicatedFalse = 1;
10719 let hasNewValue = 1;
10720 let opNewValue = 0;
10721 let addrMode = PostInc;
10722 let accessSize = ByteAccess;
10724 let BaseOpcode = "L2_loadrub_pi";
10725 let Constraints = "$Rx32 = $Rx32in";
10727 def L2_ploadrubf_zomap : HInst<
10728 (outs IntRegs:$Rd32),
10729 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10730 "if (!$Pt4) $Rd32 = memub($Rs32)",
10731 tc_ef52ed71, TypeMAPPING> {
10732 let hasNewValue = 1;
10733 let opNewValue = 0;
10735 let isCodeGenOnly = 1;
10737 def L2_ploadrubfnew_io : HInst<
10738 (outs IntRegs:$Rd32),
10739 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10740 "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10741 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10742 let Inst{13-13} = 0b0;
10743 let Inst{31-21} = 0b01000111001;
10744 let isPredicated = 1;
10745 let isPredicatedFalse = 1;
10746 let hasNewValue = 1;
10747 let opNewValue = 0;
10748 let addrMode = BaseImmOffset;
10749 let accessSize = ByteAccess;
10750 let isPredicatedNew = 1;
10752 let CextOpcode = "L2_loadrub";
10753 let BaseOpcode = "L2_loadrub_io";
10754 let isExtendable = 1;
10755 let opExtendable = 3;
10756 let isExtentSigned = 0;
10757 let opExtentBits = 6;
10758 let opExtentAlign = 0;
10760 def L2_ploadrubfnew_pi : HInst<
10761 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10762 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10763 "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10764 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
10765 let Inst{13-11} = 0b111;
10766 let Inst{31-21} = 0b10011011001;
10767 let isPredicated = 1;
10768 let isPredicatedFalse = 1;
10769 let hasNewValue = 1;
10770 let opNewValue = 0;
10771 let addrMode = PostInc;
10772 let accessSize = ByteAccess;
10773 let isPredicatedNew = 1;
10775 let BaseOpcode = "L2_loadrub_pi";
10776 let Constraints = "$Rx32 = $Rx32in";
10778 def L2_ploadrubfnew_zomap : HInst<
10779 (outs IntRegs:$Rd32),
10780 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10781 "if (!$Pt4.new) $Rd32 = memub($Rs32)",
10782 tc_2fc0c436, TypeMAPPING> {
10783 let hasNewValue = 1;
10784 let opNewValue = 0;
10786 let isCodeGenOnly = 1;
10788 def L2_ploadrubt_io : HInst<
10789 (outs IntRegs:$Rd32),
10790 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10791 "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
10792 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10793 let Inst{13-13} = 0b0;
10794 let Inst{31-21} = 0b01000001001;
10795 let isPredicated = 1;
10796 let hasNewValue = 1;
10797 let opNewValue = 0;
10798 let addrMode = BaseImmOffset;
10799 let accessSize = ByteAccess;
10801 let CextOpcode = "L2_loadrub";
10802 let BaseOpcode = "L2_loadrub_io";
10803 let isExtendable = 1;
10804 let opExtendable = 3;
10805 let isExtentSigned = 0;
10806 let opExtentBits = 6;
10807 let opExtentAlign = 0;
10809 def L2_ploadrubt_pi : HInst<
10810 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10811 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10812 "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
10813 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
10814 let Inst{13-11} = 0b100;
10815 let Inst{31-21} = 0b10011011001;
10816 let isPredicated = 1;
10817 let hasNewValue = 1;
10818 let opNewValue = 0;
10819 let addrMode = PostInc;
10820 let accessSize = ByteAccess;
10822 let BaseOpcode = "L2_loadrub_pi";
10823 let Constraints = "$Rx32 = $Rx32in";
10825 def L2_ploadrubt_zomap : HInst<
10826 (outs IntRegs:$Rd32),
10827 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10828 "if ($Pt4) $Rd32 = memub($Rs32)",
10829 tc_ef52ed71, TypeMAPPING> {
10830 let hasNewValue = 1;
10831 let opNewValue = 0;
10833 let isCodeGenOnly = 1;
10835 def L2_ploadrubtnew_io : HInst<
10836 (outs IntRegs:$Rd32),
10837 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10838 "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10839 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10840 let Inst{13-13} = 0b0;
10841 let Inst{31-21} = 0b01000011001;
10842 let isPredicated = 1;
10843 let hasNewValue = 1;
10844 let opNewValue = 0;
10845 let addrMode = BaseImmOffset;
10846 let accessSize = ByteAccess;
10847 let isPredicatedNew = 1;
10849 let CextOpcode = "L2_loadrub";
10850 let BaseOpcode = "L2_loadrub_io";
10851 let isExtendable = 1;
10852 let opExtendable = 3;
10853 let isExtentSigned = 0;
10854 let opExtentBits = 6;
10855 let opExtentAlign = 0;
10857 def L2_ploadrubtnew_pi : HInst<
10858 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10859 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10860 "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10861 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
10862 let Inst{13-11} = 0b110;
10863 let Inst{31-21} = 0b10011011001;
10864 let isPredicated = 1;
10865 let hasNewValue = 1;
10866 let opNewValue = 0;
10867 let addrMode = PostInc;
10868 let accessSize = ByteAccess;
10869 let isPredicatedNew = 1;
10871 let BaseOpcode = "L2_loadrub_pi";
10872 let Constraints = "$Rx32 = $Rx32in";
10874 def L2_ploadrubtnew_zomap : HInst<
10875 (outs IntRegs:$Rd32),
10876 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10877 "if ($Pt4.new) $Rd32 = memub($Rs32)",
10878 tc_2fc0c436, TypeMAPPING> {
10879 let hasNewValue = 1;
10880 let opNewValue = 0;
10882 let isCodeGenOnly = 1;
10884 def L2_ploadruhf_io : HInst<
10885 (outs IntRegs:$Rd32),
10886 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10887 "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
10888 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10889 let Inst{13-13} = 0b0;
10890 let Inst{31-21} = 0b01000101011;
10891 let isPredicated = 1;
10892 let isPredicatedFalse = 1;
10893 let hasNewValue = 1;
10894 let opNewValue = 0;
10895 let addrMode = BaseImmOffset;
10896 let accessSize = HalfWordAccess;
10898 let CextOpcode = "L2_loadruh";
10899 let BaseOpcode = "L2_loadruh_io";
10900 let isExtendable = 1;
10901 let opExtendable = 3;
10902 let isExtentSigned = 0;
10903 let opExtentBits = 7;
10904 let opExtentAlign = 1;
10906 def L2_ploadruhf_pi : HInst<
10907 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10908 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10909 "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
10910 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
10911 let Inst{13-11} = 0b101;
10912 let Inst{31-21} = 0b10011011011;
10913 let isPredicated = 1;
10914 let isPredicatedFalse = 1;
10915 let hasNewValue = 1;
10916 let opNewValue = 0;
10917 let addrMode = PostInc;
10918 let accessSize = HalfWordAccess;
10920 let BaseOpcode = "L2_loadruh_pi";
10921 let Constraints = "$Rx32 = $Rx32in";
10923 def L2_ploadruhf_zomap : HInst<
10924 (outs IntRegs:$Rd32),
10925 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10926 "if (!$Pt4) $Rd32 = memuh($Rs32)",
10927 tc_ef52ed71, TypeMAPPING> {
10928 let hasNewValue = 1;
10929 let opNewValue = 0;
10931 let isCodeGenOnly = 1;
10933 def L2_ploadruhfnew_io : HInst<
10934 (outs IntRegs:$Rd32),
10935 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10936 "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
10937 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10938 let Inst{13-13} = 0b0;
10939 let Inst{31-21} = 0b01000111011;
10940 let isPredicated = 1;
10941 let isPredicatedFalse = 1;
10942 let hasNewValue = 1;
10943 let opNewValue = 0;
10944 let addrMode = BaseImmOffset;
10945 let accessSize = HalfWordAccess;
10946 let isPredicatedNew = 1;
10948 let CextOpcode = "L2_loadruh";
10949 let BaseOpcode = "L2_loadruh_io";
10950 let isExtendable = 1;
10951 let opExtendable = 3;
10952 let isExtentSigned = 0;
10953 let opExtentBits = 7;
10954 let opExtentAlign = 1;
10956 def L2_ploadruhfnew_pi : HInst<
10957 (outs IntRegs:$Rd32, IntRegs:$Rx32),
10958 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10959 "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
10960 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
10961 let Inst{13-11} = 0b111;
10962 let Inst{31-21} = 0b10011011011;
10963 let isPredicated = 1;
10964 let isPredicatedFalse = 1;
10965 let hasNewValue = 1;
10966 let opNewValue = 0;
10967 let addrMode = PostInc;
10968 let accessSize = HalfWordAccess;
10969 let isPredicatedNew = 1;
10971 let BaseOpcode = "L2_loadruh_pi";
10972 let Constraints = "$Rx32 = $Rx32in";
10974 def L2_ploadruhfnew_zomap : HInst<
10975 (outs IntRegs:$Rd32),
10976 (ins PredRegs:$Pt4, IntRegs:$Rs32),
10977 "if (!$Pt4.new) $Rd32 = memuh($Rs32)",
10978 tc_2fc0c436, TypeMAPPING> {
10979 let hasNewValue = 1;
10980 let opNewValue = 0;
10982 let isCodeGenOnly = 1;
10984 def L2_ploadruht_io : HInst<
10985 (outs IntRegs:$Rd32),
10986 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10987 "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
10988 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10989 let Inst{13-13} = 0b0;
10990 let Inst{31-21} = 0b01000001011;
10991 let isPredicated = 1;
10992 let hasNewValue = 1;
10993 let opNewValue = 0;
10994 let addrMode = BaseImmOffset;
10995 let accessSize = HalfWordAccess;
10997 let CextOpcode = "L2_loadruh";
10998 let BaseOpcode = "L2_loadruh_io";
10999 let isExtendable = 1;
11000 let opExtendable = 3;
11001 let isExtentSigned = 0;
11002 let opExtentBits = 7;
11003 let opExtentAlign = 1;
11005 def L2_ploadruht_pi : HInst<
11006 (outs IntRegs:$Rd32, IntRegs:$Rx32),
11007 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11008 "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11009 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
11010 let Inst{13-11} = 0b100;
11011 let Inst{31-21} = 0b10011011011;
11012 let isPredicated = 1;
11013 let hasNewValue = 1;
11014 let opNewValue = 0;
11015 let addrMode = PostInc;
11016 let accessSize = HalfWordAccess;
11018 let BaseOpcode = "L2_loadruh_pi";
11019 let Constraints = "$Rx32 = $Rx32in";
11021 def L2_ploadruht_zomap : HInst<
11022 (outs IntRegs:$Rd32),
11023 (ins PredRegs:$Pt4, IntRegs:$Rs32),
11024 "if ($Pt4) $Rd32 = memuh($Rs32)",
11025 tc_ef52ed71, TypeMAPPING> {
11026 let hasNewValue = 1;
11027 let opNewValue = 0;
11029 let isCodeGenOnly = 1;
11031 def L2_ploadruhtnew_io : HInst<
11032 (outs IntRegs:$Rd32),
11033 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11034 "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11035 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11036 let Inst{13-13} = 0b0;
11037 let Inst{31-21} = 0b01000011011;
11038 let isPredicated = 1;
11039 let hasNewValue = 1;
11040 let opNewValue = 0;
11041 let addrMode = BaseImmOffset;
11042 let accessSize = HalfWordAccess;
11043 let isPredicatedNew = 1;
11045 let CextOpcode = "L2_loadruh";
11046 let BaseOpcode = "L2_loadruh_io";
11047 let isExtendable = 1;
11048 let opExtendable = 3;
11049 let isExtentSigned = 0;
11050 let opExtentBits = 7;
11051 let opExtentAlign = 1;
11053 def L2_ploadruhtnew_pi : HInst<
11054 (outs IntRegs:$Rd32, IntRegs:$Rx32),
11055 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11056 "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11057 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
11058 let Inst{13-11} = 0b110;
11059 let Inst{31-21} = 0b10011011011;
11060 let isPredicated = 1;
11061 let hasNewValue = 1;
11062 let opNewValue = 0;
11063 let addrMode = PostInc;
11064 let accessSize = HalfWordAccess;
11065 let isPredicatedNew = 1;
11067 let BaseOpcode = "L2_loadruh_pi";
11068 let Constraints = "$Rx32 = $Rx32in";
11070 def L2_ploadruhtnew_zomap : HInst<
11071 (outs IntRegs:$Rd32),
11072 (ins PredRegs:$Pt4, IntRegs:$Rs32),
11073 "if ($Pt4.new) $Rd32 = memuh($Rs32)",
11074 tc_2fc0c436, TypeMAPPING> {
11075 let hasNewValue = 1;
11076 let opNewValue = 0;
11078 let isCodeGenOnly = 1;
11080 def L4_add_memopb_io : HInst<
11082 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11083 "memb($Rs32+#$Ii) += $Rt32",
11084 tc_44126683, TypeV4LDST>, Enc_d44e31 {
11085 let Inst{6-5} = 0b00;
11086 let Inst{13-13} = 0b0;
11087 let Inst{31-21} = 0b00111110000;
11088 let addrMode = BaseImmOffset;
11089 let accessSize = ByteAccess;
11091 let isRestrictNoSlot1Store = 1;
11093 let isExtendable = 1;
11094 let opExtendable = 1;
11095 let isExtentSigned = 0;
11096 let opExtentBits = 6;
11097 let opExtentAlign = 0;
11099 def L4_add_memopb_zomap : HInst<
11101 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11102 "memb($Rs32) += $Rt32",
11103 tc_44126683, TypeMAPPING> {
11105 let isCodeGenOnly = 1;
11107 def L4_add_memoph_io : HInst<
11109 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11110 "memh($Rs32+#$Ii) += $Rt32",
11111 tc_44126683, TypeV4LDST>, Enc_163a3c {
11112 let Inst{6-5} = 0b00;
11113 let Inst{13-13} = 0b0;
11114 let Inst{31-21} = 0b00111110001;
11115 let addrMode = BaseImmOffset;
11116 let accessSize = HalfWordAccess;
11118 let isRestrictNoSlot1Store = 1;
11120 let isExtendable = 1;
11121 let opExtendable = 1;
11122 let isExtentSigned = 0;
11123 let opExtentBits = 7;
11124 let opExtentAlign = 1;
11126 def L4_add_memoph_zomap : HInst<
11128 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11129 "memh($Rs32) += $Rt32",
11130 tc_44126683, TypeMAPPING> {
11132 let isCodeGenOnly = 1;
11134 def L4_add_memopw_io : HInst<
11136 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11137 "memw($Rs32+#$Ii) += $Rt32",
11138 tc_44126683, TypeV4LDST>, Enc_226535 {
11139 let Inst{6-5} = 0b00;
11140 let Inst{13-13} = 0b0;
11141 let Inst{31-21} = 0b00111110010;
11142 let addrMode = BaseImmOffset;
11143 let accessSize = WordAccess;
11145 let isRestrictNoSlot1Store = 1;
11147 let isExtendable = 1;
11148 let opExtendable = 1;
11149 let isExtentSigned = 0;
11150 let opExtentBits = 8;
11151 let opExtentAlign = 2;
11153 def L4_add_memopw_zomap : HInst<
11155 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11156 "memw($Rs32) += $Rt32",
11157 tc_44126683, TypeMAPPING> {
11159 let isCodeGenOnly = 1;
11161 def L4_and_memopb_io : HInst<
11163 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11164 "memb($Rs32+#$Ii) &= $Rt32",
11165 tc_44126683, TypeV4LDST>, Enc_d44e31 {
11166 let Inst{6-5} = 0b10;
11167 let Inst{13-13} = 0b0;
11168 let Inst{31-21} = 0b00111110000;
11169 let addrMode = BaseImmOffset;
11170 let accessSize = ByteAccess;
11172 let isRestrictNoSlot1Store = 1;
11174 let isExtendable = 1;
11175 let opExtendable = 1;
11176 let isExtentSigned = 0;
11177 let opExtentBits = 6;
11178 let opExtentAlign = 0;
11180 def L4_and_memopb_zomap : HInst<
11182 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11183 "memb($Rs32) &= $Rt32",
11184 tc_44126683, TypeMAPPING> {
11186 let isCodeGenOnly = 1;
11188 def L4_and_memoph_io : HInst<
11190 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11191 "memh($Rs32+#$Ii) &= $Rt32",
11192 tc_44126683, TypeV4LDST>, Enc_163a3c {
11193 let Inst{6-5} = 0b10;
11194 let Inst{13-13} = 0b0;
11195 let Inst{31-21} = 0b00111110001;
11196 let addrMode = BaseImmOffset;
11197 let accessSize = HalfWordAccess;
11199 let isRestrictNoSlot1Store = 1;
11201 let isExtendable = 1;
11202 let opExtendable = 1;
11203 let isExtentSigned = 0;
11204 let opExtentBits = 7;
11205 let opExtentAlign = 1;
11207 def L4_and_memoph_zomap : HInst<
11209 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11210 "memh($Rs32) &= $Rt32",
11211 tc_44126683, TypeMAPPING> {
11213 let isCodeGenOnly = 1;
11215 def L4_and_memopw_io : HInst<
11217 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11218 "memw($Rs32+#$Ii) &= $Rt32",
11219 tc_44126683, TypeV4LDST>, Enc_226535 {
11220 let Inst{6-5} = 0b10;
11221 let Inst{13-13} = 0b0;
11222 let Inst{31-21} = 0b00111110010;
11223 let addrMode = BaseImmOffset;
11224 let accessSize = WordAccess;
11226 let isRestrictNoSlot1Store = 1;
11228 let isExtendable = 1;
11229 let opExtendable = 1;
11230 let isExtentSigned = 0;
11231 let opExtentBits = 8;
11232 let opExtentAlign = 2;
11234 def L4_and_memopw_zomap : HInst<
11236 (ins IntRegs:$Rs32, IntRegs:$Rt32),
11237 "memw($Rs32) &= $Rt32",
11238 tc_44126683, TypeMAPPING> {
11240 let isCodeGenOnly = 1;
11242 def L4_iadd_memopb_io : HInst<
11244 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11245 "memb($Rs32+#$Ii) += #$II",
11246 tc_44126683, TypeV4LDST>, Enc_46c951 {
11247 let Inst{6-5} = 0b00;
11248 let Inst{13-13} = 0b0;
11249 let Inst{31-21} = 0b00111111000;
11250 let addrMode = BaseImmOffset;
11251 let accessSize = ByteAccess;
11253 let isRestrictNoSlot1Store = 1;
11255 let isExtendable = 1;
11256 let opExtendable = 1;
11257 let isExtentSigned = 0;
11258 let opExtentBits = 6;
11259 let opExtentAlign = 0;
11261 def L4_iadd_memopb_zomap : HInst<
11263 (ins IntRegs:$Rs32, u5_0Imm:$II),
11264 "memb($Rs32) += #$II",
11265 tc_44126683, TypeMAPPING> {
11267 let isCodeGenOnly = 1;
11269 def L4_iadd_memoph_io : HInst<
11271 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11272 "memh($Rs32+#$Ii) += #$II",
11273 tc_44126683, TypeV4LDST>, Enc_e66a97 {
11274 let Inst{6-5} = 0b00;
11275 let Inst{13-13} = 0b0;
11276 let Inst{31-21} = 0b00111111001;
11277 let addrMode = BaseImmOffset;
11278 let accessSize = HalfWordAccess;
11280 let isRestrictNoSlot1Store = 1;
11282 let isExtendable = 1;
11283 let opExtendable = 1;
11284 let isExtentSigned = 0;
11285 let opExtentBits = 7;
11286 let opExtentAlign = 1;
11288 def L4_iadd_memoph_zomap : HInst<
11290 (ins IntRegs:$Rs32, u5_0Imm:$II),
11291 "memh($Rs32) += #$II",
11292 tc_44126683, TypeMAPPING> {
11294 let isCodeGenOnly = 1;
11296 def L4_iadd_memopw_io : HInst<
11298 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11299 "memw($Rs32+#$Ii) += #$II",
11300 tc_44126683, TypeV4LDST>, Enc_84b2cd {
11301 let Inst{6-5} = 0b00;
11302 let Inst{13-13} = 0b0;
11303 let Inst{31-21} = 0b00111111010;
11304 let addrMode = BaseImmOffset;
11305 let accessSize = WordAccess;
11307 let isRestrictNoSlot1Store = 1;
11309 let isExtendable = 1;
11310 let opExtendable = 1;
11311 let isExtentSigned = 0;
11312 let opExtentBits = 8;
11313 let opExtentAlign = 2;
11315 def L4_iadd_memopw_zomap : HInst<
11317 (ins IntRegs:$Rs32, u5_0Imm:$II),
11318 "memw($Rs32) += #$II",
11319 tc_44126683, TypeMAPPING> {
11321 let isCodeGenOnly = 1;
11323 def L4_iand_memopb_io : HInst<
11325 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11326 "memb($Rs32+#$Ii) = clrbit(#$II)",
11327 tc_44126683, TypeV4LDST>, Enc_46c951 {
11328 let Inst{6-5} = 0b10;
11329 let Inst{13-13} = 0b0;
11330 let Inst{31-21} = 0b00111111000;
11331 let addrMode = BaseImmOffset;
11332 let accessSize = ByteAccess;
11334 let isRestrictNoSlot1Store = 1;
11336 let isExtendable = 1;
11337 let opExtendable = 1;
11338 let isExtentSigned = 0;
11339 let opExtentBits = 6;
11340 let opExtentAlign = 0;
11342 def L4_iand_memopb_zomap : HInst<
11344 (ins IntRegs:$Rs32, u5_0Imm:$II),
11345 "memb($Rs32) = clrbit(#$II)",
11346 tc_44126683, TypeMAPPING> {
11348 let isCodeGenOnly = 1;
11350 def L4_iand_memoph_io : HInst<
11352 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11353 "memh($Rs32+#$Ii) = clrbit(#$II)",
11354 tc_44126683, TypeV4LDST>, Enc_e66a97 {
11355 let Inst{6-5} = 0b10;
11356 let Inst{13-13} = 0b0;
11357 let Inst{31-21} = 0b00111111001;
11358 let addrMode = BaseImmOffset;
11359 let accessSize = HalfWordAccess;
11361 let isRestrictNoSlot1Store = 1;
11363 let isExtendable = 1;
11364 let opExtendable = 1;
11365 let isExtentSigned = 0;
11366 let opExtentBits = 7;
11367 let opExtentAlign = 1;
11369 def L4_iand_memoph_zomap : HInst<
11371 (ins IntRegs:$Rs32, u5_0Imm:$II),
11372 "memh($Rs32) = clrbit(#$II)",
11373 tc_44126683, TypeMAPPING> {
11375 let isCodeGenOnly = 1;
11377 def L4_iand_memopw_io : HInst<
11379 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11380 "memw($Rs32+#$Ii) = clrbit(#$II)",
11381 tc_44126683, TypeV4LDST>, Enc_84b2cd {
11382 let Inst{6-5} = 0b10;
11383 let Inst{13-13} = 0b0;
11384 let Inst{31-21} = 0b00111111010;
11385 let addrMode = BaseImmOffset;
11386 let accessSize = WordAccess;
11388 let isRestrictNoSlot1Store = 1;
11390 let isExtendable = 1;
11391 let opExtendable = 1;
11392 let isExtentSigned = 0;
11393 let opExtentBits = 8;
11394 let opExtentAlign = 2;
11396 def L4_iand_memopw_zomap : HInst<
11398 (ins IntRegs:$Rs32, u5_0Imm:$II),
11399 "memw($Rs32) = clrbit(#$II)",
11400 tc_44126683, TypeMAPPING> {
11402 let isCodeGenOnly = 1;
11404 def L4_ior_memopb_io : HInst<
11406 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11407 "memb($Rs32+#$Ii) = setbit(#$II)",
11408 tc_44126683, TypeV4LDST>, Enc_46c951 {
11409 let Inst{6-5} = 0b11;
11410 let Inst{13-13} = 0b0;
11411 let Inst{31-21} = 0b00111111000;
11412 let addrMode = BaseImmOffset;
11413 let accessSize = ByteAccess;
11415 let isRestrictNoSlot1Store = 1;
11417 let isExtendable = 1;
11418 let opExtendable = 1;
11419 let isExtentSigned = 0;
11420 let opExtentBits = 6;
11421 let opExtentAlign = 0;
11423 def L4_ior_memopb_zomap : HInst<
11425 (ins IntRegs:$Rs32, u5_0Imm:$II),
11426 "memb($Rs32) = setbit(#$II)",
11427 tc_44126683, TypeMAPPING> {
11429 let isCodeGenOnly = 1;
11431 def L4_ior_memoph_io : HInst<
11433 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11434 "memh($Rs32+#$Ii) = setbit(#$II)",
11435 tc_44126683, TypeV4LDST>, Enc_e66a97 {
11436 let Inst{6-5} = 0b11;
11437 let Inst{13-13} = 0b0;
11438 let Inst{31-21} = 0b00111111001;
11439 let addrMode = BaseImmOffset;
11440 let accessSize = HalfWordAccess;
11442 let isRestrictNoSlot1Store = 1;
11444 let isExtendable = 1;
11445 let opExtendable = 1;
11446 let isExtentSigned = 0;
11447 let opExtentBits = 7;
11448 let opExtentAlign = 1;
11450 def L4_ior_memoph_zomap : HInst<
11452 (ins IntRegs:$Rs32, u5_0Imm:$II),
11453 "memh($Rs32) = setbit(#$II)",
11454 tc_44126683, TypeMAPPING> {
11456 let isCodeGenOnly = 1;
11458 def L4_ior_memopw_io : HInst<
11460 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11461 "memw($Rs32+#$Ii) = setbit(#$II)",
11462 tc_44126683, TypeV4LDST>, Enc_84b2cd {
11463 let Inst{6-5} = 0b11;
11464 let Inst{13-13} = 0b0;
11465 let Inst{31-21} = 0b00111111010;
11466 let addrMode = BaseImmOffset;
11467 let accessSize = WordAccess;
11469 let isRestrictNoSlot1Store = 1;
11471 let isExtendable = 1;
11472 let opExtendable = 1;
11473 let isExtentSigned = 0;
11474 let opExtentBits = 8;
11475 let opExtentAlign = 2;
11477 def L4_ior_memopw_zomap : HInst<
11479 (ins IntRegs:$Rs32, u5_0Imm:$II),
11480 "memw($Rs32) = setbit(#$II)",
11481 tc_44126683, TypeMAPPING> {
11483 let isCodeGenOnly = 1;
11485 def L4_isub_memopb_io : HInst<
11487 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11488 "memb($Rs32+#$Ii) -= #$II",
11489 tc_44126683, TypeV4LDST>, Enc_46c951 {
11490 let Inst{6-5} = 0b01;
11491 let Inst{13-13} = 0b0;
11492 let Inst{31-21} = 0b00111111000;
11493 let addrMode = BaseImmOffset;
11494 let accessSize = ByteAccess;
11496 let isRestrictNoSlot1Store = 1;
11498 let isExtendable = 1;
11499 let opExtendable = 1;
11500 let isExtentSigned = 0;
11501 let opExtentBits = 6;
11502 let opExtentAlign = 0;
11504 def L4_isub_memopb_zomap : HInst<
11506 (ins IntRegs:$Rs32, u5_0Imm:$II),
11507 "memb($Rs32) -= #$II",
11508 tc_44126683, TypeMAPPING> {
11510 let isCodeGenOnly = 1;
11512 def L4_isub_memoph_io : HInst<
11514 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11515 "memh($Rs32+#$Ii) -= #$II",
11516 tc_44126683, TypeV4LDST>, Enc_e66a97 {
11517 let Inst{6-5} = 0b01;
11518 let Inst{13-13} = 0b0;
11519 let Inst{31-21} = 0b00111111001;
11520 let addrMode = BaseImmOffset;
11521 let accessSize = HalfWordAccess;
11523 let isRestrictNoSlot1Store = 1;
11525 let isExtendable = 1;
11526 let opExtendable = 1;
11527 let isExtentSigned = 0;
11528 let opExtentBits = 7;
11529 let opExtentAlign = 1;
11531 def L4_isub_memoph_zomap : HInst<
11533 (ins IntRegs:$Rs32, u5_0Imm:$II),
11534 "memh($Rs32) -= #$II",
11535 tc_44126683, TypeMAPPING> {
11537 let isCodeGenOnly = 1;
11539 def L4_isub_memopw_io : HInst<
11541 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11542 "memw($Rs32+#$Ii) -= #$II",
11543 tc_44126683, TypeV4LDST>, Enc_84b2cd {
11544 let Inst{6-5} = 0b01;
11545 let Inst{13-13} = 0b0;
11546 let Inst{31-21} = 0b00111111010;
11547 let addrMode = BaseImmOffset;
11548 let accessSize = WordAccess;
11550 let isRestrictNoSlot1Store = 1;
11552 let isExtendable = 1;
11553 let opExtendable = 1;
11554 let isExtentSigned = 0;
11555 let opExtentBits = 8;
11556 let opExtentAlign = 2;
11558 def L4_isub_memopw_zomap : HInst<
11560 (ins IntRegs:$Rs32, u5_0Imm:$II),
11561 "memw($Rs32) -= #$II",
11562 tc_44126683, TypeMAPPING> {
11564 let isCodeGenOnly = 1;
11566 def L4_loadalignb_ap : HInst<
11567 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11568 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11569 "$Ryy32 = memb_fifo($Re32=#$II)",
11570 tc_5acef64a, TypeLD>, Enc_f394d3 {
11571 let Inst{7-7} = 0b0;
11572 let Inst{13-12} = 0b01;
11573 let Inst{31-21} = 0b10011010100;
11574 let addrMode = AbsoluteSet;
11575 let accessSize = ByteAccess;
11577 let isExtended = 1;
11578 let DecoderNamespace = "MustExtend";
11579 let isExtendable = 1;
11580 let opExtendable = 3;
11581 let isExtentSigned = 0;
11582 let opExtentBits = 6;
11583 let opExtentAlign = 0;
11584 let Constraints = "$Ryy32 = $Ryy32in";
11586 def L4_loadalignb_ur : HInst<
11587 (outs DoubleRegs:$Ryy32),
11588 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11589 "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11590 tc_0cd51c76, TypeLD>, Enc_04c959 {
11591 let Inst{12-12} = 0b1;
11592 let Inst{31-21} = 0b10011100100;
11593 let addrMode = BaseLongOffset;
11594 let accessSize = ByteAccess;
11596 let isExtended = 1;
11597 let InputType = "imm";
11598 let DecoderNamespace = "MustExtend";
11599 let isExtendable = 1;
11600 let opExtendable = 4;
11601 let isExtentSigned = 0;
11602 let opExtentBits = 6;
11603 let opExtentAlign = 0;
11604 let Constraints = "$Ryy32 = $Ryy32in";
11606 def L4_loadalignh_ap : HInst<
11607 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11608 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11609 "$Ryy32 = memh_fifo($Re32=#$II)",
11610 tc_5acef64a, TypeLD>, Enc_f394d3 {
11611 let Inst{7-7} = 0b0;
11612 let Inst{13-12} = 0b01;
11613 let Inst{31-21} = 0b10011010010;
11614 let addrMode = AbsoluteSet;
11615 let accessSize = HalfWordAccess;
11617 let isExtended = 1;
11618 let DecoderNamespace = "MustExtend";
11619 let isExtendable = 1;
11620 let opExtendable = 3;
11621 let isExtentSigned = 0;
11622 let opExtentBits = 6;
11623 let opExtentAlign = 0;
11624 let Constraints = "$Ryy32 = $Ryy32in";
11626 def L4_loadalignh_ur : HInst<
11627 (outs DoubleRegs:$Ryy32),
11628 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11629 "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11630 tc_0cd51c76, TypeLD>, Enc_04c959 {
11631 let Inst{12-12} = 0b1;
11632 let Inst{31-21} = 0b10011100010;
11633 let addrMode = BaseLongOffset;
11634 let accessSize = HalfWordAccess;
11636 let isExtended = 1;
11637 let InputType = "imm";
11638 let DecoderNamespace = "MustExtend";
11639 let isExtendable = 1;
11640 let opExtendable = 4;
11641 let isExtentSigned = 0;
11642 let opExtentBits = 6;
11643 let opExtentAlign = 0;
11644 let Constraints = "$Ryy32 = $Ryy32in";
11646 def L4_loadbsw2_ap : HInst<
11647 (outs IntRegs:$Rd32, IntRegs:$Re32),
11648 (ins u32_0Imm:$II),
11649 "$Rd32 = membh($Re32=#$II)",
11650 tc_b77c481f, TypeLD>, Enc_323f2d {
11651 let Inst{7-7} = 0b0;
11652 let Inst{13-12} = 0b01;
11653 let Inst{31-21} = 0b10011010001;
11654 let hasNewValue = 1;
11655 let opNewValue = 0;
11656 let addrMode = AbsoluteSet;
11657 let accessSize = HalfWordAccess;
11659 let isExtended = 1;
11660 let DecoderNamespace = "MustExtend";
11661 let isExtendable = 1;
11662 let opExtendable = 2;
11663 let isExtentSigned = 0;
11664 let opExtentBits = 6;
11665 let opExtentAlign = 0;
11667 def L4_loadbsw2_ur : HInst<
11668 (outs IntRegs:$Rd32),
11669 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11670 "$Rd32 = membh($Rt32<<#$Ii+#$II)",
11671 tc_cf47a43f, TypeLD>, Enc_4f677b {
11672 let Inst{12-12} = 0b1;
11673 let Inst{31-21} = 0b10011100001;
11674 let hasNewValue = 1;
11675 let opNewValue = 0;
11676 let addrMode = BaseLongOffset;
11677 let accessSize = HalfWordAccess;
11679 let isExtended = 1;
11680 let InputType = "imm";
11681 let DecoderNamespace = "MustExtend";
11682 let isExtendable = 1;
11683 let opExtendable = 3;
11684 let isExtentSigned = 0;
11685 let opExtentBits = 6;
11686 let opExtentAlign = 0;
11688 def L4_loadbsw4_ap : HInst<
11689 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11690 (ins u32_0Imm:$II),
11691 "$Rdd32 = membh($Re32=#$II)",
11692 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
11693 let Inst{7-7} = 0b0;
11694 let Inst{13-12} = 0b01;
11695 let Inst{31-21} = 0b10011010111;
11696 let addrMode = AbsoluteSet;
11697 let accessSize = WordAccess;
11699 let isExtended = 1;
11700 let DecoderNamespace = "MustExtend";
11701 let isExtendable = 1;
11702 let opExtendable = 2;
11703 let isExtentSigned = 0;
11704 let opExtentBits = 6;
11705 let opExtentAlign = 0;
11707 def L4_loadbsw4_ur : HInst<
11708 (outs DoubleRegs:$Rdd32),
11709 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11710 "$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11711 tc_cf47a43f, TypeLD>, Enc_6185fe {
11712 let Inst{12-12} = 0b1;
11713 let Inst{31-21} = 0b10011100111;
11714 let addrMode = BaseLongOffset;
11715 let accessSize = WordAccess;
11717 let isExtended = 1;
11718 let InputType = "imm";
11719 let DecoderNamespace = "MustExtend";
11720 let isExtendable = 1;
11721 let opExtendable = 3;
11722 let isExtentSigned = 0;
11723 let opExtentBits = 6;
11724 let opExtentAlign = 0;
11726 def L4_loadbzw2_ap : HInst<
11727 (outs IntRegs:$Rd32, IntRegs:$Re32),
11728 (ins u32_0Imm:$II),
11729 "$Rd32 = memubh($Re32=#$II)",
11730 tc_b77c481f, TypeLD>, Enc_323f2d {
11731 let Inst{7-7} = 0b0;
11732 let Inst{13-12} = 0b01;
11733 let Inst{31-21} = 0b10011010011;
11734 let hasNewValue = 1;
11735 let opNewValue = 0;
11736 let addrMode = AbsoluteSet;
11737 let accessSize = HalfWordAccess;
11739 let isExtended = 1;
11740 let DecoderNamespace = "MustExtend";
11741 let isExtendable = 1;
11742 let opExtendable = 2;
11743 let isExtentSigned = 0;
11744 let opExtentBits = 6;
11745 let opExtentAlign = 0;
11747 def L4_loadbzw2_ur : HInst<
11748 (outs IntRegs:$Rd32),
11749 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11750 "$Rd32 = memubh($Rt32<<#$Ii+#$II)",
11751 tc_cf47a43f, TypeLD>, Enc_4f677b {
11752 let Inst{12-12} = 0b1;
11753 let Inst{31-21} = 0b10011100011;
11754 let hasNewValue = 1;
11755 let opNewValue = 0;
11756 let addrMode = BaseLongOffset;
11757 let accessSize = HalfWordAccess;
11759 let isExtended = 1;
11760 let InputType = "imm";
11761 let DecoderNamespace = "MustExtend";
11762 let isExtendable = 1;
11763 let opExtendable = 3;
11764 let isExtentSigned = 0;
11765 let opExtentBits = 6;
11766 let opExtentAlign = 0;
11768 def L4_loadbzw4_ap : HInst<
11769 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11770 (ins u32_0Imm:$II),
11771 "$Rdd32 = memubh($Re32=#$II)",
11772 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
11773 let Inst{7-7} = 0b0;
11774 let Inst{13-12} = 0b01;
11775 let Inst{31-21} = 0b10011010101;
11776 let addrMode = AbsoluteSet;
11777 let accessSize = WordAccess;
11779 let isExtended = 1;
11780 let DecoderNamespace = "MustExtend";
11781 let isExtendable = 1;
11782 let opExtendable = 2;
11783 let isExtentSigned = 0;
11784 let opExtentBits = 6;
11785 let opExtentAlign = 0;
11787 def L4_loadbzw4_ur : HInst<
11788 (outs DoubleRegs:$Rdd32),
11789 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11790 "$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
11791 tc_cf47a43f, TypeLD>, Enc_6185fe {
11792 let Inst{12-12} = 0b1;
11793 let Inst{31-21} = 0b10011100101;
11794 let addrMode = BaseLongOffset;
11795 let accessSize = WordAccess;
11797 let isExtended = 1;
11798 let InputType = "imm";
11799 let DecoderNamespace = "MustExtend";
11800 let isExtendable = 1;
11801 let opExtendable = 3;
11802 let isExtentSigned = 0;
11803 let opExtentBits = 6;
11804 let opExtentAlign = 0;
11806 def L4_loadd_locked : HInst<
11807 (outs DoubleRegs:$Rdd32),
11808 (ins IntRegs:$Rs32),
11809 "$Rdd32 = memd_locked($Rs32)",
11810 tc_6aa5711a, TypeLD>, Enc_3a3d62 {
11811 let Inst{13-5} = 0b010000000;
11812 let Inst{31-21} = 0b10010010000;
11813 let accessSize = DoubleWordAccess;
11817 def L4_loadrb_ap : HInst<
11818 (outs IntRegs:$Rd32, IntRegs:$Re32),
11819 (ins u32_0Imm:$II),
11820 "$Rd32 = memb($Re32=#$II)",
11821 tc_b77c481f, TypeLD>, Enc_323f2d {
11822 let Inst{7-7} = 0b0;
11823 let Inst{13-12} = 0b01;
11824 let Inst{31-21} = 0b10011011000;
11825 let hasNewValue = 1;
11826 let opNewValue = 0;
11827 let addrMode = AbsoluteSet;
11828 let accessSize = ByteAccess;
11830 let isExtended = 1;
11831 let DecoderNamespace = "MustExtend";
11832 let isExtendable = 1;
11833 let opExtendable = 2;
11834 let isExtentSigned = 0;
11835 let opExtentBits = 6;
11836 let opExtentAlign = 0;
11838 def L4_loadrb_rr : HInst<
11839 (outs IntRegs:$Rd32),
11840 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
11841 "$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
11842 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
11843 let Inst{6-5} = 0b00;
11844 let Inst{31-21} = 0b00111010000;
11845 let hasNewValue = 1;
11846 let opNewValue = 0;
11847 let addrMode = BaseRegOffset;
11848 let accessSize = ByteAccess;
11850 let CextOpcode = "L2_loadrb";
11851 let InputType = "reg";
11852 let BaseOpcode = "L4_loadrb_rr";
11853 let isPredicable = 1;
11855 def L4_loadrb_ur : HInst<
11856 (outs IntRegs:$Rd32),
11857 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11858 "$Rd32 = memb($Rt32<<#$Ii+#$II)",
11859 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
11860 let Inst{12-12} = 0b1;
11861 let Inst{31-21} = 0b10011101000;
11862 let hasNewValue = 1;
11863 let opNewValue = 0;
11864 let addrMode = BaseLongOffset;
11865 let accessSize = ByteAccess;
11867 let isExtended = 1;
11868 let CextOpcode = "L2_loadrb";
11869 let InputType = "imm";
11870 let DecoderNamespace = "MustExtend";
11871 let isExtendable = 1;
11872 let opExtendable = 3;
11873 let isExtentSigned = 0;
11874 let opExtentBits = 6;
11875 let opExtentAlign = 0;
11877 def L4_loadrd_ap : HInst<
11878 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11879 (ins u32_0Imm:$II),
11880 "$Rdd32 = memd($Re32=#$II)",
11881 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
11882 let Inst{7-7} = 0b0;
11883 let Inst{13-12} = 0b01;
11884 let Inst{31-21} = 0b10011011110;
11885 let addrMode = AbsoluteSet;
11886 let accessSize = DoubleWordAccess;
11888 let isExtended = 1;
11889 let DecoderNamespace = "MustExtend";
11890 let isExtendable = 1;
11891 let opExtendable = 2;
11892 let isExtentSigned = 0;
11893 let opExtentBits = 6;
11894 let opExtentAlign = 0;
11896 def L4_loadrd_rr : HInst<
11897 (outs DoubleRegs:$Rdd32),
11898 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
11899 "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
11900 tc_f47d212f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
11901 let Inst{6-5} = 0b00;
11902 let Inst{31-21} = 0b00111010110;
11903 let addrMode = BaseRegOffset;
11904 let accessSize = DoubleWordAccess;
11906 let CextOpcode = "L2_loadrd";
11907 let InputType = "reg";
11908 let BaseOpcode = "L4_loadrd_rr";
11909 let isPredicable = 1;
11911 def L4_loadrd_ur : HInst<
11912 (outs DoubleRegs:$Rdd32),
11913 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11914 "$Rdd32 = memd($Rt32<<#$Ii+#$II)",
11915 tc_cf47a43f, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
11916 let Inst{12-12} = 0b1;
11917 let Inst{31-21} = 0b10011101110;
11918 let addrMode = BaseLongOffset;
11919 let accessSize = DoubleWordAccess;
11921 let isExtended = 1;
11922 let CextOpcode = "L2_loadrd";
11923 let InputType = "imm";
11924 let DecoderNamespace = "MustExtend";
11925 let isExtendable = 1;
11926 let opExtendable = 3;
11927 let isExtentSigned = 0;
11928 let opExtentBits = 6;
11929 let opExtentAlign = 0;
11931 def L4_loadrh_ap : HInst<
11932 (outs IntRegs:$Rd32, IntRegs:$Re32),
11933 (ins u32_0Imm:$II),
11934 "$Rd32 = memh($Re32=#$II)",
11935 tc_b77c481f, TypeLD>, Enc_323f2d {
11936 let Inst{7-7} = 0b0;
11937 let Inst{13-12} = 0b01;
11938 let Inst{31-21} = 0b10011011010;
11939 let hasNewValue = 1;
11940 let opNewValue = 0;
11941 let addrMode = AbsoluteSet;
11942 let accessSize = HalfWordAccess;
11944 let isExtended = 1;
11945 let DecoderNamespace = "MustExtend";
11946 let isExtendable = 1;
11947 let opExtendable = 2;
11948 let isExtentSigned = 0;
11949 let opExtentBits = 6;
11950 let opExtentAlign = 0;
11952 def L4_loadrh_rr : HInst<
11953 (outs IntRegs:$Rd32),
11954 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
11955 "$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
11956 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
11957 let Inst{6-5} = 0b00;
11958 let Inst{31-21} = 0b00111010010;
11959 let hasNewValue = 1;
11960 let opNewValue = 0;
11961 let addrMode = BaseRegOffset;
11962 let accessSize = HalfWordAccess;
11964 let CextOpcode = "L2_loadrh";
11965 let InputType = "reg";
11966 let BaseOpcode = "L4_loadrh_rr";
11967 let isPredicable = 1;
11969 def L4_loadrh_ur : HInst<
11970 (outs IntRegs:$Rd32),
11971 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11972 "$Rd32 = memh($Rt32<<#$Ii+#$II)",
11973 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
11974 let Inst{12-12} = 0b1;
11975 let Inst{31-21} = 0b10011101010;
11976 let hasNewValue = 1;
11977 let opNewValue = 0;
11978 let addrMode = BaseLongOffset;
11979 let accessSize = HalfWordAccess;
11981 let isExtended = 1;
11982 let CextOpcode = "L2_loadrh";
11983 let InputType = "imm";
11984 let DecoderNamespace = "MustExtend";
11985 let isExtendable = 1;
11986 let opExtendable = 3;
11987 let isExtentSigned = 0;
11988 let opExtentBits = 6;
11989 let opExtentAlign = 0;
11991 def L4_loadri_ap : HInst<
11992 (outs IntRegs:$Rd32, IntRegs:$Re32),
11993 (ins u32_0Imm:$II),
11994 "$Rd32 = memw($Re32=#$II)",
11995 tc_b77c481f, TypeLD>, Enc_323f2d {
11996 let Inst{7-7} = 0b0;
11997 let Inst{13-12} = 0b01;
11998 let Inst{31-21} = 0b10011011100;
11999 let hasNewValue = 1;
12000 let opNewValue = 0;
12001 let addrMode = AbsoluteSet;
12002 let accessSize = WordAccess;
12004 let isExtended = 1;
12005 let DecoderNamespace = "MustExtend";
12006 let isExtendable = 1;
12007 let opExtendable = 2;
12008 let isExtentSigned = 0;
12009 let opExtentBits = 6;
12010 let opExtentAlign = 0;
12012 def L4_loadri_rr : HInst<
12013 (outs IntRegs:$Rd32),
12014 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12015 "$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12016 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12017 let Inst{6-5} = 0b00;
12018 let Inst{31-21} = 0b00111010100;
12019 let hasNewValue = 1;
12020 let opNewValue = 0;
12021 let addrMode = BaseRegOffset;
12022 let accessSize = WordAccess;
12024 let CextOpcode = "L2_loadri";
12025 let InputType = "reg";
12026 let BaseOpcode = "L4_loadri_rr";
12027 let isPredicable = 1;
12029 def L4_loadri_ur : HInst<
12030 (outs IntRegs:$Rd32),
12031 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12032 "$Rd32 = memw($Rt32<<#$Ii+#$II)",
12033 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12034 let Inst{12-12} = 0b1;
12035 let Inst{31-21} = 0b10011101100;
12036 let hasNewValue = 1;
12037 let opNewValue = 0;
12038 let addrMode = BaseLongOffset;
12039 let accessSize = WordAccess;
12041 let isExtended = 1;
12042 let CextOpcode = "L2_loadri";
12043 let InputType = "imm";
12044 let DecoderNamespace = "MustExtend";
12045 let isExtendable = 1;
12046 let opExtendable = 3;
12047 let isExtentSigned = 0;
12048 let opExtentBits = 6;
12049 let opExtentAlign = 0;
12051 def L4_loadrub_ap : HInst<
12052 (outs IntRegs:$Rd32, IntRegs:$Re32),
12053 (ins u32_0Imm:$II),
12054 "$Rd32 = memub($Re32=#$II)",
12055 tc_b77c481f, TypeLD>, Enc_323f2d {
12056 let Inst{7-7} = 0b0;
12057 let Inst{13-12} = 0b01;
12058 let Inst{31-21} = 0b10011011001;
12059 let hasNewValue = 1;
12060 let opNewValue = 0;
12061 let addrMode = AbsoluteSet;
12062 let accessSize = ByteAccess;
12064 let isExtended = 1;
12065 let DecoderNamespace = "MustExtend";
12066 let isExtendable = 1;
12067 let opExtendable = 2;
12068 let isExtentSigned = 0;
12069 let opExtentBits = 6;
12070 let opExtentAlign = 0;
12072 def L4_loadrub_rr : HInst<
12073 (outs IntRegs:$Rd32),
12074 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12075 "$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12076 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12077 let Inst{6-5} = 0b00;
12078 let Inst{31-21} = 0b00111010001;
12079 let hasNewValue = 1;
12080 let opNewValue = 0;
12081 let addrMode = BaseRegOffset;
12082 let accessSize = ByteAccess;
12084 let CextOpcode = "L2_loadrub";
12085 let InputType = "reg";
12086 let BaseOpcode = "L4_loadrub_rr";
12087 let isPredicable = 1;
12089 def L4_loadrub_ur : HInst<
12090 (outs IntRegs:$Rd32),
12091 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12092 "$Rd32 = memub($Rt32<<#$Ii+#$II)",
12093 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12094 let Inst{12-12} = 0b1;
12095 let Inst{31-21} = 0b10011101001;
12096 let hasNewValue = 1;
12097 let opNewValue = 0;
12098 let addrMode = BaseLongOffset;
12099 let accessSize = ByteAccess;
12101 let isExtended = 1;
12102 let CextOpcode = "L2_loadrub";
12103 let InputType = "imm";
12104 let DecoderNamespace = "MustExtend";
12105 let isExtendable = 1;
12106 let opExtendable = 3;
12107 let isExtentSigned = 0;
12108 let opExtentBits = 6;
12109 let opExtentAlign = 0;
12111 def L4_loadruh_ap : HInst<
12112 (outs IntRegs:$Rd32, IntRegs:$Re32),
12113 (ins u32_0Imm:$II),
12114 "$Rd32 = memuh($Re32=#$II)",
12115 tc_b77c481f, TypeLD>, Enc_323f2d {
12116 let Inst{7-7} = 0b0;
12117 let Inst{13-12} = 0b01;
12118 let Inst{31-21} = 0b10011011011;
12119 let hasNewValue = 1;
12120 let opNewValue = 0;
12121 let addrMode = AbsoluteSet;
12122 let accessSize = HalfWordAccess;
12124 let isExtended = 1;
12125 let DecoderNamespace = "MustExtend";
12126 let isExtendable = 1;
12127 let opExtendable = 2;
12128 let isExtentSigned = 0;
12129 let opExtentBits = 6;
12130 let opExtentAlign = 0;
12132 def L4_loadruh_rr : HInst<
12133 (outs IntRegs:$Rd32),
12134 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12135 "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12136 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12137 let Inst{6-5} = 0b00;
12138 let Inst{31-21} = 0b00111010011;
12139 let hasNewValue = 1;
12140 let opNewValue = 0;
12141 let addrMode = BaseRegOffset;
12142 let accessSize = HalfWordAccess;
12144 let CextOpcode = "L2_loadruh";
12145 let InputType = "reg";
12146 let BaseOpcode = "L4_loadruh_rr";
12147 let isPredicable = 1;
12149 def L4_loadruh_ur : HInst<
12150 (outs IntRegs:$Rd32),
12151 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12152 "$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12153 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12154 let Inst{12-12} = 0b1;
12155 let Inst{31-21} = 0b10011101011;
12156 let hasNewValue = 1;
12157 let opNewValue = 0;
12158 let addrMode = BaseLongOffset;
12159 let accessSize = HalfWordAccess;
12161 let isExtended = 1;
12162 let CextOpcode = "L2_loadruh";
12163 let InputType = "imm";
12164 let DecoderNamespace = "MustExtend";
12165 let isExtendable = 1;
12166 let opExtendable = 3;
12167 let isExtentSigned = 0;
12168 let opExtentBits = 6;
12169 let opExtentAlign = 0;
12171 def L4_or_memopb_io : HInst<
12173 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12174 "memb($Rs32+#$Ii) |= $Rt32",
12175 tc_44126683, TypeV4LDST>, Enc_d44e31 {
12176 let Inst{6-5} = 0b11;
12177 let Inst{13-13} = 0b0;
12178 let Inst{31-21} = 0b00111110000;
12179 let addrMode = BaseImmOffset;
12180 let accessSize = ByteAccess;
12182 let isRestrictNoSlot1Store = 1;
12184 let isExtendable = 1;
12185 let opExtendable = 1;
12186 let isExtentSigned = 0;
12187 let opExtentBits = 6;
12188 let opExtentAlign = 0;
12190 def L4_or_memopb_zomap : HInst<
12192 (ins IntRegs:$Rs32, IntRegs:$Rt32),
12193 "memb($Rs32) |= $Rt32",
12194 tc_44126683, TypeMAPPING> {
12196 let isCodeGenOnly = 1;
12198 def L4_or_memoph_io : HInst<
12200 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12201 "memh($Rs32+#$Ii) |= $Rt32",
12202 tc_44126683, TypeV4LDST>, Enc_163a3c {
12203 let Inst{6-5} = 0b11;
12204 let Inst{13-13} = 0b0;
12205 let Inst{31-21} = 0b00111110001;
12206 let addrMode = BaseImmOffset;
12207 let accessSize = HalfWordAccess;
12209 let isRestrictNoSlot1Store = 1;
12211 let isExtendable = 1;
12212 let opExtendable = 1;
12213 let isExtentSigned = 0;
12214 let opExtentBits = 7;
12215 let opExtentAlign = 1;
12217 def L4_or_memoph_zomap : HInst<
12219 (ins IntRegs:$Rs32, IntRegs:$Rt32),
12220 "memh($Rs32) |= $Rt32",
12221 tc_44126683, TypeMAPPING> {
12223 let isCodeGenOnly = 1;
12225 def L4_or_memopw_io : HInst<
12227 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12228 "memw($Rs32+#$Ii) |= $Rt32",
12229 tc_44126683, TypeV4LDST>, Enc_226535 {
12230 let Inst{6-5} = 0b11;
12231 let Inst{13-13} = 0b0;
12232 let Inst{31-21} = 0b00111110010;
12233 let addrMode = BaseImmOffset;
12234 let accessSize = WordAccess;
12236 let isRestrictNoSlot1Store = 1;
12238 let isExtendable = 1;
12239 let opExtendable = 1;
12240 let isExtentSigned = 0;
12241 let opExtentBits = 8;
12242 let opExtentAlign = 2;
12244 def L4_or_memopw_zomap : HInst<
12246 (ins IntRegs:$Rs32, IntRegs:$Rt32),
12247 "memw($Rs32) |= $Rt32",
12248 tc_44126683, TypeMAPPING> {
12250 let isCodeGenOnly = 1;
12252 def L4_ploadrbf_abs : HInst<
12253 (outs IntRegs:$Rd32),
12254 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12255 "if (!$Pt4) $Rd32 = memb(#$Ii)",
12256 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12257 let Inst{7-5} = 0b100;
12258 let Inst{13-11} = 0b101;
12259 let Inst{31-21} = 0b10011111000;
12260 let isPredicated = 1;
12261 let isPredicatedFalse = 1;
12262 let hasNewValue = 1;
12263 let opNewValue = 0;
12264 let addrMode = Absolute;
12265 let accessSize = ByteAccess;
12267 let isExtended = 1;
12268 let CextOpcode = "L2_loadrb";
12269 let BaseOpcode = "L4_loadrb_abs";
12270 let DecoderNamespace = "MustExtend";
12271 let isExtendable = 1;
12272 let opExtendable = 2;
12273 let isExtentSigned = 0;
12274 let opExtentBits = 6;
12275 let opExtentAlign = 0;
12277 def L4_ploadrbf_rr : HInst<
12278 (outs IntRegs:$Rd32),
12279 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12280 "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12281 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12282 let Inst{31-21} = 0b00110001000;
12283 let isPredicated = 1;
12284 let isPredicatedFalse = 1;
12285 let hasNewValue = 1;
12286 let opNewValue = 0;
12287 let addrMode = BaseRegOffset;
12288 let accessSize = ByteAccess;
12290 let CextOpcode = "L2_loadrb";
12291 let InputType = "reg";
12292 let BaseOpcode = "L4_loadrb_rr";
12294 def L4_ploadrbfnew_abs : HInst<
12295 (outs IntRegs:$Rd32),
12296 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12297 "if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12298 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12299 let Inst{7-5} = 0b100;
12300 let Inst{13-11} = 0b111;
12301 let Inst{31-21} = 0b10011111000;
12302 let isPredicated = 1;
12303 let isPredicatedFalse = 1;
12304 let hasNewValue = 1;
12305 let opNewValue = 0;
12306 let addrMode = Absolute;
12307 let accessSize = ByteAccess;
12308 let isPredicatedNew = 1;
12310 let isExtended = 1;
12311 let CextOpcode = "L2_loadrb";
12312 let BaseOpcode = "L4_loadrb_abs";
12313 let DecoderNamespace = "MustExtend";
12314 let isExtendable = 1;
12315 let opExtendable = 2;
12316 let isExtentSigned = 0;
12317 let opExtentBits = 6;
12318 let opExtentAlign = 0;
12320 def L4_ploadrbfnew_rr : HInst<
12321 (outs IntRegs:$Rd32),
12322 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12323 "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12324 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12325 let Inst{31-21} = 0b00110011000;
12326 let isPredicated = 1;
12327 let isPredicatedFalse = 1;
12328 let hasNewValue = 1;
12329 let opNewValue = 0;
12330 let addrMode = BaseRegOffset;
12331 let accessSize = ByteAccess;
12332 let isPredicatedNew = 1;
12334 let CextOpcode = "L2_loadrb";
12335 let InputType = "reg";
12336 let BaseOpcode = "L4_loadrb_rr";
12338 def L4_ploadrbt_abs : HInst<
12339 (outs IntRegs:$Rd32),
12340 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12341 "if ($Pt4) $Rd32 = memb(#$Ii)",
12342 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12343 let Inst{7-5} = 0b100;
12344 let Inst{13-11} = 0b100;
12345 let Inst{31-21} = 0b10011111000;
12346 let isPredicated = 1;
12347 let hasNewValue = 1;
12348 let opNewValue = 0;
12349 let addrMode = Absolute;
12350 let accessSize = ByteAccess;
12352 let isExtended = 1;
12353 let CextOpcode = "L2_loadrb";
12354 let BaseOpcode = "L4_loadrb_abs";
12355 let DecoderNamespace = "MustExtend";
12356 let isExtendable = 1;
12357 let opExtendable = 2;
12358 let isExtentSigned = 0;
12359 let opExtentBits = 6;
12360 let opExtentAlign = 0;
12362 def L4_ploadrbt_rr : HInst<
12363 (outs IntRegs:$Rd32),
12364 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12365 "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12366 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12367 let Inst{31-21} = 0b00110000000;
12368 let isPredicated = 1;
12369 let hasNewValue = 1;
12370 let opNewValue = 0;
12371 let addrMode = BaseRegOffset;
12372 let accessSize = ByteAccess;
12374 let CextOpcode = "L2_loadrb";
12375 let InputType = "reg";
12376 let BaseOpcode = "L4_loadrb_rr";
12378 def L4_ploadrbtnew_abs : HInst<
12379 (outs IntRegs:$Rd32),
12380 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12381 "if ($Pt4.new) $Rd32 = memb(#$Ii)",
12382 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12383 let Inst{7-5} = 0b100;
12384 let Inst{13-11} = 0b110;
12385 let Inst{31-21} = 0b10011111000;
12386 let isPredicated = 1;
12387 let hasNewValue = 1;
12388 let opNewValue = 0;
12389 let addrMode = Absolute;
12390 let accessSize = ByteAccess;
12391 let isPredicatedNew = 1;
12393 let isExtended = 1;
12394 let CextOpcode = "L2_loadrb";
12395 let BaseOpcode = "L4_loadrb_abs";
12396 let DecoderNamespace = "MustExtend";
12397 let isExtendable = 1;
12398 let opExtendable = 2;
12399 let isExtentSigned = 0;
12400 let opExtentBits = 6;
12401 let opExtentAlign = 0;
12403 def L4_ploadrbtnew_rr : HInst<
12404 (outs IntRegs:$Rd32),
12405 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12406 "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12407 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12408 let Inst{31-21} = 0b00110010000;
12409 let isPredicated = 1;
12410 let hasNewValue = 1;
12411 let opNewValue = 0;
12412 let addrMode = BaseRegOffset;
12413 let accessSize = ByteAccess;
12414 let isPredicatedNew = 1;
12416 let CextOpcode = "L2_loadrb";
12417 let InputType = "reg";
12418 let BaseOpcode = "L4_loadrb_rr";
12420 def L4_ploadrdf_abs : HInst<
12421 (outs DoubleRegs:$Rdd32),
12422 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12423 "if (!$Pt4) $Rdd32 = memd(#$Ii)",
12424 tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
12425 let Inst{7-5} = 0b100;
12426 let Inst{13-11} = 0b101;
12427 let Inst{31-21} = 0b10011111110;
12428 let isPredicated = 1;
12429 let isPredicatedFalse = 1;
12430 let addrMode = Absolute;
12431 let accessSize = DoubleWordAccess;
12433 let isExtended = 1;
12434 let CextOpcode = "L2_loadrd";
12435 let BaseOpcode = "L4_loadrd_abs";
12436 let DecoderNamespace = "MustExtend";
12437 let isExtendable = 1;
12438 let opExtendable = 2;
12439 let isExtentSigned = 0;
12440 let opExtentBits = 6;
12441 let opExtentAlign = 0;
12443 def L4_ploadrdf_rr : HInst<
12444 (outs DoubleRegs:$Rdd32),
12445 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12446 "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12447 tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
12448 let Inst{31-21} = 0b00110001110;
12449 let isPredicated = 1;
12450 let isPredicatedFalse = 1;
12451 let addrMode = BaseRegOffset;
12452 let accessSize = DoubleWordAccess;
12454 let CextOpcode = "L2_loadrd";
12455 let InputType = "reg";
12456 let BaseOpcode = "L4_loadrd_rr";
12458 def L4_ploadrdfnew_abs : HInst<
12459 (outs DoubleRegs:$Rdd32),
12460 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12461 "if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12462 tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
12463 let Inst{7-5} = 0b100;
12464 let Inst{13-11} = 0b111;
12465 let Inst{31-21} = 0b10011111110;
12466 let isPredicated = 1;
12467 let isPredicatedFalse = 1;
12468 let addrMode = Absolute;
12469 let accessSize = DoubleWordAccess;
12470 let isPredicatedNew = 1;
12472 let isExtended = 1;
12473 let CextOpcode = "L2_loadrd";
12474 let BaseOpcode = "L4_loadrd_abs";
12475 let DecoderNamespace = "MustExtend";
12476 let isExtendable = 1;
12477 let opExtendable = 2;
12478 let isExtentSigned = 0;
12479 let opExtentBits = 6;
12480 let opExtentAlign = 0;
12482 def L4_ploadrdfnew_rr : HInst<
12483 (outs DoubleRegs:$Rdd32),
12484 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12485 "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12486 tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
12487 let Inst{31-21} = 0b00110011110;
12488 let isPredicated = 1;
12489 let isPredicatedFalse = 1;
12490 let addrMode = BaseRegOffset;
12491 let accessSize = DoubleWordAccess;
12492 let isPredicatedNew = 1;
12494 let CextOpcode = "L2_loadrd";
12495 let InputType = "reg";
12496 let BaseOpcode = "L4_loadrd_rr";
12498 def L4_ploadrdt_abs : HInst<
12499 (outs DoubleRegs:$Rdd32),
12500 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12501 "if ($Pt4) $Rdd32 = memd(#$Ii)",
12502 tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
12503 let Inst{7-5} = 0b100;
12504 let Inst{13-11} = 0b100;
12505 let Inst{31-21} = 0b10011111110;
12506 let isPredicated = 1;
12507 let addrMode = Absolute;
12508 let accessSize = DoubleWordAccess;
12510 let isExtended = 1;
12511 let CextOpcode = "L2_loadrd";
12512 let BaseOpcode = "L4_loadrd_abs";
12513 let DecoderNamespace = "MustExtend";
12514 let isExtendable = 1;
12515 let opExtendable = 2;
12516 let isExtentSigned = 0;
12517 let opExtentBits = 6;
12518 let opExtentAlign = 0;
12520 def L4_ploadrdt_rr : HInst<
12521 (outs DoubleRegs:$Rdd32),
12522 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12523 "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12524 tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
12525 let Inst{31-21} = 0b00110000110;
12526 let isPredicated = 1;
12527 let addrMode = BaseRegOffset;
12528 let accessSize = DoubleWordAccess;
12530 let CextOpcode = "L2_loadrd";
12531 let InputType = "reg";
12532 let BaseOpcode = "L4_loadrd_rr";
12534 def L4_ploadrdtnew_abs : HInst<
12535 (outs DoubleRegs:$Rdd32),
12536 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12537 "if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12538 tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
12539 let Inst{7-5} = 0b100;
12540 let Inst{13-11} = 0b110;
12541 let Inst{31-21} = 0b10011111110;
12542 let isPredicated = 1;
12543 let addrMode = Absolute;
12544 let accessSize = DoubleWordAccess;
12545 let isPredicatedNew = 1;
12547 let isExtended = 1;
12548 let CextOpcode = "L2_loadrd";
12549 let BaseOpcode = "L4_loadrd_abs";
12550 let DecoderNamespace = "MustExtend";
12551 let isExtendable = 1;
12552 let opExtendable = 2;
12553 let isExtentSigned = 0;
12554 let opExtentBits = 6;
12555 let opExtentAlign = 0;
12557 def L4_ploadrdtnew_rr : HInst<
12558 (outs DoubleRegs:$Rdd32),
12559 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12560 "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12561 tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
12562 let Inst{31-21} = 0b00110010110;
12563 let isPredicated = 1;
12564 let addrMode = BaseRegOffset;
12565 let accessSize = DoubleWordAccess;
12566 let isPredicatedNew = 1;
12568 let CextOpcode = "L2_loadrd";
12569 let InputType = "reg";
12570 let BaseOpcode = "L4_loadrd_rr";
12572 def L4_ploadrhf_abs : HInst<
12573 (outs IntRegs:$Rd32),
12574 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12575 "if (!$Pt4) $Rd32 = memh(#$Ii)",
12576 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12577 let Inst{7-5} = 0b100;
12578 let Inst{13-11} = 0b101;
12579 let Inst{31-21} = 0b10011111010;
12580 let isPredicated = 1;
12581 let isPredicatedFalse = 1;
12582 let hasNewValue = 1;
12583 let opNewValue = 0;
12584 let addrMode = Absolute;
12585 let accessSize = HalfWordAccess;
12587 let isExtended = 1;
12588 let CextOpcode = "L2_loadrh";
12589 let BaseOpcode = "L4_loadrh_abs";
12590 let DecoderNamespace = "MustExtend";
12591 let isExtendable = 1;
12592 let opExtendable = 2;
12593 let isExtentSigned = 0;
12594 let opExtentBits = 6;
12595 let opExtentAlign = 0;
12597 def L4_ploadrhf_rr : HInst<
12598 (outs IntRegs:$Rd32),
12599 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12600 "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12601 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12602 let Inst{31-21} = 0b00110001010;
12603 let isPredicated = 1;
12604 let isPredicatedFalse = 1;
12605 let hasNewValue = 1;
12606 let opNewValue = 0;
12607 let addrMode = BaseRegOffset;
12608 let accessSize = HalfWordAccess;
12610 let CextOpcode = "L2_loadrh";
12611 let InputType = "reg";
12612 let BaseOpcode = "L4_loadrh_rr";
12614 def L4_ploadrhfnew_abs : HInst<
12615 (outs IntRegs:$Rd32),
12616 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12617 "if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12618 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12619 let Inst{7-5} = 0b100;
12620 let Inst{13-11} = 0b111;
12621 let Inst{31-21} = 0b10011111010;
12622 let isPredicated = 1;
12623 let isPredicatedFalse = 1;
12624 let hasNewValue = 1;
12625 let opNewValue = 0;
12626 let addrMode = Absolute;
12627 let accessSize = HalfWordAccess;
12628 let isPredicatedNew = 1;
12630 let isExtended = 1;
12631 let CextOpcode = "L2_loadrh";
12632 let BaseOpcode = "L4_loadrh_abs";
12633 let DecoderNamespace = "MustExtend";
12634 let isExtendable = 1;
12635 let opExtendable = 2;
12636 let isExtentSigned = 0;
12637 let opExtentBits = 6;
12638 let opExtentAlign = 0;
12640 def L4_ploadrhfnew_rr : HInst<
12641 (outs IntRegs:$Rd32),
12642 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12643 "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12644 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12645 let Inst{31-21} = 0b00110011010;
12646 let isPredicated = 1;
12647 let isPredicatedFalse = 1;
12648 let hasNewValue = 1;
12649 let opNewValue = 0;
12650 let addrMode = BaseRegOffset;
12651 let accessSize = HalfWordAccess;
12652 let isPredicatedNew = 1;
12654 let CextOpcode = "L2_loadrh";
12655 let InputType = "reg";
12656 let BaseOpcode = "L4_loadrh_rr";
12658 def L4_ploadrht_abs : HInst<
12659 (outs IntRegs:$Rd32),
12660 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12661 "if ($Pt4) $Rd32 = memh(#$Ii)",
12662 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12663 let Inst{7-5} = 0b100;
12664 let Inst{13-11} = 0b100;
12665 let Inst{31-21} = 0b10011111010;
12666 let isPredicated = 1;
12667 let hasNewValue = 1;
12668 let opNewValue = 0;
12669 let addrMode = Absolute;
12670 let accessSize = HalfWordAccess;
12672 let isExtended = 1;
12673 let CextOpcode = "L2_loadrh";
12674 let BaseOpcode = "L4_loadrh_abs";
12675 let DecoderNamespace = "MustExtend";
12676 let isExtendable = 1;
12677 let opExtendable = 2;
12678 let isExtentSigned = 0;
12679 let opExtentBits = 6;
12680 let opExtentAlign = 0;
12682 def L4_ploadrht_rr : HInst<
12683 (outs IntRegs:$Rd32),
12684 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12685 "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12686 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12687 let Inst{31-21} = 0b00110000010;
12688 let isPredicated = 1;
12689 let hasNewValue = 1;
12690 let opNewValue = 0;
12691 let addrMode = BaseRegOffset;
12692 let accessSize = HalfWordAccess;
12694 let CextOpcode = "L2_loadrh";
12695 let InputType = "reg";
12696 let BaseOpcode = "L4_loadrh_rr";
12698 def L4_ploadrhtnew_abs : HInst<
12699 (outs IntRegs:$Rd32),
12700 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12701 "if ($Pt4.new) $Rd32 = memh(#$Ii)",
12702 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12703 let Inst{7-5} = 0b100;
12704 let Inst{13-11} = 0b110;
12705 let Inst{31-21} = 0b10011111010;
12706 let isPredicated = 1;
12707 let hasNewValue = 1;
12708 let opNewValue = 0;
12709 let addrMode = Absolute;
12710 let accessSize = HalfWordAccess;
12711 let isPredicatedNew = 1;
12713 let isExtended = 1;
12714 let CextOpcode = "L2_loadrh";
12715 let BaseOpcode = "L4_loadrh_abs";
12716 let DecoderNamespace = "MustExtend";
12717 let isExtendable = 1;
12718 let opExtendable = 2;
12719 let isExtentSigned = 0;
12720 let opExtentBits = 6;
12721 let opExtentAlign = 0;
12723 def L4_ploadrhtnew_rr : HInst<
12724 (outs IntRegs:$Rd32),
12725 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12726 "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12727 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12728 let Inst{31-21} = 0b00110010010;
12729 let isPredicated = 1;
12730 let hasNewValue = 1;
12731 let opNewValue = 0;
12732 let addrMode = BaseRegOffset;
12733 let accessSize = HalfWordAccess;
12734 let isPredicatedNew = 1;
12736 let CextOpcode = "L2_loadrh";
12737 let InputType = "reg";
12738 let BaseOpcode = "L4_loadrh_rr";
12740 def L4_ploadrif_abs : HInst<
12741 (outs IntRegs:$Rd32),
12742 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12743 "if (!$Pt4) $Rd32 = memw(#$Ii)",
12744 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12745 let Inst{7-5} = 0b100;
12746 let Inst{13-11} = 0b101;
12747 let Inst{31-21} = 0b10011111100;
12748 let isPredicated = 1;
12749 let isPredicatedFalse = 1;
12750 let hasNewValue = 1;
12751 let opNewValue = 0;
12752 let addrMode = Absolute;
12753 let accessSize = WordAccess;
12755 let isExtended = 1;
12756 let CextOpcode = "L2_loadri";
12757 let BaseOpcode = "L4_loadri_abs";
12758 let DecoderNamespace = "MustExtend";
12759 let isExtendable = 1;
12760 let opExtendable = 2;
12761 let isExtentSigned = 0;
12762 let opExtentBits = 6;
12763 let opExtentAlign = 0;
12765 def L4_ploadrif_rr : HInst<
12766 (outs IntRegs:$Rd32),
12767 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12768 "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12769 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12770 let Inst{31-21} = 0b00110001100;
12771 let isPredicated = 1;
12772 let isPredicatedFalse = 1;
12773 let hasNewValue = 1;
12774 let opNewValue = 0;
12775 let addrMode = BaseRegOffset;
12776 let accessSize = WordAccess;
12778 let CextOpcode = "L2_loadri";
12779 let InputType = "reg";
12780 let BaseOpcode = "L4_loadri_rr";
12782 def L4_ploadrifnew_abs : HInst<
12783 (outs IntRegs:$Rd32),
12784 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12785 "if (!$Pt4.new) $Rd32 = memw(#$Ii)",
12786 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12787 let Inst{7-5} = 0b100;
12788 let Inst{13-11} = 0b111;
12789 let Inst{31-21} = 0b10011111100;
12790 let isPredicated = 1;
12791 let isPredicatedFalse = 1;
12792 let hasNewValue = 1;
12793 let opNewValue = 0;
12794 let addrMode = Absolute;
12795 let accessSize = WordAccess;
12796 let isPredicatedNew = 1;
12798 let isExtended = 1;
12799 let CextOpcode = "L2_loadri";
12800 let BaseOpcode = "L4_loadri_abs";
12801 let DecoderNamespace = "MustExtend";
12802 let isExtendable = 1;
12803 let opExtendable = 2;
12804 let isExtentSigned = 0;
12805 let opExtentBits = 6;
12806 let opExtentAlign = 0;
12808 def L4_ploadrifnew_rr : HInst<
12809 (outs IntRegs:$Rd32),
12810 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12811 "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12812 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12813 let Inst{31-21} = 0b00110011100;
12814 let isPredicated = 1;
12815 let isPredicatedFalse = 1;
12816 let hasNewValue = 1;
12817 let opNewValue = 0;
12818 let addrMode = BaseRegOffset;
12819 let accessSize = WordAccess;
12820 let isPredicatedNew = 1;
12822 let CextOpcode = "L2_loadri";
12823 let InputType = "reg";
12824 let BaseOpcode = "L4_loadri_rr";
12826 def L4_ploadrit_abs : HInst<
12827 (outs IntRegs:$Rd32),
12828 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12829 "if ($Pt4) $Rd32 = memw(#$Ii)",
12830 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12831 let Inst{7-5} = 0b100;
12832 let Inst{13-11} = 0b100;
12833 let Inst{31-21} = 0b10011111100;
12834 let isPredicated = 1;
12835 let hasNewValue = 1;
12836 let opNewValue = 0;
12837 let addrMode = Absolute;
12838 let accessSize = WordAccess;
12840 let isExtended = 1;
12841 let CextOpcode = "L2_loadri";
12842 let BaseOpcode = "L4_loadri_abs";
12843 let DecoderNamespace = "MustExtend";
12844 let isExtendable = 1;
12845 let opExtendable = 2;
12846 let isExtentSigned = 0;
12847 let opExtentBits = 6;
12848 let opExtentAlign = 0;
12850 def L4_ploadrit_rr : HInst<
12851 (outs IntRegs:$Rd32),
12852 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12853 "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12854 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12855 let Inst{31-21} = 0b00110000100;
12856 let isPredicated = 1;
12857 let hasNewValue = 1;
12858 let opNewValue = 0;
12859 let addrMode = BaseRegOffset;
12860 let accessSize = WordAccess;
12862 let CextOpcode = "L2_loadri";
12863 let InputType = "reg";
12864 let BaseOpcode = "L4_loadri_rr";
12866 def L4_ploadritnew_abs : HInst<
12867 (outs IntRegs:$Rd32),
12868 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12869 "if ($Pt4.new) $Rd32 = memw(#$Ii)",
12870 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12871 let Inst{7-5} = 0b100;
12872 let Inst{13-11} = 0b110;
12873 let Inst{31-21} = 0b10011111100;
12874 let isPredicated = 1;
12875 let hasNewValue = 1;
12876 let opNewValue = 0;
12877 let addrMode = Absolute;
12878 let accessSize = WordAccess;
12879 let isPredicatedNew = 1;
12881 let isExtended = 1;
12882 let CextOpcode = "L2_loadri";
12883 let BaseOpcode = "L4_loadri_abs";
12884 let DecoderNamespace = "MustExtend";
12885 let isExtendable = 1;
12886 let opExtendable = 2;
12887 let isExtentSigned = 0;
12888 let opExtentBits = 6;
12889 let opExtentAlign = 0;
12891 def L4_ploadritnew_rr : HInst<
12892 (outs IntRegs:$Rd32),
12893 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12894 "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12895 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12896 let Inst{31-21} = 0b00110010100;
12897 let isPredicated = 1;
12898 let hasNewValue = 1;
12899 let opNewValue = 0;
12900 let addrMode = BaseRegOffset;
12901 let accessSize = WordAccess;
12902 let isPredicatedNew = 1;
12904 let CextOpcode = "L2_loadri";
12905 let InputType = "reg";
12906 let BaseOpcode = "L4_loadri_rr";
12908 def L4_ploadrubf_abs : HInst<
12909 (outs IntRegs:$Rd32),
12910 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12911 "if (!$Pt4) $Rd32 = memub(#$Ii)",
12912 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12913 let Inst{7-5} = 0b100;
12914 let Inst{13-11} = 0b101;
12915 let Inst{31-21} = 0b10011111001;
12916 let isPredicated = 1;
12917 let isPredicatedFalse = 1;
12918 let hasNewValue = 1;
12919 let opNewValue = 0;
12920 let addrMode = Absolute;
12921 let accessSize = ByteAccess;
12923 let isExtended = 1;
12924 let CextOpcode = "L2_loadrub";
12925 let BaseOpcode = "L4_loadrub_abs";
12926 let DecoderNamespace = "MustExtend";
12927 let isExtendable = 1;
12928 let opExtendable = 2;
12929 let isExtentSigned = 0;
12930 let opExtentBits = 6;
12931 let opExtentAlign = 0;
12933 def L4_ploadrubf_rr : HInst<
12934 (outs IntRegs:$Rd32),
12935 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12936 "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12937 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
12938 let Inst{31-21} = 0b00110001001;
12939 let isPredicated = 1;
12940 let isPredicatedFalse = 1;
12941 let hasNewValue = 1;
12942 let opNewValue = 0;
12943 let addrMode = BaseRegOffset;
12944 let accessSize = ByteAccess;
12946 let CextOpcode = "L2_loadrub";
12947 let InputType = "reg";
12948 let BaseOpcode = "L4_loadrub_rr";
12950 def L4_ploadrubfnew_abs : HInst<
12951 (outs IntRegs:$Rd32),
12952 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12953 "if (!$Pt4.new) $Rd32 = memub(#$Ii)",
12954 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
12955 let Inst{7-5} = 0b100;
12956 let Inst{13-11} = 0b111;
12957 let Inst{31-21} = 0b10011111001;
12958 let isPredicated = 1;
12959 let isPredicatedFalse = 1;
12960 let hasNewValue = 1;
12961 let opNewValue = 0;
12962 let addrMode = Absolute;
12963 let accessSize = ByteAccess;
12964 let isPredicatedNew = 1;
12966 let isExtended = 1;
12967 let CextOpcode = "L2_loadrub";
12968 let BaseOpcode = "L4_loadrub_abs";
12969 let DecoderNamespace = "MustExtend";
12970 let isExtendable = 1;
12971 let opExtendable = 2;
12972 let isExtentSigned = 0;
12973 let opExtentBits = 6;
12974 let opExtentAlign = 0;
12976 def L4_ploadrubfnew_rr : HInst<
12977 (outs IntRegs:$Rd32),
12978 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12979 "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12980 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
12981 let Inst{31-21} = 0b00110011001;
12982 let isPredicated = 1;
12983 let isPredicatedFalse = 1;
12984 let hasNewValue = 1;
12985 let opNewValue = 0;
12986 let addrMode = BaseRegOffset;
12987 let accessSize = ByteAccess;
12988 let isPredicatedNew = 1;
12990 let CextOpcode = "L2_loadrub";
12991 let InputType = "reg";
12992 let BaseOpcode = "L4_loadrub_rr";
12994 def L4_ploadrubt_abs : HInst<
12995 (outs IntRegs:$Rd32),
12996 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
12997 "if ($Pt4) $Rd32 = memub(#$Ii)",
12998 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
12999 let Inst{7-5} = 0b100;
13000 let Inst{13-11} = 0b100;
13001 let Inst{31-21} = 0b10011111001;
13002 let isPredicated = 1;
13003 let hasNewValue = 1;
13004 let opNewValue = 0;
13005 let addrMode = Absolute;
13006 let accessSize = ByteAccess;
13008 let isExtended = 1;
13009 let CextOpcode = "L2_loadrub";
13010 let BaseOpcode = "L4_loadrub_abs";
13011 let DecoderNamespace = "MustExtend";
13012 let isExtendable = 1;
13013 let opExtendable = 2;
13014 let isExtentSigned = 0;
13015 let opExtentBits = 6;
13016 let opExtentAlign = 0;
13018 def L4_ploadrubt_rr : HInst<
13019 (outs IntRegs:$Rd32),
13020 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13021 "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13022 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
13023 let Inst{31-21} = 0b00110000001;
13024 let isPredicated = 1;
13025 let hasNewValue = 1;
13026 let opNewValue = 0;
13027 let addrMode = BaseRegOffset;
13028 let accessSize = ByteAccess;
13030 let CextOpcode = "L2_loadrub";
13031 let InputType = "reg";
13032 let BaseOpcode = "L4_loadrub_rr";
13034 def L4_ploadrubtnew_abs : HInst<
13035 (outs IntRegs:$Rd32),
13036 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
13037 "if ($Pt4.new) $Rd32 = memub(#$Ii)",
13038 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
13039 let Inst{7-5} = 0b100;
13040 let Inst{13-11} = 0b110;
13041 let Inst{31-21} = 0b10011111001;
13042 let isPredicated = 1;
13043 let hasNewValue = 1;
13044 let opNewValue = 0;
13045 let addrMode = Absolute;
13046 let accessSize = ByteAccess;
13047 let isPredicatedNew = 1;
13049 let isExtended = 1;
13050 let CextOpcode = "L2_loadrub";
13051 let BaseOpcode = "L4_loadrub_abs";
13052 let DecoderNamespace = "MustExtend";
13053 let isExtendable = 1;
13054 let opExtendable = 2;
13055 let isExtentSigned = 0;
13056 let opExtentBits = 6;
13057 let opExtentAlign = 0;
13059 def L4_ploadrubtnew_rr : HInst<
13060 (outs IntRegs:$Rd32),
13061 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13062 "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13063 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
13064 let Inst{31-21} = 0b00110010001;
13065 let isPredicated = 1;
13066 let hasNewValue = 1;
13067 let opNewValue = 0;
13068 let addrMode = BaseRegOffset;
13069 let accessSize = ByteAccess;
13070 let isPredicatedNew = 1;
13072 let CextOpcode = "L2_loadrub";
13073 let InputType = "reg";
13074 let BaseOpcode = "L4_loadrub_rr";
13076 def L4_ploadruhf_abs : HInst<
13077 (outs IntRegs:$Rd32),
13078 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
13079 "if (!$Pt4) $Rd32 = memuh(#$Ii)",
13080 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
13081 let Inst{7-5} = 0b100;
13082 let Inst{13-11} = 0b101;
13083 let Inst{31-21} = 0b10011111011;
13084 let isPredicated = 1;
13085 let isPredicatedFalse = 1;
13086 let hasNewValue = 1;
13087 let opNewValue = 0;
13088 let addrMode = Absolute;
13089 let accessSize = HalfWordAccess;
13091 let isExtended = 1;
13092 let CextOpcode = "L2_loadruh";
13093 let BaseOpcode = "L4_loadruh_abs";
13094 let DecoderNamespace = "MustExtend";
13095 let isExtendable = 1;
13096 let opExtendable = 2;
13097 let isExtentSigned = 0;
13098 let opExtentBits = 6;
13099 let opExtentAlign = 0;
13101 def L4_ploadruhf_rr : HInst<
13102 (outs IntRegs:$Rd32),
13103 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13104 "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13105 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
13106 let Inst{31-21} = 0b00110001011;
13107 let isPredicated = 1;
13108 let isPredicatedFalse = 1;
13109 let hasNewValue = 1;
13110 let opNewValue = 0;
13111 let addrMode = BaseRegOffset;
13112 let accessSize = HalfWordAccess;
13114 let CextOpcode = "L2_loadruh";
13115 let InputType = "reg";
13116 let BaseOpcode = "L4_loadruh_rr";
13118 def L4_ploadruhfnew_abs : HInst<
13119 (outs IntRegs:$Rd32),
13120 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
13121 "if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13122 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
13123 let Inst{7-5} = 0b100;
13124 let Inst{13-11} = 0b111;
13125 let Inst{31-21} = 0b10011111011;
13126 let isPredicated = 1;
13127 let isPredicatedFalse = 1;
13128 let hasNewValue = 1;
13129 let opNewValue = 0;
13130 let addrMode = Absolute;
13131 let accessSize = HalfWordAccess;
13132 let isPredicatedNew = 1;
13134 let isExtended = 1;
13135 let CextOpcode = "L2_loadruh";
13136 let BaseOpcode = "L4_loadruh_abs";
13137 let DecoderNamespace = "MustExtend";
13138 let isExtendable = 1;
13139 let opExtendable = 2;
13140 let isExtentSigned = 0;
13141 let opExtentBits = 6;
13142 let opExtentAlign = 0;
13144 def L4_ploadruhfnew_rr : HInst<
13145 (outs IntRegs:$Rd32),
13146 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13147 "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13148 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
13149 let Inst{31-21} = 0b00110011011;
13150 let isPredicated = 1;
13151 let isPredicatedFalse = 1;
13152 let hasNewValue = 1;
13153 let opNewValue = 0;
13154 let addrMode = BaseRegOffset;
13155 let accessSize = HalfWordAccess;
13156 let isPredicatedNew = 1;
13158 let CextOpcode = "L2_loadruh";
13159 let InputType = "reg";
13160 let BaseOpcode = "L4_loadruh_rr";
13162 def L4_ploadruht_abs : HInst<
13163 (outs IntRegs:$Rd32),
13164 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
13165 "if ($Pt4) $Rd32 = memuh(#$Ii)",
13166 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
13167 let Inst{7-5} = 0b100;
13168 let Inst{13-11} = 0b100;
13169 let Inst{31-21} = 0b10011111011;
13170 let isPredicated = 1;
13171 let hasNewValue = 1;
13172 let opNewValue = 0;
13173 let addrMode = Absolute;
13174 let accessSize = HalfWordAccess;
13176 let isExtended = 1;
13177 let CextOpcode = "L2_loadruh";
13178 let BaseOpcode = "L4_loadruh_abs";
13179 let DecoderNamespace = "MustExtend";
13180 let isExtendable = 1;
13181 let opExtendable = 2;
13182 let isExtentSigned = 0;
13183 let opExtentBits = 6;
13184 let opExtentAlign = 0;
13186 def L4_ploadruht_rr : HInst<
13187 (outs IntRegs:$Rd32),
13188 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13189 "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13190 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
13191 let Inst{31-21} = 0b00110000011;
13192 let isPredicated = 1;
13193 let hasNewValue = 1;
13194 let opNewValue = 0;
13195 let addrMode = BaseRegOffset;
13196 let accessSize = HalfWordAccess;
13198 let CextOpcode = "L2_loadruh";
13199 let InputType = "reg";
13200 let BaseOpcode = "L4_loadruh_rr";
13202 def L4_ploadruhtnew_abs : HInst<
13203 (outs IntRegs:$Rd32),
13204 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
13205 "if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13206 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
13207 let Inst{7-5} = 0b100;
13208 let Inst{13-11} = 0b110;
13209 let Inst{31-21} = 0b10011111011;
13210 let isPredicated = 1;
13211 let hasNewValue = 1;
13212 let opNewValue = 0;
13213 let addrMode = Absolute;
13214 let accessSize = HalfWordAccess;
13215 let isPredicatedNew = 1;
13217 let isExtended = 1;
13218 let CextOpcode = "L2_loadruh";
13219 let BaseOpcode = "L4_loadruh_abs";
13220 let DecoderNamespace = "MustExtend";
13221 let isExtendable = 1;
13222 let opExtendable = 2;
13223 let isExtentSigned = 0;
13224 let opExtentBits = 6;
13225 let opExtentAlign = 0;
13227 def L4_ploadruhtnew_rr : HInst<
13228 (outs IntRegs:$Rd32),
13229 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13230 "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13231 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
13232 let Inst{31-21} = 0b00110010011;
13233 let isPredicated = 1;
13234 let hasNewValue = 1;
13235 let opNewValue = 0;
13236 let addrMode = BaseRegOffset;
13237 let accessSize = HalfWordAccess;
13238 let isPredicatedNew = 1;
13240 let CextOpcode = "L2_loadruh";
13241 let InputType = "reg";
13242 let BaseOpcode = "L4_loadruh_rr";
13244 def L4_return : HInst<
13245 (outs DoubleRegs:$Rdd32),
13246 (ins IntRegs:$Rs32),
13247 "$Rdd32 = dealloc_return($Rs32):raw",
13248 tc_3d04548d, TypeLD>, Enc_3a3d62, PredNewRel {
13249 let Inst{13-5} = 0b000000000;
13250 let Inst{31-21} = 0b10010110000;
13251 let isTerminator = 1;
13252 let isIndirectBranch = 1;
13253 let accessSize = DoubleWordAccess;
13256 let isRestrictNoSlot1Store = 1;
13258 let Uses = [FRAMEKEY];
13259 let Defs = [PC, R29];
13260 let BaseOpcode = "L4_return";
13262 let isPredicable = 1;
13265 def L4_return_f : HInst<
13266 (outs DoubleRegs:$Rdd32),
13267 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13268 "if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13269 tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
13270 let Inst{7-5} = 0b000;
13271 let Inst{13-10} = 0b1100;
13272 let Inst{31-21} = 0b10010110000;
13273 let isPredicated = 1;
13274 let isPredicatedFalse = 1;
13275 let isTerminator = 1;
13276 let isIndirectBranch = 1;
13277 let accessSize = DoubleWordAccess;
13280 let isRestrictNoSlot1Store = 1;
13282 let Uses = [FRAMEKEY];
13283 let Defs = [PC, R29];
13284 let BaseOpcode = "L4_return";
13285 let isTaken = Inst{12};
13287 def L4_return_fnew_pnt : HInst<
13288 (outs DoubleRegs:$Rdd32),
13289 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13290 "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13291 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
13292 let Inst{7-5} = 0b000;
13293 let Inst{13-10} = 0b1010;
13294 let Inst{31-21} = 0b10010110000;
13295 let isPredicated = 1;
13296 let isPredicatedFalse = 1;
13297 let isTerminator = 1;
13298 let isIndirectBranch = 1;
13299 let accessSize = DoubleWordAccess;
13300 let isPredicatedNew = 1;
13303 let isRestrictNoSlot1Store = 1;
13305 let Uses = [FRAMEKEY];
13306 let Defs = [PC, R29];
13307 let BaseOpcode = "L4_return";
13308 let isTaken = Inst{12};
13310 def L4_return_fnew_pt : HInst<
13311 (outs DoubleRegs:$Rdd32),
13312 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13313 "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13314 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
13315 let Inst{7-5} = 0b000;
13316 let Inst{13-10} = 0b1110;
13317 let Inst{31-21} = 0b10010110000;
13318 let isPredicated = 1;
13319 let isPredicatedFalse = 1;
13320 let isTerminator = 1;
13321 let isIndirectBranch = 1;
13322 let accessSize = DoubleWordAccess;
13323 let isPredicatedNew = 1;
13326 let isRestrictNoSlot1Store = 1;
13328 let Uses = [FRAMEKEY];
13329 let Defs = [PC, R29];
13330 let BaseOpcode = "L4_return";
13331 let isTaken = Inst{12};
13333 def L4_return_map_to_raw_f : HInst<
13335 (ins PredRegs:$Pv4),
13336 "if (!$Pv4) dealloc_return",
13337 tc_513bef45, TypeMAPPING>, Requires<[HasV65T]> {
13339 let isCodeGenOnly = 1;
13341 def L4_return_map_to_raw_fnew_pnt : HInst<
13343 (ins PredRegs:$Pv4),
13344 "if (!$Pv4.new) dealloc_return:nt",
13345 tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> {
13347 let isCodeGenOnly = 1;
13349 def L4_return_map_to_raw_fnew_pt : HInst<
13351 (ins PredRegs:$Pv4),
13352 "if (!$Pv4.new) dealloc_return:t",
13353 tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> {
13355 let isCodeGenOnly = 1;
13357 def L4_return_map_to_raw_t : HInst<
13359 (ins PredRegs:$Pv4),
13360 "if ($Pv4) dealloc_return",
13361 tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65T]> {
13363 let isCodeGenOnly = 1;
13365 def L4_return_map_to_raw_tnew_pnt : HInst<
13367 (ins PredRegs:$Pv4),
13368 "if ($Pv4.new) dealloc_return:nt",
13369 tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> {
13371 let isCodeGenOnly = 1;
13373 def L4_return_map_to_raw_tnew_pt : HInst<
13375 (ins PredRegs:$Pv4),
13376 "if ($Pv4.new) dealloc_return:t",
13377 tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> {
13379 let isCodeGenOnly = 1;
13381 def L4_return_t : HInst<
13382 (outs DoubleRegs:$Rdd32),
13383 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13384 "if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13385 tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
13386 let Inst{7-5} = 0b000;
13387 let Inst{13-10} = 0b0100;
13388 let Inst{31-21} = 0b10010110000;
13389 let isPredicated = 1;
13390 let isTerminator = 1;
13391 let isIndirectBranch = 1;
13392 let accessSize = DoubleWordAccess;
13395 let isRestrictNoSlot1Store = 1;
13397 let Uses = [FRAMEKEY];
13398 let Defs = [PC, R29];
13399 let BaseOpcode = "L4_return";
13400 let isTaken = Inst{12};
13402 def L4_return_tnew_pnt : HInst<
13403 (outs DoubleRegs:$Rdd32),
13404 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13405 "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13406 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
13407 let Inst{7-5} = 0b000;
13408 let Inst{13-10} = 0b0010;
13409 let Inst{31-21} = 0b10010110000;
13410 let isPredicated = 1;
13411 let isTerminator = 1;
13412 let isIndirectBranch = 1;
13413 let accessSize = DoubleWordAccess;
13414 let isPredicatedNew = 1;
13417 let isRestrictNoSlot1Store = 1;
13419 let Uses = [FRAMEKEY];
13420 let Defs = [PC, R29];
13421 let BaseOpcode = "L4_return";
13422 let isTaken = Inst{12};
13424 def L4_return_tnew_pt : HInst<
13425 (outs DoubleRegs:$Rdd32),
13426 (ins PredRegs:$Pv4, IntRegs:$Rs32),
13427 "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13428 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
13429 let Inst{7-5} = 0b000;
13430 let Inst{13-10} = 0b0110;
13431 let Inst{31-21} = 0b10010110000;
13432 let isPredicated = 1;
13433 let isTerminator = 1;
13434 let isIndirectBranch = 1;
13435 let accessSize = DoubleWordAccess;
13436 let isPredicatedNew = 1;
13439 let isRestrictNoSlot1Store = 1;
13441 let Uses = [FRAMEKEY];
13442 let Defs = [PC, R29];
13443 let BaseOpcode = "L4_return";
13444 let isTaken = Inst{12};
13446 def L4_sub_memopb_io : HInst<
13448 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13449 "memb($Rs32+#$Ii) -= $Rt32",
13450 tc_44126683, TypeV4LDST>, Enc_d44e31 {
13451 let Inst{6-5} = 0b01;
13452 let Inst{13-13} = 0b0;
13453 let Inst{31-21} = 0b00111110000;
13454 let addrMode = BaseImmOffset;
13455 let accessSize = ByteAccess;
13457 let isRestrictNoSlot1Store = 1;
13459 let isExtendable = 1;
13460 let opExtendable = 1;
13461 let isExtentSigned = 0;
13462 let opExtentBits = 6;
13463 let opExtentAlign = 0;
13465 def L4_sub_memopb_zomap : HInst<
13467 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13468 "memb($Rs32) -= $Rt32",
13469 tc_44126683, TypeMAPPING> {
13471 let isCodeGenOnly = 1;
13473 def L4_sub_memoph_io : HInst<
13475 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13476 "memh($Rs32+#$Ii) -= $Rt32",
13477 tc_44126683, TypeV4LDST>, Enc_163a3c {
13478 let Inst{6-5} = 0b01;
13479 let Inst{13-13} = 0b0;
13480 let Inst{31-21} = 0b00111110001;
13481 let addrMode = BaseImmOffset;
13482 let accessSize = HalfWordAccess;
13484 let isRestrictNoSlot1Store = 1;
13486 let isExtendable = 1;
13487 let opExtendable = 1;
13488 let isExtentSigned = 0;
13489 let opExtentBits = 7;
13490 let opExtentAlign = 1;
13492 def L4_sub_memoph_zomap : HInst<
13494 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13495 "memh($Rs32) -= $Rt32",
13496 tc_44126683, TypeMAPPING> {
13498 let isCodeGenOnly = 1;
13500 def L4_sub_memopw_io : HInst<
13502 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13503 "memw($Rs32+#$Ii) -= $Rt32",
13504 tc_44126683, TypeV4LDST>, Enc_226535 {
13505 let Inst{6-5} = 0b01;
13506 let Inst{13-13} = 0b0;
13507 let Inst{31-21} = 0b00111110010;
13508 let addrMode = BaseImmOffset;
13509 let accessSize = WordAccess;
13511 let isRestrictNoSlot1Store = 1;
13513 let isExtendable = 1;
13514 let opExtendable = 1;
13515 let isExtentSigned = 0;
13516 let opExtentBits = 8;
13517 let opExtentAlign = 2;
13519 def L4_sub_memopw_zomap : HInst<
13521 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13522 "memw($Rs32) -= $Rt32",
13523 tc_44126683, TypeMAPPING> {
13525 let isCodeGenOnly = 1;
13527 def L6_deallocframe_map_to_raw : HInst<
13531 tc_d1090e34, TypeMAPPING>, Requires<[HasV65T]> {
13533 let isCodeGenOnly = 1;
13535 def L6_return_map_to_raw : HInst<
13539 tc_3d04548d, TypeMAPPING>, Requires<[HasV65T]> {
13541 let isCodeGenOnly = 1;
13543 def M2_acci : HInst<
13544 (outs IntRegs:$Rx32),
13545 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13546 "$Rx32 += add($Rs32,$Rt32)",
13547 tc_c74f796f, TypeM>, Enc_2ae154, ImmRegRel {
13548 let Inst{7-5} = 0b001;
13549 let Inst{13-13} = 0b0;
13550 let Inst{31-21} = 0b11101111000;
13551 let hasNewValue = 1;
13552 let opNewValue = 0;
13553 let prefersSlot3 = 1;
13554 let CextOpcode = "M2_acci";
13555 let InputType = "reg";
13556 let Constraints = "$Rx32 = $Rx32in";
13558 def M2_accii : HInst<
13559 (outs IntRegs:$Rx32),
13560 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13561 "$Rx32 += add($Rs32,#$Ii)",
13562 tc_c74f796f, TypeM>, Enc_c90aca, ImmRegRel {
13563 let Inst{13-13} = 0b0;
13564 let Inst{31-21} = 0b11100010000;
13565 let hasNewValue = 1;
13566 let opNewValue = 0;
13567 let prefersSlot3 = 1;
13568 let CextOpcode = "M2_acci";
13569 let InputType = "imm";
13570 let isExtendable = 1;
13571 let opExtendable = 3;
13572 let isExtentSigned = 1;
13573 let opExtentBits = 8;
13574 let opExtentAlign = 0;
13575 let Constraints = "$Rx32 = $Rx32in";
13577 def M2_cmaci_s0 : HInst<
13578 (outs DoubleRegs:$Rxx32),
13579 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13580 "$Rxx32 += cmpyi($Rs32,$Rt32)",
13581 tc_e913dc32, TypeM>, Enc_61f0b0 {
13582 let Inst{7-5} = 0b001;
13583 let Inst{13-13} = 0b0;
13584 let Inst{31-21} = 0b11100111000;
13585 let prefersSlot3 = 1;
13586 let Constraints = "$Rxx32 = $Rxx32in";
13588 def M2_cmacr_s0 : HInst<
13589 (outs DoubleRegs:$Rxx32),
13590 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13591 "$Rxx32 += cmpyr($Rs32,$Rt32)",
13592 tc_e913dc32, TypeM>, Enc_61f0b0 {
13593 let Inst{7-5} = 0b010;
13594 let Inst{13-13} = 0b0;
13595 let Inst{31-21} = 0b11100111000;
13596 let prefersSlot3 = 1;
13597 let Constraints = "$Rxx32 = $Rxx32in";
13599 def M2_cmacs_s0 : HInst<
13600 (outs DoubleRegs:$Rxx32),
13601 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13602 "$Rxx32 += cmpy($Rs32,$Rt32):sat",
13603 tc_e913dc32, TypeM>, Enc_61f0b0 {
13604 let Inst{7-5} = 0b110;
13605 let Inst{13-13} = 0b0;
13606 let Inst{31-21} = 0b11100111000;
13607 let prefersSlot3 = 1;
13608 let Defs = [USR_OVF];
13609 let Constraints = "$Rxx32 = $Rxx32in";
13611 def M2_cmacs_s1 : HInst<
13612 (outs DoubleRegs:$Rxx32),
13613 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13614 "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13615 tc_e913dc32, TypeM>, Enc_61f0b0 {
13616 let Inst{7-5} = 0b110;
13617 let Inst{13-13} = 0b0;
13618 let Inst{31-21} = 0b11100111100;
13619 let prefersSlot3 = 1;
13620 let Defs = [USR_OVF];
13621 let Constraints = "$Rxx32 = $Rxx32in";
13623 def M2_cmacsc_s0 : HInst<
13624 (outs DoubleRegs:$Rxx32),
13625 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13626 "$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13627 tc_e913dc32, TypeM>, Enc_61f0b0 {
13628 let Inst{7-5} = 0b110;
13629 let Inst{13-13} = 0b0;
13630 let Inst{31-21} = 0b11100111010;
13631 let prefersSlot3 = 1;
13632 let Defs = [USR_OVF];
13633 let Constraints = "$Rxx32 = $Rxx32in";
13635 def M2_cmacsc_s1 : HInst<
13636 (outs DoubleRegs:$Rxx32),
13637 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13638 "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13639 tc_e913dc32, TypeM>, Enc_61f0b0 {
13640 let Inst{7-5} = 0b110;
13641 let Inst{13-13} = 0b0;
13642 let Inst{31-21} = 0b11100111110;
13643 let prefersSlot3 = 1;
13644 let Defs = [USR_OVF];
13645 let Constraints = "$Rxx32 = $Rxx32in";
13647 def M2_cmpyi_s0 : HInst<
13648 (outs DoubleRegs:$Rdd32),
13649 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13650 "$Rdd32 = cmpyi($Rs32,$Rt32)",
13651 tc_8fd5f294, TypeM>, Enc_be32a5 {
13652 let Inst{7-5} = 0b001;
13653 let Inst{13-13} = 0b0;
13654 let Inst{31-21} = 0b11100101000;
13655 let prefersSlot3 = 1;
13657 def M2_cmpyr_s0 : HInst<
13658 (outs DoubleRegs:$Rdd32),
13659 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13660 "$Rdd32 = cmpyr($Rs32,$Rt32)",
13661 tc_8fd5f294, TypeM>, Enc_be32a5 {
13662 let Inst{7-5} = 0b010;
13663 let Inst{13-13} = 0b0;
13664 let Inst{31-21} = 0b11100101000;
13665 let prefersSlot3 = 1;
13667 def M2_cmpyrs_s0 : HInst<
13668 (outs IntRegs:$Rd32),
13669 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13670 "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13671 tc_8fd5f294, TypeM>, Enc_5ab2be {
13672 let Inst{7-5} = 0b110;
13673 let Inst{13-13} = 0b0;
13674 let Inst{31-21} = 0b11101101001;
13675 let hasNewValue = 1;
13676 let opNewValue = 0;
13677 let prefersSlot3 = 1;
13678 let Defs = [USR_OVF];
13680 def M2_cmpyrs_s1 : HInst<
13681 (outs IntRegs:$Rd32),
13682 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13683 "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13684 tc_8fd5f294, TypeM>, Enc_5ab2be {
13685 let Inst{7-5} = 0b110;
13686 let Inst{13-13} = 0b0;
13687 let Inst{31-21} = 0b11101101101;
13688 let hasNewValue = 1;
13689 let opNewValue = 0;
13690 let prefersSlot3 = 1;
13691 let Defs = [USR_OVF];
13693 def M2_cmpyrsc_s0 : HInst<
13694 (outs IntRegs:$Rd32),
13695 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13696 "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13697 tc_8fd5f294, TypeM>, Enc_5ab2be {
13698 let Inst{7-5} = 0b110;
13699 let Inst{13-13} = 0b0;
13700 let Inst{31-21} = 0b11101101011;
13701 let hasNewValue = 1;
13702 let opNewValue = 0;
13703 let prefersSlot3 = 1;
13704 let Defs = [USR_OVF];
13706 def M2_cmpyrsc_s1 : HInst<
13707 (outs IntRegs:$Rd32),
13708 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13709 "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13710 tc_8fd5f294, TypeM>, Enc_5ab2be {
13711 let Inst{7-5} = 0b110;
13712 let Inst{13-13} = 0b0;
13713 let Inst{31-21} = 0b11101101111;
13714 let hasNewValue = 1;
13715 let opNewValue = 0;
13716 let prefersSlot3 = 1;
13717 let Defs = [USR_OVF];
13719 def M2_cmpys_s0 : HInst<
13720 (outs DoubleRegs:$Rdd32),
13721 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13722 "$Rdd32 = cmpy($Rs32,$Rt32):sat",
13723 tc_8fd5f294, TypeM>, Enc_be32a5 {
13724 let Inst{7-5} = 0b110;
13725 let Inst{13-13} = 0b0;
13726 let Inst{31-21} = 0b11100101000;
13727 let prefersSlot3 = 1;
13728 let Defs = [USR_OVF];
13730 def M2_cmpys_s1 : HInst<
13731 (outs DoubleRegs:$Rdd32),
13732 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13733 "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
13734 tc_8fd5f294, TypeM>, Enc_be32a5 {
13735 let Inst{7-5} = 0b110;
13736 let Inst{13-13} = 0b0;
13737 let Inst{31-21} = 0b11100101100;
13738 let prefersSlot3 = 1;
13739 let Defs = [USR_OVF];
13741 def M2_cmpysc_s0 : HInst<
13742 (outs DoubleRegs:$Rdd32),
13743 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13744 "$Rdd32 = cmpy($Rs32,$Rt32*):sat",
13745 tc_8fd5f294, TypeM>, Enc_be32a5 {
13746 let Inst{7-5} = 0b110;
13747 let Inst{13-13} = 0b0;
13748 let Inst{31-21} = 0b11100101010;
13749 let prefersSlot3 = 1;
13750 let Defs = [USR_OVF];
13752 def M2_cmpysc_s1 : HInst<
13753 (outs DoubleRegs:$Rdd32),
13754 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13755 "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
13756 tc_8fd5f294, TypeM>, Enc_be32a5 {
13757 let Inst{7-5} = 0b110;
13758 let Inst{13-13} = 0b0;
13759 let Inst{31-21} = 0b11100101110;
13760 let prefersSlot3 = 1;
13761 let Defs = [USR_OVF];
13763 def M2_cnacs_s0 : HInst<
13764 (outs DoubleRegs:$Rxx32),
13765 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13766 "$Rxx32 -= cmpy($Rs32,$Rt32):sat",
13767 tc_e913dc32, TypeM>, Enc_61f0b0 {
13768 let Inst{7-5} = 0b111;
13769 let Inst{13-13} = 0b0;
13770 let Inst{31-21} = 0b11100111000;
13771 let prefersSlot3 = 1;
13772 let Defs = [USR_OVF];
13773 let Constraints = "$Rxx32 = $Rxx32in";
13775 def M2_cnacs_s1 : HInst<
13776 (outs DoubleRegs:$Rxx32),
13777 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13778 "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
13779 tc_e913dc32, TypeM>, Enc_61f0b0 {
13780 let Inst{7-5} = 0b111;
13781 let Inst{13-13} = 0b0;
13782 let Inst{31-21} = 0b11100111100;
13783 let prefersSlot3 = 1;
13784 let Defs = [USR_OVF];
13785 let Constraints = "$Rxx32 = $Rxx32in";
13787 def M2_cnacsc_s0 : HInst<
13788 (outs DoubleRegs:$Rxx32),
13789 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13790 "$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
13791 tc_e913dc32, TypeM>, Enc_61f0b0 {
13792 let Inst{7-5} = 0b111;
13793 let Inst{13-13} = 0b0;
13794 let Inst{31-21} = 0b11100111010;
13795 let prefersSlot3 = 1;
13796 let Defs = [USR_OVF];
13797 let Constraints = "$Rxx32 = $Rxx32in";
13799 def M2_cnacsc_s1 : HInst<
13800 (outs DoubleRegs:$Rxx32),
13801 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13802 "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
13803 tc_e913dc32, TypeM>, Enc_61f0b0 {
13804 let Inst{7-5} = 0b111;
13805 let Inst{13-13} = 0b0;
13806 let Inst{31-21} = 0b11100111110;
13807 let prefersSlot3 = 1;
13808 let Defs = [USR_OVF];
13809 let Constraints = "$Rxx32 = $Rxx32in";
13811 def M2_dpmpyss_acc_s0 : HInst<
13812 (outs DoubleRegs:$Rxx32),
13813 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13814 "$Rxx32 += mpy($Rs32,$Rt32)",
13815 tc_e913dc32, TypeM>, Enc_61f0b0 {
13816 let Inst{7-5} = 0b000;
13817 let Inst{13-13} = 0b0;
13818 let Inst{31-21} = 0b11100111000;
13819 let prefersSlot3 = 1;
13820 let Constraints = "$Rxx32 = $Rxx32in";
13822 def M2_dpmpyss_nac_s0 : HInst<
13823 (outs DoubleRegs:$Rxx32),
13824 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13825 "$Rxx32 -= mpy($Rs32,$Rt32)",
13826 tc_e913dc32, TypeM>, Enc_61f0b0 {
13827 let Inst{7-5} = 0b000;
13828 let Inst{13-13} = 0b0;
13829 let Inst{31-21} = 0b11100111001;
13830 let prefersSlot3 = 1;
13831 let Constraints = "$Rxx32 = $Rxx32in";
13833 def M2_dpmpyss_rnd_s0 : HInst<
13834 (outs IntRegs:$Rd32),
13835 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13836 "$Rd32 = mpy($Rs32,$Rt32):rnd",
13837 tc_8fd5f294, TypeM>, Enc_5ab2be {
13838 let Inst{7-5} = 0b001;
13839 let Inst{13-13} = 0b0;
13840 let Inst{31-21} = 0b11101101001;
13841 let hasNewValue = 1;
13842 let opNewValue = 0;
13843 let prefersSlot3 = 1;
13845 def M2_dpmpyss_s0 : HInst<
13846 (outs DoubleRegs:$Rdd32),
13847 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13848 "$Rdd32 = mpy($Rs32,$Rt32)",
13849 tc_8fd5f294, TypeM>, Enc_be32a5 {
13850 let Inst{7-5} = 0b000;
13851 let Inst{13-13} = 0b0;
13852 let Inst{31-21} = 0b11100101000;
13853 let prefersSlot3 = 1;
13855 def M2_dpmpyuu_acc_s0 : HInst<
13856 (outs DoubleRegs:$Rxx32),
13857 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13858 "$Rxx32 += mpyu($Rs32,$Rt32)",
13859 tc_e913dc32, TypeM>, Enc_61f0b0 {
13860 let Inst{7-5} = 0b000;
13861 let Inst{13-13} = 0b0;
13862 let Inst{31-21} = 0b11100111010;
13863 let prefersSlot3 = 1;
13864 let Constraints = "$Rxx32 = $Rxx32in";
13866 def M2_dpmpyuu_nac_s0 : HInst<
13867 (outs DoubleRegs:$Rxx32),
13868 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13869 "$Rxx32 -= mpyu($Rs32,$Rt32)",
13870 tc_e913dc32, TypeM>, Enc_61f0b0 {
13871 let Inst{7-5} = 0b000;
13872 let Inst{13-13} = 0b0;
13873 let Inst{31-21} = 0b11100111011;
13874 let prefersSlot3 = 1;
13875 let Constraints = "$Rxx32 = $Rxx32in";
13877 def M2_dpmpyuu_s0 : HInst<
13878 (outs DoubleRegs:$Rdd32),
13879 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13880 "$Rdd32 = mpyu($Rs32,$Rt32)",
13881 tc_8fd5f294, TypeM>, Enc_be32a5 {
13882 let Inst{7-5} = 0b000;
13883 let Inst{13-13} = 0b0;
13884 let Inst{31-21} = 0b11100101010;
13885 let prefersSlot3 = 1;
13887 def M2_hmmpyh_rs1 : HInst<
13888 (outs IntRegs:$Rd32),
13889 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13890 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
13891 tc_8fd5f294, TypeM>, Enc_5ab2be {
13892 let Inst{7-5} = 0b100;
13893 let Inst{13-13} = 0b0;
13894 let Inst{31-21} = 0b11101101101;
13895 let hasNewValue = 1;
13896 let opNewValue = 0;
13897 let prefersSlot3 = 1;
13898 let Defs = [USR_OVF];
13900 def M2_hmmpyh_s1 : HInst<
13901 (outs IntRegs:$Rd32),
13902 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13903 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
13904 tc_8fd5f294, TypeM>, Enc_5ab2be {
13905 let Inst{7-5} = 0b000;
13906 let Inst{13-13} = 0b0;
13907 let Inst{31-21} = 0b11101101101;
13908 let hasNewValue = 1;
13909 let opNewValue = 0;
13910 let prefersSlot3 = 1;
13911 let Defs = [USR_OVF];
13913 def M2_hmmpyl_rs1 : HInst<
13914 (outs IntRegs:$Rd32),
13915 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13916 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
13917 tc_8fd5f294, TypeM>, Enc_5ab2be {
13918 let Inst{7-5} = 0b100;
13919 let Inst{13-13} = 0b0;
13920 let Inst{31-21} = 0b11101101111;
13921 let hasNewValue = 1;
13922 let opNewValue = 0;
13923 let prefersSlot3 = 1;
13924 let Defs = [USR_OVF];
13926 def M2_hmmpyl_s1 : HInst<
13927 (outs IntRegs:$Rd32),
13928 (ins IntRegs:$Rs32, IntRegs:$Rt32),
13929 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
13930 tc_8fd5f294, TypeM>, Enc_5ab2be {
13931 let Inst{7-5} = 0b001;
13932 let Inst{13-13} = 0b0;
13933 let Inst{31-21} = 0b11101101101;
13934 let hasNewValue = 1;
13935 let opNewValue = 0;
13936 let prefersSlot3 = 1;
13937 let Defs = [USR_OVF];
13939 def M2_maci : HInst<
13940 (outs IntRegs:$Rx32),
13941 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13942 "$Rx32 += mpyi($Rs32,$Rt32)",
13943 tc_e913dc32, TypeM>, Enc_2ae154, ImmRegRel {
13944 let Inst{7-5} = 0b000;
13945 let Inst{13-13} = 0b0;
13946 let Inst{31-21} = 0b11101111000;
13947 let hasNewValue = 1;
13948 let opNewValue = 0;
13949 let prefersSlot3 = 1;
13950 let CextOpcode = "M2_maci";
13951 let InputType = "reg";
13952 let Constraints = "$Rx32 = $Rx32in";
13954 def M2_macsin : HInst<
13955 (outs IntRegs:$Rx32),
13956 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
13957 "$Rx32 -= mpyi($Rs32,#$Ii)",
13958 tc_16d0d8d5, TypeM>, Enc_c90aca {
13959 let Inst{13-13} = 0b0;
13960 let Inst{31-21} = 0b11100001100;
13961 let hasNewValue = 1;
13962 let opNewValue = 0;
13963 let prefersSlot3 = 1;
13964 let InputType = "imm";
13965 let isExtendable = 1;
13966 let opExtendable = 3;
13967 let isExtentSigned = 0;
13968 let opExtentBits = 8;
13969 let opExtentAlign = 0;
13970 let Constraints = "$Rx32 = $Rx32in";
13972 def M2_macsip : HInst<
13973 (outs IntRegs:$Rx32),
13974 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
13975 "$Rx32 += mpyi($Rs32,#$Ii)",
13976 tc_16d0d8d5, TypeM>, Enc_c90aca, ImmRegRel {
13977 let Inst{13-13} = 0b0;
13978 let Inst{31-21} = 0b11100001000;
13979 let hasNewValue = 1;
13980 let opNewValue = 0;
13981 let prefersSlot3 = 1;
13982 let CextOpcode = "M2_maci";
13983 let InputType = "imm";
13984 let isExtendable = 1;
13985 let opExtendable = 3;
13986 let isExtentSigned = 0;
13987 let opExtentBits = 8;
13988 let opExtentAlign = 0;
13989 let Constraints = "$Rx32 = $Rx32in";
13991 def M2_mmachs_rs0 : HInst<
13992 (outs DoubleRegs:$Rxx32),
13993 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
13994 "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
13995 tc_e913dc32, TypeM>, Enc_88c16c {
13996 let Inst{7-5} = 0b111;
13997 let Inst{13-13} = 0b0;
13998 let Inst{31-21} = 0b11101010001;
13999 let prefersSlot3 = 1;
14000 let Defs = [USR_OVF];
14001 let Constraints = "$Rxx32 = $Rxx32in";
14003 def M2_mmachs_rs1 : HInst<
14004 (outs DoubleRegs:$Rxx32),
14005 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14006 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14007 tc_e913dc32, TypeM>, Enc_88c16c {
14008 let Inst{7-5} = 0b111;
14009 let Inst{13-13} = 0b0;
14010 let Inst{31-21} = 0b11101010101;
14011 let prefersSlot3 = 1;
14012 let Defs = [USR_OVF];
14013 let Constraints = "$Rxx32 = $Rxx32in";
14015 def M2_mmachs_s0 : HInst<
14016 (outs DoubleRegs:$Rxx32),
14017 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14018 "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14019 tc_e913dc32, TypeM>, Enc_88c16c {
14020 let Inst{7-5} = 0b111;
14021 let Inst{13-13} = 0b0;
14022 let Inst{31-21} = 0b11101010000;
14023 let prefersSlot3 = 1;
14024 let Defs = [USR_OVF];
14025 let Constraints = "$Rxx32 = $Rxx32in";
14027 def M2_mmachs_s1 : HInst<
14028 (outs DoubleRegs:$Rxx32),
14029 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14030 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14031 tc_e913dc32, TypeM>, Enc_88c16c {
14032 let Inst{7-5} = 0b111;
14033 let Inst{13-13} = 0b0;
14034 let Inst{31-21} = 0b11101010100;
14035 let prefersSlot3 = 1;
14036 let Defs = [USR_OVF];
14037 let Constraints = "$Rxx32 = $Rxx32in";
14039 def M2_mmacls_rs0 : HInst<
14040 (outs DoubleRegs:$Rxx32),
14041 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14042 "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14043 tc_e913dc32, TypeM>, Enc_88c16c {
14044 let Inst{7-5} = 0b101;
14045 let Inst{13-13} = 0b0;
14046 let Inst{31-21} = 0b11101010001;
14047 let prefersSlot3 = 1;
14048 let Defs = [USR_OVF];
14049 let Constraints = "$Rxx32 = $Rxx32in";
14051 def M2_mmacls_rs1 : HInst<
14052 (outs DoubleRegs:$Rxx32),
14053 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14054 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14055 tc_e913dc32, TypeM>, Enc_88c16c {
14056 let Inst{7-5} = 0b101;
14057 let Inst{13-13} = 0b0;
14058 let Inst{31-21} = 0b11101010101;
14059 let prefersSlot3 = 1;
14060 let Defs = [USR_OVF];
14061 let Constraints = "$Rxx32 = $Rxx32in";
14063 def M2_mmacls_s0 : HInst<
14064 (outs DoubleRegs:$Rxx32),
14065 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14066 "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14067 tc_e913dc32, TypeM>, Enc_88c16c {
14068 let Inst{7-5} = 0b101;
14069 let Inst{13-13} = 0b0;
14070 let Inst{31-21} = 0b11101010000;
14071 let prefersSlot3 = 1;
14072 let Defs = [USR_OVF];
14073 let Constraints = "$Rxx32 = $Rxx32in";
14075 def M2_mmacls_s1 : HInst<
14076 (outs DoubleRegs:$Rxx32),
14077 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14078 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14079 tc_e913dc32, TypeM>, Enc_88c16c {
14080 let Inst{7-5} = 0b101;
14081 let Inst{13-13} = 0b0;
14082 let Inst{31-21} = 0b11101010100;
14083 let prefersSlot3 = 1;
14084 let Defs = [USR_OVF];
14085 let Constraints = "$Rxx32 = $Rxx32in";
14087 def M2_mmacuhs_rs0 : HInst<
14088 (outs DoubleRegs:$Rxx32),
14089 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14090 "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14091 tc_e913dc32, TypeM>, Enc_88c16c {
14092 let Inst{7-5} = 0b111;
14093 let Inst{13-13} = 0b0;
14094 let Inst{31-21} = 0b11101010011;
14095 let prefersSlot3 = 1;
14096 let Defs = [USR_OVF];
14097 let Constraints = "$Rxx32 = $Rxx32in";
14099 def M2_mmacuhs_rs1 : HInst<
14100 (outs DoubleRegs:$Rxx32),
14101 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14102 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14103 tc_e913dc32, TypeM>, Enc_88c16c {
14104 let Inst{7-5} = 0b111;
14105 let Inst{13-13} = 0b0;
14106 let Inst{31-21} = 0b11101010111;
14107 let prefersSlot3 = 1;
14108 let Defs = [USR_OVF];
14109 let Constraints = "$Rxx32 = $Rxx32in";
14111 def M2_mmacuhs_s0 : HInst<
14112 (outs DoubleRegs:$Rxx32),
14113 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14114 "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14115 tc_e913dc32, TypeM>, Enc_88c16c {
14116 let Inst{7-5} = 0b111;
14117 let Inst{13-13} = 0b0;
14118 let Inst{31-21} = 0b11101010010;
14119 let prefersSlot3 = 1;
14120 let Defs = [USR_OVF];
14121 let Constraints = "$Rxx32 = $Rxx32in";
14123 def M2_mmacuhs_s1 : HInst<
14124 (outs DoubleRegs:$Rxx32),
14125 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14126 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14127 tc_e913dc32, TypeM>, Enc_88c16c {
14128 let Inst{7-5} = 0b111;
14129 let Inst{13-13} = 0b0;
14130 let Inst{31-21} = 0b11101010110;
14131 let prefersSlot3 = 1;
14132 let Defs = [USR_OVF];
14133 let Constraints = "$Rxx32 = $Rxx32in";
14135 def M2_mmaculs_rs0 : HInst<
14136 (outs DoubleRegs:$Rxx32),
14137 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14138 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14139 tc_e913dc32, TypeM>, Enc_88c16c {
14140 let Inst{7-5} = 0b101;
14141 let Inst{13-13} = 0b0;
14142 let Inst{31-21} = 0b11101010011;
14143 let prefersSlot3 = 1;
14144 let Defs = [USR_OVF];
14145 let Constraints = "$Rxx32 = $Rxx32in";
14147 def M2_mmaculs_rs1 : HInst<
14148 (outs DoubleRegs:$Rxx32),
14149 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14150 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14151 tc_e913dc32, TypeM>, Enc_88c16c {
14152 let Inst{7-5} = 0b101;
14153 let Inst{13-13} = 0b0;
14154 let Inst{31-21} = 0b11101010111;
14155 let prefersSlot3 = 1;
14156 let Defs = [USR_OVF];
14157 let Constraints = "$Rxx32 = $Rxx32in";
14159 def M2_mmaculs_s0 : HInst<
14160 (outs DoubleRegs:$Rxx32),
14161 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14162 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14163 tc_e913dc32, TypeM>, Enc_88c16c {
14164 let Inst{7-5} = 0b101;
14165 let Inst{13-13} = 0b0;
14166 let Inst{31-21} = 0b11101010010;
14167 let prefersSlot3 = 1;
14168 let Defs = [USR_OVF];
14169 let Constraints = "$Rxx32 = $Rxx32in";
14171 def M2_mmaculs_s1 : HInst<
14172 (outs DoubleRegs:$Rxx32),
14173 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14174 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14175 tc_e913dc32, TypeM>, Enc_88c16c {
14176 let Inst{7-5} = 0b101;
14177 let Inst{13-13} = 0b0;
14178 let Inst{31-21} = 0b11101010110;
14179 let prefersSlot3 = 1;
14180 let Defs = [USR_OVF];
14181 let Constraints = "$Rxx32 = $Rxx32in";
14183 def M2_mmpyh_rs0 : HInst<
14184 (outs DoubleRegs:$Rdd32),
14185 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14186 "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14187 tc_8fd5f294, TypeM>, Enc_a56825 {
14188 let Inst{7-5} = 0b111;
14189 let Inst{13-13} = 0b0;
14190 let Inst{31-21} = 0b11101000001;
14191 let prefersSlot3 = 1;
14192 let Defs = [USR_OVF];
14194 def M2_mmpyh_rs1 : HInst<
14195 (outs DoubleRegs:$Rdd32),
14196 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14197 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14198 tc_8fd5f294, TypeM>, Enc_a56825 {
14199 let Inst{7-5} = 0b111;
14200 let Inst{13-13} = 0b0;
14201 let Inst{31-21} = 0b11101000101;
14202 let prefersSlot3 = 1;
14203 let Defs = [USR_OVF];
14205 def M2_mmpyh_s0 : HInst<
14206 (outs DoubleRegs:$Rdd32),
14207 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14208 "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14209 tc_8fd5f294, TypeM>, Enc_a56825 {
14210 let Inst{7-5} = 0b111;
14211 let Inst{13-13} = 0b0;
14212 let Inst{31-21} = 0b11101000000;
14213 let prefersSlot3 = 1;
14214 let Defs = [USR_OVF];
14216 def M2_mmpyh_s1 : HInst<
14217 (outs DoubleRegs:$Rdd32),
14218 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14219 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14220 tc_8fd5f294, TypeM>, Enc_a56825 {
14221 let Inst{7-5} = 0b111;
14222 let Inst{13-13} = 0b0;
14223 let Inst{31-21} = 0b11101000100;
14224 let prefersSlot3 = 1;
14225 let Defs = [USR_OVF];
14227 def M2_mmpyl_rs0 : HInst<
14228 (outs DoubleRegs:$Rdd32),
14229 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14230 "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14231 tc_8fd5f294, TypeM>, Enc_a56825 {
14232 let Inst{7-5} = 0b101;
14233 let Inst{13-13} = 0b0;
14234 let Inst{31-21} = 0b11101000001;
14235 let prefersSlot3 = 1;
14236 let Defs = [USR_OVF];
14238 def M2_mmpyl_rs1 : HInst<
14239 (outs DoubleRegs:$Rdd32),
14240 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14241 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14242 tc_8fd5f294, TypeM>, Enc_a56825 {
14243 let Inst{7-5} = 0b101;
14244 let Inst{13-13} = 0b0;
14245 let Inst{31-21} = 0b11101000101;
14246 let prefersSlot3 = 1;
14247 let Defs = [USR_OVF];
14249 def M2_mmpyl_s0 : HInst<
14250 (outs DoubleRegs:$Rdd32),
14251 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14252 "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14253 tc_8fd5f294, TypeM>, Enc_a56825 {
14254 let Inst{7-5} = 0b101;
14255 let Inst{13-13} = 0b0;
14256 let Inst{31-21} = 0b11101000000;
14257 let prefersSlot3 = 1;
14258 let Defs = [USR_OVF];
14260 def M2_mmpyl_s1 : HInst<
14261 (outs DoubleRegs:$Rdd32),
14262 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14263 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14264 tc_8fd5f294, TypeM>, Enc_a56825 {
14265 let Inst{7-5} = 0b101;
14266 let Inst{13-13} = 0b0;
14267 let Inst{31-21} = 0b11101000100;
14268 let prefersSlot3 = 1;
14269 let Defs = [USR_OVF];
14271 def M2_mmpyuh_rs0 : HInst<
14272 (outs DoubleRegs:$Rdd32),
14273 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14274 "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14275 tc_8fd5f294, TypeM>, Enc_a56825 {
14276 let Inst{7-5} = 0b111;
14277 let Inst{13-13} = 0b0;
14278 let Inst{31-21} = 0b11101000011;
14279 let prefersSlot3 = 1;
14280 let Defs = [USR_OVF];
14282 def M2_mmpyuh_rs1 : HInst<
14283 (outs DoubleRegs:$Rdd32),
14284 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14285 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14286 tc_8fd5f294, TypeM>, Enc_a56825 {
14287 let Inst{7-5} = 0b111;
14288 let Inst{13-13} = 0b0;
14289 let Inst{31-21} = 0b11101000111;
14290 let prefersSlot3 = 1;
14291 let Defs = [USR_OVF];
14293 def M2_mmpyuh_s0 : HInst<
14294 (outs DoubleRegs:$Rdd32),
14295 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14296 "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14297 tc_8fd5f294, TypeM>, Enc_a56825 {
14298 let Inst{7-5} = 0b111;
14299 let Inst{13-13} = 0b0;
14300 let Inst{31-21} = 0b11101000010;
14301 let prefersSlot3 = 1;
14302 let Defs = [USR_OVF];
14304 def M2_mmpyuh_s1 : HInst<
14305 (outs DoubleRegs:$Rdd32),
14306 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14307 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14308 tc_8fd5f294, TypeM>, Enc_a56825 {
14309 let Inst{7-5} = 0b111;
14310 let Inst{13-13} = 0b0;
14311 let Inst{31-21} = 0b11101000110;
14312 let prefersSlot3 = 1;
14313 let Defs = [USR_OVF];
14315 def M2_mmpyul_rs0 : HInst<
14316 (outs DoubleRegs:$Rdd32),
14317 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14318 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14319 tc_8fd5f294, TypeM>, Enc_a56825 {
14320 let Inst{7-5} = 0b101;
14321 let Inst{13-13} = 0b0;
14322 let Inst{31-21} = 0b11101000011;
14323 let prefersSlot3 = 1;
14324 let Defs = [USR_OVF];
14326 def M2_mmpyul_rs1 : HInst<
14327 (outs DoubleRegs:$Rdd32),
14328 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14329 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14330 tc_8fd5f294, TypeM>, Enc_a56825 {
14331 let Inst{7-5} = 0b101;
14332 let Inst{13-13} = 0b0;
14333 let Inst{31-21} = 0b11101000111;
14334 let prefersSlot3 = 1;
14335 let Defs = [USR_OVF];
14337 def M2_mmpyul_s0 : HInst<
14338 (outs DoubleRegs:$Rdd32),
14339 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14340 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14341 tc_8fd5f294, TypeM>, Enc_a56825 {
14342 let Inst{7-5} = 0b101;
14343 let Inst{13-13} = 0b0;
14344 let Inst{31-21} = 0b11101000010;
14345 let prefersSlot3 = 1;
14346 let Defs = [USR_OVF];
14348 def M2_mmpyul_s1 : HInst<
14349 (outs DoubleRegs:$Rdd32),
14350 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14351 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14352 tc_8fd5f294, TypeM>, Enc_a56825 {
14353 let Inst{7-5} = 0b101;
14354 let Inst{13-13} = 0b0;
14355 let Inst{31-21} = 0b11101000110;
14356 let prefersSlot3 = 1;
14357 let Defs = [USR_OVF];
14359 def M2_mpy_acc_hh_s0 : HInst<
14360 (outs IntRegs:$Rx32),
14361 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14362 "$Rx32 += mpy($Rs32.h,$Rt32.h)",
14363 tc_e913dc32, TypeM>, Enc_2ae154 {
14364 let Inst{7-5} = 0b011;
14365 let Inst{13-13} = 0b0;
14366 let Inst{31-21} = 0b11101110000;
14367 let hasNewValue = 1;
14368 let opNewValue = 0;
14369 let prefersSlot3 = 1;
14370 let Constraints = "$Rx32 = $Rx32in";
14372 def M2_mpy_acc_hh_s1 : HInst<
14373 (outs IntRegs:$Rx32),
14374 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14375 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14376 tc_e913dc32, TypeM>, Enc_2ae154 {
14377 let Inst{7-5} = 0b011;
14378 let Inst{13-13} = 0b0;
14379 let Inst{31-21} = 0b11101110100;
14380 let hasNewValue = 1;
14381 let opNewValue = 0;
14382 let prefersSlot3 = 1;
14383 let Constraints = "$Rx32 = $Rx32in";
14385 def M2_mpy_acc_hl_s0 : HInst<
14386 (outs IntRegs:$Rx32),
14387 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14388 "$Rx32 += mpy($Rs32.h,$Rt32.l)",
14389 tc_e913dc32, TypeM>, Enc_2ae154 {
14390 let Inst{7-5} = 0b010;
14391 let Inst{13-13} = 0b0;
14392 let Inst{31-21} = 0b11101110000;
14393 let hasNewValue = 1;
14394 let opNewValue = 0;
14395 let prefersSlot3 = 1;
14396 let Constraints = "$Rx32 = $Rx32in";
14398 def M2_mpy_acc_hl_s1 : HInst<
14399 (outs IntRegs:$Rx32),
14400 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14401 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14402 tc_e913dc32, TypeM>, Enc_2ae154 {
14403 let Inst{7-5} = 0b010;
14404 let Inst{13-13} = 0b0;
14405 let Inst{31-21} = 0b11101110100;
14406 let hasNewValue = 1;
14407 let opNewValue = 0;
14408 let prefersSlot3 = 1;
14409 let Constraints = "$Rx32 = $Rx32in";
14411 def M2_mpy_acc_lh_s0 : HInst<
14412 (outs IntRegs:$Rx32),
14413 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14414 "$Rx32 += mpy($Rs32.l,$Rt32.h)",
14415 tc_e913dc32, TypeM>, Enc_2ae154 {
14416 let Inst{7-5} = 0b001;
14417 let Inst{13-13} = 0b0;
14418 let Inst{31-21} = 0b11101110000;
14419 let hasNewValue = 1;
14420 let opNewValue = 0;
14421 let prefersSlot3 = 1;
14422 let Constraints = "$Rx32 = $Rx32in";
14424 def M2_mpy_acc_lh_s1 : HInst<
14425 (outs IntRegs:$Rx32),
14426 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14427 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14428 tc_e913dc32, TypeM>, Enc_2ae154 {
14429 let Inst{7-5} = 0b001;
14430 let Inst{13-13} = 0b0;
14431 let Inst{31-21} = 0b11101110100;
14432 let hasNewValue = 1;
14433 let opNewValue = 0;
14434 let prefersSlot3 = 1;
14435 let Constraints = "$Rx32 = $Rx32in";
14437 def M2_mpy_acc_ll_s0 : HInst<
14438 (outs IntRegs:$Rx32),
14439 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14440 "$Rx32 += mpy($Rs32.l,$Rt32.l)",
14441 tc_e913dc32, TypeM>, Enc_2ae154 {
14442 let Inst{7-5} = 0b000;
14443 let Inst{13-13} = 0b0;
14444 let Inst{31-21} = 0b11101110000;
14445 let hasNewValue = 1;
14446 let opNewValue = 0;
14447 let prefersSlot3 = 1;
14448 let Constraints = "$Rx32 = $Rx32in";
14450 def M2_mpy_acc_ll_s1 : HInst<
14451 (outs IntRegs:$Rx32),
14452 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14453 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14454 tc_e913dc32, TypeM>, Enc_2ae154 {
14455 let Inst{7-5} = 0b000;
14456 let Inst{13-13} = 0b0;
14457 let Inst{31-21} = 0b11101110100;
14458 let hasNewValue = 1;
14459 let opNewValue = 0;
14460 let prefersSlot3 = 1;
14461 let Constraints = "$Rx32 = $Rx32in";
14463 def M2_mpy_acc_sat_hh_s0 : HInst<
14464 (outs IntRegs:$Rx32),
14465 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14466 "$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14467 tc_e913dc32, TypeM>, Enc_2ae154 {
14468 let Inst{7-5} = 0b111;
14469 let Inst{13-13} = 0b0;
14470 let Inst{31-21} = 0b11101110000;
14471 let hasNewValue = 1;
14472 let opNewValue = 0;
14473 let prefersSlot3 = 1;
14474 let Defs = [USR_OVF];
14475 let Constraints = "$Rx32 = $Rx32in";
14477 def M2_mpy_acc_sat_hh_s1 : HInst<
14478 (outs IntRegs:$Rx32),
14479 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14480 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14481 tc_e913dc32, TypeM>, Enc_2ae154 {
14482 let Inst{7-5} = 0b111;
14483 let Inst{13-13} = 0b0;
14484 let Inst{31-21} = 0b11101110100;
14485 let hasNewValue = 1;
14486 let opNewValue = 0;
14487 let prefersSlot3 = 1;
14488 let Defs = [USR_OVF];
14489 let Constraints = "$Rx32 = $Rx32in";
14491 def M2_mpy_acc_sat_hl_s0 : HInst<
14492 (outs IntRegs:$Rx32),
14493 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14494 "$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14495 tc_e913dc32, TypeM>, Enc_2ae154 {
14496 let Inst{7-5} = 0b110;
14497 let Inst{13-13} = 0b0;
14498 let Inst{31-21} = 0b11101110000;
14499 let hasNewValue = 1;
14500 let opNewValue = 0;
14501 let prefersSlot3 = 1;
14502 let Defs = [USR_OVF];
14503 let Constraints = "$Rx32 = $Rx32in";
14505 def M2_mpy_acc_sat_hl_s1 : HInst<
14506 (outs IntRegs:$Rx32),
14507 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14508 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14509 tc_e913dc32, TypeM>, Enc_2ae154 {
14510 let Inst{7-5} = 0b110;
14511 let Inst{13-13} = 0b0;
14512 let Inst{31-21} = 0b11101110100;
14513 let hasNewValue = 1;
14514 let opNewValue = 0;
14515 let prefersSlot3 = 1;
14516 let Defs = [USR_OVF];
14517 let Constraints = "$Rx32 = $Rx32in";
14519 def M2_mpy_acc_sat_lh_s0 : HInst<
14520 (outs IntRegs:$Rx32),
14521 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14522 "$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14523 tc_e913dc32, TypeM>, Enc_2ae154 {
14524 let Inst{7-5} = 0b101;
14525 let Inst{13-13} = 0b0;
14526 let Inst{31-21} = 0b11101110000;
14527 let hasNewValue = 1;
14528 let opNewValue = 0;
14529 let prefersSlot3 = 1;
14530 let Defs = [USR_OVF];
14531 let Constraints = "$Rx32 = $Rx32in";
14533 def M2_mpy_acc_sat_lh_s1 : HInst<
14534 (outs IntRegs:$Rx32),
14535 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14536 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14537 tc_e913dc32, TypeM>, Enc_2ae154 {
14538 let Inst{7-5} = 0b101;
14539 let Inst{13-13} = 0b0;
14540 let Inst{31-21} = 0b11101110100;
14541 let hasNewValue = 1;
14542 let opNewValue = 0;
14543 let prefersSlot3 = 1;
14544 let Defs = [USR_OVF];
14545 let Constraints = "$Rx32 = $Rx32in";
14547 def M2_mpy_acc_sat_ll_s0 : HInst<
14548 (outs IntRegs:$Rx32),
14549 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14550 "$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14551 tc_e913dc32, TypeM>, Enc_2ae154 {
14552 let Inst{7-5} = 0b100;
14553 let Inst{13-13} = 0b0;
14554 let Inst{31-21} = 0b11101110000;
14555 let hasNewValue = 1;
14556 let opNewValue = 0;
14557 let prefersSlot3 = 1;
14558 let Defs = [USR_OVF];
14559 let Constraints = "$Rx32 = $Rx32in";
14561 def M2_mpy_acc_sat_ll_s1 : HInst<
14562 (outs IntRegs:$Rx32),
14563 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14564 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14565 tc_e913dc32, TypeM>, Enc_2ae154 {
14566 let Inst{7-5} = 0b100;
14567 let Inst{13-13} = 0b0;
14568 let Inst{31-21} = 0b11101110100;
14569 let hasNewValue = 1;
14570 let opNewValue = 0;
14571 let prefersSlot3 = 1;
14572 let Defs = [USR_OVF];
14573 let Constraints = "$Rx32 = $Rx32in";
14575 def M2_mpy_hh_s0 : HInst<
14576 (outs IntRegs:$Rd32),
14577 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14578 "$Rd32 = mpy($Rs32.h,$Rt32.h)",
14579 tc_8fd5f294, TypeM>, Enc_5ab2be {
14580 let Inst{7-5} = 0b011;
14581 let Inst{13-13} = 0b0;
14582 let Inst{31-21} = 0b11101100000;
14583 let hasNewValue = 1;
14584 let opNewValue = 0;
14585 let prefersSlot3 = 1;
14587 def M2_mpy_hh_s1 : HInst<
14588 (outs IntRegs:$Rd32),
14589 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14590 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14591 tc_8fd5f294, TypeM>, Enc_5ab2be {
14592 let Inst{7-5} = 0b011;
14593 let Inst{13-13} = 0b0;
14594 let Inst{31-21} = 0b11101100100;
14595 let hasNewValue = 1;
14596 let opNewValue = 0;
14597 let prefersSlot3 = 1;
14599 def M2_mpy_hl_s0 : HInst<
14600 (outs IntRegs:$Rd32),
14601 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14602 "$Rd32 = mpy($Rs32.h,$Rt32.l)",
14603 tc_8fd5f294, TypeM>, Enc_5ab2be {
14604 let Inst{7-5} = 0b010;
14605 let Inst{13-13} = 0b0;
14606 let Inst{31-21} = 0b11101100000;
14607 let hasNewValue = 1;
14608 let opNewValue = 0;
14609 let prefersSlot3 = 1;
14611 def M2_mpy_hl_s1 : HInst<
14612 (outs IntRegs:$Rd32),
14613 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14614 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14615 tc_8fd5f294, TypeM>, Enc_5ab2be {
14616 let Inst{7-5} = 0b010;
14617 let Inst{13-13} = 0b0;
14618 let Inst{31-21} = 0b11101100100;
14619 let hasNewValue = 1;
14620 let opNewValue = 0;
14621 let prefersSlot3 = 1;
14623 def M2_mpy_lh_s0 : HInst<
14624 (outs IntRegs:$Rd32),
14625 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14626 "$Rd32 = mpy($Rs32.l,$Rt32.h)",
14627 tc_8fd5f294, TypeM>, Enc_5ab2be {
14628 let Inst{7-5} = 0b001;
14629 let Inst{13-13} = 0b0;
14630 let Inst{31-21} = 0b11101100000;
14631 let hasNewValue = 1;
14632 let opNewValue = 0;
14633 let prefersSlot3 = 1;
14635 def M2_mpy_lh_s1 : HInst<
14636 (outs IntRegs:$Rd32),
14637 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14638 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14639 tc_8fd5f294, TypeM>, Enc_5ab2be {
14640 let Inst{7-5} = 0b001;
14641 let Inst{13-13} = 0b0;
14642 let Inst{31-21} = 0b11101100100;
14643 let hasNewValue = 1;
14644 let opNewValue = 0;
14645 let prefersSlot3 = 1;
14647 def M2_mpy_ll_s0 : HInst<
14648 (outs IntRegs:$Rd32),
14649 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14650 "$Rd32 = mpy($Rs32.l,$Rt32.l)",
14651 tc_8fd5f294, TypeM>, Enc_5ab2be {
14652 let Inst{7-5} = 0b000;
14653 let Inst{13-13} = 0b0;
14654 let Inst{31-21} = 0b11101100000;
14655 let hasNewValue = 1;
14656 let opNewValue = 0;
14657 let prefersSlot3 = 1;
14659 def M2_mpy_ll_s1 : HInst<
14660 (outs IntRegs:$Rd32),
14661 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14662 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14663 tc_8fd5f294, TypeM>, Enc_5ab2be {
14664 let Inst{7-5} = 0b000;
14665 let Inst{13-13} = 0b0;
14666 let Inst{31-21} = 0b11101100100;
14667 let hasNewValue = 1;
14668 let opNewValue = 0;
14669 let prefersSlot3 = 1;
14671 def M2_mpy_nac_hh_s0 : HInst<
14672 (outs IntRegs:$Rx32),
14673 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14674 "$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14675 tc_e913dc32, TypeM>, Enc_2ae154 {
14676 let Inst{7-5} = 0b011;
14677 let Inst{13-13} = 0b0;
14678 let Inst{31-21} = 0b11101110001;
14679 let hasNewValue = 1;
14680 let opNewValue = 0;
14681 let prefersSlot3 = 1;
14682 let Constraints = "$Rx32 = $Rx32in";
14684 def M2_mpy_nac_hh_s1 : HInst<
14685 (outs IntRegs:$Rx32),
14686 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14687 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14688 tc_e913dc32, TypeM>, Enc_2ae154 {
14689 let Inst{7-5} = 0b011;
14690 let Inst{13-13} = 0b0;
14691 let Inst{31-21} = 0b11101110101;
14692 let hasNewValue = 1;
14693 let opNewValue = 0;
14694 let prefersSlot3 = 1;
14695 let Constraints = "$Rx32 = $Rx32in";
14697 def M2_mpy_nac_hl_s0 : HInst<
14698 (outs IntRegs:$Rx32),
14699 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14700 "$Rx32 -= mpy($Rs32.h,$Rt32.l)",
14701 tc_e913dc32, TypeM>, Enc_2ae154 {
14702 let Inst{7-5} = 0b010;
14703 let Inst{13-13} = 0b0;
14704 let Inst{31-21} = 0b11101110001;
14705 let hasNewValue = 1;
14706 let opNewValue = 0;
14707 let prefersSlot3 = 1;
14708 let Constraints = "$Rx32 = $Rx32in";
14710 def M2_mpy_nac_hl_s1 : HInst<
14711 (outs IntRegs:$Rx32),
14712 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14713 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
14714 tc_e913dc32, TypeM>, Enc_2ae154 {
14715 let Inst{7-5} = 0b010;
14716 let Inst{13-13} = 0b0;
14717 let Inst{31-21} = 0b11101110101;
14718 let hasNewValue = 1;
14719 let opNewValue = 0;
14720 let prefersSlot3 = 1;
14721 let Constraints = "$Rx32 = $Rx32in";
14723 def M2_mpy_nac_lh_s0 : HInst<
14724 (outs IntRegs:$Rx32),
14725 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14726 "$Rx32 -= mpy($Rs32.l,$Rt32.h)",
14727 tc_e913dc32, TypeM>, Enc_2ae154 {
14728 let Inst{7-5} = 0b001;
14729 let Inst{13-13} = 0b0;
14730 let Inst{31-21} = 0b11101110001;
14731 let hasNewValue = 1;
14732 let opNewValue = 0;
14733 let prefersSlot3 = 1;
14734 let Constraints = "$Rx32 = $Rx32in";
14736 def M2_mpy_nac_lh_s1 : HInst<
14737 (outs IntRegs:$Rx32),
14738 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14739 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
14740 tc_e913dc32, TypeM>, Enc_2ae154 {
14741 let Inst{7-5} = 0b001;
14742 let Inst{13-13} = 0b0;
14743 let Inst{31-21} = 0b11101110101;
14744 let hasNewValue = 1;
14745 let opNewValue = 0;
14746 let prefersSlot3 = 1;
14747 let Constraints = "$Rx32 = $Rx32in";
14749 def M2_mpy_nac_ll_s0 : HInst<
14750 (outs IntRegs:$Rx32),
14751 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14752 "$Rx32 -= mpy($Rs32.l,$Rt32.l)",
14753 tc_e913dc32, TypeM>, Enc_2ae154 {
14754 let Inst{7-5} = 0b000;
14755 let Inst{13-13} = 0b0;
14756 let Inst{31-21} = 0b11101110001;
14757 let hasNewValue = 1;
14758 let opNewValue = 0;
14759 let prefersSlot3 = 1;
14760 let Constraints = "$Rx32 = $Rx32in";
14762 def M2_mpy_nac_ll_s1 : HInst<
14763 (outs IntRegs:$Rx32),
14764 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14765 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
14766 tc_e913dc32, TypeM>, Enc_2ae154 {
14767 let Inst{7-5} = 0b000;
14768 let Inst{13-13} = 0b0;
14769 let Inst{31-21} = 0b11101110101;
14770 let hasNewValue = 1;
14771 let opNewValue = 0;
14772 let prefersSlot3 = 1;
14773 let Constraints = "$Rx32 = $Rx32in";
14775 def M2_mpy_nac_sat_hh_s0 : HInst<
14776 (outs IntRegs:$Rx32),
14777 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14778 "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
14779 tc_e913dc32, TypeM>, Enc_2ae154 {
14780 let Inst{7-5} = 0b111;
14781 let Inst{13-13} = 0b0;
14782 let Inst{31-21} = 0b11101110001;
14783 let hasNewValue = 1;
14784 let opNewValue = 0;
14785 let prefersSlot3 = 1;
14786 let Defs = [USR_OVF];
14787 let Constraints = "$Rx32 = $Rx32in";
14789 def M2_mpy_nac_sat_hh_s1 : HInst<
14790 (outs IntRegs:$Rx32),
14791 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14792 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
14793 tc_e913dc32, TypeM>, Enc_2ae154 {
14794 let Inst{7-5} = 0b111;
14795 let Inst{13-13} = 0b0;
14796 let Inst{31-21} = 0b11101110101;
14797 let hasNewValue = 1;
14798 let opNewValue = 0;
14799 let prefersSlot3 = 1;
14800 let Defs = [USR_OVF];
14801 let Constraints = "$Rx32 = $Rx32in";
14803 def M2_mpy_nac_sat_hl_s0 : HInst<
14804 (outs IntRegs:$Rx32),
14805 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14806 "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
14807 tc_e913dc32, TypeM>, Enc_2ae154 {
14808 let Inst{7-5} = 0b110;
14809 let Inst{13-13} = 0b0;
14810 let Inst{31-21} = 0b11101110001;
14811 let hasNewValue = 1;
14812 let opNewValue = 0;
14813 let prefersSlot3 = 1;
14814 let Defs = [USR_OVF];
14815 let Constraints = "$Rx32 = $Rx32in";
14817 def M2_mpy_nac_sat_hl_s1 : HInst<
14818 (outs IntRegs:$Rx32),
14819 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14820 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
14821 tc_e913dc32, TypeM>, Enc_2ae154 {
14822 let Inst{7-5} = 0b110;
14823 let Inst{13-13} = 0b0;
14824 let Inst{31-21} = 0b11101110101;
14825 let hasNewValue = 1;
14826 let opNewValue = 0;
14827 let prefersSlot3 = 1;
14828 let Defs = [USR_OVF];
14829 let Constraints = "$Rx32 = $Rx32in";
14831 def M2_mpy_nac_sat_lh_s0 : HInst<
14832 (outs IntRegs:$Rx32),
14833 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14834 "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
14835 tc_e913dc32, TypeM>, Enc_2ae154 {
14836 let Inst{7-5} = 0b101;
14837 let Inst{13-13} = 0b0;
14838 let Inst{31-21} = 0b11101110001;
14839 let hasNewValue = 1;
14840 let opNewValue = 0;
14841 let prefersSlot3 = 1;
14842 let Defs = [USR_OVF];
14843 let Constraints = "$Rx32 = $Rx32in";
14845 def M2_mpy_nac_sat_lh_s1 : HInst<
14846 (outs IntRegs:$Rx32),
14847 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14848 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
14849 tc_e913dc32, TypeM>, Enc_2ae154 {
14850 let Inst{7-5} = 0b101;
14851 let Inst{13-13} = 0b0;
14852 let Inst{31-21} = 0b11101110101;
14853 let hasNewValue = 1;
14854 let opNewValue = 0;
14855 let prefersSlot3 = 1;
14856 let Defs = [USR_OVF];
14857 let Constraints = "$Rx32 = $Rx32in";
14859 def M2_mpy_nac_sat_ll_s0 : HInst<
14860 (outs IntRegs:$Rx32),
14861 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14862 "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
14863 tc_e913dc32, TypeM>, Enc_2ae154 {
14864 let Inst{7-5} = 0b100;
14865 let Inst{13-13} = 0b0;
14866 let Inst{31-21} = 0b11101110001;
14867 let hasNewValue = 1;
14868 let opNewValue = 0;
14869 let prefersSlot3 = 1;
14870 let Defs = [USR_OVF];
14871 let Constraints = "$Rx32 = $Rx32in";
14873 def M2_mpy_nac_sat_ll_s1 : HInst<
14874 (outs IntRegs:$Rx32),
14875 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14876 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
14877 tc_e913dc32, TypeM>, Enc_2ae154 {
14878 let Inst{7-5} = 0b100;
14879 let Inst{13-13} = 0b0;
14880 let Inst{31-21} = 0b11101110101;
14881 let hasNewValue = 1;
14882 let opNewValue = 0;
14883 let prefersSlot3 = 1;
14884 let Defs = [USR_OVF];
14885 let Constraints = "$Rx32 = $Rx32in";
14887 def M2_mpy_rnd_hh_s0 : HInst<
14888 (outs IntRegs:$Rd32),
14889 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14890 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
14891 tc_8fd5f294, TypeM>, Enc_5ab2be {
14892 let Inst{7-5} = 0b011;
14893 let Inst{13-13} = 0b0;
14894 let Inst{31-21} = 0b11101100001;
14895 let hasNewValue = 1;
14896 let opNewValue = 0;
14897 let prefersSlot3 = 1;
14899 def M2_mpy_rnd_hh_s1 : HInst<
14900 (outs IntRegs:$Rd32),
14901 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14902 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
14903 tc_8fd5f294, TypeM>, Enc_5ab2be {
14904 let Inst{7-5} = 0b011;
14905 let Inst{13-13} = 0b0;
14906 let Inst{31-21} = 0b11101100101;
14907 let hasNewValue = 1;
14908 let opNewValue = 0;
14909 let prefersSlot3 = 1;
14911 def M2_mpy_rnd_hl_s0 : HInst<
14912 (outs IntRegs:$Rd32),
14913 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14914 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
14915 tc_8fd5f294, TypeM>, Enc_5ab2be {
14916 let Inst{7-5} = 0b010;
14917 let Inst{13-13} = 0b0;
14918 let Inst{31-21} = 0b11101100001;
14919 let hasNewValue = 1;
14920 let opNewValue = 0;
14921 let prefersSlot3 = 1;
14923 def M2_mpy_rnd_hl_s1 : HInst<
14924 (outs IntRegs:$Rd32),
14925 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14926 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
14927 tc_8fd5f294, TypeM>, Enc_5ab2be {
14928 let Inst{7-5} = 0b010;
14929 let Inst{13-13} = 0b0;
14930 let Inst{31-21} = 0b11101100101;
14931 let hasNewValue = 1;
14932 let opNewValue = 0;
14933 let prefersSlot3 = 1;
14935 def M2_mpy_rnd_lh_s0 : HInst<
14936 (outs IntRegs:$Rd32),
14937 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14938 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
14939 tc_8fd5f294, TypeM>, Enc_5ab2be {
14940 let Inst{7-5} = 0b001;
14941 let Inst{13-13} = 0b0;
14942 let Inst{31-21} = 0b11101100001;
14943 let hasNewValue = 1;
14944 let opNewValue = 0;
14945 let prefersSlot3 = 1;
14947 def M2_mpy_rnd_lh_s1 : HInst<
14948 (outs IntRegs:$Rd32),
14949 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14950 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
14951 tc_8fd5f294, TypeM>, Enc_5ab2be {
14952 let Inst{7-5} = 0b001;
14953 let Inst{13-13} = 0b0;
14954 let Inst{31-21} = 0b11101100101;
14955 let hasNewValue = 1;
14956 let opNewValue = 0;
14957 let prefersSlot3 = 1;
14959 def M2_mpy_rnd_ll_s0 : HInst<
14960 (outs IntRegs:$Rd32),
14961 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14962 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
14963 tc_8fd5f294, TypeM>, Enc_5ab2be {
14964 let Inst{7-5} = 0b000;
14965 let Inst{13-13} = 0b0;
14966 let Inst{31-21} = 0b11101100001;
14967 let hasNewValue = 1;
14968 let opNewValue = 0;
14969 let prefersSlot3 = 1;
14971 def M2_mpy_rnd_ll_s1 : HInst<
14972 (outs IntRegs:$Rd32),
14973 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14974 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
14975 tc_8fd5f294, TypeM>, Enc_5ab2be {
14976 let Inst{7-5} = 0b000;
14977 let Inst{13-13} = 0b0;
14978 let Inst{31-21} = 0b11101100101;
14979 let hasNewValue = 1;
14980 let opNewValue = 0;
14981 let prefersSlot3 = 1;
14983 def M2_mpy_sat_hh_s0 : HInst<
14984 (outs IntRegs:$Rd32),
14985 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14986 "$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
14987 tc_8fd5f294, TypeM>, Enc_5ab2be {
14988 let Inst{7-5} = 0b111;
14989 let Inst{13-13} = 0b0;
14990 let Inst{31-21} = 0b11101100000;
14991 let hasNewValue = 1;
14992 let opNewValue = 0;
14993 let prefersSlot3 = 1;
14994 let Defs = [USR_OVF];
14996 def M2_mpy_sat_hh_s1 : HInst<
14997 (outs IntRegs:$Rd32),
14998 (ins IntRegs:$Rs32, IntRegs:$Rt32),
14999 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15000 tc_8fd5f294, TypeM>, Enc_5ab2be {
15001 let Inst{7-5} = 0b111;
15002 let Inst{13-13} = 0b0;
15003 let Inst{31-21} = 0b11101100100;
15004 let hasNewValue = 1;
15005 let opNewValue = 0;
15006 let prefersSlot3 = 1;
15007 let Defs = [USR_OVF];
15009 def M2_mpy_sat_hl_s0 : HInst<
15010 (outs IntRegs:$Rd32),
15011 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15012 "$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15013 tc_8fd5f294, TypeM>, Enc_5ab2be {
15014 let Inst{7-5} = 0b110;
15015 let Inst{13-13} = 0b0;
15016 let Inst{31-21} = 0b11101100000;
15017 let hasNewValue = 1;
15018 let opNewValue = 0;
15019 let prefersSlot3 = 1;
15020 let Defs = [USR_OVF];
15022 def M2_mpy_sat_hl_s1 : HInst<
15023 (outs IntRegs:$Rd32),
15024 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15025 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15026 tc_8fd5f294, TypeM>, Enc_5ab2be {
15027 let Inst{7-5} = 0b110;
15028 let Inst{13-13} = 0b0;
15029 let Inst{31-21} = 0b11101100100;
15030 let hasNewValue = 1;
15031 let opNewValue = 0;
15032 let prefersSlot3 = 1;
15033 let Defs = [USR_OVF];
15035 def M2_mpy_sat_lh_s0 : HInst<
15036 (outs IntRegs:$Rd32),
15037 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15038 "$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15039 tc_8fd5f294, TypeM>, Enc_5ab2be {
15040 let Inst{7-5} = 0b101;
15041 let Inst{13-13} = 0b0;
15042 let Inst{31-21} = 0b11101100000;
15043 let hasNewValue = 1;
15044 let opNewValue = 0;
15045 let prefersSlot3 = 1;
15046 let Defs = [USR_OVF];
15048 def M2_mpy_sat_lh_s1 : HInst<
15049 (outs IntRegs:$Rd32),
15050 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15051 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15052 tc_8fd5f294, TypeM>, Enc_5ab2be {
15053 let Inst{7-5} = 0b101;
15054 let Inst{13-13} = 0b0;
15055 let Inst{31-21} = 0b11101100100;
15056 let hasNewValue = 1;
15057 let opNewValue = 0;
15058 let prefersSlot3 = 1;
15059 let Defs = [USR_OVF];
15061 def M2_mpy_sat_ll_s0 : HInst<
15062 (outs IntRegs:$Rd32),
15063 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15064 "$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15065 tc_8fd5f294, TypeM>, Enc_5ab2be {
15066 let Inst{7-5} = 0b100;
15067 let Inst{13-13} = 0b0;
15068 let Inst{31-21} = 0b11101100000;
15069 let hasNewValue = 1;
15070 let opNewValue = 0;
15071 let prefersSlot3 = 1;
15072 let Defs = [USR_OVF];
15074 def M2_mpy_sat_ll_s1 : HInst<
15075 (outs IntRegs:$Rd32),
15076 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15077 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15078 tc_8fd5f294, TypeM>, Enc_5ab2be {
15079 let Inst{7-5} = 0b100;
15080 let Inst{13-13} = 0b0;
15081 let Inst{31-21} = 0b11101100100;
15082 let hasNewValue = 1;
15083 let opNewValue = 0;
15084 let prefersSlot3 = 1;
15085 let Defs = [USR_OVF];
15087 def M2_mpy_sat_rnd_hh_s0 : HInst<
15088 (outs IntRegs:$Rd32),
15089 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15090 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15091 tc_8fd5f294, TypeM>, Enc_5ab2be {
15092 let Inst{7-5} = 0b111;
15093 let Inst{13-13} = 0b0;
15094 let Inst{31-21} = 0b11101100001;
15095 let hasNewValue = 1;
15096 let opNewValue = 0;
15097 let prefersSlot3 = 1;
15098 let Defs = [USR_OVF];
15100 def M2_mpy_sat_rnd_hh_s1 : HInst<
15101 (outs IntRegs:$Rd32),
15102 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15103 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15104 tc_8fd5f294, TypeM>, Enc_5ab2be {
15105 let Inst{7-5} = 0b111;
15106 let Inst{13-13} = 0b0;
15107 let Inst{31-21} = 0b11101100101;
15108 let hasNewValue = 1;
15109 let opNewValue = 0;
15110 let prefersSlot3 = 1;
15111 let Defs = [USR_OVF];
15113 def M2_mpy_sat_rnd_hl_s0 : HInst<
15114 (outs IntRegs:$Rd32),
15115 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15116 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15117 tc_8fd5f294, TypeM>, Enc_5ab2be {
15118 let Inst{7-5} = 0b110;
15119 let Inst{13-13} = 0b0;
15120 let Inst{31-21} = 0b11101100001;
15121 let hasNewValue = 1;
15122 let opNewValue = 0;
15123 let prefersSlot3 = 1;
15124 let Defs = [USR_OVF];
15126 def M2_mpy_sat_rnd_hl_s1 : HInst<
15127 (outs IntRegs:$Rd32),
15128 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15129 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15130 tc_8fd5f294, TypeM>, Enc_5ab2be {
15131 let Inst{7-5} = 0b110;
15132 let Inst{13-13} = 0b0;
15133 let Inst{31-21} = 0b11101100101;
15134 let hasNewValue = 1;
15135 let opNewValue = 0;
15136 let prefersSlot3 = 1;
15137 let Defs = [USR_OVF];
15139 def M2_mpy_sat_rnd_lh_s0 : HInst<
15140 (outs IntRegs:$Rd32),
15141 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15142 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15143 tc_8fd5f294, TypeM>, Enc_5ab2be {
15144 let Inst{7-5} = 0b101;
15145 let Inst{13-13} = 0b0;
15146 let Inst{31-21} = 0b11101100001;
15147 let hasNewValue = 1;
15148 let opNewValue = 0;
15149 let prefersSlot3 = 1;
15150 let Defs = [USR_OVF];
15152 def M2_mpy_sat_rnd_lh_s1 : HInst<
15153 (outs IntRegs:$Rd32),
15154 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15155 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15156 tc_8fd5f294, TypeM>, Enc_5ab2be {
15157 let Inst{7-5} = 0b101;
15158 let Inst{13-13} = 0b0;
15159 let Inst{31-21} = 0b11101100101;
15160 let hasNewValue = 1;
15161 let opNewValue = 0;
15162 let prefersSlot3 = 1;
15163 let Defs = [USR_OVF];
15165 def M2_mpy_sat_rnd_ll_s0 : HInst<
15166 (outs IntRegs:$Rd32),
15167 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15168 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15169 tc_8fd5f294, TypeM>, Enc_5ab2be {
15170 let Inst{7-5} = 0b100;
15171 let Inst{13-13} = 0b0;
15172 let Inst{31-21} = 0b11101100001;
15173 let hasNewValue = 1;
15174 let opNewValue = 0;
15175 let prefersSlot3 = 1;
15176 let Defs = [USR_OVF];
15178 def M2_mpy_sat_rnd_ll_s1 : HInst<
15179 (outs IntRegs:$Rd32),
15180 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15181 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15182 tc_8fd5f294, TypeM>, Enc_5ab2be {
15183 let Inst{7-5} = 0b100;
15184 let Inst{13-13} = 0b0;
15185 let Inst{31-21} = 0b11101100101;
15186 let hasNewValue = 1;
15187 let opNewValue = 0;
15188 let prefersSlot3 = 1;
15189 let Defs = [USR_OVF];
15191 def M2_mpy_up : HInst<
15192 (outs IntRegs:$Rd32),
15193 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15194 "$Rd32 = mpy($Rs32,$Rt32)",
15195 tc_8fd5f294, TypeM>, Enc_5ab2be {
15196 let Inst{7-5} = 0b001;
15197 let Inst{13-13} = 0b0;
15198 let Inst{31-21} = 0b11101101000;
15199 let hasNewValue = 1;
15200 let opNewValue = 0;
15201 let prefersSlot3 = 1;
15203 def M2_mpy_up_s1 : HInst<
15204 (outs IntRegs:$Rd32),
15205 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15206 "$Rd32 = mpy($Rs32,$Rt32):<<1",
15207 tc_8fd5f294, TypeM>, Enc_5ab2be {
15208 let Inst{7-5} = 0b010;
15209 let Inst{13-13} = 0b0;
15210 let Inst{31-21} = 0b11101101101;
15211 let hasNewValue = 1;
15212 let opNewValue = 0;
15213 let prefersSlot3 = 1;
15215 def M2_mpy_up_s1_sat : HInst<
15216 (outs IntRegs:$Rd32),
15217 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15218 "$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15219 tc_8fd5f294, TypeM>, Enc_5ab2be {
15220 let Inst{7-5} = 0b000;
15221 let Inst{13-13} = 0b0;
15222 let Inst{31-21} = 0b11101101111;
15223 let hasNewValue = 1;
15224 let opNewValue = 0;
15225 let prefersSlot3 = 1;
15226 let Defs = [USR_OVF];
15228 def M2_mpyd_acc_hh_s0 : HInst<
15229 (outs DoubleRegs:$Rxx32),
15230 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15231 "$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15232 tc_e913dc32, TypeM>, Enc_61f0b0 {
15233 let Inst{7-5} = 0b011;
15234 let Inst{13-13} = 0b0;
15235 let Inst{31-21} = 0b11100110000;
15236 let prefersSlot3 = 1;
15237 let Constraints = "$Rxx32 = $Rxx32in";
15239 def M2_mpyd_acc_hh_s1 : HInst<
15240 (outs DoubleRegs:$Rxx32),
15241 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15242 "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15243 tc_e913dc32, TypeM>, Enc_61f0b0 {
15244 let Inst{7-5} = 0b011;
15245 let Inst{13-13} = 0b0;
15246 let Inst{31-21} = 0b11100110100;
15247 let prefersSlot3 = 1;
15248 let Constraints = "$Rxx32 = $Rxx32in";
15250 def M2_mpyd_acc_hl_s0 : HInst<
15251 (outs DoubleRegs:$Rxx32),
15252 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15253 "$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15254 tc_e913dc32, TypeM>, Enc_61f0b0 {
15255 let Inst{7-5} = 0b010;
15256 let Inst{13-13} = 0b0;
15257 let Inst{31-21} = 0b11100110000;
15258 let prefersSlot3 = 1;
15259 let Constraints = "$Rxx32 = $Rxx32in";
15261 def M2_mpyd_acc_hl_s1 : HInst<
15262 (outs DoubleRegs:$Rxx32),
15263 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15264 "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15265 tc_e913dc32, TypeM>, Enc_61f0b0 {
15266 let Inst{7-5} = 0b010;
15267 let Inst{13-13} = 0b0;
15268 let Inst{31-21} = 0b11100110100;
15269 let prefersSlot3 = 1;
15270 let Constraints = "$Rxx32 = $Rxx32in";
15272 def M2_mpyd_acc_lh_s0 : HInst<
15273 (outs DoubleRegs:$Rxx32),
15274 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15275 "$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15276 tc_e913dc32, TypeM>, Enc_61f0b0 {
15277 let Inst{7-5} = 0b001;
15278 let Inst{13-13} = 0b0;
15279 let Inst{31-21} = 0b11100110000;
15280 let prefersSlot3 = 1;
15281 let Constraints = "$Rxx32 = $Rxx32in";
15283 def M2_mpyd_acc_lh_s1 : HInst<
15284 (outs DoubleRegs:$Rxx32),
15285 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15286 "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15287 tc_e913dc32, TypeM>, Enc_61f0b0 {
15288 let Inst{7-5} = 0b001;
15289 let Inst{13-13} = 0b0;
15290 let Inst{31-21} = 0b11100110100;
15291 let prefersSlot3 = 1;
15292 let Constraints = "$Rxx32 = $Rxx32in";
15294 def M2_mpyd_acc_ll_s0 : HInst<
15295 (outs DoubleRegs:$Rxx32),
15296 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15297 "$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15298 tc_e913dc32, TypeM>, Enc_61f0b0 {
15299 let Inst{7-5} = 0b000;
15300 let Inst{13-13} = 0b0;
15301 let Inst{31-21} = 0b11100110000;
15302 let prefersSlot3 = 1;
15303 let Constraints = "$Rxx32 = $Rxx32in";
15305 def M2_mpyd_acc_ll_s1 : HInst<
15306 (outs DoubleRegs:$Rxx32),
15307 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15308 "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15309 tc_e913dc32, TypeM>, Enc_61f0b0 {
15310 let Inst{7-5} = 0b000;
15311 let Inst{13-13} = 0b0;
15312 let Inst{31-21} = 0b11100110100;
15313 let prefersSlot3 = 1;
15314 let Constraints = "$Rxx32 = $Rxx32in";
15316 def M2_mpyd_hh_s0 : HInst<
15317 (outs DoubleRegs:$Rdd32),
15318 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15319 "$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15320 tc_8fd5f294, TypeM>, Enc_be32a5 {
15321 let Inst{7-5} = 0b011;
15322 let Inst{13-13} = 0b0;
15323 let Inst{31-21} = 0b11100100000;
15324 let prefersSlot3 = 1;
15326 def M2_mpyd_hh_s1 : HInst<
15327 (outs DoubleRegs:$Rdd32),
15328 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15329 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15330 tc_8fd5f294, TypeM>, Enc_be32a5 {
15331 let Inst{7-5} = 0b011;
15332 let Inst{13-13} = 0b0;
15333 let Inst{31-21} = 0b11100100100;
15334 let prefersSlot3 = 1;
15336 def M2_mpyd_hl_s0 : HInst<
15337 (outs DoubleRegs:$Rdd32),
15338 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15339 "$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15340 tc_8fd5f294, TypeM>, Enc_be32a5 {
15341 let Inst{7-5} = 0b010;
15342 let Inst{13-13} = 0b0;
15343 let Inst{31-21} = 0b11100100000;
15344 let prefersSlot3 = 1;
15346 def M2_mpyd_hl_s1 : HInst<
15347 (outs DoubleRegs:$Rdd32),
15348 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15349 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15350 tc_8fd5f294, TypeM>, Enc_be32a5 {
15351 let Inst{7-5} = 0b010;
15352 let Inst{13-13} = 0b0;
15353 let Inst{31-21} = 0b11100100100;
15354 let prefersSlot3 = 1;
15356 def M2_mpyd_lh_s0 : HInst<
15357 (outs DoubleRegs:$Rdd32),
15358 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15359 "$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15360 tc_8fd5f294, TypeM>, Enc_be32a5 {
15361 let Inst{7-5} = 0b001;
15362 let Inst{13-13} = 0b0;
15363 let Inst{31-21} = 0b11100100000;
15364 let prefersSlot3 = 1;
15366 def M2_mpyd_lh_s1 : HInst<
15367 (outs DoubleRegs:$Rdd32),
15368 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15369 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15370 tc_8fd5f294, TypeM>, Enc_be32a5 {
15371 let Inst{7-5} = 0b001;
15372 let Inst{13-13} = 0b0;
15373 let Inst{31-21} = 0b11100100100;
15374 let prefersSlot3 = 1;
15376 def M2_mpyd_ll_s0 : HInst<
15377 (outs DoubleRegs:$Rdd32),
15378 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15379 "$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15380 tc_8fd5f294, TypeM>, Enc_be32a5 {
15381 let Inst{7-5} = 0b000;
15382 let Inst{13-13} = 0b0;
15383 let Inst{31-21} = 0b11100100000;
15384 let prefersSlot3 = 1;
15386 def M2_mpyd_ll_s1 : HInst<
15387 (outs DoubleRegs:$Rdd32),
15388 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15389 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15390 tc_8fd5f294, TypeM>, Enc_be32a5 {
15391 let Inst{7-5} = 0b000;
15392 let Inst{13-13} = 0b0;
15393 let Inst{31-21} = 0b11100100100;
15394 let prefersSlot3 = 1;
15396 def M2_mpyd_nac_hh_s0 : HInst<
15397 (outs DoubleRegs:$Rxx32),
15398 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15399 "$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15400 tc_e913dc32, TypeM>, Enc_61f0b0 {
15401 let Inst{7-5} = 0b011;
15402 let Inst{13-13} = 0b0;
15403 let Inst{31-21} = 0b11100110001;
15404 let prefersSlot3 = 1;
15405 let Constraints = "$Rxx32 = $Rxx32in";
15407 def M2_mpyd_nac_hh_s1 : HInst<
15408 (outs DoubleRegs:$Rxx32),
15409 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15410 "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15411 tc_e913dc32, TypeM>, Enc_61f0b0 {
15412 let Inst{7-5} = 0b011;
15413 let Inst{13-13} = 0b0;
15414 let Inst{31-21} = 0b11100110101;
15415 let prefersSlot3 = 1;
15416 let Constraints = "$Rxx32 = $Rxx32in";
15418 def M2_mpyd_nac_hl_s0 : HInst<
15419 (outs DoubleRegs:$Rxx32),
15420 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15421 "$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15422 tc_e913dc32, TypeM>, Enc_61f0b0 {
15423 let Inst{7-5} = 0b010;
15424 let Inst{13-13} = 0b0;
15425 let Inst{31-21} = 0b11100110001;
15426 let prefersSlot3 = 1;
15427 let Constraints = "$Rxx32 = $Rxx32in";
15429 def M2_mpyd_nac_hl_s1 : HInst<
15430 (outs DoubleRegs:$Rxx32),
15431 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15432 "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15433 tc_e913dc32, TypeM>, Enc_61f0b0 {
15434 let Inst{7-5} = 0b010;
15435 let Inst{13-13} = 0b0;
15436 let Inst{31-21} = 0b11100110101;
15437 let prefersSlot3 = 1;
15438 let Constraints = "$Rxx32 = $Rxx32in";
15440 def M2_mpyd_nac_lh_s0 : HInst<
15441 (outs DoubleRegs:$Rxx32),
15442 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15443 "$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15444 tc_e913dc32, TypeM>, Enc_61f0b0 {
15445 let Inst{7-5} = 0b001;
15446 let Inst{13-13} = 0b0;
15447 let Inst{31-21} = 0b11100110001;
15448 let prefersSlot3 = 1;
15449 let Constraints = "$Rxx32 = $Rxx32in";
15451 def M2_mpyd_nac_lh_s1 : HInst<
15452 (outs DoubleRegs:$Rxx32),
15453 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15454 "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15455 tc_e913dc32, TypeM>, Enc_61f0b0 {
15456 let Inst{7-5} = 0b001;
15457 let Inst{13-13} = 0b0;
15458 let Inst{31-21} = 0b11100110101;
15459 let prefersSlot3 = 1;
15460 let Constraints = "$Rxx32 = $Rxx32in";
15462 def M2_mpyd_nac_ll_s0 : HInst<
15463 (outs DoubleRegs:$Rxx32),
15464 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15465 "$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15466 tc_e913dc32, TypeM>, Enc_61f0b0 {
15467 let Inst{7-5} = 0b000;
15468 let Inst{13-13} = 0b0;
15469 let Inst{31-21} = 0b11100110001;
15470 let prefersSlot3 = 1;
15471 let Constraints = "$Rxx32 = $Rxx32in";
15473 def M2_mpyd_nac_ll_s1 : HInst<
15474 (outs DoubleRegs:$Rxx32),
15475 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15476 "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15477 tc_e913dc32, TypeM>, Enc_61f0b0 {
15478 let Inst{7-5} = 0b000;
15479 let Inst{13-13} = 0b0;
15480 let Inst{31-21} = 0b11100110101;
15481 let prefersSlot3 = 1;
15482 let Constraints = "$Rxx32 = $Rxx32in";
15484 def M2_mpyd_rnd_hh_s0 : HInst<
15485 (outs DoubleRegs:$Rdd32),
15486 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15487 "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15488 tc_8fd5f294, TypeM>, Enc_be32a5 {
15489 let Inst{7-5} = 0b011;
15490 let Inst{13-13} = 0b0;
15491 let Inst{31-21} = 0b11100100001;
15492 let prefersSlot3 = 1;
15494 def M2_mpyd_rnd_hh_s1 : HInst<
15495 (outs DoubleRegs:$Rdd32),
15496 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15497 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15498 tc_8fd5f294, TypeM>, Enc_be32a5 {
15499 let Inst{7-5} = 0b011;
15500 let Inst{13-13} = 0b0;
15501 let Inst{31-21} = 0b11100100101;
15502 let prefersSlot3 = 1;
15504 def M2_mpyd_rnd_hl_s0 : HInst<
15505 (outs DoubleRegs:$Rdd32),
15506 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15507 "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15508 tc_8fd5f294, TypeM>, Enc_be32a5 {
15509 let Inst{7-5} = 0b010;
15510 let Inst{13-13} = 0b0;
15511 let Inst{31-21} = 0b11100100001;
15512 let prefersSlot3 = 1;
15514 def M2_mpyd_rnd_hl_s1 : HInst<
15515 (outs DoubleRegs:$Rdd32),
15516 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15517 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15518 tc_8fd5f294, TypeM>, Enc_be32a5 {
15519 let Inst{7-5} = 0b010;
15520 let Inst{13-13} = 0b0;
15521 let Inst{31-21} = 0b11100100101;
15522 let prefersSlot3 = 1;
15524 def M2_mpyd_rnd_lh_s0 : HInst<
15525 (outs DoubleRegs:$Rdd32),
15526 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15527 "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15528 tc_8fd5f294, TypeM>, Enc_be32a5 {
15529 let Inst{7-5} = 0b001;
15530 let Inst{13-13} = 0b0;
15531 let Inst{31-21} = 0b11100100001;
15532 let prefersSlot3 = 1;
15534 def M2_mpyd_rnd_lh_s1 : HInst<
15535 (outs DoubleRegs:$Rdd32),
15536 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15537 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15538 tc_8fd5f294, TypeM>, Enc_be32a5 {
15539 let Inst{7-5} = 0b001;
15540 let Inst{13-13} = 0b0;
15541 let Inst{31-21} = 0b11100100101;
15542 let prefersSlot3 = 1;
15544 def M2_mpyd_rnd_ll_s0 : HInst<
15545 (outs DoubleRegs:$Rdd32),
15546 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15547 "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15548 tc_8fd5f294, TypeM>, Enc_be32a5 {
15549 let Inst{7-5} = 0b000;
15550 let Inst{13-13} = 0b0;
15551 let Inst{31-21} = 0b11100100001;
15552 let prefersSlot3 = 1;
15554 def M2_mpyd_rnd_ll_s1 : HInst<
15555 (outs DoubleRegs:$Rdd32),
15556 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15557 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15558 tc_8fd5f294, TypeM>, Enc_be32a5 {
15559 let Inst{7-5} = 0b000;
15560 let Inst{13-13} = 0b0;
15561 let Inst{31-21} = 0b11100100101;
15562 let prefersSlot3 = 1;
15564 def M2_mpyi : HInst<
15565 (outs IntRegs:$Rd32),
15566 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15567 "$Rd32 = mpyi($Rs32,$Rt32)",
15568 tc_8fd5f294, TypeM>, Enc_5ab2be, ImmRegRel {
15569 let Inst{7-5} = 0b000;
15570 let Inst{13-13} = 0b0;
15571 let Inst{31-21} = 0b11101101000;
15572 let hasNewValue = 1;
15573 let opNewValue = 0;
15574 let prefersSlot3 = 1;
15575 let CextOpcode = "M2_mpyi";
15576 let InputType = "reg";
15578 def M2_mpysin : HInst<
15579 (outs IntRegs:$Rd32),
15580 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
15581 "$Rd32 = -mpyi($Rs32,#$Ii)",
15582 tc_1853ea6d, TypeM>, Enc_b8c967 {
15583 let Inst{13-13} = 0b0;
15584 let Inst{31-21} = 0b11100000100;
15585 let hasNewValue = 1;
15586 let opNewValue = 0;
15587 let prefersSlot3 = 1;
15589 def M2_mpysip : HInst<
15590 (outs IntRegs:$Rd32),
15591 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
15592 "$Rd32 = +mpyi($Rs32,#$Ii)",
15593 tc_1853ea6d, TypeM>, Enc_b8c967 {
15594 let Inst{13-13} = 0b0;
15595 let Inst{31-21} = 0b11100000000;
15596 let hasNewValue = 1;
15597 let opNewValue = 0;
15598 let prefersSlot3 = 1;
15599 let isExtendable = 1;
15600 let opExtendable = 2;
15601 let isExtentSigned = 0;
15602 let opExtentBits = 8;
15603 let opExtentAlign = 0;
15605 def M2_mpysmi : HInst<
15606 (outs IntRegs:$Rd32),
15607 (ins IntRegs:$Rs32, m32_0Imm:$Ii),
15608 "$Rd32 = mpyi($Rs32,#$Ii)",
15609 tc_1853ea6d, TypeM>, ImmRegRel {
15610 let hasNewValue = 1;
15611 let opNewValue = 0;
15612 let CextOpcode = "M2_mpyi";
15613 let InputType = "imm";
15615 let isExtendable = 1;
15616 let opExtendable = 2;
15617 let isExtentSigned = 1;
15618 let opExtentBits = 9;
15619 let opExtentAlign = 0;
15621 def M2_mpysu_up : HInst<
15622 (outs IntRegs:$Rd32),
15623 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15624 "$Rd32 = mpysu($Rs32,$Rt32)",
15625 tc_8fd5f294, TypeM>, Enc_5ab2be {
15626 let Inst{7-5} = 0b001;
15627 let Inst{13-13} = 0b0;
15628 let Inst{31-21} = 0b11101101011;
15629 let hasNewValue = 1;
15630 let opNewValue = 0;
15631 let prefersSlot3 = 1;
15633 def M2_mpyu_acc_hh_s0 : HInst<
15634 (outs IntRegs:$Rx32),
15635 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15636 "$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15637 tc_e913dc32, TypeM>, Enc_2ae154 {
15638 let Inst{7-5} = 0b011;
15639 let Inst{13-13} = 0b0;
15640 let Inst{31-21} = 0b11101110010;
15641 let hasNewValue = 1;
15642 let opNewValue = 0;
15643 let prefersSlot3 = 1;
15644 let Constraints = "$Rx32 = $Rx32in";
15646 def M2_mpyu_acc_hh_s1 : HInst<
15647 (outs IntRegs:$Rx32),
15648 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15649 "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15650 tc_e913dc32, TypeM>, Enc_2ae154 {
15651 let Inst{7-5} = 0b011;
15652 let Inst{13-13} = 0b0;
15653 let Inst{31-21} = 0b11101110110;
15654 let hasNewValue = 1;
15655 let opNewValue = 0;
15656 let prefersSlot3 = 1;
15657 let Constraints = "$Rx32 = $Rx32in";
15659 def M2_mpyu_acc_hl_s0 : HInst<
15660 (outs IntRegs:$Rx32),
15661 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15662 "$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15663 tc_e913dc32, TypeM>, Enc_2ae154 {
15664 let Inst{7-5} = 0b010;
15665 let Inst{13-13} = 0b0;
15666 let Inst{31-21} = 0b11101110010;
15667 let hasNewValue = 1;
15668 let opNewValue = 0;
15669 let prefersSlot3 = 1;
15670 let Constraints = "$Rx32 = $Rx32in";
15672 def M2_mpyu_acc_hl_s1 : HInst<
15673 (outs IntRegs:$Rx32),
15674 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15675 "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15676 tc_e913dc32, TypeM>, Enc_2ae154 {
15677 let Inst{7-5} = 0b010;
15678 let Inst{13-13} = 0b0;
15679 let Inst{31-21} = 0b11101110110;
15680 let hasNewValue = 1;
15681 let opNewValue = 0;
15682 let prefersSlot3 = 1;
15683 let Constraints = "$Rx32 = $Rx32in";
15685 def M2_mpyu_acc_lh_s0 : HInst<
15686 (outs IntRegs:$Rx32),
15687 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15688 "$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15689 tc_e913dc32, TypeM>, Enc_2ae154 {
15690 let Inst{7-5} = 0b001;
15691 let Inst{13-13} = 0b0;
15692 let Inst{31-21} = 0b11101110010;
15693 let hasNewValue = 1;
15694 let opNewValue = 0;
15695 let prefersSlot3 = 1;
15696 let Constraints = "$Rx32 = $Rx32in";
15698 def M2_mpyu_acc_lh_s1 : HInst<
15699 (outs IntRegs:$Rx32),
15700 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15701 "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
15702 tc_e913dc32, TypeM>, Enc_2ae154 {
15703 let Inst{7-5} = 0b001;
15704 let Inst{13-13} = 0b0;
15705 let Inst{31-21} = 0b11101110110;
15706 let hasNewValue = 1;
15707 let opNewValue = 0;
15708 let prefersSlot3 = 1;
15709 let Constraints = "$Rx32 = $Rx32in";
15711 def M2_mpyu_acc_ll_s0 : HInst<
15712 (outs IntRegs:$Rx32),
15713 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15714 "$Rx32 += mpyu($Rs32.l,$Rt32.l)",
15715 tc_e913dc32, TypeM>, Enc_2ae154 {
15716 let Inst{7-5} = 0b000;
15717 let Inst{13-13} = 0b0;
15718 let Inst{31-21} = 0b11101110010;
15719 let hasNewValue = 1;
15720 let opNewValue = 0;
15721 let prefersSlot3 = 1;
15722 let Constraints = "$Rx32 = $Rx32in";
15724 def M2_mpyu_acc_ll_s1 : HInst<
15725 (outs IntRegs:$Rx32),
15726 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15727 "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
15728 tc_e913dc32, TypeM>, Enc_2ae154 {
15729 let Inst{7-5} = 0b000;
15730 let Inst{13-13} = 0b0;
15731 let Inst{31-21} = 0b11101110110;
15732 let hasNewValue = 1;
15733 let opNewValue = 0;
15734 let prefersSlot3 = 1;
15735 let Constraints = "$Rx32 = $Rx32in";
15737 def M2_mpyu_hh_s0 : HInst<
15738 (outs IntRegs:$Rd32),
15739 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15740 "$Rd32 = mpyu($Rs32.h,$Rt32.h)",
15741 tc_8fd5f294, TypeM>, Enc_5ab2be {
15742 let Inst{7-5} = 0b011;
15743 let Inst{13-13} = 0b0;
15744 let Inst{31-21} = 0b11101100010;
15745 let hasNewValue = 1;
15746 let opNewValue = 0;
15747 let prefersSlot3 = 1;
15749 def M2_mpyu_hh_s1 : HInst<
15750 (outs IntRegs:$Rd32),
15751 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15752 "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
15753 tc_8fd5f294, TypeM>, Enc_5ab2be {
15754 let Inst{7-5} = 0b011;
15755 let Inst{13-13} = 0b0;
15756 let Inst{31-21} = 0b11101100110;
15757 let hasNewValue = 1;
15758 let opNewValue = 0;
15759 let prefersSlot3 = 1;
15761 def M2_mpyu_hl_s0 : HInst<
15762 (outs IntRegs:$Rd32),
15763 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15764 "$Rd32 = mpyu($Rs32.h,$Rt32.l)",
15765 tc_8fd5f294, TypeM>, Enc_5ab2be {
15766 let Inst{7-5} = 0b010;
15767 let Inst{13-13} = 0b0;
15768 let Inst{31-21} = 0b11101100010;
15769 let hasNewValue = 1;
15770 let opNewValue = 0;
15771 let prefersSlot3 = 1;
15773 def M2_mpyu_hl_s1 : HInst<
15774 (outs IntRegs:$Rd32),
15775 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15776 "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
15777 tc_8fd5f294, TypeM>, Enc_5ab2be {
15778 let Inst{7-5} = 0b010;
15779 let Inst{13-13} = 0b0;
15780 let Inst{31-21} = 0b11101100110;
15781 let hasNewValue = 1;
15782 let opNewValue = 0;
15783 let prefersSlot3 = 1;
15785 def M2_mpyu_lh_s0 : HInst<
15786 (outs IntRegs:$Rd32),
15787 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15788 "$Rd32 = mpyu($Rs32.l,$Rt32.h)",
15789 tc_8fd5f294, TypeM>, Enc_5ab2be {
15790 let Inst{7-5} = 0b001;
15791 let Inst{13-13} = 0b0;
15792 let Inst{31-21} = 0b11101100010;
15793 let hasNewValue = 1;
15794 let opNewValue = 0;
15795 let prefersSlot3 = 1;
15797 def M2_mpyu_lh_s1 : HInst<
15798 (outs IntRegs:$Rd32),
15799 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15800 "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
15801 tc_8fd5f294, TypeM>, Enc_5ab2be {
15802 let Inst{7-5} = 0b001;
15803 let Inst{13-13} = 0b0;
15804 let Inst{31-21} = 0b11101100110;
15805 let hasNewValue = 1;
15806 let opNewValue = 0;
15807 let prefersSlot3 = 1;
15809 def M2_mpyu_ll_s0 : HInst<
15810 (outs IntRegs:$Rd32),
15811 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15812 "$Rd32 = mpyu($Rs32.l,$Rt32.l)",
15813 tc_8fd5f294, TypeM>, Enc_5ab2be {
15814 let Inst{7-5} = 0b000;
15815 let Inst{13-13} = 0b0;
15816 let Inst{31-21} = 0b11101100010;
15817 let hasNewValue = 1;
15818 let opNewValue = 0;
15819 let prefersSlot3 = 1;
15821 def M2_mpyu_ll_s1 : HInst<
15822 (outs IntRegs:$Rd32),
15823 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15824 "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
15825 tc_8fd5f294, TypeM>, Enc_5ab2be {
15826 let Inst{7-5} = 0b000;
15827 let Inst{13-13} = 0b0;
15828 let Inst{31-21} = 0b11101100110;
15829 let hasNewValue = 1;
15830 let opNewValue = 0;
15831 let prefersSlot3 = 1;
15833 def M2_mpyu_nac_hh_s0 : HInst<
15834 (outs IntRegs:$Rx32),
15835 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15836 "$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
15837 tc_e913dc32, TypeM>, Enc_2ae154 {
15838 let Inst{7-5} = 0b011;
15839 let Inst{13-13} = 0b0;
15840 let Inst{31-21} = 0b11101110011;
15841 let hasNewValue = 1;
15842 let opNewValue = 0;
15843 let prefersSlot3 = 1;
15844 let Constraints = "$Rx32 = $Rx32in";
15846 def M2_mpyu_nac_hh_s1 : HInst<
15847 (outs IntRegs:$Rx32),
15848 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15849 "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
15850 tc_e913dc32, TypeM>, Enc_2ae154 {
15851 let Inst{7-5} = 0b011;
15852 let Inst{13-13} = 0b0;
15853 let Inst{31-21} = 0b11101110111;
15854 let hasNewValue = 1;
15855 let opNewValue = 0;
15856 let prefersSlot3 = 1;
15857 let Constraints = "$Rx32 = $Rx32in";
15859 def M2_mpyu_nac_hl_s0 : HInst<
15860 (outs IntRegs:$Rx32),
15861 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15862 "$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
15863 tc_e913dc32, TypeM>, Enc_2ae154 {
15864 let Inst{7-5} = 0b010;
15865 let Inst{13-13} = 0b0;
15866 let Inst{31-21} = 0b11101110011;
15867 let hasNewValue = 1;
15868 let opNewValue = 0;
15869 let prefersSlot3 = 1;
15870 let Constraints = "$Rx32 = $Rx32in";
15872 def M2_mpyu_nac_hl_s1 : HInst<
15873 (outs IntRegs:$Rx32),
15874 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15875 "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
15876 tc_e913dc32, TypeM>, Enc_2ae154 {
15877 let Inst{7-5} = 0b010;
15878 let Inst{13-13} = 0b0;
15879 let Inst{31-21} = 0b11101110111;
15880 let hasNewValue = 1;
15881 let opNewValue = 0;
15882 let prefersSlot3 = 1;
15883 let Constraints = "$Rx32 = $Rx32in";
15885 def M2_mpyu_nac_lh_s0 : HInst<
15886 (outs IntRegs:$Rx32),
15887 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15888 "$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
15889 tc_e913dc32, TypeM>, Enc_2ae154 {
15890 let Inst{7-5} = 0b001;
15891 let Inst{13-13} = 0b0;
15892 let Inst{31-21} = 0b11101110011;
15893 let hasNewValue = 1;
15894 let opNewValue = 0;
15895 let prefersSlot3 = 1;
15896 let Constraints = "$Rx32 = $Rx32in";
15898 def M2_mpyu_nac_lh_s1 : HInst<
15899 (outs IntRegs:$Rx32),
15900 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15901 "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
15902 tc_e913dc32, TypeM>, Enc_2ae154 {
15903 let Inst{7-5} = 0b001;
15904 let Inst{13-13} = 0b0;
15905 let Inst{31-21} = 0b11101110111;
15906 let hasNewValue = 1;
15907 let opNewValue = 0;
15908 let prefersSlot3 = 1;
15909 let Constraints = "$Rx32 = $Rx32in";
15911 def M2_mpyu_nac_ll_s0 : HInst<
15912 (outs IntRegs:$Rx32),
15913 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15914 "$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
15915 tc_e913dc32, TypeM>, Enc_2ae154 {
15916 let Inst{7-5} = 0b000;
15917 let Inst{13-13} = 0b0;
15918 let Inst{31-21} = 0b11101110011;
15919 let hasNewValue = 1;
15920 let opNewValue = 0;
15921 let prefersSlot3 = 1;
15922 let Constraints = "$Rx32 = $Rx32in";
15924 def M2_mpyu_nac_ll_s1 : HInst<
15925 (outs IntRegs:$Rx32),
15926 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15927 "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
15928 tc_e913dc32, TypeM>, Enc_2ae154 {
15929 let Inst{7-5} = 0b000;
15930 let Inst{13-13} = 0b0;
15931 let Inst{31-21} = 0b11101110111;
15932 let hasNewValue = 1;
15933 let opNewValue = 0;
15934 let prefersSlot3 = 1;
15935 let Constraints = "$Rx32 = $Rx32in";
15937 def M2_mpyu_up : HInst<
15938 (outs IntRegs:$Rd32),
15939 (ins IntRegs:$Rs32, IntRegs:$Rt32),
15940 "$Rd32 = mpyu($Rs32,$Rt32)",
15941 tc_8fd5f294, TypeM>, Enc_5ab2be {
15942 let Inst{7-5} = 0b001;
15943 let Inst{13-13} = 0b0;
15944 let Inst{31-21} = 0b11101101010;
15945 let hasNewValue = 1;
15946 let opNewValue = 0;
15947 let prefersSlot3 = 1;
15949 def M2_mpyud_acc_hh_s0 : HInst<
15950 (outs DoubleRegs:$Rxx32),
15951 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15952 "$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
15953 tc_e913dc32, TypeM>, Enc_61f0b0 {
15954 let Inst{7-5} = 0b011;
15955 let Inst{13-13} = 0b0;
15956 let Inst{31-21} = 0b11100110010;
15957 let prefersSlot3 = 1;
15958 let Constraints = "$Rxx32 = $Rxx32in";
15960 def M2_mpyud_acc_hh_s1 : HInst<
15961 (outs DoubleRegs:$Rxx32),
15962 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15963 "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15964 tc_e913dc32, TypeM>, Enc_61f0b0 {
15965 let Inst{7-5} = 0b011;
15966 let Inst{13-13} = 0b0;
15967 let Inst{31-21} = 0b11100110110;
15968 let prefersSlot3 = 1;
15969 let Constraints = "$Rxx32 = $Rxx32in";
15971 def M2_mpyud_acc_hl_s0 : HInst<
15972 (outs DoubleRegs:$Rxx32),
15973 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15974 "$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
15975 tc_e913dc32, TypeM>, Enc_61f0b0 {
15976 let Inst{7-5} = 0b010;
15977 let Inst{13-13} = 0b0;
15978 let Inst{31-21} = 0b11100110010;
15979 let prefersSlot3 = 1;
15980 let Constraints = "$Rxx32 = $Rxx32in";
15982 def M2_mpyud_acc_hl_s1 : HInst<
15983 (outs DoubleRegs:$Rxx32),
15984 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15985 "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15986 tc_e913dc32, TypeM>, Enc_61f0b0 {
15987 let Inst{7-5} = 0b010;
15988 let Inst{13-13} = 0b0;
15989 let Inst{31-21} = 0b11100110110;
15990 let prefersSlot3 = 1;
15991 let Constraints = "$Rxx32 = $Rxx32in";
15993 def M2_mpyud_acc_lh_s0 : HInst<
15994 (outs DoubleRegs:$Rxx32),
15995 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15996 "$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
15997 tc_e913dc32, TypeM>, Enc_61f0b0 {
15998 let Inst{7-5} = 0b001;
15999 let Inst{13-13} = 0b0;
16000 let Inst{31-21} = 0b11100110010;
16001 let prefersSlot3 = 1;
16002 let Constraints = "$Rxx32 = $Rxx32in";
16004 def M2_mpyud_acc_lh_s1 : HInst<
16005 (outs DoubleRegs:$Rxx32),
16006 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16007 "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16008 tc_e913dc32, TypeM>, Enc_61f0b0 {
16009 let Inst{7-5} = 0b001;
16010 let Inst{13-13} = 0b0;
16011 let Inst{31-21} = 0b11100110110;
16012 let prefersSlot3 = 1;
16013 let Constraints = "$Rxx32 = $Rxx32in";
16015 def M2_mpyud_acc_ll_s0 : HInst<
16016 (outs DoubleRegs:$Rxx32),
16017 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16018 "$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16019 tc_e913dc32, TypeM>, Enc_61f0b0 {
16020 let Inst{7-5} = 0b000;
16021 let Inst{13-13} = 0b0;
16022 let Inst{31-21} = 0b11100110010;
16023 let prefersSlot3 = 1;
16024 let Constraints = "$Rxx32 = $Rxx32in";
16026 def M2_mpyud_acc_ll_s1 : HInst<
16027 (outs DoubleRegs:$Rxx32),
16028 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16029 "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16030 tc_e913dc32, TypeM>, Enc_61f0b0 {
16031 let Inst{7-5} = 0b000;
16032 let Inst{13-13} = 0b0;
16033 let Inst{31-21} = 0b11100110110;
16034 let prefersSlot3 = 1;
16035 let Constraints = "$Rxx32 = $Rxx32in";
16037 def M2_mpyud_hh_s0 : HInst<
16038 (outs DoubleRegs:$Rdd32),
16039 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16040 "$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16041 tc_8fd5f294, TypeM>, Enc_be32a5 {
16042 let Inst{7-5} = 0b011;
16043 let Inst{13-13} = 0b0;
16044 let Inst{31-21} = 0b11100100010;
16045 let prefersSlot3 = 1;
16047 def M2_mpyud_hh_s1 : HInst<
16048 (outs DoubleRegs:$Rdd32),
16049 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16050 "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16051 tc_8fd5f294, TypeM>, Enc_be32a5 {
16052 let Inst{7-5} = 0b011;
16053 let Inst{13-13} = 0b0;
16054 let Inst{31-21} = 0b11100100110;
16055 let prefersSlot3 = 1;
16057 def M2_mpyud_hl_s0 : HInst<
16058 (outs DoubleRegs:$Rdd32),
16059 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16060 "$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16061 tc_8fd5f294, TypeM>, Enc_be32a5 {
16062 let Inst{7-5} = 0b010;
16063 let Inst{13-13} = 0b0;
16064 let Inst{31-21} = 0b11100100010;
16065 let prefersSlot3 = 1;
16067 def M2_mpyud_hl_s1 : HInst<
16068 (outs DoubleRegs:$Rdd32),
16069 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16070 "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16071 tc_8fd5f294, TypeM>, Enc_be32a5 {
16072 let Inst{7-5} = 0b010;
16073 let Inst{13-13} = 0b0;
16074 let Inst{31-21} = 0b11100100110;
16075 let prefersSlot3 = 1;
16077 def M2_mpyud_lh_s0 : HInst<
16078 (outs DoubleRegs:$Rdd32),
16079 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16080 "$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16081 tc_8fd5f294, TypeM>, Enc_be32a5 {
16082 let Inst{7-5} = 0b001;
16083 let Inst{13-13} = 0b0;
16084 let Inst{31-21} = 0b11100100010;
16085 let prefersSlot3 = 1;
16087 def M2_mpyud_lh_s1 : HInst<
16088 (outs DoubleRegs:$Rdd32),
16089 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16090 "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16091 tc_8fd5f294, TypeM>, Enc_be32a5 {
16092 let Inst{7-5} = 0b001;
16093 let Inst{13-13} = 0b0;
16094 let Inst{31-21} = 0b11100100110;
16095 let prefersSlot3 = 1;
16097 def M2_mpyud_ll_s0 : HInst<
16098 (outs DoubleRegs:$Rdd32),
16099 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16100 "$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16101 tc_8fd5f294, TypeM>, Enc_be32a5 {
16102 let Inst{7-5} = 0b000;
16103 let Inst{13-13} = 0b0;
16104 let Inst{31-21} = 0b11100100010;
16105 let prefersSlot3 = 1;
16107 def M2_mpyud_ll_s1 : HInst<
16108 (outs DoubleRegs:$Rdd32),
16109 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16110 "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16111 tc_8fd5f294, TypeM>, Enc_be32a5 {
16112 let Inst{7-5} = 0b000;
16113 let Inst{13-13} = 0b0;
16114 let Inst{31-21} = 0b11100100110;
16115 let prefersSlot3 = 1;
16117 def M2_mpyud_nac_hh_s0 : HInst<
16118 (outs DoubleRegs:$Rxx32),
16119 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16120 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16121 tc_e913dc32, TypeM>, Enc_61f0b0 {
16122 let Inst{7-5} = 0b011;
16123 let Inst{13-13} = 0b0;
16124 let Inst{31-21} = 0b11100110011;
16125 let prefersSlot3 = 1;
16126 let Constraints = "$Rxx32 = $Rxx32in";
16128 def M2_mpyud_nac_hh_s1 : HInst<
16129 (outs DoubleRegs:$Rxx32),
16130 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16131 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16132 tc_e913dc32, TypeM>, Enc_61f0b0 {
16133 let Inst{7-5} = 0b011;
16134 let Inst{13-13} = 0b0;
16135 let Inst{31-21} = 0b11100110111;
16136 let prefersSlot3 = 1;
16137 let Constraints = "$Rxx32 = $Rxx32in";
16139 def M2_mpyud_nac_hl_s0 : HInst<
16140 (outs DoubleRegs:$Rxx32),
16141 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16142 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16143 tc_e913dc32, TypeM>, Enc_61f0b0 {
16144 let Inst{7-5} = 0b010;
16145 let Inst{13-13} = 0b0;
16146 let Inst{31-21} = 0b11100110011;
16147 let prefersSlot3 = 1;
16148 let Constraints = "$Rxx32 = $Rxx32in";
16150 def M2_mpyud_nac_hl_s1 : HInst<
16151 (outs DoubleRegs:$Rxx32),
16152 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16153 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16154 tc_e913dc32, TypeM>, Enc_61f0b0 {
16155 let Inst{7-5} = 0b010;
16156 let Inst{13-13} = 0b0;
16157 let Inst{31-21} = 0b11100110111;
16158 let prefersSlot3 = 1;
16159 let Constraints = "$Rxx32 = $Rxx32in";
16161 def M2_mpyud_nac_lh_s0 : HInst<
16162 (outs DoubleRegs:$Rxx32),
16163 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16164 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16165 tc_e913dc32, TypeM>, Enc_61f0b0 {
16166 let Inst{7-5} = 0b001;
16167 let Inst{13-13} = 0b0;
16168 let Inst{31-21} = 0b11100110011;
16169 let prefersSlot3 = 1;
16170 let Constraints = "$Rxx32 = $Rxx32in";
16172 def M2_mpyud_nac_lh_s1 : HInst<
16173 (outs DoubleRegs:$Rxx32),
16174 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16175 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16176 tc_e913dc32, TypeM>, Enc_61f0b0 {
16177 let Inst{7-5} = 0b001;
16178 let Inst{13-13} = 0b0;
16179 let Inst{31-21} = 0b11100110111;
16180 let prefersSlot3 = 1;
16181 let Constraints = "$Rxx32 = $Rxx32in";
16183 def M2_mpyud_nac_ll_s0 : HInst<
16184 (outs DoubleRegs:$Rxx32),
16185 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16186 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16187 tc_e913dc32, TypeM>, Enc_61f0b0 {
16188 let Inst{7-5} = 0b000;
16189 let Inst{13-13} = 0b0;
16190 let Inst{31-21} = 0b11100110011;
16191 let prefersSlot3 = 1;
16192 let Constraints = "$Rxx32 = $Rxx32in";
16194 def M2_mpyud_nac_ll_s1 : HInst<
16195 (outs DoubleRegs:$Rxx32),
16196 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16197 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16198 tc_e913dc32, TypeM>, Enc_61f0b0 {
16199 let Inst{7-5} = 0b000;
16200 let Inst{13-13} = 0b0;
16201 let Inst{31-21} = 0b11100110111;
16202 let prefersSlot3 = 1;
16203 let Constraints = "$Rxx32 = $Rxx32in";
16205 def M2_mpyui : HInst<
16206 (outs IntRegs:$Rd32),
16207 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16208 "$Rd32 = mpyui($Rs32,$Rt32)",
16209 tc_8fd5f294, TypeM> {
16210 let hasNewValue = 1;
16211 let opNewValue = 0;
16213 let isCodeGenOnly = 1;
16215 def M2_nacci : HInst<
16216 (outs IntRegs:$Rx32),
16217 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16218 "$Rx32 -= add($Rs32,$Rt32)",
16219 tc_c74f796f, TypeM>, Enc_2ae154 {
16220 let Inst{7-5} = 0b001;
16221 let Inst{13-13} = 0b0;
16222 let Inst{31-21} = 0b11101111100;
16223 let hasNewValue = 1;
16224 let opNewValue = 0;
16225 let prefersSlot3 = 1;
16226 let InputType = "reg";
16227 let Constraints = "$Rx32 = $Rx32in";
16229 def M2_naccii : HInst<
16230 (outs IntRegs:$Rx32),
16231 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16232 "$Rx32 -= add($Rs32,#$Ii)",
16233 tc_c74f796f, TypeM>, Enc_c90aca {
16234 let Inst{13-13} = 0b0;
16235 let Inst{31-21} = 0b11100010100;
16236 let hasNewValue = 1;
16237 let opNewValue = 0;
16238 let prefersSlot3 = 1;
16239 let InputType = "imm";
16240 let isExtendable = 1;
16241 let opExtendable = 3;
16242 let isExtentSigned = 1;
16243 let opExtentBits = 8;
16244 let opExtentAlign = 0;
16245 let Constraints = "$Rx32 = $Rx32in";
16247 def M2_subacc : HInst<
16248 (outs IntRegs:$Rx32),
16249 (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16250 "$Rx32 += sub($Rt32,$Rs32)",
16251 tc_c74f796f, TypeM>, Enc_a568d4 {
16252 let Inst{7-5} = 0b011;
16253 let Inst{13-13} = 0b0;
16254 let Inst{31-21} = 0b11101111000;
16255 let hasNewValue = 1;
16256 let opNewValue = 0;
16257 let prefersSlot3 = 1;
16258 let InputType = "reg";
16259 let Constraints = "$Rx32 = $Rx32in";
16261 def M2_vabsdiffh : HInst<
16262 (outs DoubleRegs:$Rdd32),
16263 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16264 "$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16265 tc_2b6f77c6, TypeM>, Enc_ea23e4 {
16266 let Inst{7-5} = 0b000;
16267 let Inst{13-13} = 0b0;
16268 let Inst{31-21} = 0b11101000011;
16269 let prefersSlot3 = 1;
16271 def M2_vabsdiffw : HInst<
16272 (outs DoubleRegs:$Rdd32),
16273 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16274 "$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16275 tc_2b6f77c6, TypeM>, Enc_ea23e4 {
16276 let Inst{7-5} = 0b000;
16277 let Inst{13-13} = 0b0;
16278 let Inst{31-21} = 0b11101000001;
16279 let prefersSlot3 = 1;
16281 def M2_vcmac_s0_sat_i : HInst<
16282 (outs DoubleRegs:$Rxx32),
16283 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16284 "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16285 tc_e913dc32, TypeM>, Enc_88c16c {
16286 let Inst{7-5} = 0b100;
16287 let Inst{13-13} = 0b0;
16288 let Inst{31-21} = 0b11101010010;
16289 let prefersSlot3 = 1;
16290 let Defs = [USR_OVF];
16291 let Constraints = "$Rxx32 = $Rxx32in";
16293 def M2_vcmac_s0_sat_r : HInst<
16294 (outs DoubleRegs:$Rxx32),
16295 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16296 "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16297 tc_e913dc32, TypeM>, Enc_88c16c {
16298 let Inst{7-5} = 0b100;
16299 let Inst{13-13} = 0b0;
16300 let Inst{31-21} = 0b11101010001;
16301 let prefersSlot3 = 1;
16302 let Defs = [USR_OVF];
16303 let Constraints = "$Rxx32 = $Rxx32in";
16305 def M2_vcmpy_s0_sat_i : HInst<
16306 (outs DoubleRegs:$Rdd32),
16307 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16308 "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16309 tc_8fd5f294, TypeM>, Enc_a56825 {
16310 let Inst{7-5} = 0b110;
16311 let Inst{13-13} = 0b0;
16312 let Inst{31-21} = 0b11101000010;
16313 let prefersSlot3 = 1;
16314 let Defs = [USR_OVF];
16316 def M2_vcmpy_s0_sat_r : HInst<
16317 (outs DoubleRegs:$Rdd32),
16318 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16319 "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16320 tc_8fd5f294, TypeM>, Enc_a56825 {
16321 let Inst{7-5} = 0b110;
16322 let Inst{13-13} = 0b0;
16323 let Inst{31-21} = 0b11101000001;
16324 let prefersSlot3 = 1;
16325 let Defs = [USR_OVF];
16327 def M2_vcmpy_s1_sat_i : HInst<
16328 (outs DoubleRegs:$Rdd32),
16329 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16330 "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16331 tc_8fd5f294, TypeM>, Enc_a56825 {
16332 let Inst{7-5} = 0b110;
16333 let Inst{13-13} = 0b0;
16334 let Inst{31-21} = 0b11101000110;
16335 let prefersSlot3 = 1;
16336 let Defs = [USR_OVF];
16338 def M2_vcmpy_s1_sat_r : HInst<
16339 (outs DoubleRegs:$Rdd32),
16340 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16341 "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16342 tc_8fd5f294, TypeM>, Enc_a56825 {
16343 let Inst{7-5} = 0b110;
16344 let Inst{13-13} = 0b0;
16345 let Inst{31-21} = 0b11101000101;
16346 let prefersSlot3 = 1;
16347 let Defs = [USR_OVF];
16349 def M2_vdmacs_s0 : HInst<
16350 (outs DoubleRegs:$Rxx32),
16351 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16352 "$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16353 tc_e913dc32, TypeM>, Enc_88c16c {
16354 let Inst{7-5} = 0b100;
16355 let Inst{13-13} = 0b0;
16356 let Inst{31-21} = 0b11101010000;
16357 let prefersSlot3 = 1;
16358 let Defs = [USR_OVF];
16359 let Constraints = "$Rxx32 = $Rxx32in";
16361 def M2_vdmacs_s1 : HInst<
16362 (outs DoubleRegs:$Rxx32),
16363 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16364 "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16365 tc_e913dc32, TypeM>, Enc_88c16c {
16366 let Inst{7-5} = 0b100;
16367 let Inst{13-13} = 0b0;
16368 let Inst{31-21} = 0b11101010100;
16369 let prefersSlot3 = 1;
16370 let Defs = [USR_OVF];
16371 let Constraints = "$Rxx32 = $Rxx32in";
16373 def M2_vdmpyrs_s0 : HInst<
16374 (outs IntRegs:$Rd32),
16375 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16376 "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16377 tc_8fd5f294, TypeM>, Enc_d2216a {
16378 let Inst{7-5} = 0b000;
16379 let Inst{13-13} = 0b0;
16380 let Inst{31-21} = 0b11101001000;
16381 let hasNewValue = 1;
16382 let opNewValue = 0;
16383 let prefersSlot3 = 1;
16384 let Defs = [USR_OVF];
16386 def M2_vdmpyrs_s1 : HInst<
16387 (outs IntRegs:$Rd32),
16388 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16389 "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16390 tc_8fd5f294, TypeM>, Enc_d2216a {
16391 let Inst{7-5} = 0b000;
16392 let Inst{13-13} = 0b0;
16393 let Inst{31-21} = 0b11101001100;
16394 let hasNewValue = 1;
16395 let opNewValue = 0;
16396 let prefersSlot3 = 1;
16397 let Defs = [USR_OVF];
16399 def M2_vdmpys_s0 : HInst<
16400 (outs DoubleRegs:$Rdd32),
16401 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16402 "$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16403 tc_8fd5f294, TypeM>, Enc_a56825 {
16404 let Inst{7-5} = 0b100;
16405 let Inst{13-13} = 0b0;
16406 let Inst{31-21} = 0b11101000000;
16407 let prefersSlot3 = 1;
16408 let Defs = [USR_OVF];
16410 def M2_vdmpys_s1 : HInst<
16411 (outs DoubleRegs:$Rdd32),
16412 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16413 "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16414 tc_8fd5f294, TypeM>, Enc_a56825 {
16415 let Inst{7-5} = 0b100;
16416 let Inst{13-13} = 0b0;
16417 let Inst{31-21} = 0b11101000100;
16418 let prefersSlot3 = 1;
16419 let Defs = [USR_OVF];
16421 def M2_vmac2 : HInst<
16422 (outs DoubleRegs:$Rxx32),
16423 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16424 "$Rxx32 += vmpyh($Rs32,$Rt32)",
16425 tc_e913dc32, TypeM>, Enc_61f0b0 {
16426 let Inst{7-5} = 0b001;
16427 let Inst{13-13} = 0b0;
16428 let Inst{31-21} = 0b11100111001;
16429 let prefersSlot3 = 1;
16430 let Constraints = "$Rxx32 = $Rxx32in";
16432 def M2_vmac2es : HInst<
16433 (outs DoubleRegs:$Rxx32),
16434 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16435 "$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16436 tc_e913dc32, TypeM>, Enc_88c16c {
16437 let Inst{7-5} = 0b010;
16438 let Inst{13-13} = 0b0;
16439 let Inst{31-21} = 0b11101010001;
16440 let prefersSlot3 = 1;
16441 let Constraints = "$Rxx32 = $Rxx32in";
16443 def M2_vmac2es_s0 : HInst<
16444 (outs DoubleRegs:$Rxx32),
16445 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16446 "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16447 tc_e913dc32, TypeM>, Enc_88c16c {
16448 let Inst{7-5} = 0b110;
16449 let Inst{13-13} = 0b0;
16450 let Inst{31-21} = 0b11101010000;
16451 let prefersSlot3 = 1;
16452 let Defs = [USR_OVF];
16453 let Constraints = "$Rxx32 = $Rxx32in";
16455 def M2_vmac2es_s1 : HInst<
16456 (outs DoubleRegs:$Rxx32),
16457 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16458 "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16459 tc_e913dc32, TypeM>, Enc_88c16c {
16460 let Inst{7-5} = 0b110;
16461 let Inst{13-13} = 0b0;
16462 let Inst{31-21} = 0b11101010100;
16463 let prefersSlot3 = 1;
16464 let Defs = [USR_OVF];
16465 let Constraints = "$Rxx32 = $Rxx32in";
16467 def M2_vmac2s_s0 : HInst<
16468 (outs DoubleRegs:$Rxx32),
16469 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16470 "$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16471 tc_e913dc32, TypeM>, Enc_61f0b0 {
16472 let Inst{7-5} = 0b101;
16473 let Inst{13-13} = 0b0;
16474 let Inst{31-21} = 0b11100111000;
16475 let prefersSlot3 = 1;
16476 let Defs = [USR_OVF];
16477 let Constraints = "$Rxx32 = $Rxx32in";
16479 def M2_vmac2s_s1 : HInst<
16480 (outs DoubleRegs:$Rxx32),
16481 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16482 "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16483 tc_e913dc32, TypeM>, Enc_61f0b0 {
16484 let Inst{7-5} = 0b101;
16485 let Inst{13-13} = 0b0;
16486 let Inst{31-21} = 0b11100111100;
16487 let prefersSlot3 = 1;
16488 let Defs = [USR_OVF];
16489 let Constraints = "$Rxx32 = $Rxx32in";
16491 def M2_vmac2su_s0 : HInst<
16492 (outs DoubleRegs:$Rxx32),
16493 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16494 "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16495 tc_e913dc32, TypeM>, Enc_61f0b0 {
16496 let Inst{7-5} = 0b101;
16497 let Inst{13-13} = 0b0;
16498 let Inst{31-21} = 0b11100111011;
16499 let prefersSlot3 = 1;
16500 let Defs = [USR_OVF];
16501 let Constraints = "$Rxx32 = $Rxx32in";
16503 def M2_vmac2su_s1 : HInst<
16504 (outs DoubleRegs:$Rxx32),
16505 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16506 "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16507 tc_e913dc32, TypeM>, Enc_61f0b0 {
16508 let Inst{7-5} = 0b101;
16509 let Inst{13-13} = 0b0;
16510 let Inst{31-21} = 0b11100111111;
16511 let prefersSlot3 = 1;
16512 let Defs = [USR_OVF];
16513 let Constraints = "$Rxx32 = $Rxx32in";
16515 def M2_vmpy2es_s0 : HInst<
16516 (outs DoubleRegs:$Rdd32),
16517 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16518 "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16519 tc_8fd5f294, TypeM>, Enc_a56825 {
16520 let Inst{7-5} = 0b110;
16521 let Inst{13-13} = 0b0;
16522 let Inst{31-21} = 0b11101000000;
16523 let prefersSlot3 = 1;
16524 let Defs = [USR_OVF];
16526 def M2_vmpy2es_s1 : HInst<
16527 (outs DoubleRegs:$Rdd32),
16528 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16529 "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16530 tc_8fd5f294, TypeM>, Enc_a56825 {
16531 let Inst{7-5} = 0b110;
16532 let Inst{13-13} = 0b0;
16533 let Inst{31-21} = 0b11101000100;
16534 let prefersSlot3 = 1;
16535 let Defs = [USR_OVF];
16537 def M2_vmpy2s_s0 : HInst<
16538 (outs DoubleRegs:$Rdd32),
16539 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16540 "$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16541 tc_8fd5f294, TypeM>, Enc_be32a5 {
16542 let Inst{7-5} = 0b101;
16543 let Inst{13-13} = 0b0;
16544 let Inst{31-21} = 0b11100101000;
16545 let prefersSlot3 = 1;
16546 let Defs = [USR_OVF];
16548 def M2_vmpy2s_s0pack : HInst<
16549 (outs IntRegs:$Rd32),
16550 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16551 "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16552 tc_8fd5f294, TypeM>, Enc_5ab2be {
16553 let Inst{7-5} = 0b111;
16554 let Inst{13-13} = 0b0;
16555 let Inst{31-21} = 0b11101101001;
16556 let hasNewValue = 1;
16557 let opNewValue = 0;
16558 let prefersSlot3 = 1;
16559 let Defs = [USR_OVF];
16561 def M2_vmpy2s_s1 : HInst<
16562 (outs DoubleRegs:$Rdd32),
16563 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16564 "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16565 tc_8fd5f294, TypeM>, Enc_be32a5 {
16566 let Inst{7-5} = 0b101;
16567 let Inst{13-13} = 0b0;
16568 let Inst{31-21} = 0b11100101100;
16569 let prefersSlot3 = 1;
16570 let Defs = [USR_OVF];
16572 def M2_vmpy2s_s1pack : HInst<
16573 (outs IntRegs:$Rd32),
16574 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16575 "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16576 tc_8fd5f294, TypeM>, Enc_5ab2be {
16577 let Inst{7-5} = 0b111;
16578 let Inst{13-13} = 0b0;
16579 let Inst{31-21} = 0b11101101101;
16580 let hasNewValue = 1;
16581 let opNewValue = 0;
16582 let prefersSlot3 = 1;
16583 let Defs = [USR_OVF];
16585 def M2_vmpy2su_s0 : HInst<
16586 (outs DoubleRegs:$Rdd32),
16587 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16588 "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16589 tc_8fd5f294, TypeM>, Enc_be32a5 {
16590 let Inst{7-5} = 0b111;
16591 let Inst{13-13} = 0b0;
16592 let Inst{31-21} = 0b11100101000;
16593 let prefersSlot3 = 1;
16594 let Defs = [USR_OVF];
16596 def M2_vmpy2su_s1 : HInst<
16597 (outs DoubleRegs:$Rdd32),
16598 (ins IntRegs:$Rs32, IntRegs:$Rt32),
16599 "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16600 tc_8fd5f294, TypeM>, Enc_be32a5 {
16601 let Inst{7-5} = 0b111;
16602 let Inst{13-13} = 0b0;
16603 let Inst{31-21} = 0b11100101100;
16604 let prefersSlot3 = 1;
16605 let Defs = [USR_OVF];
16607 def M2_vraddh : HInst<
16608 (outs IntRegs:$Rd32),
16609 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16610 "$Rd32 = vraddh($Rss32,$Rtt32)",
16611 tc_8fd5f294, TypeM>, Enc_d2216a {
16612 let Inst{7-5} = 0b111;
16613 let Inst{13-13} = 0b0;
16614 let Inst{31-21} = 0b11101001001;
16615 let hasNewValue = 1;
16616 let opNewValue = 0;
16617 let prefersSlot3 = 1;
16619 def M2_vradduh : HInst<
16620 (outs IntRegs:$Rd32),
16621 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16622 "$Rd32 = vradduh($Rss32,$Rtt32)",
16623 tc_8fd5f294, TypeM>, Enc_d2216a {
16624 let Inst{7-5} = 0b001;
16625 let Inst{13-13} = 0b0;
16626 let Inst{31-21} = 0b11101001000;
16627 let hasNewValue = 1;
16628 let opNewValue = 0;
16629 let prefersSlot3 = 1;
16631 def M2_vrcmaci_s0 : HInst<
16632 (outs DoubleRegs:$Rxx32),
16633 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16634 "$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16635 tc_e913dc32, TypeM>, Enc_88c16c {
16636 let Inst{7-5} = 0b000;
16637 let Inst{13-13} = 0b0;
16638 let Inst{31-21} = 0b11101010000;
16639 let prefersSlot3 = 1;
16640 let Constraints = "$Rxx32 = $Rxx32in";
16642 def M2_vrcmaci_s0c : HInst<
16643 (outs DoubleRegs:$Rxx32),
16644 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16645 "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16646 tc_e913dc32, TypeM>, Enc_88c16c {
16647 let Inst{7-5} = 0b000;
16648 let Inst{13-13} = 0b0;
16649 let Inst{31-21} = 0b11101010010;
16650 let prefersSlot3 = 1;
16651 let Constraints = "$Rxx32 = $Rxx32in";
16653 def M2_vrcmacr_s0 : HInst<
16654 (outs DoubleRegs:$Rxx32),
16655 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16656 "$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16657 tc_e913dc32, TypeM>, Enc_88c16c {
16658 let Inst{7-5} = 0b001;
16659 let Inst{13-13} = 0b0;
16660 let Inst{31-21} = 0b11101010000;
16661 let prefersSlot3 = 1;
16662 let Constraints = "$Rxx32 = $Rxx32in";
16664 def M2_vrcmacr_s0c : HInst<
16665 (outs DoubleRegs:$Rxx32),
16666 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16667 "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16668 tc_e913dc32, TypeM>, Enc_88c16c {
16669 let Inst{7-5} = 0b001;
16670 let Inst{13-13} = 0b0;
16671 let Inst{31-21} = 0b11101010011;
16672 let prefersSlot3 = 1;
16673 let Constraints = "$Rxx32 = $Rxx32in";
16675 def M2_vrcmpyi_s0 : HInst<
16676 (outs DoubleRegs:$Rdd32),
16677 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16678 "$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16679 tc_8fd5f294, TypeM>, Enc_a56825 {
16680 let Inst{7-5} = 0b000;
16681 let Inst{13-13} = 0b0;
16682 let Inst{31-21} = 0b11101000000;
16683 let prefersSlot3 = 1;
16685 def M2_vrcmpyi_s0c : HInst<
16686 (outs DoubleRegs:$Rdd32),
16687 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16688 "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16689 tc_8fd5f294, TypeM>, Enc_a56825 {
16690 let Inst{7-5} = 0b000;
16691 let Inst{13-13} = 0b0;
16692 let Inst{31-21} = 0b11101000010;
16693 let prefersSlot3 = 1;
16695 def M2_vrcmpyr_s0 : HInst<
16696 (outs DoubleRegs:$Rdd32),
16697 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16698 "$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
16699 tc_8fd5f294, TypeM>, Enc_a56825 {
16700 let Inst{7-5} = 0b001;
16701 let Inst{13-13} = 0b0;
16702 let Inst{31-21} = 0b11101000000;
16703 let prefersSlot3 = 1;
16705 def M2_vrcmpyr_s0c : HInst<
16706 (outs DoubleRegs:$Rdd32),
16707 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16708 "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
16709 tc_8fd5f294, TypeM>, Enc_a56825 {
16710 let Inst{7-5} = 0b001;
16711 let Inst{13-13} = 0b0;
16712 let Inst{31-21} = 0b11101000011;
16713 let prefersSlot3 = 1;
16715 def M2_vrcmpys_acc_s1 : HInst<
16716 (outs DoubleRegs:$Rxx32),
16717 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
16718 "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
16719 tc_e913dc32, TypeM> {
16721 let Constraints = "$Rxx32 = $Rxx32in";
16723 def M2_vrcmpys_acc_s1_h : HInst<
16724 (outs DoubleRegs:$Rxx32),
16725 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16726 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16727 tc_e913dc32, TypeM>, Enc_88c16c {
16728 let Inst{7-5} = 0b100;
16729 let Inst{13-13} = 0b0;
16730 let Inst{31-21} = 0b11101010101;
16731 let prefersSlot3 = 1;
16732 let Defs = [USR_OVF];
16733 let Constraints = "$Rxx32 = $Rxx32in";
16735 def M2_vrcmpys_acc_s1_l : HInst<
16736 (outs DoubleRegs:$Rxx32),
16737 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16738 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
16739 tc_e913dc32, TypeM>, Enc_88c16c {
16740 let Inst{7-5} = 0b100;
16741 let Inst{13-13} = 0b0;
16742 let Inst{31-21} = 0b11101010111;
16743 let prefersSlot3 = 1;
16744 let Defs = [USR_OVF];
16745 let Constraints = "$Rxx32 = $Rxx32in";
16747 def M2_vrcmpys_s1 : HInst<
16748 (outs DoubleRegs:$Rdd32),
16749 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16750 "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
16751 tc_8fd5f294, TypeM> {
16754 def M2_vrcmpys_s1_h : HInst<
16755 (outs DoubleRegs:$Rdd32),
16756 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16757 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16758 tc_8fd5f294, TypeM>, Enc_a56825 {
16759 let Inst{7-5} = 0b100;
16760 let Inst{13-13} = 0b0;
16761 let Inst{31-21} = 0b11101000101;
16762 let prefersSlot3 = 1;
16763 let Defs = [USR_OVF];
16765 def M2_vrcmpys_s1_l : HInst<
16766 (outs DoubleRegs:$Rdd32),
16767 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16768 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
16769 tc_8fd5f294, TypeM>, Enc_a56825 {
16770 let Inst{7-5} = 0b100;
16771 let Inst{13-13} = 0b0;
16772 let Inst{31-21} = 0b11101000111;
16773 let prefersSlot3 = 1;
16774 let Defs = [USR_OVF];
16776 def M2_vrcmpys_s1rp : HInst<
16777 (outs IntRegs:$Rd32),
16778 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16779 "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
16780 tc_8fd5f294, TypeM> {
16781 let hasNewValue = 1;
16782 let opNewValue = 0;
16785 def M2_vrcmpys_s1rp_h : HInst<
16786 (outs IntRegs:$Rd32),
16787 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16788 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
16789 tc_8fd5f294, TypeM>, Enc_d2216a {
16790 let Inst{7-5} = 0b110;
16791 let Inst{13-13} = 0b0;
16792 let Inst{31-21} = 0b11101001101;
16793 let hasNewValue = 1;
16794 let opNewValue = 0;
16795 let prefersSlot3 = 1;
16796 let Defs = [USR_OVF];
16798 def M2_vrcmpys_s1rp_l : HInst<
16799 (outs IntRegs:$Rd32),
16800 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16801 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
16802 tc_8fd5f294, TypeM>, Enc_d2216a {
16803 let Inst{7-5} = 0b111;
16804 let Inst{13-13} = 0b0;
16805 let Inst{31-21} = 0b11101001101;
16806 let hasNewValue = 1;
16807 let opNewValue = 0;
16808 let prefersSlot3 = 1;
16809 let Defs = [USR_OVF];
16811 def M2_vrmac_s0 : HInst<
16812 (outs DoubleRegs:$Rxx32),
16813 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16814 "$Rxx32 += vrmpyh($Rss32,$Rtt32)",
16815 tc_e913dc32, TypeM>, Enc_88c16c {
16816 let Inst{7-5} = 0b010;
16817 let Inst{13-13} = 0b0;
16818 let Inst{31-21} = 0b11101010000;
16819 let prefersSlot3 = 1;
16820 let Constraints = "$Rxx32 = $Rxx32in";
16822 def M2_vrmpy_s0 : HInst<
16823 (outs DoubleRegs:$Rdd32),
16824 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16825 "$Rdd32 = vrmpyh($Rss32,$Rtt32)",
16826 tc_8fd5f294, TypeM>, Enc_a56825 {
16827 let Inst{7-5} = 0b010;
16828 let Inst{13-13} = 0b0;
16829 let Inst{31-21} = 0b11101000000;
16830 let prefersSlot3 = 1;
16832 def M2_xor_xacc : HInst<
16833 (outs IntRegs:$Rx32),
16834 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16835 "$Rx32 ^= xor($Rs32,$Rt32)",
16836 tc_84df2cd3, TypeM>, Enc_2ae154 {
16837 let Inst{7-5} = 0b011;
16838 let Inst{13-13} = 0b0;
16839 let Inst{31-21} = 0b11101111100;
16840 let hasNewValue = 1;
16841 let opNewValue = 0;
16842 let prefersSlot3 = 1;
16843 let InputType = "reg";
16844 let Constraints = "$Rx32 = $Rx32in";
16846 def M4_and_and : HInst<
16847 (outs IntRegs:$Rx32),
16848 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16849 "$Rx32 &= and($Rs32,$Rt32)",
16850 tc_84df2cd3, TypeM>, Enc_2ae154 {
16851 let Inst{7-5} = 0b000;
16852 let Inst{13-13} = 0b0;
16853 let Inst{31-21} = 0b11101111010;
16854 let hasNewValue = 1;
16855 let opNewValue = 0;
16856 let prefersSlot3 = 1;
16857 let InputType = "reg";
16858 let Constraints = "$Rx32 = $Rx32in";
16860 def M4_and_andn : HInst<
16861 (outs IntRegs:$Rx32),
16862 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16863 "$Rx32 &= and($Rs32,~$Rt32)",
16864 tc_84df2cd3, TypeM>, Enc_2ae154 {
16865 let Inst{7-5} = 0b001;
16866 let Inst{13-13} = 0b0;
16867 let Inst{31-21} = 0b11101111001;
16868 let hasNewValue = 1;
16869 let opNewValue = 0;
16870 let prefersSlot3 = 1;
16871 let InputType = "reg";
16872 let Constraints = "$Rx32 = $Rx32in";
16874 def M4_and_or : HInst<
16875 (outs IntRegs:$Rx32),
16876 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16877 "$Rx32 &= or($Rs32,$Rt32)",
16878 tc_84df2cd3, TypeM>, Enc_2ae154 {
16879 let Inst{7-5} = 0b001;
16880 let Inst{13-13} = 0b0;
16881 let Inst{31-21} = 0b11101111010;
16882 let hasNewValue = 1;
16883 let opNewValue = 0;
16884 let prefersSlot3 = 1;
16885 let InputType = "reg";
16886 let Constraints = "$Rx32 = $Rx32in";
16888 def M4_and_xor : HInst<
16889 (outs IntRegs:$Rx32),
16890 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16891 "$Rx32 &= xor($Rs32,$Rt32)",
16892 tc_84df2cd3, TypeM>, Enc_2ae154 {
16893 let Inst{7-5} = 0b010;
16894 let Inst{13-13} = 0b0;
16895 let Inst{31-21} = 0b11101111010;
16896 let hasNewValue = 1;
16897 let opNewValue = 0;
16898 let prefersSlot3 = 1;
16899 let InputType = "reg";
16900 let Constraints = "$Rx32 = $Rx32in";
16902 def M4_cmpyi_wh : HInst<
16903 (outs IntRegs:$Rd32),
16904 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16905 "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
16906 tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
16907 let Inst{7-5} = 0b100;
16908 let Inst{13-13} = 0b0;
16909 let Inst{31-21} = 0b11000101000;
16910 let hasNewValue = 1;
16911 let opNewValue = 0;
16912 let prefersSlot3 = 1;
16913 let Defs = [USR_OVF];
16915 def M4_cmpyi_whc : HInst<
16916 (outs IntRegs:$Rd32),
16917 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16918 "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
16919 tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
16920 let Inst{7-5} = 0b101;
16921 let Inst{13-13} = 0b0;
16922 let Inst{31-21} = 0b11000101000;
16923 let hasNewValue = 1;
16924 let opNewValue = 0;
16925 let prefersSlot3 = 1;
16926 let Defs = [USR_OVF];
16928 def M4_cmpyr_wh : HInst<
16929 (outs IntRegs:$Rd32),
16930 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16931 "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
16932 tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
16933 let Inst{7-5} = 0b110;
16934 let Inst{13-13} = 0b0;
16935 let Inst{31-21} = 0b11000101000;
16936 let hasNewValue = 1;
16937 let opNewValue = 0;
16938 let prefersSlot3 = 1;
16939 let Defs = [USR_OVF];
16941 def M4_cmpyr_whc : HInst<
16942 (outs IntRegs:$Rd32),
16943 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16944 "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
16945 tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
16946 let Inst{7-5} = 0b111;
16947 let Inst{13-13} = 0b0;
16948 let Inst{31-21} = 0b11000101000;
16949 let hasNewValue = 1;
16950 let opNewValue = 0;
16951 let prefersSlot3 = 1;
16952 let Defs = [USR_OVF];
16954 def M4_mac_up_s1_sat : HInst<
16955 (outs IntRegs:$Rx32),
16956 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16957 "$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
16958 tc_e913dc32, TypeM>, Enc_2ae154 {
16959 let Inst{7-5} = 0b000;
16960 let Inst{13-13} = 0b0;
16961 let Inst{31-21} = 0b11101111011;
16962 let hasNewValue = 1;
16963 let opNewValue = 0;
16964 let prefersSlot3 = 1;
16965 let Defs = [USR_OVF];
16966 let InputType = "reg";
16967 let Constraints = "$Rx32 = $Rx32in";
16969 def M4_mpyri_addi : HInst<
16970 (outs IntRegs:$Rd32),
16971 (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
16972 "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
16973 tc_16d0d8d5, TypeALU64>, Enc_322e1b, ImmRegRel {
16974 let Inst{31-24} = 0b11011000;
16975 let hasNewValue = 1;
16976 let opNewValue = 0;
16977 let prefersSlot3 = 1;
16978 let CextOpcode = "M4_mpyri_addr";
16979 let isExtendable = 1;
16980 let opExtendable = 1;
16981 let isExtentSigned = 0;
16982 let opExtentBits = 6;
16983 let opExtentAlign = 0;
16985 def M4_mpyri_addr : HInst<
16986 (outs IntRegs:$Rd32),
16987 (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
16988 "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
16989 tc_16d0d8d5, TypeALU64>, Enc_420cf3, ImmRegRel {
16990 let Inst{31-23} = 0b110111111;
16991 let hasNewValue = 1;
16992 let opNewValue = 0;
16993 let prefersSlot3 = 1;
16994 let CextOpcode = "M4_mpyri_addr";
16995 let InputType = "imm";
16996 let isExtendable = 1;
16997 let opExtendable = 3;
16998 let isExtentSigned = 0;
16999 let opExtentBits = 6;
17000 let opExtentAlign = 0;
17002 def M4_mpyri_addr_u2 : HInst<
17003 (outs IntRegs:$Rd32),
17004 (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17005 "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17006 tc_bcc96cee, TypeALU64>, Enc_277737 {
17007 let Inst{31-23} = 0b110111110;
17008 let hasNewValue = 1;
17009 let opNewValue = 0;
17010 let prefersSlot3 = 1;
17012 def M4_mpyrr_addi : HInst<
17013 (outs IntRegs:$Rd32),
17014 (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17015 "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17016 tc_e913dc32, TypeALU64>, Enc_a7b8e8, ImmRegRel {
17017 let Inst{31-23} = 0b110101110;
17018 let hasNewValue = 1;
17019 let opNewValue = 0;
17020 let prefersSlot3 = 1;
17021 let CextOpcode = "M4_mpyrr_addr";
17022 let InputType = "imm";
17023 let isExtendable = 1;
17024 let opExtendable = 1;
17025 let isExtentSigned = 0;
17026 let opExtentBits = 6;
17027 let opExtentAlign = 0;
17029 def M4_mpyrr_addr : HInst<
17030 (outs IntRegs:$Ry32),
17031 (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17032 "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17033 tc_e913dc32, TypeM>, Enc_7f1a05, ImmRegRel {
17034 let Inst{7-5} = 0b000;
17035 let Inst{13-13} = 0b0;
17036 let Inst{31-21} = 0b11100011000;
17037 let hasNewValue = 1;
17038 let opNewValue = 0;
17039 let prefersSlot3 = 1;
17040 let CextOpcode = "M4_mpyrr_addr";
17041 let InputType = "reg";
17042 let Constraints = "$Ry32 = $Ry32in";
17044 def M4_nac_up_s1_sat : HInst<
17045 (outs IntRegs:$Rx32),
17046 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17047 "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17048 tc_e913dc32, TypeM>, Enc_2ae154 {
17049 let Inst{7-5} = 0b001;
17050 let Inst{13-13} = 0b0;
17051 let Inst{31-21} = 0b11101111011;
17052 let hasNewValue = 1;
17053 let opNewValue = 0;
17054 let prefersSlot3 = 1;
17055 let Defs = [USR_OVF];
17056 let InputType = "reg";
17057 let Constraints = "$Rx32 = $Rx32in";
17059 def M4_or_and : HInst<
17060 (outs IntRegs:$Rx32),
17061 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17062 "$Rx32 |= and($Rs32,$Rt32)",
17063 tc_84df2cd3, TypeM>, Enc_2ae154 {
17064 let Inst{7-5} = 0b011;
17065 let Inst{13-13} = 0b0;
17066 let Inst{31-21} = 0b11101111010;
17067 let hasNewValue = 1;
17068 let opNewValue = 0;
17069 let prefersSlot3 = 1;
17070 let InputType = "reg";
17071 let Constraints = "$Rx32 = $Rx32in";
17073 def M4_or_andn : HInst<
17074 (outs IntRegs:$Rx32),
17075 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17076 "$Rx32 |= and($Rs32,~$Rt32)",
17077 tc_84df2cd3, TypeM>, Enc_2ae154 {
17078 let Inst{7-5} = 0b000;
17079 let Inst{13-13} = 0b0;
17080 let Inst{31-21} = 0b11101111001;
17081 let hasNewValue = 1;
17082 let opNewValue = 0;
17083 let prefersSlot3 = 1;
17084 let InputType = "reg";
17085 let Constraints = "$Rx32 = $Rx32in";
17087 def M4_or_or : HInst<
17088 (outs IntRegs:$Rx32),
17089 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17090 "$Rx32 |= or($Rs32,$Rt32)",
17091 tc_84df2cd3, TypeM>, Enc_2ae154 {
17092 let Inst{7-5} = 0b000;
17093 let Inst{13-13} = 0b0;
17094 let Inst{31-21} = 0b11101111110;
17095 let hasNewValue = 1;
17096 let opNewValue = 0;
17097 let prefersSlot3 = 1;
17098 let InputType = "reg";
17099 let Constraints = "$Rx32 = $Rx32in";
17101 def M4_or_xor : HInst<
17102 (outs IntRegs:$Rx32),
17103 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17104 "$Rx32 |= xor($Rs32,$Rt32)",
17105 tc_84df2cd3, TypeM>, Enc_2ae154 {
17106 let Inst{7-5} = 0b001;
17107 let Inst{13-13} = 0b0;
17108 let Inst{31-21} = 0b11101111110;
17109 let hasNewValue = 1;
17110 let opNewValue = 0;
17111 let prefersSlot3 = 1;
17112 let InputType = "reg";
17113 let Constraints = "$Rx32 = $Rx32in";
17115 def M4_pmpyw : HInst<
17116 (outs DoubleRegs:$Rdd32),
17117 (ins IntRegs:$Rs32, IntRegs:$Rt32),
17118 "$Rdd32 = pmpyw($Rs32,$Rt32)",
17119 tc_8fd5f294, TypeM>, Enc_be32a5 {
17120 let Inst{7-5} = 0b111;
17121 let Inst{13-13} = 0b0;
17122 let Inst{31-21} = 0b11100101010;
17123 let prefersSlot3 = 1;
17125 def M4_pmpyw_acc : HInst<
17126 (outs DoubleRegs:$Rxx32),
17127 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17128 "$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17129 tc_e913dc32, TypeM>, Enc_61f0b0 {
17130 let Inst{7-5} = 0b111;
17131 let Inst{13-13} = 0b0;
17132 let Inst{31-21} = 0b11100111001;
17133 let prefersSlot3 = 1;
17134 let Constraints = "$Rxx32 = $Rxx32in";
17136 def M4_vpmpyh : HInst<
17137 (outs DoubleRegs:$Rdd32),
17138 (ins IntRegs:$Rs32, IntRegs:$Rt32),
17139 "$Rdd32 = vpmpyh($Rs32,$Rt32)",
17140 tc_8fd5f294, TypeM>, Enc_be32a5 {
17141 let Inst{7-5} = 0b111;
17142 let Inst{13-13} = 0b0;
17143 let Inst{31-21} = 0b11100101110;
17144 let prefersSlot3 = 1;
17146 def M4_vpmpyh_acc : HInst<
17147 (outs DoubleRegs:$Rxx32),
17148 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17149 "$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17150 tc_e913dc32, TypeM>, Enc_61f0b0 {
17151 let Inst{7-5} = 0b111;
17152 let Inst{13-13} = 0b0;
17153 let Inst{31-21} = 0b11100111101;
17154 let prefersSlot3 = 1;
17155 let Constraints = "$Rxx32 = $Rxx32in";
17157 def M4_vrmpyeh_acc_s0 : HInst<
17158 (outs DoubleRegs:$Rxx32),
17159 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17160 "$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17161 tc_e913dc32, TypeM>, Enc_88c16c {
17162 let Inst{7-5} = 0b110;
17163 let Inst{13-13} = 0b0;
17164 let Inst{31-21} = 0b11101010001;
17165 let prefersSlot3 = 1;
17166 let Constraints = "$Rxx32 = $Rxx32in";
17168 def M4_vrmpyeh_acc_s1 : HInst<
17169 (outs DoubleRegs:$Rxx32),
17170 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17171 "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17172 tc_e913dc32, TypeM>, Enc_88c16c {
17173 let Inst{7-5} = 0b110;
17174 let Inst{13-13} = 0b0;
17175 let Inst{31-21} = 0b11101010101;
17176 let prefersSlot3 = 1;
17177 let Constraints = "$Rxx32 = $Rxx32in";
17179 def M4_vrmpyeh_s0 : HInst<
17180 (outs DoubleRegs:$Rdd32),
17181 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17182 "$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17183 tc_8fd5f294, TypeM>, Enc_a56825 {
17184 let Inst{7-5} = 0b100;
17185 let Inst{13-13} = 0b0;
17186 let Inst{31-21} = 0b11101000010;
17187 let prefersSlot3 = 1;
17189 def M4_vrmpyeh_s1 : HInst<
17190 (outs DoubleRegs:$Rdd32),
17191 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17192 "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17193 tc_8fd5f294, TypeM>, Enc_a56825 {
17194 let Inst{7-5} = 0b100;
17195 let Inst{13-13} = 0b0;
17196 let Inst{31-21} = 0b11101000110;
17197 let prefersSlot3 = 1;
17199 def M4_vrmpyoh_acc_s0 : HInst<
17200 (outs DoubleRegs:$Rxx32),
17201 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17202 "$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17203 tc_e913dc32, TypeM>, Enc_88c16c {
17204 let Inst{7-5} = 0b110;
17205 let Inst{13-13} = 0b0;
17206 let Inst{31-21} = 0b11101010011;
17207 let prefersSlot3 = 1;
17208 let Constraints = "$Rxx32 = $Rxx32in";
17210 def M4_vrmpyoh_acc_s1 : HInst<
17211 (outs DoubleRegs:$Rxx32),
17212 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17213 "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17214 tc_e913dc32, TypeM>, Enc_88c16c {
17215 let Inst{7-5} = 0b110;
17216 let Inst{13-13} = 0b0;
17217 let Inst{31-21} = 0b11101010111;
17218 let prefersSlot3 = 1;
17219 let Constraints = "$Rxx32 = $Rxx32in";
17221 def M4_vrmpyoh_s0 : HInst<
17222 (outs DoubleRegs:$Rdd32),
17223 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17224 "$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17225 tc_8fd5f294, TypeM>, Enc_a56825 {
17226 let Inst{7-5} = 0b010;
17227 let Inst{13-13} = 0b0;
17228 let Inst{31-21} = 0b11101000001;
17229 let prefersSlot3 = 1;
17231 def M4_vrmpyoh_s1 : HInst<
17232 (outs DoubleRegs:$Rdd32),
17233 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17234 "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17235 tc_8fd5f294, TypeM>, Enc_a56825 {
17236 let Inst{7-5} = 0b010;
17237 let Inst{13-13} = 0b0;
17238 let Inst{31-21} = 0b11101000101;
17239 let prefersSlot3 = 1;
17241 def M4_xor_and : HInst<
17242 (outs IntRegs:$Rx32),
17243 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17244 "$Rx32 ^= and($Rs32,$Rt32)",
17245 tc_84df2cd3, TypeM>, Enc_2ae154 {
17246 let Inst{7-5} = 0b010;
17247 let Inst{13-13} = 0b0;
17248 let Inst{31-21} = 0b11101111110;
17249 let hasNewValue = 1;
17250 let opNewValue = 0;
17251 let prefersSlot3 = 1;
17252 let InputType = "reg";
17253 let Constraints = "$Rx32 = $Rx32in";
17255 def M4_xor_andn : HInst<
17256 (outs IntRegs:$Rx32),
17257 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17258 "$Rx32 ^= and($Rs32,~$Rt32)",
17259 tc_84df2cd3, TypeM>, Enc_2ae154 {
17260 let Inst{7-5} = 0b010;
17261 let Inst{13-13} = 0b0;
17262 let Inst{31-21} = 0b11101111001;
17263 let hasNewValue = 1;
17264 let opNewValue = 0;
17265 let prefersSlot3 = 1;
17266 let InputType = "reg";
17267 let Constraints = "$Rx32 = $Rx32in";
17269 def M4_xor_or : HInst<
17270 (outs IntRegs:$Rx32),
17271 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17272 "$Rx32 ^= or($Rs32,$Rt32)",
17273 tc_84df2cd3, TypeM>, Enc_2ae154 {
17274 let Inst{7-5} = 0b011;
17275 let Inst{13-13} = 0b0;
17276 let Inst{31-21} = 0b11101111110;
17277 let hasNewValue = 1;
17278 let opNewValue = 0;
17279 let prefersSlot3 = 1;
17280 let InputType = "reg";
17281 let Constraints = "$Rx32 = $Rx32in";
17283 def M4_xor_xacc : HInst<
17284 (outs DoubleRegs:$Rxx32),
17285 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17286 "$Rxx32 ^= xor($Rss32,$Rtt32)",
17287 tc_84df2cd3, TypeS_3op>, Enc_88c16c {
17288 let Inst{7-5} = 0b000;
17289 let Inst{13-13} = 0b0;
17290 let Inst{31-21} = 0b11001010100;
17291 let prefersSlot3 = 1;
17292 let Constraints = "$Rxx32 = $Rxx32in";
17294 def M5_vdmacbsu : HInst<
17295 (outs DoubleRegs:$Rxx32),
17296 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17297 "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17298 tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5T]> {
17299 let Inst{7-5} = 0b001;
17300 let Inst{13-13} = 0b0;
17301 let Inst{31-21} = 0b11101010001;
17302 let prefersSlot3 = 1;
17303 let Defs = [USR_OVF];
17304 let Constraints = "$Rxx32 = $Rxx32in";
17306 def M5_vdmpybsu : HInst<
17307 (outs DoubleRegs:$Rdd32),
17308 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17309 "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17310 tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5T]> {
17311 let Inst{7-5} = 0b001;
17312 let Inst{13-13} = 0b0;
17313 let Inst{31-21} = 0b11101000101;
17314 let prefersSlot3 = 1;
17315 let Defs = [USR_OVF];
17317 def M5_vmacbsu : HInst<
17318 (outs DoubleRegs:$Rxx32),
17319 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17320 "$Rxx32 += vmpybsu($Rs32,$Rt32)",
17321 tc_e913dc32, TypeM>, Enc_61f0b0 {
17322 let Inst{7-5} = 0b001;
17323 let Inst{13-13} = 0b0;
17324 let Inst{31-21} = 0b11100111110;
17325 let prefersSlot3 = 1;
17326 let Constraints = "$Rxx32 = $Rxx32in";
17328 def M5_vmacbuu : HInst<
17329 (outs DoubleRegs:$Rxx32),
17330 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17331 "$Rxx32 += vmpybu($Rs32,$Rt32)",
17332 tc_e913dc32, TypeM>, Enc_61f0b0 {
17333 let Inst{7-5} = 0b001;
17334 let Inst{13-13} = 0b0;
17335 let Inst{31-21} = 0b11100111100;
17336 let prefersSlot3 = 1;
17337 let Constraints = "$Rxx32 = $Rxx32in";
17339 def M5_vmpybsu : HInst<
17340 (outs DoubleRegs:$Rdd32),
17341 (ins IntRegs:$Rs32, IntRegs:$Rt32),
17342 "$Rdd32 = vmpybsu($Rs32,$Rt32)",
17343 tc_8fd5f294, TypeM>, Enc_be32a5 {
17344 let Inst{7-5} = 0b001;
17345 let Inst{13-13} = 0b0;
17346 let Inst{31-21} = 0b11100101010;
17347 let prefersSlot3 = 1;
17349 def M5_vmpybuu : HInst<
17350 (outs DoubleRegs:$Rdd32),
17351 (ins IntRegs:$Rs32, IntRegs:$Rt32),
17352 "$Rdd32 = vmpybu($Rs32,$Rt32)",
17353 tc_8fd5f294, TypeM>, Enc_be32a5 {
17354 let Inst{7-5} = 0b001;
17355 let Inst{13-13} = 0b0;
17356 let Inst{31-21} = 0b11100101100;
17357 let prefersSlot3 = 1;
17359 def M5_vrmacbsu : HInst<
17360 (outs DoubleRegs:$Rxx32),
17361 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17362 "$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17363 tc_e913dc32, TypeM>, Enc_88c16c {
17364 let Inst{7-5} = 0b001;
17365 let Inst{13-13} = 0b0;
17366 let Inst{31-21} = 0b11101010110;
17367 let prefersSlot3 = 1;
17368 let Constraints = "$Rxx32 = $Rxx32in";
17370 def M5_vrmacbuu : HInst<
17371 (outs DoubleRegs:$Rxx32),
17372 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17373 "$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17374 tc_e913dc32, TypeM>, Enc_88c16c {
17375 let Inst{7-5} = 0b001;
17376 let Inst{13-13} = 0b0;
17377 let Inst{31-21} = 0b11101010100;
17378 let prefersSlot3 = 1;
17379 let Constraints = "$Rxx32 = $Rxx32in";
17381 def M5_vrmpybsu : HInst<
17382 (outs DoubleRegs:$Rdd32),
17383 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17384 "$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17385 tc_8fd5f294, TypeM>, Enc_a56825 {
17386 let Inst{7-5} = 0b001;
17387 let Inst{13-13} = 0b0;
17388 let Inst{31-21} = 0b11101000110;
17389 let prefersSlot3 = 1;
17391 def M5_vrmpybuu : HInst<
17392 (outs DoubleRegs:$Rdd32),
17393 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17394 "$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17395 tc_8fd5f294, TypeM>, Enc_a56825 {
17396 let Inst{7-5} = 0b001;
17397 let Inst{13-13} = 0b0;
17398 let Inst{31-21} = 0b11101000100;
17399 let prefersSlot3 = 1;
17401 def M6_vabsdiffb : HInst<
17402 (outs DoubleRegs:$Rdd32),
17403 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17404 "$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17405 tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
17406 let Inst{7-5} = 0b000;
17407 let Inst{13-13} = 0b0;
17408 let Inst{31-21} = 0b11101000111;
17409 let prefersSlot3 = 1;
17411 def M6_vabsdiffub : HInst<
17412 (outs DoubleRegs:$Rdd32),
17413 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17414 "$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17415 tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
17416 let Inst{7-5} = 0b000;
17417 let Inst{13-13} = 0b0;
17418 let Inst{31-21} = 0b11101000101;
17419 let prefersSlot3 = 1;
17421 def PS_loadrbabs : HInst<
17422 (outs IntRegs:$Rd32),
17423 (ins u32_0Imm:$Ii),
17424 "$Rd32 = memb(#$Ii)",
17425 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17426 let Inst{24-21} = 0b1000;
17427 let Inst{31-27} = 0b01001;
17428 let hasNewValue = 1;
17429 let opNewValue = 0;
17430 let addrMode = Absolute;
17431 let accessSize = ByteAccess;
17433 let isExtended = 1;
17434 let CextOpcode = "L2_loadrb";
17435 let BaseOpcode = "L4_loadrb_abs";
17436 let isPredicable = 1;
17437 let DecoderNamespace = "MustExtend";
17438 let isExtended = 1;
17439 let opExtendable = 1;
17440 let isExtentSigned = 0;
17441 let opExtentBits = 16;
17442 let opExtentAlign = 0;
17444 def PS_loadrdabs : HInst<
17445 (outs DoubleRegs:$Rdd32),
17446 (ins u29_3Imm:$Ii),
17447 "$Rdd32 = memd(#$Ii)",
17448 tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
17449 let Inst{24-21} = 0b1110;
17450 let Inst{31-27} = 0b01001;
17451 let addrMode = Absolute;
17452 let accessSize = DoubleWordAccess;
17454 let isExtended = 1;
17455 let CextOpcode = "L2_loadrd";
17456 let BaseOpcode = "L4_loadrd_abs";
17457 let isPredicable = 1;
17458 let DecoderNamespace = "MustExtend";
17459 let isExtended = 1;
17460 let opExtendable = 1;
17461 let isExtentSigned = 0;
17462 let opExtentBits = 19;
17463 let opExtentAlign = 3;
17465 def PS_loadrhabs : HInst<
17466 (outs IntRegs:$Rd32),
17467 (ins u31_1Imm:$Ii),
17468 "$Rd32 = memh(#$Ii)",
17469 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17470 let Inst{24-21} = 0b1010;
17471 let Inst{31-27} = 0b01001;
17472 let hasNewValue = 1;
17473 let opNewValue = 0;
17474 let addrMode = Absolute;
17475 let accessSize = HalfWordAccess;
17477 let isExtended = 1;
17478 let CextOpcode = "L2_loadrh";
17479 let BaseOpcode = "L4_loadrh_abs";
17480 let isPredicable = 1;
17481 let DecoderNamespace = "MustExtend";
17482 let isExtended = 1;
17483 let opExtendable = 1;
17484 let isExtentSigned = 0;
17485 let opExtentBits = 17;
17486 let opExtentAlign = 1;
17488 def PS_loadriabs : HInst<
17489 (outs IntRegs:$Rd32),
17490 (ins u30_2Imm:$Ii),
17491 "$Rd32 = memw(#$Ii)",
17492 tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17493 let Inst{24-21} = 0b1100;
17494 let Inst{31-27} = 0b01001;
17495 let hasNewValue = 1;
17496 let opNewValue = 0;
17497 let addrMode = Absolute;
17498 let accessSize = WordAccess;
17500 let isExtended = 1;
17501 let CextOpcode = "L2_loadri";
17502 let BaseOpcode = "L4_loadri_abs";
17503 let isPredicable = 1;
17504 let DecoderNamespace = "MustExtend";
17505 let isExtended = 1;
17506 let opExtendable = 1;
17507 let isExtentSigned = 0;
17508 let opExtentBits = 18;
17509 let opExtentAlign = 2;
17511 def PS_loadrubabs : HInst<
17512 (outs IntRegs:$Rd32),
17513 (ins u32_0Imm:$Ii),
17514 "$Rd32 = memub(#$Ii)",
17515 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17516 let Inst{24-21} = 0b1001;
17517 let Inst{31-27} = 0b01001;
17518 let hasNewValue = 1;
17519 let opNewValue = 0;
17520 let addrMode = Absolute;
17521 let accessSize = ByteAccess;
17523 let isExtended = 1;
17524 let CextOpcode = "L2_loadrub";
17525 let BaseOpcode = "L4_loadrub_abs";
17526 let isPredicable = 1;
17527 let DecoderNamespace = "MustExtend";
17528 let isExtended = 1;
17529 let opExtendable = 1;
17530 let isExtentSigned = 0;
17531 let opExtentBits = 16;
17532 let opExtentAlign = 0;
17534 def PS_loadruhabs : HInst<
17535 (outs IntRegs:$Rd32),
17536 (ins u31_1Imm:$Ii),
17537 "$Rd32 = memuh(#$Ii)",
17538 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17539 let Inst{24-21} = 0b1011;
17540 let Inst{31-27} = 0b01001;
17541 let hasNewValue = 1;
17542 let opNewValue = 0;
17543 let addrMode = Absolute;
17544 let accessSize = HalfWordAccess;
17546 let isExtended = 1;
17547 let CextOpcode = "L2_loadruh";
17548 let BaseOpcode = "L4_loadruh_abs";
17549 let isPredicable = 1;
17550 let DecoderNamespace = "MustExtend";
17551 let isExtended = 1;
17552 let opExtendable = 1;
17553 let isExtentSigned = 0;
17554 let opExtentBits = 17;
17555 let opExtentAlign = 1;
17557 def PS_storerbabs : HInst<
17559 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
17560 "memb(#$Ii) = $Rt32",
17561 tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
17562 let Inst{24-21} = 0b0000;
17563 let Inst{31-27} = 0b01001;
17564 let addrMode = Absolute;
17565 let accessSize = ByteAccess;
17566 let isExtended = 1;
17568 let CextOpcode = "S2_storerb";
17569 let BaseOpcode = "S2_storerbabs";
17570 let isPredicable = 1;
17571 let isNVStorable = 1;
17572 let DecoderNamespace = "MustExtend";
17573 let isExtended = 1;
17574 let opExtendable = 0;
17575 let isExtentSigned = 0;
17576 let opExtentBits = 16;
17577 let opExtentAlign = 0;
17579 def PS_storerbnewabs : HInst<
17581 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
17582 "memb(#$Ii) = $Nt8.new",
17583 tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
17584 let Inst{12-11} = 0b00;
17585 let Inst{24-21} = 0b0101;
17586 let Inst{31-27} = 0b01001;
17587 let addrMode = Absolute;
17588 let accessSize = ByteAccess;
17590 let isNewValue = 1;
17591 let isExtended = 1;
17592 let isRestrictNoSlot1Store = 1;
17594 let CextOpcode = "S2_storerb";
17595 let BaseOpcode = "S2_storerbabs";
17596 let isPredicable = 1;
17597 let DecoderNamespace = "MustExtend";
17598 let isExtended = 1;
17599 let opExtendable = 0;
17600 let isExtentSigned = 0;
17601 let opExtentBits = 16;
17602 let opExtentAlign = 0;
17603 let opNewValue = 1;
17605 def PS_storerdabs : HInst<
17607 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
17608 "memd(#$Ii) = $Rtt32",
17609 tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
17610 let Inst{24-21} = 0b0110;
17611 let Inst{31-27} = 0b01001;
17612 let addrMode = Absolute;
17613 let accessSize = DoubleWordAccess;
17614 let isExtended = 1;
17616 let CextOpcode = "S2_storerd";
17617 let BaseOpcode = "S2_storerdabs";
17618 let isPredicable = 1;
17619 let DecoderNamespace = "MustExtend";
17620 let isExtended = 1;
17621 let opExtendable = 0;
17622 let isExtentSigned = 0;
17623 let opExtentBits = 19;
17624 let opExtentAlign = 3;
17626 def PS_storerfabs : HInst<
17628 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
17629 "memh(#$Ii) = $Rt32.h",
17630 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
17631 let Inst{24-21} = 0b0011;
17632 let Inst{31-27} = 0b01001;
17633 let addrMode = Absolute;
17634 let accessSize = HalfWordAccess;
17635 let isExtended = 1;
17637 let CextOpcode = "S2_storerf";
17638 let BaseOpcode = "S2_storerfabs";
17639 let isPredicable = 1;
17640 let DecoderNamespace = "MustExtend";
17641 let isExtended = 1;
17642 let opExtendable = 0;
17643 let isExtentSigned = 0;
17644 let opExtentBits = 17;
17645 let opExtentAlign = 1;
17647 def PS_storerhabs : HInst<
17649 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
17650 "memh(#$Ii) = $Rt32",
17651 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
17652 let Inst{24-21} = 0b0010;
17653 let Inst{31-27} = 0b01001;
17654 let addrMode = Absolute;
17655 let accessSize = HalfWordAccess;
17656 let isExtended = 1;
17658 let CextOpcode = "S2_storerh";
17659 let BaseOpcode = "S2_storerhabs";
17660 let isPredicable = 1;
17661 let isNVStorable = 1;
17662 let DecoderNamespace = "MustExtend";
17663 let isExtended = 1;
17664 let opExtendable = 0;
17665 let isExtentSigned = 0;
17666 let opExtentBits = 17;
17667 let opExtentAlign = 1;
17669 def PS_storerhnewabs : HInst<
17671 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
17672 "memh(#$Ii) = $Nt8.new",
17673 tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
17674 let Inst{12-11} = 0b01;
17675 let Inst{24-21} = 0b0101;
17676 let Inst{31-27} = 0b01001;
17677 let addrMode = Absolute;
17678 let accessSize = HalfWordAccess;
17680 let isNewValue = 1;
17681 let isExtended = 1;
17682 let isRestrictNoSlot1Store = 1;
17684 let CextOpcode = "S2_storerh";
17685 let BaseOpcode = "S2_storerhabs";
17686 let isPredicable = 1;
17687 let DecoderNamespace = "MustExtend";
17688 let isExtended = 1;
17689 let opExtendable = 0;
17690 let isExtentSigned = 0;
17691 let opExtentBits = 17;
17692 let opExtentAlign = 1;
17693 let opNewValue = 1;
17695 def PS_storeriabs : HInst<
17697 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
17698 "memw(#$Ii) = $Rt32",
17699 tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
17700 let Inst{24-21} = 0b0100;
17701 let Inst{31-27} = 0b01001;
17702 let addrMode = Absolute;
17703 let accessSize = WordAccess;
17704 let isExtended = 1;
17706 let CextOpcode = "S2_storeri";
17707 let BaseOpcode = "S2_storeriabs";
17708 let isPredicable = 1;
17709 let isNVStorable = 1;
17710 let DecoderNamespace = "MustExtend";
17711 let isExtended = 1;
17712 let opExtendable = 0;
17713 let isExtentSigned = 0;
17714 let opExtentBits = 18;
17715 let opExtentAlign = 2;
17717 def PS_storerinewabs : HInst<
17719 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
17720 "memw(#$Ii) = $Nt8.new",
17721 tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
17722 let Inst{12-11} = 0b10;
17723 let Inst{24-21} = 0b0101;
17724 let Inst{31-27} = 0b01001;
17725 let addrMode = Absolute;
17726 let accessSize = WordAccess;
17728 let isNewValue = 1;
17729 let isExtended = 1;
17730 let isRestrictNoSlot1Store = 1;
17732 let CextOpcode = "S2_storeri";
17733 let BaseOpcode = "S2_storeriabs";
17734 let isPredicable = 1;
17735 let DecoderNamespace = "MustExtend";
17736 let isExtended = 1;
17737 let opExtendable = 0;
17738 let isExtentSigned = 0;
17739 let opExtentBits = 18;
17740 let opExtentAlign = 2;
17741 let opNewValue = 1;
17743 def S2_addasl_rrri : HInst<
17744 (outs IntRegs:$Rd32),
17745 (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
17746 "$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
17747 tc_c74f796f, TypeS_3op>, Enc_47ef61 {
17748 let Inst{13-13} = 0b0;
17749 let Inst{31-21} = 0b11000100000;
17750 let hasNewValue = 1;
17751 let opNewValue = 0;
17752 let prefersSlot3 = 1;
17754 def S2_allocframe : HInst<
17755 (outs IntRegs:$Rx32),
17756 (ins IntRegs:$Rx32in, u11_3Imm:$Ii),
17757 "allocframe($Rx32,#$Ii):raw",
17758 tc_e216a5db, TypeST>, Enc_22c845 {
17759 let Inst{13-11} = 0b000;
17760 let Inst{31-21} = 0b10100000100;
17761 let hasNewValue = 1;
17762 let opNewValue = 0;
17763 let addrMode = BaseImmOffset;
17764 let accessSize = DoubleWordAccess;
17766 let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
17768 let Constraints = "$Rx32 = $Rx32in";
17770 def S2_asl_i_p : HInst<
17771 (outs DoubleRegs:$Rdd32),
17772 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
17773 "$Rdd32 = asl($Rss32,#$Ii)",
17774 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
17775 let Inst{7-5} = 0b010;
17776 let Inst{31-21} = 0b10000000000;
17778 def S2_asl_i_p_acc : HInst<
17779 (outs DoubleRegs:$Rxx32),
17780 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17781 "$Rxx32 += asl($Rss32,#$Ii)",
17782 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
17783 let Inst{7-5} = 0b110;
17784 let Inst{31-21} = 0b10000010000;
17785 let prefersSlot3 = 1;
17786 let Constraints = "$Rxx32 = $Rxx32in";
17788 def S2_asl_i_p_and : HInst<
17789 (outs DoubleRegs:$Rxx32),
17790 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17791 "$Rxx32 &= asl($Rss32,#$Ii)",
17792 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
17793 let Inst{7-5} = 0b010;
17794 let Inst{31-21} = 0b10000010010;
17795 let prefersSlot3 = 1;
17796 let Constraints = "$Rxx32 = $Rxx32in";
17798 def S2_asl_i_p_nac : HInst<
17799 (outs DoubleRegs:$Rxx32),
17800 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17801 "$Rxx32 -= asl($Rss32,#$Ii)",
17802 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
17803 let Inst{7-5} = 0b010;
17804 let Inst{31-21} = 0b10000010000;
17805 let prefersSlot3 = 1;
17806 let Constraints = "$Rxx32 = $Rxx32in";
17808 def S2_asl_i_p_or : HInst<
17809 (outs DoubleRegs:$Rxx32),
17810 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17811 "$Rxx32 |= asl($Rss32,#$Ii)",
17812 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
17813 let Inst{7-5} = 0b110;
17814 let Inst{31-21} = 0b10000010010;
17815 let prefersSlot3 = 1;
17816 let Constraints = "$Rxx32 = $Rxx32in";
17818 def S2_asl_i_p_xacc : HInst<
17819 (outs DoubleRegs:$Rxx32),
17820 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17821 "$Rxx32 ^= asl($Rss32,#$Ii)",
17822 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
17823 let Inst{7-5} = 0b010;
17824 let Inst{31-21} = 0b10000010100;
17825 let prefersSlot3 = 1;
17826 let Constraints = "$Rxx32 = $Rxx32in";
17828 def S2_asl_i_r : HInst<
17829 (outs IntRegs:$Rd32),
17830 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
17831 "$Rd32 = asl($Rs32,#$Ii)",
17832 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
17833 let Inst{7-5} = 0b010;
17834 let Inst{13-13} = 0b0;
17835 let Inst{31-21} = 0b10001100000;
17836 let hasNewValue = 1;
17837 let opNewValue = 0;
17839 def S2_asl_i_r_acc : HInst<
17840 (outs IntRegs:$Rx32),
17841 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17842 "$Rx32 += asl($Rs32,#$Ii)",
17843 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
17844 let Inst{7-5} = 0b110;
17845 let Inst{13-13} = 0b0;
17846 let Inst{31-21} = 0b10001110000;
17847 let hasNewValue = 1;
17848 let opNewValue = 0;
17849 let prefersSlot3 = 1;
17850 let Constraints = "$Rx32 = $Rx32in";
17852 def S2_asl_i_r_and : HInst<
17853 (outs IntRegs:$Rx32),
17854 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17855 "$Rx32 &= asl($Rs32,#$Ii)",
17856 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
17857 let Inst{7-5} = 0b010;
17858 let Inst{13-13} = 0b0;
17859 let Inst{31-21} = 0b10001110010;
17860 let hasNewValue = 1;
17861 let opNewValue = 0;
17862 let prefersSlot3 = 1;
17863 let Constraints = "$Rx32 = $Rx32in";
17865 def S2_asl_i_r_nac : HInst<
17866 (outs IntRegs:$Rx32),
17867 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17868 "$Rx32 -= asl($Rs32,#$Ii)",
17869 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
17870 let Inst{7-5} = 0b010;
17871 let Inst{13-13} = 0b0;
17872 let Inst{31-21} = 0b10001110000;
17873 let hasNewValue = 1;
17874 let opNewValue = 0;
17875 let prefersSlot3 = 1;
17876 let Constraints = "$Rx32 = $Rx32in";
17878 def S2_asl_i_r_or : HInst<
17879 (outs IntRegs:$Rx32),
17880 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17881 "$Rx32 |= asl($Rs32,#$Ii)",
17882 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
17883 let Inst{7-5} = 0b110;
17884 let Inst{13-13} = 0b0;
17885 let Inst{31-21} = 0b10001110010;
17886 let hasNewValue = 1;
17887 let opNewValue = 0;
17888 let prefersSlot3 = 1;
17889 let Constraints = "$Rx32 = $Rx32in";
17891 def S2_asl_i_r_sat : HInst<
17892 (outs IntRegs:$Rd32),
17893 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
17894 "$Rd32 = asl($Rs32,#$Ii):sat",
17895 tc_b44c6e2a, TypeS_2op>, Enc_a05677 {
17896 let Inst{7-5} = 0b010;
17897 let Inst{13-13} = 0b0;
17898 let Inst{31-21} = 0b10001100010;
17899 let hasNewValue = 1;
17900 let opNewValue = 0;
17901 let prefersSlot3 = 1;
17902 let Defs = [USR_OVF];
17904 def S2_asl_i_r_xacc : HInst<
17905 (outs IntRegs:$Rx32),
17906 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17907 "$Rx32 ^= asl($Rs32,#$Ii)",
17908 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
17909 let Inst{7-5} = 0b010;
17910 let Inst{13-13} = 0b0;
17911 let Inst{31-21} = 0b10001110100;
17912 let hasNewValue = 1;
17913 let opNewValue = 0;
17914 let prefersSlot3 = 1;
17915 let Constraints = "$Rx32 = $Rx32in";
17917 def S2_asl_i_vh : HInst<
17918 (outs DoubleRegs:$Rdd32),
17919 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
17920 "$Rdd32 = vaslh($Rss32,#$Ii)",
17921 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
17922 let Inst{7-5} = 0b010;
17923 let Inst{13-12} = 0b00;
17924 let Inst{31-21} = 0b10000000100;
17926 def S2_asl_i_vw : HInst<
17927 (outs DoubleRegs:$Rdd32),
17928 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
17929 "$Rdd32 = vaslw($Rss32,#$Ii)",
17930 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
17931 let Inst{7-5} = 0b010;
17932 let Inst{13-13} = 0b0;
17933 let Inst{31-21} = 0b10000000010;
17935 def S2_asl_r_p : HInst<
17936 (outs DoubleRegs:$Rdd32),
17937 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17938 "$Rdd32 = asl($Rss32,$Rt32)",
17939 tc_540fdfbc, TypeS_3op>, Enc_927852 {
17940 let Inst{7-5} = 0b100;
17941 let Inst{13-13} = 0b0;
17942 let Inst{31-21} = 0b11000011100;
17944 def S2_asl_r_p_acc : HInst<
17945 (outs DoubleRegs:$Rxx32),
17946 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17947 "$Rxx32 += asl($Rss32,$Rt32)",
17948 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
17949 let Inst{7-5} = 0b100;
17950 let Inst{13-13} = 0b0;
17951 let Inst{31-21} = 0b11001011110;
17952 let prefersSlot3 = 1;
17953 let Constraints = "$Rxx32 = $Rxx32in";
17955 def S2_asl_r_p_and : HInst<
17956 (outs DoubleRegs:$Rxx32),
17957 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17958 "$Rxx32 &= asl($Rss32,$Rt32)",
17959 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
17960 let Inst{7-5} = 0b100;
17961 let Inst{13-13} = 0b0;
17962 let Inst{31-21} = 0b11001011010;
17963 let prefersSlot3 = 1;
17964 let Constraints = "$Rxx32 = $Rxx32in";
17966 def S2_asl_r_p_nac : HInst<
17967 (outs DoubleRegs:$Rxx32),
17968 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17969 "$Rxx32 -= asl($Rss32,$Rt32)",
17970 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
17971 let Inst{7-5} = 0b100;
17972 let Inst{13-13} = 0b0;
17973 let Inst{31-21} = 0b11001011100;
17974 let prefersSlot3 = 1;
17975 let Constraints = "$Rxx32 = $Rxx32in";
17977 def S2_asl_r_p_or : HInst<
17978 (outs DoubleRegs:$Rxx32),
17979 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17980 "$Rxx32 |= asl($Rss32,$Rt32)",
17981 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
17982 let Inst{7-5} = 0b100;
17983 let Inst{13-13} = 0b0;
17984 let Inst{31-21} = 0b11001011000;
17985 let prefersSlot3 = 1;
17986 let Constraints = "$Rxx32 = $Rxx32in";
17988 def S2_asl_r_p_xor : HInst<
17989 (outs DoubleRegs:$Rxx32),
17990 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17991 "$Rxx32 ^= asl($Rss32,$Rt32)",
17992 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
17993 let Inst{7-5} = 0b100;
17994 let Inst{13-13} = 0b0;
17995 let Inst{31-21} = 0b11001011011;
17996 let prefersSlot3 = 1;
17997 let Constraints = "$Rxx32 = $Rxx32in";
17999 def S2_asl_r_r : HInst<
18000 (outs IntRegs:$Rd32),
18001 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18002 "$Rd32 = asl($Rs32,$Rt32)",
18003 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
18004 let Inst{7-5} = 0b100;
18005 let Inst{13-13} = 0b0;
18006 let Inst{31-21} = 0b11000110010;
18007 let hasNewValue = 1;
18008 let opNewValue = 0;
18010 def S2_asl_r_r_acc : HInst<
18011 (outs IntRegs:$Rx32),
18012 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18013 "$Rx32 += asl($Rs32,$Rt32)",
18014 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18015 let Inst{7-5} = 0b100;
18016 let Inst{13-13} = 0b0;
18017 let Inst{31-21} = 0b11001100110;
18018 let hasNewValue = 1;
18019 let opNewValue = 0;
18020 let prefersSlot3 = 1;
18021 let Constraints = "$Rx32 = $Rx32in";
18023 def S2_asl_r_r_and : HInst<
18024 (outs IntRegs:$Rx32),
18025 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18026 "$Rx32 &= asl($Rs32,$Rt32)",
18027 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18028 let Inst{7-5} = 0b100;
18029 let Inst{13-13} = 0b0;
18030 let Inst{31-21} = 0b11001100010;
18031 let hasNewValue = 1;
18032 let opNewValue = 0;
18033 let prefersSlot3 = 1;
18034 let Constraints = "$Rx32 = $Rx32in";
18036 def S2_asl_r_r_nac : HInst<
18037 (outs IntRegs:$Rx32),
18038 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18039 "$Rx32 -= asl($Rs32,$Rt32)",
18040 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18041 let Inst{7-5} = 0b100;
18042 let Inst{13-13} = 0b0;
18043 let Inst{31-21} = 0b11001100100;
18044 let hasNewValue = 1;
18045 let opNewValue = 0;
18046 let prefersSlot3 = 1;
18047 let Constraints = "$Rx32 = $Rx32in";
18049 def S2_asl_r_r_or : HInst<
18050 (outs IntRegs:$Rx32),
18051 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18052 "$Rx32 |= asl($Rs32,$Rt32)",
18053 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18054 let Inst{7-5} = 0b100;
18055 let Inst{13-13} = 0b0;
18056 let Inst{31-21} = 0b11001100000;
18057 let hasNewValue = 1;
18058 let opNewValue = 0;
18059 let prefersSlot3 = 1;
18060 let Constraints = "$Rx32 = $Rx32in";
18062 def S2_asl_r_r_sat : HInst<
18063 (outs IntRegs:$Rd32),
18064 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18065 "$Rd32 = asl($Rs32,$Rt32):sat",
18066 tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
18067 let Inst{7-5} = 0b100;
18068 let Inst{13-13} = 0b0;
18069 let Inst{31-21} = 0b11000110000;
18070 let hasNewValue = 1;
18071 let opNewValue = 0;
18072 let prefersSlot3 = 1;
18073 let Defs = [USR_OVF];
18075 def S2_asl_r_vh : HInst<
18076 (outs DoubleRegs:$Rdd32),
18077 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18078 "$Rdd32 = vaslh($Rss32,$Rt32)",
18079 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18080 let Inst{7-5} = 0b100;
18081 let Inst{13-13} = 0b0;
18082 let Inst{31-21} = 0b11000011010;
18084 def S2_asl_r_vw : HInst<
18085 (outs DoubleRegs:$Rdd32),
18086 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18087 "$Rdd32 = vaslw($Rss32,$Rt32)",
18088 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18089 let Inst{7-5} = 0b100;
18090 let Inst{13-13} = 0b0;
18091 let Inst{31-21} = 0b11000011000;
18093 def S2_asr_i_p : HInst<
18094 (outs DoubleRegs:$Rdd32),
18095 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18096 "$Rdd32 = asr($Rss32,#$Ii)",
18097 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
18098 let Inst{7-5} = 0b000;
18099 let Inst{31-21} = 0b10000000000;
18101 def S2_asr_i_p_acc : HInst<
18102 (outs DoubleRegs:$Rxx32),
18103 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18104 "$Rxx32 += asr($Rss32,#$Ii)",
18105 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
18106 let Inst{7-5} = 0b100;
18107 let Inst{31-21} = 0b10000010000;
18108 let prefersSlot3 = 1;
18109 let Constraints = "$Rxx32 = $Rxx32in";
18111 def S2_asr_i_p_and : HInst<
18112 (outs DoubleRegs:$Rxx32),
18113 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18114 "$Rxx32 &= asr($Rss32,#$Ii)",
18115 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
18116 let Inst{7-5} = 0b000;
18117 let Inst{31-21} = 0b10000010010;
18118 let prefersSlot3 = 1;
18119 let Constraints = "$Rxx32 = $Rxx32in";
18121 def S2_asr_i_p_nac : HInst<
18122 (outs DoubleRegs:$Rxx32),
18123 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18124 "$Rxx32 -= asr($Rss32,#$Ii)",
18125 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
18126 let Inst{7-5} = 0b000;
18127 let Inst{31-21} = 0b10000010000;
18128 let prefersSlot3 = 1;
18129 let Constraints = "$Rxx32 = $Rxx32in";
18131 def S2_asr_i_p_or : HInst<
18132 (outs DoubleRegs:$Rxx32),
18133 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18134 "$Rxx32 |= asr($Rss32,#$Ii)",
18135 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
18136 let Inst{7-5} = 0b100;
18137 let Inst{31-21} = 0b10000010010;
18138 let prefersSlot3 = 1;
18139 let Constraints = "$Rxx32 = $Rxx32in";
18141 def S2_asr_i_p_rnd : HInst<
18142 (outs DoubleRegs:$Rdd32),
18143 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18144 "$Rdd32 = asr($Rss32,#$Ii):rnd",
18145 tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> {
18146 let Inst{7-5} = 0b111;
18147 let Inst{31-21} = 0b10000000110;
18148 let prefersSlot3 = 1;
18150 def S2_asr_i_p_rnd_goodsyntax : HInst<
18151 (outs DoubleRegs:$Rdd32),
18152 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18153 "$Rdd32 = asrrnd($Rss32,#$Ii)",
18154 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
18157 def S2_asr_i_r : HInst<
18158 (outs IntRegs:$Rd32),
18159 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
18160 "$Rd32 = asr($Rs32,#$Ii)",
18161 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
18162 let Inst{7-5} = 0b000;
18163 let Inst{13-13} = 0b0;
18164 let Inst{31-21} = 0b10001100000;
18165 let hasNewValue = 1;
18166 let opNewValue = 0;
18168 def S2_asr_i_r_acc : HInst<
18169 (outs IntRegs:$Rx32),
18170 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18171 "$Rx32 += asr($Rs32,#$Ii)",
18172 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
18173 let Inst{7-5} = 0b100;
18174 let Inst{13-13} = 0b0;
18175 let Inst{31-21} = 0b10001110000;
18176 let hasNewValue = 1;
18177 let opNewValue = 0;
18178 let prefersSlot3 = 1;
18179 let Constraints = "$Rx32 = $Rx32in";
18181 def S2_asr_i_r_and : HInst<
18182 (outs IntRegs:$Rx32),
18183 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18184 "$Rx32 &= asr($Rs32,#$Ii)",
18185 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
18186 let Inst{7-5} = 0b000;
18187 let Inst{13-13} = 0b0;
18188 let Inst{31-21} = 0b10001110010;
18189 let hasNewValue = 1;
18190 let opNewValue = 0;
18191 let prefersSlot3 = 1;
18192 let Constraints = "$Rx32 = $Rx32in";
18194 def S2_asr_i_r_nac : HInst<
18195 (outs IntRegs:$Rx32),
18196 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18197 "$Rx32 -= asr($Rs32,#$Ii)",
18198 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
18199 let Inst{7-5} = 0b000;
18200 let Inst{13-13} = 0b0;
18201 let Inst{31-21} = 0b10001110000;
18202 let hasNewValue = 1;
18203 let opNewValue = 0;
18204 let prefersSlot3 = 1;
18205 let Constraints = "$Rx32 = $Rx32in";
18207 def S2_asr_i_r_or : HInst<
18208 (outs IntRegs:$Rx32),
18209 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18210 "$Rx32 |= asr($Rs32,#$Ii)",
18211 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
18212 let Inst{7-5} = 0b100;
18213 let Inst{13-13} = 0b0;
18214 let Inst{31-21} = 0b10001110010;
18215 let hasNewValue = 1;
18216 let opNewValue = 0;
18217 let prefersSlot3 = 1;
18218 let Constraints = "$Rx32 = $Rx32in";
18220 def S2_asr_i_r_rnd : HInst<
18221 (outs IntRegs:$Rd32),
18222 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
18223 "$Rd32 = asr($Rs32,#$Ii):rnd",
18224 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
18225 let Inst{7-5} = 0b000;
18226 let Inst{13-13} = 0b0;
18227 let Inst{31-21} = 0b10001100010;
18228 let hasNewValue = 1;
18229 let opNewValue = 0;
18230 let prefersSlot3 = 1;
18232 def S2_asr_i_r_rnd_goodsyntax : HInst<
18233 (outs IntRegs:$Rd32),
18234 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
18235 "$Rd32 = asrrnd($Rs32,#$Ii)",
18236 tc_2b6f77c6, TypeS_2op> {
18237 let hasNewValue = 1;
18238 let opNewValue = 0;
18241 def S2_asr_i_svw_trun : HInst<
18242 (outs IntRegs:$Rd32),
18243 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18244 "$Rd32 = vasrw($Rss32,#$Ii)",
18245 tc_1b9c9ee5, TypeS_2op>, Enc_8dec2e {
18246 let Inst{7-5} = 0b010;
18247 let Inst{13-13} = 0b0;
18248 let Inst{31-21} = 0b10001000110;
18249 let hasNewValue = 1;
18250 let opNewValue = 0;
18251 let prefersSlot3 = 1;
18253 def S2_asr_i_vh : HInst<
18254 (outs DoubleRegs:$Rdd32),
18255 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18256 "$Rdd32 = vasrh($Rss32,#$Ii)",
18257 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
18258 let Inst{7-5} = 0b000;
18259 let Inst{13-12} = 0b00;
18260 let Inst{31-21} = 0b10000000100;
18262 def S2_asr_i_vw : HInst<
18263 (outs DoubleRegs:$Rdd32),
18264 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18265 "$Rdd32 = vasrw($Rss32,#$Ii)",
18266 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
18267 let Inst{7-5} = 0b000;
18268 let Inst{13-13} = 0b0;
18269 let Inst{31-21} = 0b10000000010;
18271 def S2_asr_r_p : HInst<
18272 (outs DoubleRegs:$Rdd32),
18273 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18274 "$Rdd32 = asr($Rss32,$Rt32)",
18275 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18276 let Inst{7-5} = 0b000;
18277 let Inst{13-13} = 0b0;
18278 let Inst{31-21} = 0b11000011100;
18280 def S2_asr_r_p_acc : HInst<
18281 (outs DoubleRegs:$Rxx32),
18282 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18283 "$Rxx32 += asr($Rss32,$Rt32)",
18284 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
18285 let Inst{7-5} = 0b000;
18286 let Inst{13-13} = 0b0;
18287 let Inst{31-21} = 0b11001011110;
18288 let prefersSlot3 = 1;
18289 let Constraints = "$Rxx32 = $Rxx32in";
18291 def S2_asr_r_p_and : HInst<
18292 (outs DoubleRegs:$Rxx32),
18293 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18294 "$Rxx32 &= asr($Rss32,$Rt32)",
18295 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18296 let Inst{7-5} = 0b000;
18297 let Inst{13-13} = 0b0;
18298 let Inst{31-21} = 0b11001011010;
18299 let prefersSlot3 = 1;
18300 let Constraints = "$Rxx32 = $Rxx32in";
18302 def S2_asr_r_p_nac : HInst<
18303 (outs DoubleRegs:$Rxx32),
18304 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18305 "$Rxx32 -= asr($Rss32,$Rt32)",
18306 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
18307 let Inst{7-5} = 0b000;
18308 let Inst{13-13} = 0b0;
18309 let Inst{31-21} = 0b11001011100;
18310 let prefersSlot3 = 1;
18311 let Constraints = "$Rxx32 = $Rxx32in";
18313 def S2_asr_r_p_or : HInst<
18314 (outs DoubleRegs:$Rxx32),
18315 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18316 "$Rxx32 |= asr($Rss32,$Rt32)",
18317 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18318 let Inst{7-5} = 0b000;
18319 let Inst{13-13} = 0b0;
18320 let Inst{31-21} = 0b11001011000;
18321 let prefersSlot3 = 1;
18322 let Constraints = "$Rxx32 = $Rxx32in";
18324 def S2_asr_r_p_xor : HInst<
18325 (outs DoubleRegs:$Rxx32),
18326 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18327 "$Rxx32 ^= asr($Rss32,$Rt32)",
18328 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18329 let Inst{7-5} = 0b000;
18330 let Inst{13-13} = 0b0;
18331 let Inst{31-21} = 0b11001011011;
18332 let prefersSlot3 = 1;
18333 let Constraints = "$Rxx32 = $Rxx32in";
18335 def S2_asr_r_r : HInst<
18336 (outs IntRegs:$Rd32),
18337 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18338 "$Rd32 = asr($Rs32,$Rt32)",
18339 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
18340 let Inst{7-5} = 0b000;
18341 let Inst{13-13} = 0b0;
18342 let Inst{31-21} = 0b11000110010;
18343 let hasNewValue = 1;
18344 let opNewValue = 0;
18346 def S2_asr_r_r_acc : HInst<
18347 (outs IntRegs:$Rx32),
18348 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18349 "$Rx32 += asr($Rs32,$Rt32)",
18350 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18351 let Inst{7-5} = 0b000;
18352 let Inst{13-13} = 0b0;
18353 let Inst{31-21} = 0b11001100110;
18354 let hasNewValue = 1;
18355 let opNewValue = 0;
18356 let prefersSlot3 = 1;
18357 let Constraints = "$Rx32 = $Rx32in";
18359 def S2_asr_r_r_and : HInst<
18360 (outs IntRegs:$Rx32),
18361 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18362 "$Rx32 &= asr($Rs32,$Rt32)",
18363 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18364 let Inst{7-5} = 0b000;
18365 let Inst{13-13} = 0b0;
18366 let Inst{31-21} = 0b11001100010;
18367 let hasNewValue = 1;
18368 let opNewValue = 0;
18369 let prefersSlot3 = 1;
18370 let Constraints = "$Rx32 = $Rx32in";
18372 def S2_asr_r_r_nac : HInst<
18373 (outs IntRegs:$Rx32),
18374 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18375 "$Rx32 -= asr($Rs32,$Rt32)",
18376 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18377 let Inst{7-5} = 0b000;
18378 let Inst{13-13} = 0b0;
18379 let Inst{31-21} = 0b11001100100;
18380 let hasNewValue = 1;
18381 let opNewValue = 0;
18382 let prefersSlot3 = 1;
18383 let Constraints = "$Rx32 = $Rx32in";
18385 def S2_asr_r_r_or : HInst<
18386 (outs IntRegs:$Rx32),
18387 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18388 "$Rx32 |= asr($Rs32,$Rt32)",
18389 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18390 let Inst{7-5} = 0b000;
18391 let Inst{13-13} = 0b0;
18392 let Inst{31-21} = 0b11001100000;
18393 let hasNewValue = 1;
18394 let opNewValue = 0;
18395 let prefersSlot3 = 1;
18396 let Constraints = "$Rx32 = $Rx32in";
18398 def S2_asr_r_r_sat : HInst<
18399 (outs IntRegs:$Rd32),
18400 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18401 "$Rd32 = asr($Rs32,$Rt32):sat",
18402 tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
18403 let Inst{7-5} = 0b000;
18404 let Inst{13-13} = 0b0;
18405 let Inst{31-21} = 0b11000110000;
18406 let hasNewValue = 1;
18407 let opNewValue = 0;
18408 let prefersSlot3 = 1;
18409 let Defs = [USR_OVF];
18411 def S2_asr_r_svw_trun : HInst<
18412 (outs IntRegs:$Rd32),
18413 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18414 "$Rd32 = vasrw($Rss32,$Rt32)",
18415 tc_1b9c9ee5, TypeS_3op>, Enc_3d5b28 {
18416 let Inst{7-5} = 0b010;
18417 let Inst{13-13} = 0b0;
18418 let Inst{31-21} = 0b11000101000;
18419 let hasNewValue = 1;
18420 let opNewValue = 0;
18421 let prefersSlot3 = 1;
18423 def S2_asr_r_vh : HInst<
18424 (outs DoubleRegs:$Rdd32),
18425 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18426 "$Rdd32 = vasrh($Rss32,$Rt32)",
18427 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18428 let Inst{7-5} = 0b000;
18429 let Inst{13-13} = 0b0;
18430 let Inst{31-21} = 0b11000011010;
18432 def S2_asr_r_vw : HInst<
18433 (outs DoubleRegs:$Rdd32),
18434 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18435 "$Rdd32 = vasrw($Rss32,$Rt32)",
18436 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18437 let Inst{7-5} = 0b000;
18438 let Inst{13-13} = 0b0;
18439 let Inst{31-21} = 0b11000011000;
18441 def S2_brev : HInst<
18442 (outs IntRegs:$Rd32),
18443 (ins IntRegs:$Rs32),
18444 "$Rd32 = brev($Rs32)",
18445 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18446 let Inst{13-5} = 0b000000110;
18447 let Inst{31-21} = 0b10001100010;
18448 let hasNewValue = 1;
18449 let opNewValue = 0;
18450 let prefersSlot3 = 1;
18452 def S2_brevp : HInst<
18453 (outs DoubleRegs:$Rdd32),
18454 (ins DoubleRegs:$Rss32),
18455 "$Rdd32 = brev($Rss32)",
18456 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
18457 let Inst{13-5} = 0b000000110;
18458 let Inst{31-21} = 0b10000000110;
18459 let prefersSlot3 = 1;
18461 def S2_cabacdecbin : HInst<
18462 (outs DoubleRegs:$Rdd32),
18463 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18464 "$Rdd32 = decbin($Rss32,$Rtt32)",
18465 tc_c6ebf8dd, TypeS_3op>, Enc_a56825 {
18466 let Inst{7-5} = 0b110;
18467 let Inst{13-13} = 0b0;
18468 let Inst{31-21} = 0b11000001110;
18469 let isPredicateLate = 1;
18470 let prefersSlot3 = 1;
18473 def S2_cl0 : HInst<
18474 (outs IntRegs:$Rd32),
18475 (ins IntRegs:$Rs32),
18476 "$Rd32 = cl0($Rs32)",
18477 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18478 let Inst{13-5} = 0b000000101;
18479 let Inst{31-21} = 0b10001100000;
18480 let hasNewValue = 1;
18481 let opNewValue = 0;
18482 let prefersSlot3 = 1;
18484 def S2_cl0p : HInst<
18485 (outs IntRegs:$Rd32),
18486 (ins DoubleRegs:$Rss32),
18487 "$Rd32 = cl0($Rss32)",
18488 tc_d088982c, TypeS_2op>, Enc_90cd8b {
18489 let Inst{13-5} = 0b000000010;
18490 let Inst{31-21} = 0b10001000010;
18491 let hasNewValue = 1;
18492 let opNewValue = 0;
18493 let prefersSlot3 = 1;
18495 def S2_cl1 : HInst<
18496 (outs IntRegs:$Rd32),
18497 (ins IntRegs:$Rs32),
18498 "$Rd32 = cl1($Rs32)",
18499 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18500 let Inst{13-5} = 0b000000110;
18501 let Inst{31-21} = 0b10001100000;
18502 let hasNewValue = 1;
18503 let opNewValue = 0;
18504 let prefersSlot3 = 1;
18506 def S2_cl1p : HInst<
18507 (outs IntRegs:$Rd32),
18508 (ins DoubleRegs:$Rss32),
18509 "$Rd32 = cl1($Rss32)",
18510 tc_d088982c, TypeS_2op>, Enc_90cd8b {
18511 let Inst{13-5} = 0b000000100;
18512 let Inst{31-21} = 0b10001000010;
18513 let hasNewValue = 1;
18514 let opNewValue = 0;
18515 let prefersSlot3 = 1;
18517 def S2_clb : HInst<
18518 (outs IntRegs:$Rd32),
18519 (ins IntRegs:$Rs32),
18520 "$Rd32 = clb($Rs32)",
18521 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18522 let Inst{13-5} = 0b000000100;
18523 let Inst{31-21} = 0b10001100000;
18524 let hasNewValue = 1;
18525 let opNewValue = 0;
18526 let prefersSlot3 = 1;
18528 def S2_clbnorm : HInst<
18529 (outs IntRegs:$Rd32),
18530 (ins IntRegs:$Rs32),
18531 "$Rd32 = normamt($Rs32)",
18532 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18533 let Inst{13-5} = 0b000000111;
18534 let Inst{31-21} = 0b10001100000;
18535 let hasNewValue = 1;
18536 let opNewValue = 0;
18537 let prefersSlot3 = 1;
18539 def S2_clbp : HInst<
18540 (outs IntRegs:$Rd32),
18541 (ins DoubleRegs:$Rss32),
18542 "$Rd32 = clb($Rss32)",
18543 tc_d088982c, TypeS_2op>, Enc_90cd8b {
18544 let Inst{13-5} = 0b000000000;
18545 let Inst{31-21} = 0b10001000010;
18546 let hasNewValue = 1;
18547 let opNewValue = 0;
18548 let prefersSlot3 = 1;
18550 def S2_clrbit_i : HInst<
18551 (outs IntRegs:$Rd32),
18552 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
18553 "$Rd32 = clrbit($Rs32,#$Ii)",
18554 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
18555 let Inst{7-5} = 0b001;
18556 let Inst{13-13} = 0b0;
18557 let Inst{31-21} = 0b10001100110;
18558 let hasNewValue = 1;
18559 let opNewValue = 0;
18561 def S2_clrbit_r : HInst<
18562 (outs IntRegs:$Rd32),
18563 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18564 "$Rd32 = clrbit($Rs32,$Rt32)",
18565 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
18566 let Inst{7-5} = 0b010;
18567 let Inst{13-13} = 0b0;
18568 let Inst{31-21} = 0b11000110100;
18569 let hasNewValue = 1;
18570 let opNewValue = 0;
18572 def S2_ct0 : HInst<
18573 (outs IntRegs:$Rd32),
18574 (ins IntRegs:$Rs32),
18575 "$Rd32 = ct0($Rs32)",
18576 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18577 let Inst{13-5} = 0b000000100;
18578 let Inst{31-21} = 0b10001100010;
18579 let hasNewValue = 1;
18580 let opNewValue = 0;
18581 let prefersSlot3 = 1;
18583 def S2_ct0p : HInst<
18584 (outs IntRegs:$Rd32),
18585 (ins DoubleRegs:$Rss32),
18586 "$Rd32 = ct0($Rss32)",
18587 tc_d088982c, TypeS_2op>, Enc_90cd8b {
18588 let Inst{13-5} = 0b000000010;
18589 let Inst{31-21} = 0b10001000111;
18590 let hasNewValue = 1;
18591 let opNewValue = 0;
18592 let prefersSlot3 = 1;
18594 def S2_ct1 : HInst<
18595 (outs IntRegs:$Rd32),
18596 (ins IntRegs:$Rs32),
18597 "$Rd32 = ct1($Rs32)",
18598 tc_d088982c, TypeS_2op>, Enc_5e2823 {
18599 let Inst{13-5} = 0b000000101;
18600 let Inst{31-21} = 0b10001100010;
18601 let hasNewValue = 1;
18602 let opNewValue = 0;
18603 let prefersSlot3 = 1;
18605 def S2_ct1p : HInst<
18606 (outs IntRegs:$Rd32),
18607 (ins DoubleRegs:$Rss32),
18608 "$Rd32 = ct1($Rss32)",
18609 tc_d088982c, TypeS_2op>, Enc_90cd8b {
18610 let Inst{13-5} = 0b000000100;
18611 let Inst{31-21} = 0b10001000111;
18612 let hasNewValue = 1;
18613 let opNewValue = 0;
18614 let prefersSlot3 = 1;
18616 def S2_deinterleave : HInst<
18617 (outs DoubleRegs:$Rdd32),
18618 (ins DoubleRegs:$Rss32),
18619 "$Rdd32 = deinterleave($Rss32)",
18620 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
18621 let Inst{13-5} = 0b000000100;
18622 let Inst{31-21} = 0b10000000110;
18623 let prefersSlot3 = 1;
18625 def S2_extractu : HInst<
18626 (outs IntRegs:$Rd32),
18627 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
18628 "$Rd32 = extractu($Rs32,#$Ii,#$II)",
18629 tc_c74f796f, TypeS_2op>, Enc_b388cf {
18630 let Inst{13-13} = 0b0;
18631 let Inst{31-23} = 0b100011010;
18632 let hasNewValue = 1;
18633 let opNewValue = 0;
18634 let prefersSlot3 = 1;
18636 def S2_extractu_rp : HInst<
18637 (outs IntRegs:$Rd32),
18638 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
18639 "$Rd32 = extractu($Rs32,$Rtt32)",
18640 tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
18641 let Inst{7-5} = 0b000;
18642 let Inst{13-13} = 0b0;
18643 let Inst{31-21} = 0b11001001000;
18644 let hasNewValue = 1;
18645 let opNewValue = 0;
18646 let prefersSlot3 = 1;
18648 def S2_extractup : HInst<
18649 (outs DoubleRegs:$Rdd32),
18650 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
18651 "$Rdd32 = extractu($Rss32,#$Ii,#$II)",
18652 tc_c74f796f, TypeS_2op>, Enc_b84c4c {
18653 let Inst{31-24} = 0b10000001;
18654 let prefersSlot3 = 1;
18656 def S2_extractup_rp : HInst<
18657 (outs DoubleRegs:$Rdd32),
18658 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18659 "$Rdd32 = extractu($Rss32,$Rtt32)",
18660 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
18661 let Inst{7-5} = 0b000;
18662 let Inst{13-13} = 0b0;
18663 let Inst{31-21} = 0b11000001000;
18664 let prefersSlot3 = 1;
18666 def S2_insert : HInst<
18667 (outs IntRegs:$Rx32),
18668 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
18669 "$Rx32 = insert($Rs32,#$Ii,#$II)",
18670 tc_87735c3b, TypeS_2op>, Enc_a1e29d {
18671 let Inst{13-13} = 0b0;
18672 let Inst{31-23} = 0b100011110;
18673 let hasNewValue = 1;
18674 let opNewValue = 0;
18675 let prefersSlot3 = 1;
18676 let Constraints = "$Rx32 = $Rx32in";
18678 def S2_insert_rp : HInst<
18679 (outs IntRegs:$Rx32),
18680 (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
18681 "$Rx32 = insert($Rs32,$Rtt32)",
18682 tc_84df2cd3, TypeS_3op>, Enc_179b35 {
18683 let Inst{7-5} = 0b000;
18684 let Inst{13-13} = 0b0;
18685 let Inst{31-21} = 0b11001000000;
18686 let hasNewValue = 1;
18687 let opNewValue = 0;
18688 let prefersSlot3 = 1;
18689 let Constraints = "$Rx32 = $Rx32in";
18691 def S2_insertp : HInst<
18692 (outs DoubleRegs:$Rxx32),
18693 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
18694 "$Rxx32 = insert($Rss32,#$Ii,#$II)",
18695 tc_87735c3b, TypeS_2op>, Enc_143a3c {
18696 let Inst{31-24} = 0b10000011;
18697 let prefersSlot3 = 1;
18698 let Constraints = "$Rxx32 = $Rxx32in";
18700 def S2_insertp_rp : HInst<
18701 (outs DoubleRegs:$Rxx32),
18702 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18703 "$Rxx32 = insert($Rss32,$Rtt32)",
18704 tc_84df2cd3, TypeS_3op>, Enc_88c16c {
18705 let Inst{7-5} = 0b000;
18706 let Inst{13-13} = 0b0;
18707 let Inst{31-21} = 0b11001010000;
18708 let prefersSlot3 = 1;
18709 let Constraints = "$Rxx32 = $Rxx32in";
18711 def S2_interleave : HInst<
18712 (outs DoubleRegs:$Rdd32),
18713 (ins DoubleRegs:$Rss32),
18714 "$Rdd32 = interleave($Rss32)",
18715 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
18716 let Inst{13-5} = 0b000000101;
18717 let Inst{31-21} = 0b10000000110;
18718 let prefersSlot3 = 1;
18720 def S2_lfsp : HInst<
18721 (outs DoubleRegs:$Rdd32),
18722 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18723 "$Rdd32 = lfs($Rss32,$Rtt32)",
18724 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
18725 let Inst{7-5} = 0b110;
18726 let Inst{13-13} = 0b0;
18727 let Inst{31-21} = 0b11000001100;
18728 let prefersSlot3 = 1;
18730 def S2_lsl_r_p : HInst<
18731 (outs DoubleRegs:$Rdd32),
18732 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18733 "$Rdd32 = lsl($Rss32,$Rt32)",
18734 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18735 let Inst{7-5} = 0b110;
18736 let Inst{13-13} = 0b0;
18737 let Inst{31-21} = 0b11000011100;
18739 def S2_lsl_r_p_acc : HInst<
18740 (outs DoubleRegs:$Rxx32),
18741 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18742 "$Rxx32 += lsl($Rss32,$Rt32)",
18743 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
18744 let Inst{7-5} = 0b110;
18745 let Inst{13-13} = 0b0;
18746 let Inst{31-21} = 0b11001011110;
18747 let prefersSlot3 = 1;
18748 let Constraints = "$Rxx32 = $Rxx32in";
18750 def S2_lsl_r_p_and : HInst<
18751 (outs DoubleRegs:$Rxx32),
18752 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18753 "$Rxx32 &= lsl($Rss32,$Rt32)",
18754 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18755 let Inst{7-5} = 0b110;
18756 let Inst{13-13} = 0b0;
18757 let Inst{31-21} = 0b11001011010;
18758 let prefersSlot3 = 1;
18759 let Constraints = "$Rxx32 = $Rxx32in";
18761 def S2_lsl_r_p_nac : HInst<
18762 (outs DoubleRegs:$Rxx32),
18763 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18764 "$Rxx32 -= lsl($Rss32,$Rt32)",
18765 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
18766 let Inst{7-5} = 0b110;
18767 let Inst{13-13} = 0b0;
18768 let Inst{31-21} = 0b11001011100;
18769 let prefersSlot3 = 1;
18770 let Constraints = "$Rxx32 = $Rxx32in";
18772 def S2_lsl_r_p_or : HInst<
18773 (outs DoubleRegs:$Rxx32),
18774 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18775 "$Rxx32 |= lsl($Rss32,$Rt32)",
18776 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18777 let Inst{7-5} = 0b110;
18778 let Inst{13-13} = 0b0;
18779 let Inst{31-21} = 0b11001011000;
18780 let prefersSlot3 = 1;
18781 let Constraints = "$Rxx32 = $Rxx32in";
18783 def S2_lsl_r_p_xor : HInst<
18784 (outs DoubleRegs:$Rxx32),
18785 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18786 "$Rxx32 ^= lsl($Rss32,$Rt32)",
18787 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
18788 let Inst{7-5} = 0b110;
18789 let Inst{13-13} = 0b0;
18790 let Inst{31-21} = 0b11001011011;
18791 let prefersSlot3 = 1;
18792 let Constraints = "$Rxx32 = $Rxx32in";
18794 def S2_lsl_r_r : HInst<
18795 (outs IntRegs:$Rd32),
18796 (ins IntRegs:$Rs32, IntRegs:$Rt32),
18797 "$Rd32 = lsl($Rs32,$Rt32)",
18798 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
18799 let Inst{7-5} = 0b110;
18800 let Inst{13-13} = 0b0;
18801 let Inst{31-21} = 0b11000110010;
18802 let hasNewValue = 1;
18803 let opNewValue = 0;
18805 def S2_lsl_r_r_acc : HInst<
18806 (outs IntRegs:$Rx32),
18807 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18808 "$Rx32 += lsl($Rs32,$Rt32)",
18809 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18810 let Inst{7-5} = 0b110;
18811 let Inst{13-13} = 0b0;
18812 let Inst{31-21} = 0b11001100110;
18813 let hasNewValue = 1;
18814 let opNewValue = 0;
18815 let prefersSlot3 = 1;
18816 let Constraints = "$Rx32 = $Rx32in";
18818 def S2_lsl_r_r_and : HInst<
18819 (outs IntRegs:$Rx32),
18820 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18821 "$Rx32 &= lsl($Rs32,$Rt32)",
18822 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18823 let Inst{7-5} = 0b110;
18824 let Inst{13-13} = 0b0;
18825 let Inst{31-21} = 0b11001100010;
18826 let hasNewValue = 1;
18827 let opNewValue = 0;
18828 let prefersSlot3 = 1;
18829 let Constraints = "$Rx32 = $Rx32in";
18831 def S2_lsl_r_r_nac : HInst<
18832 (outs IntRegs:$Rx32),
18833 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18834 "$Rx32 -= lsl($Rs32,$Rt32)",
18835 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
18836 let Inst{7-5} = 0b110;
18837 let Inst{13-13} = 0b0;
18838 let Inst{31-21} = 0b11001100100;
18839 let hasNewValue = 1;
18840 let opNewValue = 0;
18841 let prefersSlot3 = 1;
18842 let Constraints = "$Rx32 = $Rx32in";
18844 def S2_lsl_r_r_or : HInst<
18845 (outs IntRegs:$Rx32),
18846 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18847 "$Rx32 |= lsl($Rs32,$Rt32)",
18848 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
18849 let Inst{7-5} = 0b110;
18850 let Inst{13-13} = 0b0;
18851 let Inst{31-21} = 0b11001100000;
18852 let hasNewValue = 1;
18853 let opNewValue = 0;
18854 let prefersSlot3 = 1;
18855 let Constraints = "$Rx32 = $Rx32in";
18857 def S2_lsl_r_vh : HInst<
18858 (outs DoubleRegs:$Rdd32),
18859 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18860 "$Rdd32 = vlslh($Rss32,$Rt32)",
18861 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18862 let Inst{7-5} = 0b110;
18863 let Inst{13-13} = 0b0;
18864 let Inst{31-21} = 0b11000011010;
18866 def S2_lsl_r_vw : HInst<
18867 (outs DoubleRegs:$Rdd32),
18868 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18869 "$Rdd32 = vlslw($Rss32,$Rt32)",
18870 tc_540fdfbc, TypeS_3op>, Enc_927852 {
18871 let Inst{7-5} = 0b110;
18872 let Inst{13-13} = 0b0;
18873 let Inst{31-21} = 0b11000011000;
18875 def S2_lsr_i_p : HInst<
18876 (outs DoubleRegs:$Rdd32),
18877 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18878 "$Rdd32 = lsr($Rss32,#$Ii)",
18879 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
18880 let Inst{7-5} = 0b001;
18881 let Inst{31-21} = 0b10000000000;
18883 def S2_lsr_i_p_acc : HInst<
18884 (outs DoubleRegs:$Rxx32),
18885 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18886 "$Rxx32 += lsr($Rss32,#$Ii)",
18887 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
18888 let Inst{7-5} = 0b101;
18889 let Inst{31-21} = 0b10000010000;
18890 let prefersSlot3 = 1;
18891 let Constraints = "$Rxx32 = $Rxx32in";
18893 def S2_lsr_i_p_and : HInst<
18894 (outs DoubleRegs:$Rxx32),
18895 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18896 "$Rxx32 &= lsr($Rss32,#$Ii)",
18897 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
18898 let Inst{7-5} = 0b001;
18899 let Inst{31-21} = 0b10000010010;
18900 let prefersSlot3 = 1;
18901 let Constraints = "$Rxx32 = $Rxx32in";
18903 def S2_lsr_i_p_nac : HInst<
18904 (outs DoubleRegs:$Rxx32),
18905 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18906 "$Rxx32 -= lsr($Rss32,#$Ii)",
18907 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
18908 let Inst{7-5} = 0b001;
18909 let Inst{31-21} = 0b10000010000;
18910 let prefersSlot3 = 1;
18911 let Constraints = "$Rxx32 = $Rxx32in";
18913 def S2_lsr_i_p_or : HInst<
18914 (outs DoubleRegs:$Rxx32),
18915 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18916 "$Rxx32 |= lsr($Rss32,#$Ii)",
18917 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
18918 let Inst{7-5} = 0b101;
18919 let Inst{31-21} = 0b10000010010;
18920 let prefersSlot3 = 1;
18921 let Constraints = "$Rxx32 = $Rxx32in";
18923 def S2_lsr_i_p_xacc : HInst<
18924 (outs DoubleRegs:$Rxx32),
18925 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18926 "$Rxx32 ^= lsr($Rss32,#$Ii)",
18927 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
18928 let Inst{7-5} = 0b001;
18929 let Inst{31-21} = 0b10000010100;
18930 let prefersSlot3 = 1;
18931 let Constraints = "$Rxx32 = $Rxx32in";
18933 def S2_lsr_i_r : HInst<
18934 (outs IntRegs:$Rd32),
18935 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
18936 "$Rd32 = lsr($Rs32,#$Ii)",
18937 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
18938 let Inst{7-5} = 0b001;
18939 let Inst{13-13} = 0b0;
18940 let Inst{31-21} = 0b10001100000;
18941 let hasNewValue = 1;
18942 let opNewValue = 0;
18944 def S2_lsr_i_r_acc : HInst<
18945 (outs IntRegs:$Rx32),
18946 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18947 "$Rx32 += lsr($Rs32,#$Ii)",
18948 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
18949 let Inst{7-5} = 0b101;
18950 let Inst{13-13} = 0b0;
18951 let Inst{31-21} = 0b10001110000;
18952 let hasNewValue = 1;
18953 let opNewValue = 0;
18954 let prefersSlot3 = 1;
18955 let Constraints = "$Rx32 = $Rx32in";
18957 def S2_lsr_i_r_and : HInst<
18958 (outs IntRegs:$Rx32),
18959 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18960 "$Rx32 &= lsr($Rs32,#$Ii)",
18961 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
18962 let Inst{7-5} = 0b001;
18963 let Inst{13-13} = 0b0;
18964 let Inst{31-21} = 0b10001110010;
18965 let hasNewValue = 1;
18966 let opNewValue = 0;
18967 let prefersSlot3 = 1;
18968 let Constraints = "$Rx32 = $Rx32in";
18970 def S2_lsr_i_r_nac : HInst<
18971 (outs IntRegs:$Rx32),
18972 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18973 "$Rx32 -= lsr($Rs32,#$Ii)",
18974 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
18975 let Inst{7-5} = 0b001;
18976 let Inst{13-13} = 0b0;
18977 let Inst{31-21} = 0b10001110000;
18978 let hasNewValue = 1;
18979 let opNewValue = 0;
18980 let prefersSlot3 = 1;
18981 let Constraints = "$Rx32 = $Rx32in";
18983 def S2_lsr_i_r_or : HInst<
18984 (outs IntRegs:$Rx32),
18985 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18986 "$Rx32 |= lsr($Rs32,#$Ii)",
18987 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
18988 let Inst{7-5} = 0b101;
18989 let Inst{13-13} = 0b0;
18990 let Inst{31-21} = 0b10001110010;
18991 let hasNewValue = 1;
18992 let opNewValue = 0;
18993 let prefersSlot3 = 1;
18994 let Constraints = "$Rx32 = $Rx32in";
18996 def S2_lsr_i_r_xacc : HInst<
18997 (outs IntRegs:$Rx32),
18998 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18999 "$Rx32 ^= lsr($Rs32,#$Ii)",
19000 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
19001 let Inst{7-5} = 0b001;
19002 let Inst{13-13} = 0b0;
19003 let Inst{31-21} = 0b10001110100;
19004 let hasNewValue = 1;
19005 let opNewValue = 0;
19006 let prefersSlot3 = 1;
19007 let Constraints = "$Rx32 = $Rx32in";
19009 def S2_lsr_i_vh : HInst<
19010 (outs DoubleRegs:$Rdd32),
19011 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19012 "$Rdd32 = vlsrh($Rss32,#$Ii)",
19013 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
19014 let Inst{7-5} = 0b001;
19015 let Inst{13-12} = 0b00;
19016 let Inst{31-21} = 0b10000000100;
19018 def S2_lsr_i_vw : HInst<
19019 (outs DoubleRegs:$Rdd32),
19020 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19021 "$Rdd32 = vlsrw($Rss32,#$Ii)",
19022 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
19023 let Inst{7-5} = 0b001;
19024 let Inst{13-13} = 0b0;
19025 let Inst{31-21} = 0b10000000010;
19027 def S2_lsr_r_p : HInst<
19028 (outs DoubleRegs:$Rdd32),
19029 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19030 "$Rdd32 = lsr($Rss32,$Rt32)",
19031 tc_540fdfbc, TypeS_3op>, Enc_927852 {
19032 let Inst{7-5} = 0b010;
19033 let Inst{13-13} = 0b0;
19034 let Inst{31-21} = 0b11000011100;
19036 def S2_lsr_r_p_acc : HInst<
19037 (outs DoubleRegs:$Rxx32),
19038 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19039 "$Rxx32 += lsr($Rss32,$Rt32)",
19040 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
19041 let Inst{7-5} = 0b010;
19042 let Inst{13-13} = 0b0;
19043 let Inst{31-21} = 0b11001011110;
19044 let prefersSlot3 = 1;
19045 let Constraints = "$Rxx32 = $Rxx32in";
19047 def S2_lsr_r_p_and : HInst<
19048 (outs DoubleRegs:$Rxx32),
19049 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19050 "$Rxx32 &= lsr($Rss32,$Rt32)",
19051 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
19052 let Inst{7-5} = 0b010;
19053 let Inst{13-13} = 0b0;
19054 let Inst{31-21} = 0b11001011010;
19055 let prefersSlot3 = 1;
19056 let Constraints = "$Rxx32 = $Rxx32in";
19058 def S2_lsr_r_p_nac : HInst<
19059 (outs DoubleRegs:$Rxx32),
19060 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19061 "$Rxx32 -= lsr($Rss32,$Rt32)",
19062 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
19063 let Inst{7-5} = 0b010;
19064 let Inst{13-13} = 0b0;
19065 let Inst{31-21} = 0b11001011100;
19066 let prefersSlot3 = 1;
19067 let Constraints = "$Rxx32 = $Rxx32in";
19069 def S2_lsr_r_p_or : HInst<
19070 (outs DoubleRegs:$Rxx32),
19071 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19072 "$Rxx32 |= lsr($Rss32,$Rt32)",
19073 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
19074 let Inst{7-5} = 0b010;
19075 let Inst{13-13} = 0b0;
19076 let Inst{31-21} = 0b11001011000;
19077 let prefersSlot3 = 1;
19078 let Constraints = "$Rxx32 = $Rxx32in";
19080 def S2_lsr_r_p_xor : HInst<
19081 (outs DoubleRegs:$Rxx32),
19082 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19083 "$Rxx32 ^= lsr($Rss32,$Rt32)",
19084 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
19085 let Inst{7-5} = 0b010;
19086 let Inst{13-13} = 0b0;
19087 let Inst{31-21} = 0b11001011011;
19088 let prefersSlot3 = 1;
19089 let Constraints = "$Rxx32 = $Rxx32in";
19091 def S2_lsr_r_r : HInst<
19092 (outs IntRegs:$Rd32),
19093 (ins IntRegs:$Rs32, IntRegs:$Rt32),
19094 "$Rd32 = lsr($Rs32,$Rt32)",
19095 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
19096 let Inst{7-5} = 0b010;
19097 let Inst{13-13} = 0b0;
19098 let Inst{31-21} = 0b11000110010;
19099 let hasNewValue = 1;
19100 let opNewValue = 0;
19102 def S2_lsr_r_r_acc : HInst<
19103 (outs IntRegs:$Rx32),
19104 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19105 "$Rx32 += lsr($Rs32,$Rt32)",
19106 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
19107 let Inst{7-5} = 0b010;
19108 let Inst{13-13} = 0b0;
19109 let Inst{31-21} = 0b11001100110;
19110 let hasNewValue = 1;
19111 let opNewValue = 0;
19112 let prefersSlot3 = 1;
19113 let Constraints = "$Rx32 = $Rx32in";
19115 def S2_lsr_r_r_and : HInst<
19116 (outs IntRegs:$Rx32),
19117 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19118 "$Rx32 &= lsr($Rs32,$Rt32)",
19119 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
19120 let Inst{7-5} = 0b010;
19121 let Inst{13-13} = 0b0;
19122 let Inst{31-21} = 0b11001100010;
19123 let hasNewValue = 1;
19124 let opNewValue = 0;
19125 let prefersSlot3 = 1;
19126 let Constraints = "$Rx32 = $Rx32in";
19128 def S2_lsr_r_r_nac : HInst<
19129 (outs IntRegs:$Rx32),
19130 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19131 "$Rx32 -= lsr($Rs32,$Rt32)",
19132 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
19133 let Inst{7-5} = 0b010;
19134 let Inst{13-13} = 0b0;
19135 let Inst{31-21} = 0b11001100100;
19136 let hasNewValue = 1;
19137 let opNewValue = 0;
19138 let prefersSlot3 = 1;
19139 let Constraints = "$Rx32 = $Rx32in";
19141 def S2_lsr_r_r_or : HInst<
19142 (outs IntRegs:$Rx32),
19143 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19144 "$Rx32 |= lsr($Rs32,$Rt32)",
19145 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
19146 let Inst{7-5} = 0b010;
19147 let Inst{13-13} = 0b0;
19148 let Inst{31-21} = 0b11001100000;
19149 let hasNewValue = 1;
19150 let opNewValue = 0;
19151 let prefersSlot3 = 1;
19152 let Constraints = "$Rx32 = $Rx32in";
19154 def S2_lsr_r_vh : HInst<
19155 (outs DoubleRegs:$Rdd32),
19156 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19157 "$Rdd32 = vlsrh($Rss32,$Rt32)",
19158 tc_540fdfbc, TypeS_3op>, Enc_927852 {
19159 let Inst{7-5} = 0b010;
19160 let Inst{13-13} = 0b0;
19161 let Inst{31-21} = 0b11000011010;
19163 def S2_lsr_r_vw : HInst<
19164 (outs DoubleRegs:$Rdd32),
19165 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19166 "$Rdd32 = vlsrw($Rss32,$Rt32)",
19167 tc_540fdfbc, TypeS_3op>, Enc_927852 {
19168 let Inst{7-5} = 0b010;
19169 let Inst{13-13} = 0b0;
19170 let Inst{31-21} = 0b11000011000;
19172 def S2_packhl : HInst<
19173 (outs DoubleRegs:$Rdd32),
19174 (ins IntRegs:$Rs32, IntRegs:$Rt32),
19175 "$Rdd32 = packhl($Rs32,$Rt32)",
19176 tc_b9488031, TypeALU32_3op>, Enc_be32a5 {
19177 let Inst{7-5} = 0b000;
19178 let Inst{13-13} = 0b0;
19179 let Inst{31-21} = 0b11110101100;
19180 let InputType = "reg";
19182 def S2_parityp : HInst<
19183 (outs IntRegs:$Rd32),
19184 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19185 "$Rd32 = parity($Rss32,$Rtt32)",
19186 tc_2b6f77c6, TypeALU64>, Enc_d2216a {
19187 let Inst{7-5} = 0b000;
19188 let Inst{13-13} = 0b0;
19189 let Inst{31-21} = 0b11010000000;
19190 let hasNewValue = 1;
19191 let opNewValue = 0;
19192 let prefersSlot3 = 1;
19194 def S2_pstorerbf_io : HInst<
19196 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19197 "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19198 tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19199 let Inst{2-2} = 0b0;
19200 let Inst{31-21} = 0b01000100000;
19201 let isPredicated = 1;
19202 let isPredicatedFalse = 1;
19203 let addrMode = BaseImmOffset;
19204 let accessSize = ByteAccess;
19206 let CextOpcode = "S2_storerb";
19207 let InputType = "imm";
19208 let BaseOpcode = "S2_storerb_io";
19209 let isNVStorable = 1;
19210 let isExtendable = 1;
19211 let opExtendable = 2;
19212 let isExtentSigned = 0;
19213 let opExtentBits = 6;
19214 let opExtentAlign = 0;
19216 def S2_pstorerbf_pi : HInst<
19217 (outs IntRegs:$Rx32),
19218 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19219 "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19220 tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
19221 let Inst{2-2} = 0b1;
19222 let Inst{7-7} = 0b0;
19223 let Inst{13-13} = 0b1;
19224 let Inst{31-21} = 0b10101011000;
19225 let isPredicated = 1;
19226 let isPredicatedFalse = 1;
19227 let addrMode = PostInc;
19228 let accessSize = ByteAccess;
19230 let BaseOpcode = "S2_storerb_pi";
19231 let isNVStorable = 1;
19232 let Constraints = "$Rx32 = $Rx32in";
19234 def S2_pstorerbf_zomap : HInst<
19236 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19237 "if (!$Pv4) memb($Rs32) = $Rt32",
19238 tc_8b15472a, TypeMAPPING> {
19240 let isCodeGenOnly = 1;
19242 def S2_pstorerbfnew_pi : HInst<
19243 (outs IntRegs:$Rx32),
19244 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19245 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19246 tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
19247 let Inst{2-2} = 0b1;
19248 let Inst{7-7} = 0b1;
19249 let Inst{13-13} = 0b1;
19250 let Inst{31-21} = 0b10101011000;
19251 let isPredicated = 1;
19252 let isPredicatedFalse = 1;
19253 let addrMode = PostInc;
19254 let accessSize = ByteAccess;
19255 let isPredicatedNew = 1;
19257 let BaseOpcode = "S2_storerb_pi";
19258 let isNVStorable = 1;
19259 let Constraints = "$Rx32 = $Rx32in";
19261 def S2_pstorerbnewf_io : HInst<
19263 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19264 "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19265 tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
19266 let Inst{2-2} = 0b0;
19267 let Inst{12-11} = 0b00;
19268 let Inst{31-21} = 0b01000100101;
19269 let isPredicated = 1;
19270 let isPredicatedFalse = 1;
19271 let addrMode = BaseImmOffset;
19272 let accessSize = ByteAccess;
19274 let isNewValue = 1;
19275 let isRestrictNoSlot1Store = 1;
19277 let CextOpcode = "S2_storerb";
19278 let InputType = "imm";
19279 let BaseOpcode = "S2_storerb_io";
19280 let isExtendable = 1;
19281 let opExtendable = 2;
19282 let isExtentSigned = 0;
19283 let opExtentBits = 6;
19284 let opExtentAlign = 0;
19285 let opNewValue = 3;
19287 def S2_pstorerbnewf_pi : HInst<
19288 (outs IntRegs:$Rx32),
19289 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19290 "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19291 tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
19292 let Inst{2-2} = 0b1;
19293 let Inst{7-7} = 0b0;
19294 let Inst{13-11} = 0b100;
19295 let Inst{31-21} = 0b10101011101;
19296 let isPredicated = 1;
19297 let isPredicatedFalse = 1;
19298 let addrMode = PostInc;
19299 let accessSize = ByteAccess;
19301 let isNewValue = 1;
19302 let isRestrictNoSlot1Store = 1;
19304 let CextOpcode = "S2_storerb";
19305 let BaseOpcode = "S2_storerb_pi";
19306 let opNewValue = 4;
19307 let Constraints = "$Rx32 = $Rx32in";
19309 def S2_pstorerbnewf_zomap : HInst<
19311 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19312 "if (!$Pv4) memb($Rs32) = $Nt8.new",
19313 tc_594ab548, TypeMAPPING> {
19315 let isCodeGenOnly = 1;
19316 let opNewValue = 2;
19318 def S2_pstorerbnewfnew_pi : HInst<
19319 (outs IntRegs:$Rx32),
19320 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19321 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19322 tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
19323 let Inst{2-2} = 0b1;
19324 let Inst{7-7} = 0b1;
19325 let Inst{13-11} = 0b100;
19326 let Inst{31-21} = 0b10101011101;
19327 let isPredicated = 1;
19328 let isPredicatedFalse = 1;
19329 let addrMode = PostInc;
19330 let accessSize = ByteAccess;
19332 let isPredicatedNew = 1;
19333 let isNewValue = 1;
19334 let isRestrictNoSlot1Store = 1;
19336 let CextOpcode = "S2_storerb";
19337 let BaseOpcode = "S2_storerb_pi";
19338 let opNewValue = 4;
19339 let Constraints = "$Rx32 = $Rx32in";
19341 def S2_pstorerbnewt_io : HInst<
19343 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19344 "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19345 tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
19346 let Inst{2-2} = 0b0;
19347 let Inst{12-11} = 0b00;
19348 let Inst{31-21} = 0b01000000101;
19349 let isPredicated = 1;
19350 let addrMode = BaseImmOffset;
19351 let accessSize = ByteAccess;
19353 let isNewValue = 1;
19354 let isRestrictNoSlot1Store = 1;
19356 let CextOpcode = "S2_storerb";
19357 let InputType = "imm";
19358 let BaseOpcode = "S2_storerb_io";
19359 let isExtendable = 1;
19360 let opExtendable = 2;
19361 let isExtentSigned = 0;
19362 let opExtentBits = 6;
19363 let opExtentAlign = 0;
19364 let opNewValue = 3;
19366 def S2_pstorerbnewt_pi : HInst<
19367 (outs IntRegs:$Rx32),
19368 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19369 "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19370 tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
19371 let Inst{2-2} = 0b0;
19372 let Inst{7-7} = 0b0;
19373 let Inst{13-11} = 0b100;
19374 let Inst{31-21} = 0b10101011101;
19375 let isPredicated = 1;
19376 let addrMode = PostInc;
19377 let accessSize = ByteAccess;
19379 let isNewValue = 1;
19380 let isRestrictNoSlot1Store = 1;
19382 let CextOpcode = "S2_storerb";
19383 let BaseOpcode = "S2_storerb_pi";
19384 let opNewValue = 4;
19385 let Constraints = "$Rx32 = $Rx32in";
19387 def S2_pstorerbnewt_zomap : HInst<
19389 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19390 "if ($Pv4) memb($Rs32) = $Nt8.new",
19391 tc_594ab548, TypeMAPPING> {
19393 let isCodeGenOnly = 1;
19394 let opNewValue = 2;
19396 def S2_pstorerbnewtnew_pi : HInst<
19397 (outs IntRegs:$Rx32),
19398 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19399 "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19400 tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
19401 let Inst{2-2} = 0b0;
19402 let Inst{7-7} = 0b1;
19403 let Inst{13-11} = 0b100;
19404 let Inst{31-21} = 0b10101011101;
19405 let isPredicated = 1;
19406 let addrMode = PostInc;
19407 let accessSize = ByteAccess;
19409 let isPredicatedNew = 1;
19410 let isNewValue = 1;
19411 let isRestrictNoSlot1Store = 1;
19413 let CextOpcode = "S2_storerb";
19414 let BaseOpcode = "S2_storerb_pi";
19415 let opNewValue = 4;
19416 let Constraints = "$Rx32 = $Rx32in";
19418 def S2_pstorerbt_io : HInst<
19420 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19421 "if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19422 tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19423 let Inst{2-2} = 0b0;
19424 let Inst{31-21} = 0b01000000000;
19425 let isPredicated = 1;
19426 let addrMode = BaseImmOffset;
19427 let accessSize = ByteAccess;
19429 let CextOpcode = "S2_storerb";
19430 let InputType = "imm";
19431 let BaseOpcode = "S2_storerb_io";
19432 let isNVStorable = 1;
19433 let isExtendable = 1;
19434 let opExtendable = 2;
19435 let isExtentSigned = 0;
19436 let opExtentBits = 6;
19437 let opExtentAlign = 0;
19439 def S2_pstorerbt_pi : HInst<
19440 (outs IntRegs:$Rx32),
19441 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19442 "if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19443 tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
19444 let Inst{2-2} = 0b0;
19445 let Inst{7-7} = 0b0;
19446 let Inst{13-13} = 0b1;
19447 let Inst{31-21} = 0b10101011000;
19448 let isPredicated = 1;
19449 let addrMode = PostInc;
19450 let accessSize = ByteAccess;
19452 let BaseOpcode = "S2_storerb_pi";
19453 let isNVStorable = 1;
19454 let Constraints = "$Rx32 = $Rx32in";
19456 def S2_pstorerbt_zomap : HInst<
19458 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19459 "if ($Pv4) memb($Rs32) = $Rt32",
19460 tc_8b15472a, TypeMAPPING> {
19462 let isCodeGenOnly = 1;
19464 def S2_pstorerbtnew_pi : HInst<
19465 (outs IntRegs:$Rx32),
19466 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19467 "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19468 tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
19469 let Inst{2-2} = 0b0;
19470 let Inst{7-7} = 0b1;
19471 let Inst{13-13} = 0b1;
19472 let Inst{31-21} = 0b10101011000;
19473 let isPredicated = 1;
19474 let addrMode = PostInc;
19475 let accessSize = ByteAccess;
19476 let isPredicatedNew = 1;
19478 let BaseOpcode = "S2_storerb_pi";
19479 let isNVStorable = 1;
19480 let Constraints = "$Rx32 = $Rx32in";
19482 def S2_pstorerdf_io : HInst<
19484 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19485 "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
19486 tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19487 let Inst{2-2} = 0b0;
19488 let Inst{31-21} = 0b01000100110;
19489 let isPredicated = 1;
19490 let isPredicatedFalse = 1;
19491 let addrMode = BaseImmOffset;
19492 let accessSize = DoubleWordAccess;
19494 let CextOpcode = "S2_storerd";
19495 let InputType = "imm";
19496 let BaseOpcode = "S2_storerd_io";
19497 let isExtendable = 1;
19498 let opExtendable = 2;
19499 let isExtentSigned = 0;
19500 let opExtentBits = 9;
19501 let opExtentAlign = 3;
19503 def S2_pstorerdf_pi : HInst<
19504 (outs IntRegs:$Rx32),
19505 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19506 "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
19507 tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
19508 let Inst{2-2} = 0b1;
19509 let Inst{7-7} = 0b0;
19510 let Inst{13-13} = 0b1;
19511 let Inst{31-21} = 0b10101011110;
19512 let isPredicated = 1;
19513 let isPredicatedFalse = 1;
19514 let addrMode = PostInc;
19515 let accessSize = DoubleWordAccess;
19517 let CextOpcode = "S2_storerd";
19518 let BaseOpcode = "S2_storerd_pi";
19519 let Constraints = "$Rx32 = $Rx32in";
19521 def S2_pstorerdf_zomap : HInst<
19523 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19524 "if (!$Pv4) memd($Rs32) = $Rtt32",
19525 tc_8b15472a, TypeMAPPING> {
19527 let isCodeGenOnly = 1;
19529 def S2_pstorerdfnew_pi : HInst<
19530 (outs IntRegs:$Rx32),
19531 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19532 "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
19533 tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
19534 let Inst{2-2} = 0b1;
19535 let Inst{7-7} = 0b1;
19536 let Inst{13-13} = 0b1;
19537 let Inst{31-21} = 0b10101011110;
19538 let isPredicated = 1;
19539 let isPredicatedFalse = 1;
19540 let addrMode = PostInc;
19541 let accessSize = DoubleWordAccess;
19542 let isPredicatedNew = 1;
19544 let CextOpcode = "S2_storerd";
19545 let BaseOpcode = "S2_storerd_pi";
19546 let Constraints = "$Rx32 = $Rx32in";
19548 def S2_pstorerdt_io : HInst<
19550 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19551 "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
19552 tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19553 let Inst{2-2} = 0b0;
19554 let Inst{31-21} = 0b01000000110;
19555 let isPredicated = 1;
19556 let addrMode = BaseImmOffset;
19557 let accessSize = DoubleWordAccess;
19559 let CextOpcode = "S2_storerd";
19560 let InputType = "imm";
19561 let BaseOpcode = "S2_storerd_io";
19562 let isExtendable = 1;
19563 let opExtendable = 2;
19564 let isExtentSigned = 0;
19565 let opExtentBits = 9;
19566 let opExtentAlign = 3;
19568 def S2_pstorerdt_pi : HInst<
19569 (outs IntRegs:$Rx32),
19570 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19571 "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
19572 tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
19573 let Inst{2-2} = 0b0;
19574 let Inst{7-7} = 0b0;
19575 let Inst{13-13} = 0b1;
19576 let Inst{31-21} = 0b10101011110;
19577 let isPredicated = 1;
19578 let addrMode = PostInc;
19579 let accessSize = DoubleWordAccess;
19581 let CextOpcode = "S2_storerd";
19582 let BaseOpcode = "S2_storerd_pi";
19583 let Constraints = "$Rx32 = $Rx32in";
19585 def S2_pstorerdt_zomap : HInst<
19587 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19588 "if ($Pv4) memd($Rs32) = $Rtt32",
19589 tc_8b15472a, TypeMAPPING> {
19591 let isCodeGenOnly = 1;
19593 def S2_pstorerdtnew_pi : HInst<
19594 (outs IntRegs:$Rx32),
19595 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19596 "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
19597 tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
19598 let Inst{2-2} = 0b0;
19599 let Inst{7-7} = 0b1;
19600 let Inst{13-13} = 0b1;
19601 let Inst{31-21} = 0b10101011110;
19602 let isPredicated = 1;
19603 let addrMode = PostInc;
19604 let accessSize = DoubleWordAccess;
19605 let isPredicatedNew = 1;
19607 let CextOpcode = "S2_storerd";
19608 let BaseOpcode = "S2_storerd_pi";
19609 let Constraints = "$Rx32 = $Rx32in";
19611 def S2_pstorerff_io : HInst<
19613 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19614 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
19615 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19616 let Inst{2-2} = 0b0;
19617 let Inst{31-21} = 0b01000100011;
19618 let isPredicated = 1;
19619 let isPredicatedFalse = 1;
19620 let addrMode = BaseImmOffset;
19621 let accessSize = HalfWordAccess;
19623 let CextOpcode = "S2_storerf";
19624 let InputType = "imm";
19625 let BaseOpcode = "S2_storerf_io";
19626 let isExtendable = 1;
19627 let opExtendable = 2;
19628 let isExtentSigned = 0;
19629 let opExtentBits = 7;
19630 let opExtentAlign = 1;
19632 def S2_pstorerff_pi : HInst<
19633 (outs IntRegs:$Rx32),
19634 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19635 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
19636 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
19637 let Inst{2-2} = 0b1;
19638 let Inst{7-7} = 0b0;
19639 let Inst{13-13} = 0b1;
19640 let Inst{31-21} = 0b10101011011;
19641 let isPredicated = 1;
19642 let isPredicatedFalse = 1;
19643 let addrMode = PostInc;
19644 let accessSize = HalfWordAccess;
19646 let CextOpcode = "S2_storerf";
19647 let BaseOpcode = "S2_storerf_pi";
19648 let Constraints = "$Rx32 = $Rx32in";
19650 def S2_pstorerff_zomap : HInst<
19652 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19653 "if (!$Pv4) memh($Rs32) = $Rt32.h",
19654 tc_8b15472a, TypeMAPPING> {
19656 let isCodeGenOnly = 1;
19658 def S2_pstorerffnew_pi : HInst<
19659 (outs IntRegs:$Rx32),
19660 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19661 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
19662 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
19663 let Inst{2-2} = 0b1;
19664 let Inst{7-7} = 0b1;
19665 let Inst{13-13} = 0b1;
19666 let Inst{31-21} = 0b10101011011;
19667 let isPredicated = 1;
19668 let isPredicatedFalse = 1;
19669 let addrMode = PostInc;
19670 let accessSize = HalfWordAccess;
19671 let isPredicatedNew = 1;
19673 let CextOpcode = "S2_storerf";
19674 let BaseOpcode = "S2_storerf_pi";
19675 let Constraints = "$Rx32 = $Rx32in";
19677 def S2_pstorerft_io : HInst<
19679 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19680 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
19681 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19682 let Inst{2-2} = 0b0;
19683 let Inst{31-21} = 0b01000000011;
19684 let isPredicated = 1;
19685 let addrMode = BaseImmOffset;
19686 let accessSize = HalfWordAccess;
19688 let CextOpcode = "S2_storerf";
19689 let InputType = "imm";
19690 let BaseOpcode = "S2_storerf_io";
19691 let isExtendable = 1;
19692 let opExtendable = 2;
19693 let isExtentSigned = 0;
19694 let opExtentBits = 7;
19695 let opExtentAlign = 1;
19697 def S2_pstorerft_pi : HInst<
19698 (outs IntRegs:$Rx32),
19699 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19700 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
19701 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
19702 let Inst{2-2} = 0b0;
19703 let Inst{7-7} = 0b0;
19704 let Inst{13-13} = 0b1;
19705 let Inst{31-21} = 0b10101011011;
19706 let isPredicated = 1;
19707 let addrMode = PostInc;
19708 let accessSize = HalfWordAccess;
19710 let CextOpcode = "S2_storerf";
19711 let BaseOpcode = "S2_storerf_pi";
19712 let Constraints = "$Rx32 = $Rx32in";
19714 def S2_pstorerft_zomap : HInst<
19716 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19717 "if ($Pv4) memh($Rs32) = $Rt32.h",
19718 tc_8b15472a, TypeMAPPING> {
19720 let isCodeGenOnly = 1;
19722 def S2_pstorerftnew_pi : HInst<
19723 (outs IntRegs:$Rx32),
19724 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19725 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
19726 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
19727 let Inst{2-2} = 0b0;
19728 let Inst{7-7} = 0b1;
19729 let Inst{13-13} = 0b1;
19730 let Inst{31-21} = 0b10101011011;
19731 let isPredicated = 1;
19732 let addrMode = PostInc;
19733 let accessSize = HalfWordAccess;
19734 let isPredicatedNew = 1;
19736 let CextOpcode = "S2_storerf";
19737 let BaseOpcode = "S2_storerf_pi";
19738 let Constraints = "$Rx32 = $Rx32in";
19740 def S2_pstorerhf_io : HInst<
19742 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19743 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
19744 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19745 let Inst{2-2} = 0b0;
19746 let Inst{31-21} = 0b01000100010;
19747 let isPredicated = 1;
19748 let isPredicatedFalse = 1;
19749 let addrMode = BaseImmOffset;
19750 let accessSize = HalfWordAccess;
19752 let CextOpcode = "S2_storerh";
19753 let InputType = "imm";
19754 let BaseOpcode = "S2_storerh_io";
19755 let isNVStorable = 1;
19756 let isExtendable = 1;
19757 let opExtendable = 2;
19758 let isExtentSigned = 0;
19759 let opExtentBits = 7;
19760 let opExtentAlign = 1;
19762 def S2_pstorerhf_pi : HInst<
19763 (outs IntRegs:$Rx32),
19764 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19765 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
19766 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
19767 let Inst{2-2} = 0b1;
19768 let Inst{7-7} = 0b0;
19769 let Inst{13-13} = 0b1;
19770 let Inst{31-21} = 0b10101011010;
19771 let isPredicated = 1;
19772 let isPredicatedFalse = 1;
19773 let addrMode = PostInc;
19774 let accessSize = HalfWordAccess;
19776 let BaseOpcode = "S2_storerh_pi";
19777 let isNVStorable = 1;
19778 let Constraints = "$Rx32 = $Rx32in";
19780 def S2_pstorerhf_zomap : HInst<
19782 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19783 "if (!$Pv4) memh($Rs32) = $Rt32",
19784 tc_8b15472a, TypeMAPPING> {
19786 let isCodeGenOnly = 1;
19788 def S2_pstorerhfnew_pi : HInst<
19789 (outs IntRegs:$Rx32),
19790 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19791 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
19792 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
19793 let Inst{2-2} = 0b1;
19794 let Inst{7-7} = 0b1;
19795 let Inst{13-13} = 0b1;
19796 let Inst{31-21} = 0b10101011010;
19797 let isPredicated = 1;
19798 let isPredicatedFalse = 1;
19799 let addrMode = PostInc;
19800 let accessSize = HalfWordAccess;
19801 let isPredicatedNew = 1;
19803 let BaseOpcode = "S2_storerh_pi";
19804 let isNVStorable = 1;
19805 let Constraints = "$Rx32 = $Rx32in";
19807 def S2_pstorerhnewf_io : HInst<
19809 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
19810 "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
19811 tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
19812 let Inst{2-2} = 0b0;
19813 let Inst{12-11} = 0b01;
19814 let Inst{31-21} = 0b01000100101;
19815 let isPredicated = 1;
19816 let isPredicatedFalse = 1;
19817 let addrMode = BaseImmOffset;
19818 let accessSize = HalfWordAccess;
19820 let isNewValue = 1;
19821 let isRestrictNoSlot1Store = 1;
19823 let CextOpcode = "S2_storerh";
19824 let InputType = "imm";
19825 let BaseOpcode = "S2_storerh_io";
19826 let isExtendable = 1;
19827 let opExtendable = 2;
19828 let isExtentSigned = 0;
19829 let opExtentBits = 7;
19830 let opExtentAlign = 1;
19831 let opNewValue = 3;
19833 def S2_pstorerhnewf_pi : HInst<
19834 (outs IntRegs:$Rx32),
19835 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
19836 "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
19837 tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
19838 let Inst{2-2} = 0b1;
19839 let Inst{7-7} = 0b0;
19840 let Inst{13-11} = 0b101;
19841 let Inst{31-21} = 0b10101011101;
19842 let isPredicated = 1;
19843 let isPredicatedFalse = 1;
19844 let addrMode = PostInc;
19845 let accessSize = HalfWordAccess;
19847 let isNewValue = 1;
19848 let isRestrictNoSlot1Store = 1;
19850 let CextOpcode = "S2_storerh";
19851 let BaseOpcode = "S2_storerh_pi";
19852 let opNewValue = 4;
19853 let Constraints = "$Rx32 = $Rx32in";
19855 def S2_pstorerhnewf_zomap : HInst<
19857 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19858 "if (!$Pv4) memh($Rs32) = $Nt8.new",
19859 tc_594ab548, TypeMAPPING> {
19861 let isCodeGenOnly = 1;
19862 let opNewValue = 2;
19864 def S2_pstorerhnewfnew_pi : HInst<
19865 (outs IntRegs:$Rx32),
19866 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
19867 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
19868 tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
19869 let Inst{2-2} = 0b1;
19870 let Inst{7-7} = 0b1;
19871 let Inst{13-11} = 0b101;
19872 let Inst{31-21} = 0b10101011101;
19873 let isPredicated = 1;
19874 let isPredicatedFalse = 1;
19875 let addrMode = PostInc;
19876 let accessSize = HalfWordAccess;
19878 let isPredicatedNew = 1;
19879 let isNewValue = 1;
19880 let isRestrictNoSlot1Store = 1;
19882 let CextOpcode = "S2_storerh";
19883 let BaseOpcode = "S2_storerh_pi";
19884 let opNewValue = 4;
19885 let Constraints = "$Rx32 = $Rx32in";
19887 def S2_pstorerhnewt_io : HInst<
19889 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
19890 "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
19891 tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
19892 let Inst{2-2} = 0b0;
19893 let Inst{12-11} = 0b01;
19894 let Inst{31-21} = 0b01000000101;
19895 let isPredicated = 1;
19896 let addrMode = BaseImmOffset;
19897 let accessSize = HalfWordAccess;
19899 let isNewValue = 1;
19900 let isRestrictNoSlot1Store = 1;
19902 let CextOpcode = "S2_storerh";
19903 let InputType = "imm";
19904 let BaseOpcode = "S2_storerh_io";
19905 let isExtendable = 1;
19906 let opExtendable = 2;
19907 let isExtentSigned = 0;
19908 let opExtentBits = 7;
19909 let opExtentAlign = 1;
19910 let opNewValue = 3;
19912 def S2_pstorerhnewt_pi : HInst<
19913 (outs IntRegs:$Rx32),
19914 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
19915 "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
19916 tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
19917 let Inst{2-2} = 0b0;
19918 let Inst{7-7} = 0b0;
19919 let Inst{13-11} = 0b101;
19920 let Inst{31-21} = 0b10101011101;
19921 let isPredicated = 1;
19922 let addrMode = PostInc;
19923 let accessSize = HalfWordAccess;
19925 let isNewValue = 1;
19926 let isRestrictNoSlot1Store = 1;
19928 let CextOpcode = "S2_storerh";
19929 let BaseOpcode = "S2_storerh_pi";
19930 let opNewValue = 4;
19931 let Constraints = "$Rx32 = $Rx32in";
19933 def S2_pstorerhnewt_zomap : HInst<
19935 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19936 "if ($Pv4) memh($Rs32) = $Nt8.new",
19937 tc_594ab548, TypeMAPPING> {
19939 let isCodeGenOnly = 1;
19940 let opNewValue = 2;
19942 def S2_pstorerhnewtnew_pi : HInst<
19943 (outs IntRegs:$Rx32),
19944 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
19945 "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
19946 tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
19947 let Inst{2-2} = 0b0;
19948 let Inst{7-7} = 0b1;
19949 let Inst{13-11} = 0b101;
19950 let Inst{31-21} = 0b10101011101;
19951 let isPredicated = 1;
19952 let addrMode = PostInc;
19953 let accessSize = HalfWordAccess;
19955 let isPredicatedNew = 1;
19956 let isNewValue = 1;
19957 let isRestrictNoSlot1Store = 1;
19959 let CextOpcode = "S2_storerh";
19960 let BaseOpcode = "S2_storerh_pi";
19961 let opNewValue = 4;
19962 let Constraints = "$Rx32 = $Rx32in";
19964 def S2_pstorerht_io : HInst<
19966 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19967 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
19968 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19969 let Inst{2-2} = 0b0;
19970 let Inst{31-21} = 0b01000000010;
19971 let isPredicated = 1;
19972 let addrMode = BaseImmOffset;
19973 let accessSize = HalfWordAccess;
19975 let CextOpcode = "S2_storerh";
19976 let InputType = "imm";
19977 let BaseOpcode = "S2_storerh_io";
19978 let isNVStorable = 1;
19979 let isExtendable = 1;
19980 let opExtendable = 2;
19981 let isExtentSigned = 0;
19982 let opExtentBits = 7;
19983 let opExtentAlign = 1;
19985 def S2_pstorerht_pi : HInst<
19986 (outs IntRegs:$Rx32),
19987 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19988 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
19989 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
19990 let Inst{2-2} = 0b0;
19991 let Inst{7-7} = 0b0;
19992 let Inst{13-13} = 0b1;
19993 let Inst{31-21} = 0b10101011010;
19994 let isPredicated = 1;
19995 let addrMode = PostInc;
19996 let accessSize = HalfWordAccess;
19998 let BaseOpcode = "S2_storerh_pi";
19999 let isNVStorable = 1;
20000 let Constraints = "$Rx32 = $Rx32in";
20002 def S2_pstorerht_zomap : HInst<
20004 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20005 "if ($Pv4) memh($Rs32) = $Rt32",
20006 tc_8b15472a, TypeMAPPING> {
20008 let isCodeGenOnly = 1;
20010 def S2_pstorerhtnew_pi : HInst<
20011 (outs IntRegs:$Rx32),
20012 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20013 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20014 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
20015 let Inst{2-2} = 0b0;
20016 let Inst{7-7} = 0b1;
20017 let Inst{13-13} = 0b1;
20018 let Inst{31-21} = 0b10101011010;
20019 let isPredicated = 1;
20020 let addrMode = PostInc;
20021 let accessSize = HalfWordAccess;
20022 let isPredicatedNew = 1;
20024 let BaseOpcode = "S2_storerh_pi";
20025 let isNVStorable = 1;
20026 let Constraints = "$Rx32 = $Rx32in";
20028 def S2_pstorerif_io : HInst<
20030 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20031 "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20032 tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
20033 let Inst{2-2} = 0b0;
20034 let Inst{31-21} = 0b01000100100;
20035 let isPredicated = 1;
20036 let isPredicatedFalse = 1;
20037 let addrMode = BaseImmOffset;
20038 let accessSize = WordAccess;
20040 let CextOpcode = "S2_storeri";
20041 let InputType = "imm";
20042 let BaseOpcode = "S2_storeri_io";
20043 let isNVStorable = 1;
20044 let isExtendable = 1;
20045 let opExtendable = 2;
20046 let isExtentSigned = 0;
20047 let opExtentBits = 8;
20048 let opExtentAlign = 2;
20050 def S2_pstorerif_pi : HInst<
20051 (outs IntRegs:$Rx32),
20052 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20053 "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20054 tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
20055 let Inst{2-2} = 0b1;
20056 let Inst{7-7} = 0b0;
20057 let Inst{13-13} = 0b1;
20058 let Inst{31-21} = 0b10101011100;
20059 let isPredicated = 1;
20060 let isPredicatedFalse = 1;
20061 let addrMode = PostInc;
20062 let accessSize = WordAccess;
20064 let BaseOpcode = "S2_storeri_pi";
20065 let isNVStorable = 1;
20066 let Constraints = "$Rx32 = $Rx32in";
20068 def S2_pstorerif_zomap : HInst<
20070 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20071 "if (!$Pv4) memw($Rs32) = $Rt32",
20072 tc_8b15472a, TypeMAPPING> {
20074 let isCodeGenOnly = 1;
20076 def S2_pstorerifnew_pi : HInst<
20077 (outs IntRegs:$Rx32),
20078 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20079 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20080 tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
20081 let Inst{2-2} = 0b1;
20082 let Inst{7-7} = 0b1;
20083 let Inst{13-13} = 0b1;
20084 let Inst{31-21} = 0b10101011100;
20085 let isPredicated = 1;
20086 let isPredicatedFalse = 1;
20087 let addrMode = PostInc;
20088 let accessSize = WordAccess;
20089 let isPredicatedNew = 1;
20091 let CextOpcode = "S2_storeri";
20092 let BaseOpcode = "S2_storeri_pi";
20093 let isNVStorable = 1;
20094 let Constraints = "$Rx32 = $Rx32in";
20096 def S2_pstorerinewf_io : HInst<
20098 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20099 "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20100 tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20101 let Inst{2-2} = 0b0;
20102 let Inst{12-11} = 0b10;
20103 let Inst{31-21} = 0b01000100101;
20104 let isPredicated = 1;
20105 let isPredicatedFalse = 1;
20106 let addrMode = BaseImmOffset;
20107 let accessSize = WordAccess;
20109 let isNewValue = 1;
20110 let isRestrictNoSlot1Store = 1;
20112 let CextOpcode = "S2_storeri";
20113 let InputType = "imm";
20114 let BaseOpcode = "S2_storeri_io";
20115 let isExtendable = 1;
20116 let opExtendable = 2;
20117 let isExtentSigned = 0;
20118 let opExtentBits = 8;
20119 let opExtentAlign = 2;
20120 let opNewValue = 3;
20122 def S2_pstorerinewf_pi : HInst<
20123 (outs IntRegs:$Rx32),
20124 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20125 "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20126 tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
20127 let Inst{2-2} = 0b1;
20128 let Inst{7-7} = 0b0;
20129 let Inst{13-11} = 0b110;
20130 let Inst{31-21} = 0b10101011101;
20131 let isPredicated = 1;
20132 let isPredicatedFalse = 1;
20133 let addrMode = PostInc;
20134 let accessSize = WordAccess;
20136 let isNewValue = 1;
20137 let isRestrictNoSlot1Store = 1;
20139 let CextOpcode = "S2_storeri";
20140 let BaseOpcode = "S2_storeri_pi";
20141 let opNewValue = 4;
20142 let Constraints = "$Rx32 = $Rx32in";
20144 def S2_pstorerinewf_zomap : HInst<
20146 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20147 "if (!$Pv4) memw($Rs32) = $Nt8.new",
20148 tc_594ab548, TypeMAPPING> {
20150 let isCodeGenOnly = 1;
20151 let opNewValue = 2;
20153 def S2_pstorerinewfnew_pi : HInst<
20154 (outs IntRegs:$Rx32),
20155 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20156 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20157 tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
20158 let Inst{2-2} = 0b1;
20159 let Inst{7-7} = 0b1;
20160 let Inst{13-11} = 0b110;
20161 let Inst{31-21} = 0b10101011101;
20162 let isPredicated = 1;
20163 let isPredicatedFalse = 1;
20164 let addrMode = PostInc;
20165 let accessSize = WordAccess;
20167 let isPredicatedNew = 1;
20168 let isNewValue = 1;
20169 let isRestrictNoSlot1Store = 1;
20171 let CextOpcode = "S2_storeri";
20172 let BaseOpcode = "S2_storeri_pi";
20173 let opNewValue = 4;
20174 let Constraints = "$Rx32 = $Rx32in";
20176 def S2_pstorerinewt_io : HInst<
20178 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20179 "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20180 tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20181 let Inst{2-2} = 0b0;
20182 let Inst{12-11} = 0b10;
20183 let Inst{31-21} = 0b01000000101;
20184 let isPredicated = 1;
20185 let addrMode = BaseImmOffset;
20186 let accessSize = WordAccess;
20188 let isNewValue = 1;
20189 let isRestrictNoSlot1Store = 1;
20191 let CextOpcode = "S2_storeri";
20192 let InputType = "imm";
20193 let BaseOpcode = "S2_storeri_io";
20194 let isExtendable = 1;
20195 let opExtendable = 2;
20196 let isExtentSigned = 0;
20197 let opExtentBits = 8;
20198 let opExtentAlign = 2;
20199 let opNewValue = 3;
20201 def S2_pstorerinewt_pi : HInst<
20202 (outs IntRegs:$Rx32),
20203 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20204 "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20205 tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
20206 let Inst{2-2} = 0b0;
20207 let Inst{7-7} = 0b0;
20208 let Inst{13-11} = 0b110;
20209 let Inst{31-21} = 0b10101011101;
20210 let isPredicated = 1;
20211 let addrMode = PostInc;
20212 let accessSize = WordAccess;
20214 let isNewValue = 1;
20215 let isRestrictNoSlot1Store = 1;
20217 let CextOpcode = "S2_storeri";
20218 let BaseOpcode = "S2_storeri_pi";
20219 let opNewValue = 4;
20220 let Constraints = "$Rx32 = $Rx32in";
20222 def S2_pstorerinewt_zomap : HInst<
20224 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20225 "if ($Pv4) memw($Rs32) = $Nt8.new",
20226 tc_594ab548, TypeMAPPING> {
20228 let isCodeGenOnly = 1;
20229 let opNewValue = 2;
20231 def S2_pstorerinewtnew_pi : HInst<
20232 (outs IntRegs:$Rx32),
20233 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20234 "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20235 tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
20236 let Inst{2-2} = 0b0;
20237 let Inst{7-7} = 0b1;
20238 let Inst{13-11} = 0b110;
20239 let Inst{31-21} = 0b10101011101;
20240 let isPredicated = 1;
20241 let addrMode = PostInc;
20242 let accessSize = WordAccess;
20244 let isPredicatedNew = 1;
20245 let isNewValue = 1;
20246 let isRestrictNoSlot1Store = 1;
20248 let CextOpcode = "S2_storeri";
20249 let BaseOpcode = "S2_storeri_pi";
20250 let opNewValue = 4;
20251 let Constraints = "$Rx32 = $Rx32in";
20253 def S2_pstorerit_io : HInst<
20255 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20256 "if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20257 tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
20258 let Inst{2-2} = 0b0;
20259 let Inst{31-21} = 0b01000000100;
20260 let isPredicated = 1;
20261 let addrMode = BaseImmOffset;
20262 let accessSize = WordAccess;
20264 let CextOpcode = "S2_storeri";
20265 let InputType = "imm";
20266 let BaseOpcode = "S2_storeri_io";
20267 let isNVStorable = 1;
20268 let isExtendable = 1;
20269 let opExtendable = 2;
20270 let isExtentSigned = 0;
20271 let opExtentBits = 8;
20272 let opExtentAlign = 2;
20274 def S2_pstorerit_pi : HInst<
20275 (outs IntRegs:$Rx32),
20276 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20277 "if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20278 tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
20279 let Inst{2-2} = 0b0;
20280 let Inst{7-7} = 0b0;
20281 let Inst{13-13} = 0b1;
20282 let Inst{31-21} = 0b10101011100;
20283 let isPredicated = 1;
20284 let addrMode = PostInc;
20285 let accessSize = WordAccess;
20287 let BaseOpcode = "S2_storeri_pi";
20288 let isNVStorable = 1;
20289 let Constraints = "$Rx32 = $Rx32in";
20291 def S2_pstorerit_zomap : HInst<
20293 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20294 "if ($Pv4) memw($Rs32) = $Rt32",
20295 tc_8b15472a, TypeMAPPING> {
20297 let isCodeGenOnly = 1;
20299 def S2_pstoreritnew_pi : HInst<
20300 (outs IntRegs:$Rx32),
20301 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20302 "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20303 tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
20304 let Inst{2-2} = 0b0;
20305 let Inst{7-7} = 0b1;
20306 let Inst{13-13} = 0b1;
20307 let Inst{31-21} = 0b10101011100;
20308 let isPredicated = 1;
20309 let addrMode = PostInc;
20310 let accessSize = WordAccess;
20311 let isPredicatedNew = 1;
20313 let BaseOpcode = "S2_storeri_pi";
20314 let isNVStorable = 1;
20315 let Constraints = "$Rx32 = $Rx32in";
20317 def S2_setbit_i : HInst<
20318 (outs IntRegs:$Rd32),
20319 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
20320 "$Rd32 = setbit($Rs32,#$Ii)",
20321 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
20322 let Inst{7-5} = 0b000;
20323 let Inst{13-13} = 0b0;
20324 let Inst{31-21} = 0b10001100110;
20325 let hasNewValue = 1;
20326 let opNewValue = 0;
20328 def S2_setbit_r : HInst<
20329 (outs IntRegs:$Rd32),
20330 (ins IntRegs:$Rs32, IntRegs:$Rt32),
20331 "$Rd32 = setbit($Rs32,$Rt32)",
20332 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
20333 let Inst{7-5} = 0b000;
20334 let Inst{13-13} = 0b0;
20335 let Inst{31-21} = 0b11000110100;
20336 let hasNewValue = 1;
20337 let opNewValue = 0;
20339 def S2_shuffeb : HInst<
20340 (outs DoubleRegs:$Rdd32),
20341 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20342 "$Rdd32 = shuffeb($Rss32,$Rtt32)",
20343 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
20344 let Inst{7-5} = 0b010;
20345 let Inst{13-13} = 0b0;
20346 let Inst{31-21} = 0b11000001000;
20348 def S2_shuffeh : HInst<
20349 (outs DoubleRegs:$Rdd32),
20350 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20351 "$Rdd32 = shuffeh($Rss32,$Rtt32)",
20352 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
20353 let Inst{7-5} = 0b110;
20354 let Inst{13-13} = 0b0;
20355 let Inst{31-21} = 0b11000001000;
20357 def S2_shuffob : HInst<
20358 (outs DoubleRegs:$Rdd32),
20359 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20360 "$Rdd32 = shuffob($Rtt32,$Rss32)",
20361 tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
20362 let Inst{7-5} = 0b100;
20363 let Inst{13-13} = 0b0;
20364 let Inst{31-21} = 0b11000001000;
20366 def S2_shuffoh : HInst<
20367 (outs DoubleRegs:$Rdd32),
20368 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20369 "$Rdd32 = shuffoh($Rtt32,$Rss32)",
20370 tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
20371 let Inst{7-5} = 0b000;
20372 let Inst{13-13} = 0b0;
20373 let Inst{31-21} = 0b11000001100;
20375 def S2_storerb_io : HInst<
20377 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20378 "memb($Rs32+#$Ii) = $Rt32",
20379 tc_05b6c987, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20380 let Inst{24-21} = 0b1000;
20381 let Inst{31-27} = 0b10100;
20382 let addrMode = BaseImmOffset;
20383 let accessSize = ByteAccess;
20385 let CextOpcode = "S2_storerb";
20386 let InputType = "imm";
20387 let BaseOpcode = "S2_storerb_io";
20388 let isPredicable = 1;
20389 let isNVStorable = 1;
20390 let isExtendable = 1;
20391 let opExtendable = 1;
20392 let isExtentSigned = 1;
20393 let opExtentBits = 11;
20394 let opExtentAlign = 0;
20396 def S2_storerb_pbr : HInst<
20397 (outs IntRegs:$Rx32),
20398 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20399 "memb($Rx32++$Mu2:brev) = $Rt32",
20400 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
20401 let Inst{7-0} = 0b00000000;
20402 let Inst{31-21} = 0b10101111000;
20403 let accessSize = ByteAccess;
20405 let BaseOpcode = "S2_storerb_pbr";
20406 let isNVStorable = 1;
20407 let Constraints = "$Rx32 = $Rx32in";
20409 def S2_storerb_pci : HInst<
20410 (outs IntRegs:$Rx32),
20411 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20412 "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20413 tc_9fdb5406, TypeST>, Enc_b15941, AddrModeRel {
20414 let Inst{2-0} = 0b000;
20415 let Inst{7-7} = 0b0;
20416 let Inst{31-21} = 0b10101001000;
20417 let addrMode = PostInc;
20418 let accessSize = ByteAccess;
20421 let BaseOpcode = "S2_storerb_pci";
20422 let isNVStorable = 1;
20423 let Constraints = "$Rx32 = $Rx32in";
20425 def S2_storerb_pcr : HInst<
20426 (outs IntRegs:$Rx32),
20427 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20428 "memb($Rx32++I:circ($Mu2)) = $Rt32",
20429 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
20430 let Inst{7-0} = 0b00000010;
20431 let Inst{31-21} = 0b10101001000;
20432 let addrMode = PostInc;
20433 let accessSize = ByteAccess;
20436 let BaseOpcode = "S2_storerb_pcr";
20437 let isNVStorable = 1;
20438 let Constraints = "$Rx32 = $Rx32in";
20440 def S2_storerb_pi : HInst<
20441 (outs IntRegs:$Rx32),
20442 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20443 "memb($Rx32++#$Ii) = $Rt32",
20444 tc_f86c328a, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20445 let Inst{2-0} = 0b000;
20446 let Inst{7-7} = 0b0;
20447 let Inst{13-13} = 0b0;
20448 let Inst{31-21} = 0b10101011000;
20449 let addrMode = PostInc;
20450 let accessSize = ByteAccess;
20452 let CextOpcode = "S2_storerb";
20453 let BaseOpcode = "S2_storerb_pi";
20454 let isPredicable = 1;
20455 let isNVStorable = 1;
20456 let Constraints = "$Rx32 = $Rx32in";
20458 def S2_storerb_pr : HInst<
20459 (outs IntRegs:$Rx32),
20460 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20461 "memb($Rx32++$Mu2) = $Rt32",
20462 tc_f86c328a, TypeST>, Enc_d5c73f {
20463 let Inst{7-0} = 0b00000000;
20464 let Inst{31-21} = 0b10101101000;
20465 let addrMode = PostInc;
20466 let accessSize = ByteAccess;
20468 let isNVStorable = 1;
20469 let Constraints = "$Rx32 = $Rx32in";
20471 def S2_storerb_zomap : HInst<
20473 (ins IntRegs:$Rs32, IntRegs:$Rt32),
20474 "memb($Rs32) = $Rt32",
20475 tc_05b6c987, TypeMAPPING> {
20477 let isCodeGenOnly = 1;
20479 def S2_storerbgp : HInst<
20481 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
20482 "memb(gp+#$Ii) = $Rt32",
20483 tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
20484 let Inst{24-21} = 0b0000;
20485 let Inst{31-27} = 0b01001;
20486 let accessSize = ByteAccess;
20489 let BaseOpcode = "S2_storerbabs";
20490 let isPredicable = 1;
20491 let isNVStorable = 1;
20492 let opExtendable = 0;
20493 let isExtentSigned = 0;
20494 let opExtentBits = 16;
20495 let opExtentAlign = 0;
20497 def S2_storerbnew_io : HInst<
20499 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
20500 "memb($Rs32+#$Ii) = $Nt8.new",
20501 tc_f7dd9c9f, TypeST>, Enc_4df4e9, AddrModeRel {
20502 let Inst{12-11} = 0b00;
20503 let Inst{24-21} = 0b1101;
20504 let Inst{31-27} = 0b10100;
20505 let addrMode = BaseImmOffset;
20506 let accessSize = ByteAccess;
20508 let isNewValue = 1;
20509 let isRestrictNoSlot1Store = 1;
20511 let CextOpcode = "S2_storerb";
20512 let InputType = "imm";
20513 let BaseOpcode = "S2_storerb_io";
20514 let isPredicable = 1;
20515 let isExtendable = 1;
20516 let opExtendable = 1;
20517 let isExtentSigned = 1;
20518 let opExtentBits = 11;
20519 let opExtentAlign = 0;
20520 let opNewValue = 2;
20522 def S2_storerbnew_pbr : HInst<
20523 (outs IntRegs:$Rx32),
20524 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20525 "memb($Rx32++$Mu2:brev) = $Nt8.new",
20526 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
20527 let Inst{7-0} = 0b00000000;
20528 let Inst{12-11} = 0b00;
20529 let Inst{31-21} = 0b10101111101;
20530 let accessSize = ByteAccess;
20532 let isNewValue = 1;
20533 let isRestrictNoSlot1Store = 1;
20535 let BaseOpcode = "S2_storerb_pbr";
20536 let opNewValue = 3;
20537 let Constraints = "$Rx32 = $Rx32in";
20539 def S2_storerbnew_pci : HInst<
20540 (outs IntRegs:$Rx32),
20541 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
20542 "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
20543 tc_9d5941c7, TypeST>, Enc_96ce4f, AddrModeRel {
20544 let Inst{2-0} = 0b000;
20545 let Inst{7-7} = 0b0;
20546 let Inst{12-11} = 0b00;
20547 let Inst{31-21} = 0b10101001101;
20548 let addrMode = PostInc;
20549 let accessSize = ByteAccess;
20551 let isNewValue = 1;
20552 let isRestrictNoSlot1Store = 1;
20555 let BaseOpcode = "S2_storerb_pci";
20556 let opNewValue = 4;
20557 let Constraints = "$Rx32 = $Rx32in";
20559 def S2_storerbnew_pcr : HInst<
20560 (outs IntRegs:$Rx32),
20561 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20562 "memb($Rx32++I:circ($Mu2)) = $Nt8.new",
20563 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
20564 let Inst{7-0} = 0b00000010;
20565 let Inst{12-11} = 0b00;
20566 let Inst{31-21} = 0b10101001101;
20567 let addrMode = PostInc;
20568 let accessSize = ByteAccess;
20570 let isNewValue = 1;
20571 let isRestrictNoSlot1Store = 1;
20574 let BaseOpcode = "S2_storerb_pcr";
20575 let opNewValue = 3;
20576 let Constraints = "$Rx32 = $Rx32in";
20578 def S2_storerbnew_pi : HInst<
20579 (outs IntRegs:$Rx32),
20580 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
20581 "memb($Rx32++#$Ii) = $Nt8.new",
20582 tc_e7d02c66, TypeST>, Enc_c7cd90, AddrModeRel {
20583 let Inst{2-0} = 0b000;
20584 let Inst{7-7} = 0b0;
20585 let Inst{13-11} = 0b000;
20586 let Inst{31-21} = 0b10101011101;
20587 let addrMode = PostInc;
20588 let accessSize = ByteAccess;
20590 let isNewValue = 1;
20591 let isRestrictNoSlot1Store = 1;
20593 let BaseOpcode = "S2_storerb_pi";
20594 let isPredicable = 1;
20595 let isNVStorable = 1;
20596 let opNewValue = 3;
20597 let Constraints = "$Rx32 = $Rx32in";
20599 def S2_storerbnew_pr : HInst<
20600 (outs IntRegs:$Rx32),
20601 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20602 "memb($Rx32++$Mu2) = $Nt8.new",
20603 tc_e7d02c66, TypeST>, Enc_8dbe85 {
20604 let Inst{7-0} = 0b00000000;
20605 let Inst{12-11} = 0b00;
20606 let Inst{31-21} = 0b10101101101;
20607 let addrMode = PostInc;
20608 let accessSize = ByteAccess;
20610 let isNewValue = 1;
20611 let isRestrictNoSlot1Store = 1;
20613 let opNewValue = 3;
20614 let Constraints = "$Rx32 = $Rx32in";
20616 def S2_storerbnew_zomap : HInst<
20618 (ins IntRegs:$Rs32, IntRegs:$Nt8),
20619 "memb($Rs32) = $Nt8.new",
20620 tc_f7dd9c9f, TypeMAPPING> {
20622 let isCodeGenOnly = 1;
20623 let opNewValue = 1;
20625 def S2_storerbnewgp : HInst<
20627 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
20628 "memb(gp+#$Ii) = $Nt8.new",
20629 tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
20630 let Inst{12-11} = 0b00;
20631 let Inst{24-21} = 0b0101;
20632 let Inst{31-27} = 0b01001;
20633 let accessSize = ByteAccess;
20635 let isNewValue = 1;
20636 let isRestrictNoSlot1Store = 1;
20639 let BaseOpcode = "S2_storerbabs";
20640 let isPredicable = 1;
20641 let opExtendable = 0;
20642 let isExtentSigned = 0;
20643 let opExtentBits = 16;
20644 let opExtentAlign = 0;
20645 let opNewValue = 1;
20647 def S2_storerd_io : HInst<
20649 (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
20650 "memd($Rs32+#$Ii) = $Rtt32",
20651 tc_05b6c987, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
20652 let Inst{24-21} = 0b1110;
20653 let Inst{31-27} = 0b10100;
20654 let addrMode = BaseImmOffset;
20655 let accessSize = DoubleWordAccess;
20657 let CextOpcode = "S2_storerd";
20658 let InputType = "imm";
20659 let BaseOpcode = "S2_storerd_io";
20660 let isPredicable = 1;
20661 let isExtendable = 1;
20662 let opExtendable = 1;
20663 let isExtentSigned = 1;
20664 let opExtentBits = 14;
20665 let opExtentAlign = 3;
20667 def S2_storerd_pbr : HInst<
20668 (outs IntRegs:$Rx32),
20669 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20670 "memd($Rx32++$Mu2:brev) = $Rtt32",
20671 tc_f86c328a, TypeST>, Enc_928ca1 {
20672 let Inst{7-0} = 0b00000000;
20673 let Inst{31-21} = 0b10101111110;
20674 let accessSize = DoubleWordAccess;
20676 let Constraints = "$Rx32 = $Rx32in";
20678 def S2_storerd_pci : HInst<
20679 (outs IntRegs:$Rx32),
20680 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20681 "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
20682 tc_9fdb5406, TypeST>, Enc_395cc4 {
20683 let Inst{2-0} = 0b000;
20684 let Inst{7-7} = 0b0;
20685 let Inst{31-21} = 0b10101001110;
20686 let addrMode = PostInc;
20687 let accessSize = DoubleWordAccess;
20690 let Constraints = "$Rx32 = $Rx32in";
20692 def S2_storerd_pcr : HInst<
20693 (outs IntRegs:$Rx32),
20694 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20695 "memd($Rx32++I:circ($Mu2)) = $Rtt32",
20696 tc_f86c328a, TypeST>, Enc_928ca1 {
20697 let Inst{7-0} = 0b00000010;
20698 let Inst{31-21} = 0b10101001110;
20699 let addrMode = PostInc;
20700 let accessSize = DoubleWordAccess;
20703 let Constraints = "$Rx32 = $Rx32in";
20705 def S2_storerd_pi : HInst<
20706 (outs IntRegs:$Rx32),
20707 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20708 "memd($Rx32++#$Ii) = $Rtt32",
20709 tc_f86c328a, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
20710 let Inst{2-0} = 0b000;
20711 let Inst{7-7} = 0b0;
20712 let Inst{13-13} = 0b0;
20713 let Inst{31-21} = 0b10101011110;
20714 let addrMode = PostInc;
20715 let accessSize = DoubleWordAccess;
20717 let CextOpcode = "S2_storerd";
20718 let BaseOpcode = "S2_storerd_pi";
20719 let isPredicable = 1;
20720 let Constraints = "$Rx32 = $Rx32in";
20722 def S2_storerd_pr : HInst<
20723 (outs IntRegs:$Rx32),
20724 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20725 "memd($Rx32++$Mu2) = $Rtt32",
20726 tc_f86c328a, TypeST>, Enc_928ca1 {
20727 let Inst{7-0} = 0b00000000;
20728 let Inst{31-21} = 0b10101101110;
20729 let addrMode = PostInc;
20730 let accessSize = DoubleWordAccess;
20732 let Constraints = "$Rx32 = $Rx32in";
20734 def S2_storerd_zomap : HInst<
20736 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
20737 "memd($Rs32) = $Rtt32",
20738 tc_05b6c987, TypeMAPPING> {
20740 let isCodeGenOnly = 1;
20742 def S2_storerdgp : HInst<
20744 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20745 "memd(gp+#$Ii) = $Rtt32",
20746 tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
20747 let Inst{24-21} = 0b0110;
20748 let Inst{31-27} = 0b01001;
20749 let accessSize = DoubleWordAccess;
20752 let BaseOpcode = "S2_storerdabs";
20753 let isPredicable = 1;
20754 let opExtendable = 0;
20755 let isExtentSigned = 0;
20756 let opExtentBits = 19;
20757 let opExtentAlign = 3;
20759 def S2_storerf_io : HInst<
20761 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
20762 "memh($Rs32+#$Ii) = $Rt32.h",
20763 tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
20764 let Inst{24-21} = 0b1011;
20765 let Inst{31-27} = 0b10100;
20766 let addrMode = BaseImmOffset;
20767 let accessSize = HalfWordAccess;
20769 let CextOpcode = "S2_storerf";
20770 let InputType = "imm";
20771 let BaseOpcode = "S2_storerf_io";
20772 let isPredicable = 1;
20773 let isExtendable = 1;
20774 let opExtendable = 1;
20775 let isExtentSigned = 1;
20776 let opExtentBits = 12;
20777 let opExtentAlign = 1;
20779 def S2_storerf_pbr : HInst<
20780 (outs IntRegs:$Rx32),
20781 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20782 "memh($Rx32++$Mu2:brev) = $Rt32.h",
20783 tc_f86c328a, TypeST>, Enc_d5c73f {
20784 let Inst{7-0} = 0b00000000;
20785 let Inst{31-21} = 0b10101111011;
20786 let accessSize = HalfWordAccess;
20788 let Constraints = "$Rx32 = $Rx32in";
20790 def S2_storerf_pci : HInst<
20791 (outs IntRegs:$Rx32),
20792 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20793 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
20794 tc_9fdb5406, TypeST>, Enc_935d9b {
20795 let Inst{2-0} = 0b000;
20796 let Inst{7-7} = 0b0;
20797 let Inst{31-21} = 0b10101001011;
20798 let addrMode = PostInc;
20799 let accessSize = HalfWordAccess;
20802 let Constraints = "$Rx32 = $Rx32in";
20804 def S2_storerf_pcr : HInst<
20805 (outs IntRegs:$Rx32),
20806 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20807 "memh($Rx32++I:circ($Mu2)) = $Rt32.h",
20808 tc_f86c328a, TypeST>, Enc_d5c73f {
20809 let Inst{7-0} = 0b00000010;
20810 let Inst{31-21} = 0b10101001011;
20811 let addrMode = PostInc;
20812 let accessSize = HalfWordAccess;
20815 let Constraints = "$Rx32 = $Rx32in";
20817 def S2_storerf_pi : HInst<
20818 (outs IntRegs:$Rx32),
20819 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20820 "memh($Rx32++#$Ii) = $Rt32.h",
20821 tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
20822 let Inst{2-0} = 0b000;
20823 let Inst{7-7} = 0b0;
20824 let Inst{13-13} = 0b0;
20825 let Inst{31-21} = 0b10101011011;
20826 let addrMode = PostInc;
20827 let accessSize = HalfWordAccess;
20829 let CextOpcode = "S2_storerf";
20830 let BaseOpcode = "S2_storerf_pi";
20831 let isPredicable = 1;
20832 let Constraints = "$Rx32 = $Rx32in";
20834 def S2_storerf_pr : HInst<
20835 (outs IntRegs:$Rx32),
20836 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20837 "memh($Rx32++$Mu2) = $Rt32.h",
20838 tc_f86c328a, TypeST>, Enc_d5c73f {
20839 let Inst{7-0} = 0b00000000;
20840 let Inst{31-21} = 0b10101101011;
20841 let addrMode = PostInc;
20842 let accessSize = HalfWordAccess;
20844 let Constraints = "$Rx32 = $Rx32in";
20846 def S2_storerf_zomap : HInst<
20848 (ins IntRegs:$Rs32, IntRegs:$Rt32),
20849 "memh($Rs32) = $Rt32.h",
20850 tc_05b6c987, TypeMAPPING> {
20852 let isCodeGenOnly = 1;
20854 def S2_storerfgp : HInst<
20856 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
20857 "memh(gp+#$Ii) = $Rt32.h",
20858 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
20859 let Inst{24-21} = 0b0011;
20860 let Inst{31-27} = 0b01001;
20861 let accessSize = HalfWordAccess;
20864 let BaseOpcode = "S2_storerfabs";
20865 let isPredicable = 1;
20866 let opExtendable = 0;
20867 let isExtentSigned = 0;
20868 let opExtentBits = 17;
20869 let opExtentAlign = 1;
20871 def S2_storerh_io : HInst<
20873 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
20874 "memh($Rs32+#$Ii) = $Rt32",
20875 tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
20876 let Inst{24-21} = 0b1010;
20877 let Inst{31-27} = 0b10100;
20878 let addrMode = BaseImmOffset;
20879 let accessSize = HalfWordAccess;
20881 let CextOpcode = "S2_storerh";
20882 let InputType = "imm";
20883 let BaseOpcode = "S2_storerh_io";
20884 let isPredicable = 1;
20885 let isNVStorable = 1;
20886 let isExtendable = 1;
20887 let opExtendable = 1;
20888 let isExtentSigned = 1;
20889 let opExtentBits = 12;
20890 let opExtentAlign = 1;
20892 def S2_storerh_pbr : HInst<
20893 (outs IntRegs:$Rx32),
20894 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20895 "memh($Rx32++$Mu2:brev) = $Rt32",
20896 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
20897 let Inst{7-0} = 0b00000000;
20898 let Inst{31-21} = 0b10101111010;
20899 let accessSize = HalfWordAccess;
20901 let BaseOpcode = "S2_storerh_pbr";
20902 let isNVStorable = 1;
20903 let Constraints = "$Rx32 = $Rx32in";
20905 def S2_storerh_pci : HInst<
20906 (outs IntRegs:$Rx32),
20907 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20908 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20909 tc_9fdb5406, TypeST>, Enc_935d9b, AddrModeRel {
20910 let Inst{2-0} = 0b000;
20911 let Inst{7-7} = 0b0;
20912 let Inst{31-21} = 0b10101001010;
20913 let addrMode = PostInc;
20914 let accessSize = HalfWordAccess;
20917 let BaseOpcode = "S2_storerh_pci";
20918 let isNVStorable = 1;
20919 let Constraints = "$Rx32 = $Rx32in";
20921 def S2_storerh_pcr : HInst<
20922 (outs IntRegs:$Rx32),
20923 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20924 "memh($Rx32++I:circ($Mu2)) = $Rt32",
20925 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
20926 let Inst{7-0} = 0b00000010;
20927 let Inst{31-21} = 0b10101001010;
20928 let addrMode = PostInc;
20929 let accessSize = HalfWordAccess;
20932 let BaseOpcode = "S2_storerh_pcr";
20933 let isNVStorable = 1;
20934 let Constraints = "$Rx32 = $Rx32in";
20936 def S2_storerh_pi : HInst<
20937 (outs IntRegs:$Rx32),
20938 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20939 "memh($Rx32++#$Ii) = $Rt32",
20940 tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
20941 let Inst{2-0} = 0b000;
20942 let Inst{7-7} = 0b0;
20943 let Inst{13-13} = 0b0;
20944 let Inst{31-21} = 0b10101011010;
20945 let addrMode = PostInc;
20946 let accessSize = HalfWordAccess;
20948 let CextOpcode = "S2_storerh";
20949 let BaseOpcode = "S2_storerh_pi";
20950 let isPredicable = 1;
20951 let isNVStorable = 1;
20952 let Constraints = "$Rx32 = $Rx32in";
20954 def S2_storerh_pr : HInst<
20955 (outs IntRegs:$Rx32),
20956 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20957 "memh($Rx32++$Mu2) = $Rt32",
20958 tc_f86c328a, TypeST>, Enc_d5c73f {
20959 let Inst{7-0} = 0b00000000;
20960 let Inst{31-21} = 0b10101101010;
20961 let addrMode = PostInc;
20962 let accessSize = HalfWordAccess;
20964 let isNVStorable = 1;
20965 let Constraints = "$Rx32 = $Rx32in";
20967 def S2_storerh_zomap : HInst<
20969 (ins IntRegs:$Rs32, IntRegs:$Rt32),
20970 "memh($Rs32) = $Rt32",
20971 tc_05b6c987, TypeMAPPING> {
20973 let isCodeGenOnly = 1;
20975 def S2_storerhgp : HInst<
20977 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
20978 "memh(gp+#$Ii) = $Rt32",
20979 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
20980 let Inst{24-21} = 0b0010;
20981 let Inst{31-27} = 0b01001;
20982 let accessSize = HalfWordAccess;
20985 let BaseOpcode = "S2_storerhabs";
20986 let isPredicable = 1;
20987 let isNVStorable = 1;
20988 let opExtendable = 0;
20989 let isExtentSigned = 0;
20990 let opExtentBits = 17;
20991 let opExtentAlign = 1;
20993 def S2_storerhnew_io : HInst<
20995 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
20996 "memh($Rs32+#$Ii) = $Nt8.new",
20997 tc_f7dd9c9f, TypeST>, Enc_0d8870, AddrModeRel {
20998 let Inst{12-11} = 0b01;
20999 let Inst{24-21} = 0b1101;
21000 let Inst{31-27} = 0b10100;
21001 let addrMode = BaseImmOffset;
21002 let accessSize = HalfWordAccess;
21004 let isNewValue = 1;
21005 let isRestrictNoSlot1Store = 1;
21007 let CextOpcode = "S2_storerh";
21008 let InputType = "imm";
21009 let BaseOpcode = "S2_storerh_io";
21010 let isPredicable = 1;
21011 let isExtendable = 1;
21012 let opExtendable = 1;
21013 let isExtentSigned = 1;
21014 let opExtentBits = 12;
21015 let opExtentAlign = 1;
21016 let opNewValue = 2;
21018 def S2_storerhnew_pbr : HInst<
21019 (outs IntRegs:$Rx32),
21020 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21021 "memh($Rx32++$Mu2:brev) = $Nt8.new",
21022 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
21023 let Inst{7-0} = 0b00000000;
21024 let Inst{12-11} = 0b01;
21025 let Inst{31-21} = 0b10101111101;
21026 let accessSize = HalfWordAccess;
21028 let isNewValue = 1;
21029 let isRestrictNoSlot1Store = 1;
21031 let BaseOpcode = "S2_storerh_pbr";
21032 let opNewValue = 3;
21033 let Constraints = "$Rx32 = $Rx32in";
21035 def S2_storerhnew_pci : HInst<
21036 (outs IntRegs:$Rx32),
21037 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21038 "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21039 tc_9d5941c7, TypeST>, Enc_91b9fe, AddrModeRel {
21040 let Inst{2-0} = 0b000;
21041 let Inst{7-7} = 0b0;
21042 let Inst{12-11} = 0b01;
21043 let Inst{31-21} = 0b10101001101;
21044 let addrMode = PostInc;
21045 let accessSize = HalfWordAccess;
21047 let isNewValue = 1;
21048 let isRestrictNoSlot1Store = 1;
21051 let BaseOpcode = "S2_storerh_pci";
21052 let opNewValue = 4;
21053 let Constraints = "$Rx32 = $Rx32in";
21055 def S2_storerhnew_pcr : HInst<
21056 (outs IntRegs:$Rx32),
21057 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21058 "memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21059 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
21060 let Inst{7-0} = 0b00000010;
21061 let Inst{12-11} = 0b01;
21062 let Inst{31-21} = 0b10101001101;
21063 let addrMode = PostInc;
21064 let accessSize = HalfWordAccess;
21066 let isNewValue = 1;
21067 let isRestrictNoSlot1Store = 1;
21070 let BaseOpcode = "S2_storerh_pcr";
21071 let opNewValue = 3;
21072 let Constraints = "$Rx32 = $Rx32in";
21074 def S2_storerhnew_pi : HInst<
21075 (outs IntRegs:$Rx32),
21076 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21077 "memh($Rx32++#$Ii) = $Nt8.new",
21078 tc_e7d02c66, TypeST>, Enc_e26546, AddrModeRel {
21079 let Inst{2-0} = 0b000;
21080 let Inst{7-7} = 0b0;
21081 let Inst{13-11} = 0b001;
21082 let Inst{31-21} = 0b10101011101;
21083 let addrMode = PostInc;
21084 let accessSize = HalfWordAccess;
21086 let isNewValue = 1;
21087 let isRestrictNoSlot1Store = 1;
21089 let BaseOpcode = "S2_storerh_pi";
21090 let isNVStorable = 1;
21091 let isPredicable = 1;
21092 let opNewValue = 3;
21093 let Constraints = "$Rx32 = $Rx32in";
21095 def S2_storerhnew_pr : HInst<
21096 (outs IntRegs:$Rx32),
21097 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21098 "memh($Rx32++$Mu2) = $Nt8.new",
21099 tc_e7d02c66, TypeST>, Enc_8dbe85 {
21100 let Inst{7-0} = 0b00000000;
21101 let Inst{12-11} = 0b01;
21102 let Inst{31-21} = 0b10101101101;
21103 let addrMode = PostInc;
21104 let accessSize = HalfWordAccess;
21106 let isNewValue = 1;
21107 let isRestrictNoSlot1Store = 1;
21109 let opNewValue = 3;
21110 let Constraints = "$Rx32 = $Rx32in";
21112 def S2_storerhnew_zomap : HInst<
21114 (ins IntRegs:$Rs32, IntRegs:$Nt8),
21115 "memh($Rs32) = $Nt8.new",
21116 tc_f7dd9c9f, TypeMAPPING> {
21118 let isCodeGenOnly = 1;
21119 let opNewValue = 1;
21121 def S2_storerhnewgp : HInst<
21123 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
21124 "memh(gp+#$Ii) = $Nt8.new",
21125 tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21126 let Inst{12-11} = 0b01;
21127 let Inst{24-21} = 0b0101;
21128 let Inst{31-27} = 0b01001;
21129 let accessSize = HalfWordAccess;
21131 let isNewValue = 1;
21132 let isRestrictNoSlot1Store = 1;
21135 let BaseOpcode = "S2_storerhabs";
21136 let isPredicable = 1;
21137 let opExtendable = 0;
21138 let isExtentSigned = 0;
21139 let opExtentBits = 17;
21140 let opExtentAlign = 1;
21141 let opNewValue = 1;
21143 def S2_storeri_io : HInst<
21145 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21146 "memw($Rs32+#$Ii) = $Rt32",
21147 tc_05b6c987, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21148 let Inst{24-21} = 0b1100;
21149 let Inst{31-27} = 0b10100;
21150 let addrMode = BaseImmOffset;
21151 let accessSize = WordAccess;
21153 let CextOpcode = "S2_storeri";
21154 let InputType = "imm";
21155 let BaseOpcode = "S2_storeri_io";
21156 let isPredicable = 1;
21157 let isNVStorable = 1;
21158 let isExtendable = 1;
21159 let opExtendable = 1;
21160 let isExtentSigned = 1;
21161 let opExtentBits = 13;
21162 let opExtentAlign = 2;
21164 def S2_storeri_pbr : HInst<
21165 (outs IntRegs:$Rx32),
21166 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21167 "memw($Rx32++$Mu2:brev) = $Rt32",
21168 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
21169 let Inst{7-0} = 0b00000000;
21170 let Inst{31-21} = 0b10101111100;
21171 let accessSize = WordAccess;
21173 let BaseOpcode = "S2_storeri_pbr";
21174 let isNVStorable = 1;
21175 let Constraints = "$Rx32 = $Rx32in";
21177 def S2_storeri_pci : HInst<
21178 (outs IntRegs:$Rx32),
21179 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21180 "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21181 tc_9fdb5406, TypeST>, Enc_79b8c8, AddrModeRel {
21182 let Inst{2-0} = 0b000;
21183 let Inst{7-7} = 0b0;
21184 let Inst{31-21} = 0b10101001100;
21185 let addrMode = PostInc;
21186 let accessSize = WordAccess;
21189 let BaseOpcode = "S2_storeri_pci";
21190 let isNVStorable = 1;
21191 let Constraints = "$Rx32 = $Rx32in";
21193 def S2_storeri_pcr : HInst<
21194 (outs IntRegs:$Rx32),
21195 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21196 "memw($Rx32++I:circ($Mu2)) = $Rt32",
21197 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
21198 let Inst{7-0} = 0b00000010;
21199 let Inst{31-21} = 0b10101001100;
21200 let addrMode = PostInc;
21201 let accessSize = WordAccess;
21204 let BaseOpcode = "S2_storeri_pcr";
21205 let isNVStorable = 1;
21206 let Constraints = "$Rx32 = $Rx32in";
21208 def S2_storeri_pi : HInst<
21209 (outs IntRegs:$Rx32),
21210 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21211 "memw($Rx32++#$Ii) = $Rt32",
21212 tc_f86c328a, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21213 let Inst{2-0} = 0b000;
21214 let Inst{7-7} = 0b0;
21215 let Inst{13-13} = 0b0;
21216 let Inst{31-21} = 0b10101011100;
21217 let addrMode = PostInc;
21218 let accessSize = WordAccess;
21220 let CextOpcode = "S2_storeri";
21221 let BaseOpcode = "S2_storeri_pi";
21222 let isPredicable = 1;
21223 let isNVStorable = 1;
21224 let Constraints = "$Rx32 = $Rx32in";
21226 def S2_storeri_pr : HInst<
21227 (outs IntRegs:$Rx32),
21228 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21229 "memw($Rx32++$Mu2) = $Rt32",
21230 tc_f86c328a, TypeST>, Enc_d5c73f {
21231 let Inst{7-0} = 0b00000000;
21232 let Inst{31-21} = 0b10101101100;
21233 let addrMode = PostInc;
21234 let accessSize = WordAccess;
21236 let isNVStorable = 1;
21237 let Constraints = "$Rx32 = $Rx32in";
21239 def S2_storeri_zomap : HInst<
21241 (ins IntRegs:$Rs32, IntRegs:$Rt32),
21242 "memw($Rs32) = $Rt32",
21243 tc_05b6c987, TypeMAPPING> {
21245 let isCodeGenOnly = 1;
21247 def S2_storerigp : HInst<
21249 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
21250 "memw(gp+#$Ii) = $Rt32",
21251 tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
21252 let Inst{24-21} = 0b0100;
21253 let Inst{31-27} = 0b01001;
21254 let accessSize = WordAccess;
21257 let BaseOpcode = "S2_storeriabs";
21258 let isPredicable = 1;
21259 let isNVStorable = 1;
21260 let opExtendable = 0;
21261 let isExtentSigned = 0;
21262 let opExtentBits = 18;
21263 let opExtentAlign = 2;
21265 def S2_storerinew_io : HInst<
21267 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21268 "memw($Rs32+#$Ii) = $Nt8.new",
21269 tc_f7dd9c9f, TypeST>, Enc_690862, AddrModeRel {
21270 let Inst{12-11} = 0b10;
21271 let Inst{24-21} = 0b1101;
21272 let Inst{31-27} = 0b10100;
21273 let addrMode = BaseImmOffset;
21274 let accessSize = WordAccess;
21276 let isNewValue = 1;
21277 let isRestrictNoSlot1Store = 1;
21279 let CextOpcode = "S2_storeri";
21280 let InputType = "imm";
21281 let BaseOpcode = "S2_storeri_io";
21282 let isPredicable = 1;
21283 let isExtendable = 1;
21284 let opExtendable = 1;
21285 let isExtentSigned = 1;
21286 let opExtentBits = 13;
21287 let opExtentAlign = 2;
21288 let opNewValue = 2;
21290 def S2_storerinew_pbr : HInst<
21291 (outs IntRegs:$Rx32),
21292 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21293 "memw($Rx32++$Mu2:brev) = $Nt8.new",
21294 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
21295 let Inst{7-0} = 0b00000000;
21296 let Inst{12-11} = 0b10;
21297 let Inst{31-21} = 0b10101111101;
21298 let accessSize = WordAccess;
21300 let isNewValue = 1;
21301 let isRestrictNoSlot1Store = 1;
21303 let BaseOpcode = "S2_storeri_pbr";
21304 let opNewValue = 3;
21305 let Constraints = "$Rx32 = $Rx32in";
21307 def S2_storerinew_pci : HInst<
21308 (outs IntRegs:$Rx32),
21309 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21310 "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21311 tc_9d5941c7, TypeST>, Enc_3f97c8, AddrModeRel {
21312 let Inst{2-0} = 0b000;
21313 let Inst{7-7} = 0b0;
21314 let Inst{12-11} = 0b10;
21315 let Inst{31-21} = 0b10101001101;
21316 let addrMode = PostInc;
21317 let accessSize = WordAccess;
21319 let isNewValue = 1;
21320 let isRestrictNoSlot1Store = 1;
21323 let BaseOpcode = "S2_storeri_pci";
21324 let opNewValue = 4;
21325 let Constraints = "$Rx32 = $Rx32in";
21327 def S2_storerinew_pcr : HInst<
21328 (outs IntRegs:$Rx32),
21329 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21330 "memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21331 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
21332 let Inst{7-0} = 0b00000010;
21333 let Inst{12-11} = 0b10;
21334 let Inst{31-21} = 0b10101001101;
21335 let addrMode = PostInc;
21336 let accessSize = WordAccess;
21338 let isNewValue = 1;
21339 let isRestrictNoSlot1Store = 1;
21342 let BaseOpcode = "S2_storeri_pcr";
21343 let opNewValue = 3;
21344 let Constraints = "$Rx32 = $Rx32in";
21346 def S2_storerinew_pi : HInst<
21347 (outs IntRegs:$Rx32),
21348 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21349 "memw($Rx32++#$Ii) = $Nt8.new",
21350 tc_e7d02c66, TypeST>, Enc_223005, AddrModeRel {
21351 let Inst{2-0} = 0b000;
21352 let Inst{7-7} = 0b0;
21353 let Inst{13-11} = 0b010;
21354 let Inst{31-21} = 0b10101011101;
21355 let addrMode = PostInc;
21356 let accessSize = WordAccess;
21358 let isNewValue = 1;
21359 let isRestrictNoSlot1Store = 1;
21361 let BaseOpcode = "S2_storeri_pi";
21362 let isPredicable = 1;
21363 let opNewValue = 3;
21364 let Constraints = "$Rx32 = $Rx32in";
21366 def S2_storerinew_pr : HInst<
21367 (outs IntRegs:$Rx32),
21368 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21369 "memw($Rx32++$Mu2) = $Nt8.new",
21370 tc_e7d02c66, TypeST>, Enc_8dbe85 {
21371 let Inst{7-0} = 0b00000000;
21372 let Inst{12-11} = 0b10;
21373 let Inst{31-21} = 0b10101101101;
21374 let addrMode = PostInc;
21375 let accessSize = WordAccess;
21377 let isNewValue = 1;
21378 let isRestrictNoSlot1Store = 1;
21380 let opNewValue = 3;
21381 let Constraints = "$Rx32 = $Rx32in";
21383 def S2_storerinew_zomap : HInst<
21385 (ins IntRegs:$Rs32, IntRegs:$Nt8),
21386 "memw($Rs32) = $Nt8.new",
21387 tc_f7dd9c9f, TypeMAPPING> {
21389 let isCodeGenOnly = 1;
21390 let opNewValue = 1;
21392 def S2_storerinewgp : HInst<
21394 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
21395 "memw(gp+#$Ii) = $Nt8.new",
21396 tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21397 let Inst{12-11} = 0b10;
21398 let Inst{24-21} = 0b0101;
21399 let Inst{31-27} = 0b01001;
21400 let accessSize = WordAccess;
21402 let isNewValue = 1;
21403 let isRestrictNoSlot1Store = 1;
21406 let BaseOpcode = "S2_storeriabs";
21407 let isPredicable = 1;
21408 let opExtendable = 0;
21409 let isExtentSigned = 0;
21410 let opExtentBits = 18;
21411 let opExtentAlign = 2;
21412 let opNewValue = 1;
21414 def S2_storew_locked : HInst<
21415 (outs PredRegs:$Pd4),
21416 (ins IntRegs:$Rs32, IntRegs:$Rt32),
21417 "memw_locked($Rs32,$Pd4) = $Rt32",
21418 tc_1372bca1, TypeST>, Enc_c2b48e {
21419 let Inst{7-2} = 0b000000;
21420 let Inst{13-13} = 0b0;
21421 let Inst{31-21} = 0b10100000101;
21422 let accessSize = WordAccess;
21423 let isPredicateLate = 1;
21427 def S2_svsathb : HInst<
21428 (outs IntRegs:$Rd32),
21429 (ins IntRegs:$Rs32),
21430 "$Rd32 = vsathb($Rs32)",
21431 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
21432 let Inst{13-5} = 0b000000000;
21433 let Inst{31-21} = 0b10001100100;
21434 let hasNewValue = 1;
21435 let opNewValue = 0;
21436 let Defs = [USR_OVF];
21438 def S2_svsathub : HInst<
21439 (outs IntRegs:$Rd32),
21440 (ins IntRegs:$Rs32),
21441 "$Rd32 = vsathub($Rs32)",
21442 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
21443 let Inst{13-5} = 0b000000010;
21444 let Inst{31-21} = 0b10001100100;
21445 let hasNewValue = 1;
21446 let opNewValue = 0;
21447 let Defs = [USR_OVF];
21449 def S2_tableidxb : HInst<
21450 (outs IntRegs:$Rx32),
21451 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21452 "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
21453 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
21454 let Inst{31-22} = 0b1000011100;
21455 let hasNewValue = 1;
21456 let opNewValue = 0;
21457 let prefersSlot3 = 1;
21458 let Constraints = "$Rx32 = $Rx32in";
21460 def S2_tableidxb_goodsyntax : HInst<
21461 (outs IntRegs:$Rx32),
21462 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21463 "$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
21464 tc_87735c3b, TypeS_2op> {
21465 let hasNewValue = 1;
21466 let opNewValue = 0;
21468 let isCodeGenOnly = 1;
21469 let Constraints = "$Rx32 = $Rx32in";
21471 def S2_tableidxd : HInst<
21472 (outs IntRegs:$Rx32),
21473 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21474 "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
21475 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
21476 let Inst{31-22} = 0b1000011111;
21477 let hasNewValue = 1;
21478 let opNewValue = 0;
21479 let prefersSlot3 = 1;
21480 let Constraints = "$Rx32 = $Rx32in";
21482 def S2_tableidxd_goodsyntax : HInst<
21483 (outs IntRegs:$Rx32),
21484 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21485 "$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
21486 tc_87735c3b, TypeS_2op> {
21487 let hasNewValue = 1;
21488 let opNewValue = 0;
21490 let Constraints = "$Rx32 = $Rx32in";
21492 def S2_tableidxh : HInst<
21493 (outs IntRegs:$Rx32),
21494 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21495 "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
21496 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
21497 let Inst{31-22} = 0b1000011101;
21498 let hasNewValue = 1;
21499 let opNewValue = 0;
21500 let prefersSlot3 = 1;
21501 let Constraints = "$Rx32 = $Rx32in";
21503 def S2_tableidxh_goodsyntax : HInst<
21504 (outs IntRegs:$Rx32),
21505 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21506 "$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
21507 tc_87735c3b, TypeS_2op> {
21508 let hasNewValue = 1;
21509 let opNewValue = 0;
21511 let Constraints = "$Rx32 = $Rx32in";
21513 def S2_tableidxw : HInst<
21514 (outs IntRegs:$Rx32),
21515 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21516 "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
21517 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
21518 let Inst{31-22} = 0b1000011110;
21519 let hasNewValue = 1;
21520 let opNewValue = 0;
21521 let prefersSlot3 = 1;
21522 let Constraints = "$Rx32 = $Rx32in";
21524 def S2_tableidxw_goodsyntax : HInst<
21525 (outs IntRegs:$Rx32),
21526 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21527 "$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
21528 tc_87735c3b, TypeS_2op> {
21529 let hasNewValue = 1;
21530 let opNewValue = 0;
21532 let Constraints = "$Rx32 = $Rx32in";
21534 def S2_togglebit_i : HInst<
21535 (outs IntRegs:$Rd32),
21536 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
21537 "$Rd32 = togglebit($Rs32,#$Ii)",
21538 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
21539 let Inst{7-5} = 0b010;
21540 let Inst{13-13} = 0b0;
21541 let Inst{31-21} = 0b10001100110;
21542 let hasNewValue = 1;
21543 let opNewValue = 0;
21545 def S2_togglebit_r : HInst<
21546 (outs IntRegs:$Rd32),
21547 (ins IntRegs:$Rs32, IntRegs:$Rt32),
21548 "$Rd32 = togglebit($Rs32,$Rt32)",
21549 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
21550 let Inst{7-5} = 0b100;
21551 let Inst{13-13} = 0b0;
21552 let Inst{31-21} = 0b11000110100;
21553 let hasNewValue = 1;
21554 let opNewValue = 0;
21556 def S2_tstbit_i : HInst<
21557 (outs PredRegs:$Pd4),
21558 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
21559 "$Pd4 = tstbit($Rs32,#$Ii)",
21560 tc_7a830544, TypeS_2op>, Enc_83ee64 {
21561 let Inst{7-2} = 0b000000;
21562 let Inst{13-13} = 0b0;
21563 let Inst{31-21} = 0b10000101000;
21565 def S2_tstbit_r : HInst<
21566 (outs PredRegs:$Pd4),
21567 (ins IntRegs:$Rs32, IntRegs:$Rt32),
21568 "$Pd4 = tstbit($Rs32,$Rt32)",
21569 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
21570 let Inst{7-2} = 0b000000;
21571 let Inst{13-13} = 0b0;
21572 let Inst{31-21} = 0b11000111000;
21574 def S2_valignib : HInst<
21575 (outs DoubleRegs:$Rdd32),
21576 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
21577 "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
21578 tc_f8eeed7a, TypeS_3op>, Enc_729ff7 {
21579 let Inst{13-13} = 0b0;
21580 let Inst{31-21} = 0b11000000000;
21582 def S2_valignrb : HInst<
21583 (outs DoubleRegs:$Rdd32),
21584 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
21585 "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
21586 tc_f8eeed7a, TypeS_3op>, Enc_8c6530 {
21587 let Inst{7-7} = 0b0;
21588 let Inst{13-13} = 0b0;
21589 let Inst{31-21} = 0b11000010000;
21591 def S2_vcnegh : HInst<
21592 (outs DoubleRegs:$Rdd32),
21593 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
21594 "$Rdd32 = vcnegh($Rss32,$Rt32)",
21595 tc_b44c6e2a, TypeS_3op>, Enc_927852 {
21596 let Inst{7-5} = 0b010;
21597 let Inst{13-13} = 0b0;
21598 let Inst{31-21} = 0b11000011110;
21599 let prefersSlot3 = 1;
21600 let Defs = [USR_OVF];
21602 def S2_vcrotate : HInst<
21603 (outs DoubleRegs:$Rdd32),
21604 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
21605 "$Rdd32 = vcrotate($Rss32,$Rt32)",
21606 tc_2b6f77c6, TypeS_3op>, Enc_927852 {
21607 let Inst{7-5} = 0b000;
21608 let Inst{13-13} = 0b0;
21609 let Inst{31-21} = 0b11000011110;
21610 let prefersSlot3 = 1;
21611 let Defs = [USR_OVF];
21613 def S2_vrcnegh : HInst<
21614 (outs DoubleRegs:$Rxx32),
21615 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
21616 "$Rxx32 += vrcnegh($Rss32,$Rt32)",
21617 tc_e913dc32, TypeS_3op>, Enc_1aa186 {
21618 let Inst{7-5} = 0b111;
21619 let Inst{13-13} = 0b1;
21620 let Inst{31-21} = 0b11001011001;
21621 let prefersSlot3 = 1;
21622 let Constraints = "$Rxx32 = $Rxx32in";
21624 def S2_vrndpackwh : HInst<
21625 (outs IntRegs:$Rd32),
21626 (ins DoubleRegs:$Rss32),
21627 "$Rd32 = vrndwh($Rss32)",
21628 tc_d088982c, TypeS_2op>, Enc_90cd8b {
21629 let Inst{13-5} = 0b000000100;
21630 let Inst{31-21} = 0b10001000100;
21631 let hasNewValue = 1;
21632 let opNewValue = 0;
21633 let prefersSlot3 = 1;
21635 def S2_vrndpackwhs : HInst<
21636 (outs IntRegs:$Rd32),
21637 (ins DoubleRegs:$Rss32),
21638 "$Rd32 = vrndwh($Rss32):sat",
21639 tc_c2f7d806, TypeS_2op>, Enc_90cd8b {
21640 let Inst{13-5} = 0b000000110;
21641 let Inst{31-21} = 0b10001000100;
21642 let hasNewValue = 1;
21643 let opNewValue = 0;
21644 let prefersSlot3 = 1;
21645 let Defs = [USR_OVF];
21647 def S2_vsathb : HInst<
21648 (outs IntRegs:$Rd32),
21649 (ins DoubleRegs:$Rss32),
21650 "$Rd32 = vsathb($Rss32)",
21651 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21652 let Inst{13-5} = 0b000000110;
21653 let Inst{31-21} = 0b10001000000;
21654 let hasNewValue = 1;
21655 let opNewValue = 0;
21656 let Defs = [USR_OVF];
21658 def S2_vsathb_nopack : HInst<
21659 (outs DoubleRegs:$Rdd32),
21660 (ins DoubleRegs:$Rss32),
21661 "$Rdd32 = vsathb($Rss32)",
21662 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
21663 let Inst{13-5} = 0b000000111;
21664 let Inst{31-21} = 0b10000000000;
21665 let Defs = [USR_OVF];
21667 def S2_vsathub : HInst<
21668 (outs IntRegs:$Rd32),
21669 (ins DoubleRegs:$Rss32),
21670 "$Rd32 = vsathub($Rss32)",
21671 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21672 let Inst{13-5} = 0b000000000;
21673 let Inst{31-21} = 0b10001000000;
21674 let hasNewValue = 1;
21675 let opNewValue = 0;
21676 let Defs = [USR_OVF];
21678 def S2_vsathub_nopack : HInst<
21679 (outs DoubleRegs:$Rdd32),
21680 (ins DoubleRegs:$Rss32),
21681 "$Rdd32 = vsathub($Rss32)",
21682 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
21683 let Inst{13-5} = 0b000000100;
21684 let Inst{31-21} = 0b10000000000;
21685 let Defs = [USR_OVF];
21687 def S2_vsatwh : HInst<
21688 (outs IntRegs:$Rd32),
21689 (ins DoubleRegs:$Rss32),
21690 "$Rd32 = vsatwh($Rss32)",
21691 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21692 let Inst{13-5} = 0b000000010;
21693 let Inst{31-21} = 0b10001000000;
21694 let hasNewValue = 1;
21695 let opNewValue = 0;
21696 let Defs = [USR_OVF];
21698 def S2_vsatwh_nopack : HInst<
21699 (outs DoubleRegs:$Rdd32),
21700 (ins DoubleRegs:$Rss32),
21701 "$Rdd32 = vsatwh($Rss32)",
21702 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
21703 let Inst{13-5} = 0b000000110;
21704 let Inst{31-21} = 0b10000000000;
21705 let Defs = [USR_OVF];
21707 def S2_vsatwuh : HInst<
21708 (outs IntRegs:$Rd32),
21709 (ins DoubleRegs:$Rss32),
21710 "$Rd32 = vsatwuh($Rss32)",
21711 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21712 let Inst{13-5} = 0b000000100;
21713 let Inst{31-21} = 0b10001000000;
21714 let hasNewValue = 1;
21715 let opNewValue = 0;
21716 let Defs = [USR_OVF];
21718 def S2_vsatwuh_nopack : HInst<
21719 (outs DoubleRegs:$Rdd32),
21720 (ins DoubleRegs:$Rss32),
21721 "$Rdd32 = vsatwuh($Rss32)",
21722 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
21723 let Inst{13-5} = 0b000000101;
21724 let Inst{31-21} = 0b10000000000;
21725 let Defs = [USR_OVF];
21727 def S2_vsplatrb : HInst<
21728 (outs IntRegs:$Rd32),
21729 (ins IntRegs:$Rs32),
21730 "$Rd32 = vsplatb($Rs32)",
21731 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
21732 let Inst{13-5} = 0b000000111;
21733 let Inst{31-21} = 0b10001100010;
21734 let hasNewValue = 1;
21735 let opNewValue = 0;
21736 let isReMaterializable = 1;
21737 let isAsCheapAsAMove = 1;
21739 def S2_vsplatrh : HInst<
21740 (outs DoubleRegs:$Rdd32),
21741 (ins IntRegs:$Rs32),
21742 "$Rdd32 = vsplath($Rs32)",
21743 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
21744 let Inst{13-5} = 0b000000010;
21745 let Inst{31-21} = 0b10000100010;
21746 let isReMaterializable = 1;
21747 let isAsCheapAsAMove = 1;
21749 def S2_vspliceib : HInst<
21750 (outs DoubleRegs:$Rdd32),
21751 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
21752 "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
21753 tc_f8eeed7a, TypeS_3op>, Enc_d50cd3 {
21754 let Inst{13-13} = 0b0;
21755 let Inst{31-21} = 0b11000000100;
21757 def S2_vsplicerb : HInst<
21758 (outs DoubleRegs:$Rdd32),
21759 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
21760 "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
21761 tc_f8eeed7a, TypeS_3op>, Enc_dbd70c {
21762 let Inst{7-7} = 0b0;
21763 let Inst{13-13} = 0b0;
21764 let Inst{31-21} = 0b11000010100;
21766 def S2_vsxtbh : HInst<
21767 (outs DoubleRegs:$Rdd32),
21768 (ins IntRegs:$Rs32),
21769 "$Rdd32 = vsxtbh($Rs32)",
21770 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
21771 let Inst{13-5} = 0b000000000;
21772 let Inst{31-21} = 0b10000100000;
21773 let isReMaterializable = 1;
21774 let isAsCheapAsAMove = 1;
21776 def S2_vsxthw : HInst<
21777 (outs DoubleRegs:$Rdd32),
21778 (ins IntRegs:$Rs32),
21779 "$Rdd32 = vsxthw($Rs32)",
21780 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
21781 let Inst{13-5} = 0b000000100;
21782 let Inst{31-21} = 0b10000100000;
21783 let isReMaterializable = 1;
21784 let isAsCheapAsAMove = 1;
21786 def S2_vtrunehb : HInst<
21787 (outs IntRegs:$Rd32),
21788 (ins DoubleRegs:$Rss32),
21789 "$Rd32 = vtrunehb($Rss32)",
21790 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21791 let Inst{13-5} = 0b000000010;
21792 let Inst{31-21} = 0b10001000100;
21793 let hasNewValue = 1;
21794 let opNewValue = 0;
21796 def S2_vtrunewh : HInst<
21797 (outs DoubleRegs:$Rdd32),
21798 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
21799 "$Rdd32 = vtrunewh($Rss32,$Rtt32)",
21800 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
21801 let Inst{7-5} = 0b010;
21802 let Inst{13-13} = 0b0;
21803 let Inst{31-21} = 0b11000001100;
21805 def S2_vtrunohb : HInst<
21806 (outs IntRegs:$Rd32),
21807 (ins DoubleRegs:$Rss32),
21808 "$Rd32 = vtrunohb($Rss32)",
21809 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
21810 let Inst{13-5} = 0b000000000;
21811 let Inst{31-21} = 0b10001000100;
21812 let hasNewValue = 1;
21813 let opNewValue = 0;
21815 def S2_vtrunowh : HInst<
21816 (outs DoubleRegs:$Rdd32),
21817 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
21818 "$Rdd32 = vtrunowh($Rss32,$Rtt32)",
21819 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
21820 let Inst{7-5} = 0b100;
21821 let Inst{13-13} = 0b0;
21822 let Inst{31-21} = 0b11000001100;
21824 def S2_vzxtbh : HInst<
21825 (outs DoubleRegs:$Rdd32),
21826 (ins IntRegs:$Rs32),
21827 "$Rdd32 = vzxtbh($Rs32)",
21828 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
21829 let Inst{13-5} = 0b000000010;
21830 let Inst{31-21} = 0b10000100000;
21831 let isReMaterializable = 1;
21832 let isAsCheapAsAMove = 1;
21834 def S2_vzxthw : HInst<
21835 (outs DoubleRegs:$Rdd32),
21836 (ins IntRegs:$Rs32),
21837 "$Rdd32 = vzxthw($Rs32)",
21838 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
21839 let Inst{13-5} = 0b000000110;
21840 let Inst{31-21} = 0b10000100000;
21841 let isReMaterializable = 1;
21842 let isAsCheapAsAMove = 1;
21844 def S4_addaddi : HInst<
21845 (outs IntRegs:$Rd32),
21846 (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
21847 "$Rd32 = add($Rs32,add($Ru32,#$Ii))",
21848 tc_c74f796f, TypeALU64>, Enc_8b8d61 {
21849 let Inst{31-23} = 0b110110110;
21850 let hasNewValue = 1;
21851 let opNewValue = 0;
21852 let prefersSlot3 = 1;
21853 let isExtendable = 1;
21854 let opExtendable = 3;
21855 let isExtentSigned = 1;
21856 let opExtentBits = 6;
21857 let opExtentAlign = 0;
21859 def S4_addi_asl_ri : HInst<
21860 (outs IntRegs:$Rx32),
21861 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
21862 "$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
21863 tc_c74f796f, TypeALU64>, Enc_c31910 {
21864 let Inst{2-0} = 0b100;
21865 let Inst{4-4} = 0b0;
21866 let Inst{31-24} = 0b11011110;
21867 let hasNewValue = 1;
21868 let opNewValue = 0;
21869 let prefersSlot3 = 1;
21870 let isExtendable = 1;
21871 let opExtendable = 1;
21872 let isExtentSigned = 0;
21873 let opExtentBits = 8;
21874 let opExtentAlign = 0;
21875 let Constraints = "$Rx32 = $Rx32in";
21877 def S4_addi_lsr_ri : HInst<
21878 (outs IntRegs:$Rx32),
21879 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
21880 "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
21881 tc_c74f796f, TypeALU64>, Enc_c31910 {
21882 let Inst{2-0} = 0b100;
21883 let Inst{4-4} = 0b1;
21884 let Inst{31-24} = 0b11011110;
21885 let hasNewValue = 1;
21886 let opNewValue = 0;
21887 let prefersSlot3 = 1;
21888 let isExtendable = 1;
21889 let opExtendable = 1;
21890 let isExtentSigned = 0;
21891 let opExtentBits = 8;
21892 let opExtentAlign = 0;
21893 let Constraints = "$Rx32 = $Rx32in";
21895 def S4_andi_asl_ri : HInst<
21896 (outs IntRegs:$Rx32),
21897 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
21898 "$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
21899 tc_84df2cd3, TypeALU64>, Enc_c31910 {
21900 let Inst{2-0} = 0b000;
21901 let Inst{4-4} = 0b0;
21902 let Inst{31-24} = 0b11011110;
21903 let hasNewValue = 1;
21904 let opNewValue = 0;
21905 let prefersSlot3 = 1;
21906 let isExtendable = 1;
21907 let opExtendable = 1;
21908 let isExtentSigned = 0;
21909 let opExtentBits = 8;
21910 let opExtentAlign = 0;
21911 let Constraints = "$Rx32 = $Rx32in";
21913 def S4_andi_lsr_ri : HInst<
21914 (outs IntRegs:$Rx32),
21915 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
21916 "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
21917 tc_84df2cd3, TypeALU64>, Enc_c31910 {
21918 let Inst{2-0} = 0b000;
21919 let Inst{4-4} = 0b1;
21920 let Inst{31-24} = 0b11011110;
21921 let hasNewValue = 1;
21922 let opNewValue = 0;
21923 let prefersSlot3 = 1;
21924 let isExtendable = 1;
21925 let opExtendable = 1;
21926 let isExtentSigned = 0;
21927 let opExtentBits = 8;
21928 let opExtentAlign = 0;
21929 let Constraints = "$Rx32 = $Rx32in";
21931 def S4_clbaddi : HInst<
21932 (outs IntRegs:$Rd32),
21933 (ins IntRegs:$Rs32, s6_0Imm:$Ii),
21934 "$Rd32 = add(clb($Rs32),#$Ii)",
21935 tc_2b6f77c6, TypeS_2op>, Enc_9fae8a {
21936 let Inst{7-5} = 0b000;
21937 let Inst{31-21} = 0b10001100001;
21938 let hasNewValue = 1;
21939 let opNewValue = 0;
21940 let prefersSlot3 = 1;
21942 def S4_clbpaddi : HInst<
21943 (outs IntRegs:$Rd32),
21944 (ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
21945 "$Rd32 = add(clb($Rss32),#$Ii)",
21946 tc_2b6f77c6, TypeS_2op>, Enc_a1640c {
21947 let Inst{7-5} = 0b010;
21948 let Inst{31-21} = 0b10001000011;
21949 let hasNewValue = 1;
21950 let opNewValue = 0;
21951 let prefersSlot3 = 1;
21953 def S4_clbpnorm : HInst<
21954 (outs IntRegs:$Rd32),
21955 (ins DoubleRegs:$Rss32),
21956 "$Rd32 = normamt($Rss32)",
21957 tc_d088982c, TypeS_2op>, Enc_90cd8b {
21958 let Inst{13-5} = 0b000000000;
21959 let Inst{31-21} = 0b10001000011;
21960 let hasNewValue = 1;
21961 let opNewValue = 0;
21962 let prefersSlot3 = 1;
21964 def S4_extract : HInst<
21965 (outs IntRegs:$Rd32),
21966 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
21967 "$Rd32 = extract($Rs32,#$Ii,#$II)",
21968 tc_c74f796f, TypeS_2op>, Enc_b388cf {
21969 let Inst{13-13} = 0b0;
21970 let Inst{31-23} = 0b100011011;
21971 let hasNewValue = 1;
21972 let opNewValue = 0;
21973 let prefersSlot3 = 1;
21975 def S4_extract_rp : HInst<
21976 (outs IntRegs:$Rd32),
21977 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21978 "$Rd32 = extract($Rs32,$Rtt32)",
21979 tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
21980 let Inst{7-5} = 0b010;
21981 let Inst{13-13} = 0b0;
21982 let Inst{31-21} = 0b11001001000;
21983 let hasNewValue = 1;
21984 let opNewValue = 0;
21985 let prefersSlot3 = 1;
21987 def S4_extractp : HInst<
21988 (outs DoubleRegs:$Rdd32),
21989 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
21990 "$Rdd32 = extract($Rss32,#$Ii,#$II)",
21991 tc_c74f796f, TypeS_2op>, Enc_b84c4c {
21992 let Inst{31-24} = 0b10001010;
21993 let prefersSlot3 = 1;
21995 def S4_extractp_rp : HInst<
21996 (outs DoubleRegs:$Rdd32),
21997 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
21998 "$Rdd32 = extract($Rss32,$Rtt32)",
21999 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
22000 let Inst{7-5} = 0b100;
22001 let Inst{13-13} = 0b0;
22002 let Inst{31-21} = 0b11000001110;
22003 let prefersSlot3 = 1;
22005 def S4_lsli : HInst<
22006 (outs IntRegs:$Rd32),
22007 (ins s6_0Imm:$Ii, IntRegs:$Rt32),
22008 "$Rd32 = lsl(#$Ii,$Rt32)",
22009 tc_540fdfbc, TypeS_3op>, Enc_fef969 {
22010 let Inst{7-6} = 0b11;
22011 let Inst{13-13} = 0b0;
22012 let Inst{31-21} = 0b11000110100;
22013 let hasNewValue = 1;
22014 let opNewValue = 0;
22016 def S4_ntstbit_i : HInst<
22017 (outs PredRegs:$Pd4),
22018 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
22019 "$Pd4 = !tstbit($Rs32,#$Ii)",
22020 tc_7a830544, TypeS_2op>, Enc_83ee64 {
22021 let Inst{7-2} = 0b000000;
22022 let Inst{13-13} = 0b0;
22023 let Inst{31-21} = 0b10000101001;
22025 def S4_ntstbit_r : HInst<
22026 (outs PredRegs:$Pd4),
22027 (ins IntRegs:$Rs32, IntRegs:$Rt32),
22028 "$Pd4 = !tstbit($Rs32,$Rt32)",
22029 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
22030 let Inst{7-2} = 0b000000;
22031 let Inst{13-13} = 0b0;
22032 let Inst{31-21} = 0b11000111001;
22034 def S4_or_andi : HInst<
22035 (outs IntRegs:$Rx32),
22036 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22037 "$Rx32 |= and($Rs32,#$Ii)",
22038 tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
22039 let Inst{31-22} = 0b1101101000;
22040 let hasNewValue = 1;
22041 let opNewValue = 0;
22042 let prefersSlot3 = 1;
22043 let InputType = "imm";
22044 let isExtendable = 1;
22045 let opExtendable = 3;
22046 let isExtentSigned = 1;
22047 let opExtentBits = 10;
22048 let opExtentAlign = 0;
22049 let Constraints = "$Rx32 = $Rx32in";
22051 def S4_or_andix : HInst<
22052 (outs IntRegs:$Rx32),
22053 (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22054 "$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22055 tc_84df2cd3, TypeALU64>, Enc_b4e6cf {
22056 let Inst{31-22} = 0b1101101001;
22057 let hasNewValue = 1;
22058 let opNewValue = 0;
22059 let prefersSlot3 = 1;
22060 let isExtendable = 1;
22061 let opExtendable = 3;
22062 let isExtentSigned = 1;
22063 let opExtentBits = 10;
22064 let opExtentAlign = 0;
22065 let Constraints = "$Rx32 = $Rx32in";
22067 def S4_or_ori : HInst<
22068 (outs IntRegs:$Rx32),
22069 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22070 "$Rx32 |= or($Rs32,#$Ii)",
22071 tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
22072 let Inst{31-22} = 0b1101101010;
22073 let hasNewValue = 1;
22074 let opNewValue = 0;
22075 let prefersSlot3 = 1;
22076 let InputType = "imm";
22077 let isExtendable = 1;
22078 let opExtendable = 3;
22079 let isExtentSigned = 1;
22080 let opExtentBits = 10;
22081 let opExtentAlign = 0;
22082 let Constraints = "$Rx32 = $Rx32in";
22084 def S4_ori_asl_ri : HInst<
22085 (outs IntRegs:$Rx32),
22086 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22087 "$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22088 tc_84df2cd3, TypeALU64>, Enc_c31910 {
22089 let Inst{2-0} = 0b010;
22090 let Inst{4-4} = 0b0;
22091 let Inst{31-24} = 0b11011110;
22092 let hasNewValue = 1;
22093 let opNewValue = 0;
22094 let prefersSlot3 = 1;
22095 let isExtendable = 1;
22096 let opExtendable = 1;
22097 let isExtentSigned = 0;
22098 let opExtentBits = 8;
22099 let opExtentAlign = 0;
22100 let Constraints = "$Rx32 = $Rx32in";
22102 def S4_ori_lsr_ri : HInst<
22103 (outs IntRegs:$Rx32),
22104 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22105 "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22106 tc_84df2cd3, TypeALU64>, Enc_c31910 {
22107 let Inst{2-0} = 0b010;
22108 let Inst{4-4} = 0b1;
22109 let Inst{31-24} = 0b11011110;
22110 let hasNewValue = 1;
22111 let opNewValue = 0;
22112 let prefersSlot3 = 1;
22113 let isExtendable = 1;
22114 let opExtendable = 1;
22115 let isExtentSigned = 0;
22116 let opExtentBits = 8;
22117 let opExtentAlign = 0;
22118 let Constraints = "$Rx32 = $Rx32in";
22120 def S4_parity : HInst<
22121 (outs IntRegs:$Rd32),
22122 (ins IntRegs:$Rs32, IntRegs:$Rt32),
22123 "$Rd32 = parity($Rs32,$Rt32)",
22124 tc_2b6f77c6, TypeALU64>, Enc_5ab2be {
22125 let Inst{7-5} = 0b000;
22126 let Inst{13-13} = 0b0;
22127 let Inst{31-21} = 0b11010101111;
22128 let hasNewValue = 1;
22129 let opNewValue = 0;
22130 let prefersSlot3 = 1;
22132 def S4_pstorerbf_abs : HInst<
22134 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22135 "if (!$Pv4) memb(#$Ii) = $Rt32",
22136 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
22137 let Inst{2-2} = 0b1;
22138 let Inst{7-7} = 0b1;
22139 let Inst{13-13} = 0b0;
22140 let Inst{31-18} = 0b10101111000000;
22141 let isPredicated = 1;
22142 let isPredicatedFalse = 1;
22143 let addrMode = Absolute;
22144 let accessSize = ByteAccess;
22145 let isExtended = 1;
22147 let CextOpcode = "S2_storerb";
22148 let BaseOpcode = "S2_storerbabs";
22149 let isNVStorable = 1;
22150 let DecoderNamespace = "MustExtend";
22151 let isExtendable = 1;
22152 let opExtendable = 1;
22153 let isExtentSigned = 0;
22154 let opExtentBits = 6;
22155 let opExtentAlign = 0;
22157 def S4_pstorerbf_rr : HInst<
22159 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22160 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22161 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
22162 let Inst{31-21} = 0b00110101000;
22163 let isPredicated = 1;
22164 let isPredicatedFalse = 1;
22165 let addrMode = BaseRegOffset;
22166 let accessSize = ByteAccess;
22168 let CextOpcode = "S2_storerb";
22169 let InputType = "reg";
22170 let BaseOpcode = "S4_storerb_rr";
22171 let isNVStorable = 1;
22173 def S4_pstorerbfnew_abs : HInst<
22175 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22176 "if (!$Pv4.new) memb(#$Ii) = $Rt32",
22177 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
22178 let Inst{2-2} = 0b1;
22179 let Inst{7-7} = 0b1;
22180 let Inst{13-13} = 0b1;
22181 let Inst{31-18} = 0b10101111000000;
22182 let isPredicated = 1;
22183 let isPredicatedFalse = 1;
22184 let addrMode = Absolute;
22185 let accessSize = ByteAccess;
22186 let isPredicatedNew = 1;
22187 let isExtended = 1;
22189 let CextOpcode = "S2_storerb";
22190 let BaseOpcode = "S2_storerbabs";
22191 let isNVStorable = 1;
22192 let DecoderNamespace = "MustExtend";
22193 let isExtendable = 1;
22194 let opExtendable = 1;
22195 let isExtentSigned = 0;
22196 let opExtentBits = 6;
22197 let opExtentAlign = 0;
22199 def S4_pstorerbfnew_io : HInst<
22201 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22202 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22203 tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22204 let Inst{2-2} = 0b0;
22205 let Inst{31-21} = 0b01000110000;
22206 let isPredicated = 1;
22207 let isPredicatedFalse = 1;
22208 let addrMode = BaseImmOffset;
22209 let accessSize = ByteAccess;
22210 let isPredicatedNew = 1;
22212 let CextOpcode = "S2_storerb";
22213 let InputType = "imm";
22214 let BaseOpcode = "S2_storerb_io";
22215 let isNVStorable = 1;
22216 let isExtendable = 1;
22217 let opExtendable = 2;
22218 let isExtentSigned = 0;
22219 let opExtentBits = 6;
22220 let opExtentAlign = 0;
22222 def S4_pstorerbfnew_rr : HInst<
22224 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22225 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22226 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
22227 let Inst{31-21} = 0b00110111000;
22228 let isPredicated = 1;
22229 let isPredicatedFalse = 1;
22230 let addrMode = BaseRegOffset;
22231 let accessSize = ByteAccess;
22232 let isPredicatedNew = 1;
22234 let CextOpcode = "S2_storerb";
22235 let InputType = "reg";
22236 let BaseOpcode = "S4_storerb_rr";
22237 let isNVStorable = 1;
22239 def S4_pstorerbfnew_zomap : HInst<
22241 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22242 "if (!$Pv4.new) memb($Rs32) = $Rt32",
22243 tc_f86c328a, TypeMAPPING> {
22245 let isCodeGenOnly = 1;
22247 def S4_pstorerbnewf_abs : HInst<
22249 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22250 "if (!$Pv4) memb(#$Ii) = $Nt8.new",
22251 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
22252 let Inst{2-2} = 0b1;
22253 let Inst{7-7} = 0b1;
22254 let Inst{13-11} = 0b000;
22255 let Inst{31-18} = 0b10101111101000;
22256 let isPredicated = 1;
22257 let isPredicatedFalse = 1;
22258 let addrMode = Absolute;
22259 let accessSize = ByteAccess;
22261 let isNewValue = 1;
22262 let isExtended = 1;
22263 let isRestrictNoSlot1Store = 1;
22265 let CextOpcode = "S2_storerb";
22266 let BaseOpcode = "S2_storerbabs";
22267 let DecoderNamespace = "MustExtend";
22268 let isExtendable = 1;
22269 let opExtendable = 1;
22270 let isExtentSigned = 0;
22271 let opExtentBits = 6;
22272 let opExtentAlign = 0;
22273 let opNewValue = 2;
22275 def S4_pstorerbnewf_rr : HInst<
22277 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22278 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22279 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
22280 let Inst{4-3} = 0b00;
22281 let Inst{31-21} = 0b00110101101;
22282 let isPredicated = 1;
22283 let isPredicatedFalse = 1;
22284 let addrMode = BaseRegOffset;
22285 let accessSize = ByteAccess;
22287 let isNewValue = 1;
22288 let isRestrictNoSlot1Store = 1;
22290 let CextOpcode = "S2_storerb";
22291 let InputType = "reg";
22292 let BaseOpcode = "S4_storerb_rr";
22293 let opNewValue = 4;
22295 def S4_pstorerbnewfnew_abs : HInst<
22297 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22298 "if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22299 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
22300 let Inst{2-2} = 0b1;
22301 let Inst{7-7} = 0b1;
22302 let Inst{13-11} = 0b100;
22303 let Inst{31-18} = 0b10101111101000;
22304 let isPredicated = 1;
22305 let isPredicatedFalse = 1;
22306 let addrMode = Absolute;
22307 let accessSize = ByteAccess;
22309 let isPredicatedNew = 1;
22310 let isNewValue = 1;
22311 let isExtended = 1;
22312 let isRestrictNoSlot1Store = 1;
22314 let CextOpcode = "S2_storerb";
22315 let BaseOpcode = "S2_storerbabs";
22316 let DecoderNamespace = "MustExtend";
22317 let isExtendable = 1;
22318 let opExtendable = 1;
22319 let isExtentSigned = 0;
22320 let opExtentBits = 6;
22321 let opExtentAlign = 0;
22322 let opNewValue = 2;
22324 def S4_pstorerbnewfnew_io : HInst<
22326 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22327 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22328 tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
22329 let Inst{2-2} = 0b0;
22330 let Inst{12-11} = 0b00;
22331 let Inst{31-21} = 0b01000110101;
22332 let isPredicated = 1;
22333 let isPredicatedFalse = 1;
22334 let addrMode = BaseImmOffset;
22335 let accessSize = ByteAccess;
22337 let isPredicatedNew = 1;
22338 let isNewValue = 1;
22339 let isRestrictNoSlot1Store = 1;
22341 let CextOpcode = "S2_storerb";
22342 let InputType = "imm";
22343 let BaseOpcode = "S2_storerb_io";
22344 let isExtendable = 1;
22345 let opExtendable = 2;
22346 let isExtentSigned = 0;
22347 let opExtentBits = 6;
22348 let opExtentAlign = 0;
22349 let opNewValue = 3;
22351 def S4_pstorerbnewfnew_rr : HInst<
22353 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22354 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22355 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
22356 let Inst{4-3} = 0b00;
22357 let Inst{31-21} = 0b00110111101;
22358 let isPredicated = 1;
22359 let isPredicatedFalse = 1;
22360 let addrMode = BaseRegOffset;
22361 let accessSize = ByteAccess;
22363 let isPredicatedNew = 1;
22364 let isNewValue = 1;
22365 let isRestrictNoSlot1Store = 1;
22367 let CextOpcode = "S2_storerb";
22368 let InputType = "reg";
22369 let BaseOpcode = "S4_storerb_rr";
22370 let opNewValue = 4;
22372 def S4_pstorerbnewfnew_zomap : HInst<
22374 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22375 "if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22376 tc_e7d02c66, TypeMAPPING> {
22378 let isCodeGenOnly = 1;
22379 let opNewValue = 2;
22381 def S4_pstorerbnewt_abs : HInst<
22383 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22384 "if ($Pv4) memb(#$Ii) = $Nt8.new",
22385 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
22386 let Inst{2-2} = 0b0;
22387 let Inst{7-7} = 0b1;
22388 let Inst{13-11} = 0b000;
22389 let Inst{31-18} = 0b10101111101000;
22390 let isPredicated = 1;
22391 let addrMode = Absolute;
22392 let accessSize = ByteAccess;
22394 let isNewValue = 1;
22395 let isExtended = 1;
22396 let isRestrictNoSlot1Store = 1;
22398 let CextOpcode = "S2_storerb";
22399 let BaseOpcode = "S2_storerbabs";
22400 let DecoderNamespace = "MustExtend";
22401 let isExtendable = 1;
22402 let opExtendable = 1;
22403 let isExtentSigned = 0;
22404 let opExtentBits = 6;
22405 let opExtentAlign = 0;
22406 let opNewValue = 2;
22408 def S4_pstorerbnewt_rr : HInst<
22410 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22411 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22412 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
22413 let Inst{4-3} = 0b00;
22414 let Inst{31-21} = 0b00110100101;
22415 let isPredicated = 1;
22416 let addrMode = BaseRegOffset;
22417 let accessSize = ByteAccess;
22419 let isNewValue = 1;
22420 let isRestrictNoSlot1Store = 1;
22422 let CextOpcode = "S2_storerb";
22423 let InputType = "reg";
22424 let BaseOpcode = "S4_storerb_rr";
22425 let opNewValue = 4;
22427 def S4_pstorerbnewtnew_abs : HInst<
22429 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22430 "if ($Pv4.new) memb(#$Ii) = $Nt8.new",
22431 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
22432 let Inst{2-2} = 0b0;
22433 let Inst{7-7} = 0b1;
22434 let Inst{13-11} = 0b100;
22435 let Inst{31-18} = 0b10101111101000;
22436 let isPredicated = 1;
22437 let addrMode = Absolute;
22438 let accessSize = ByteAccess;
22440 let isPredicatedNew = 1;
22441 let isNewValue = 1;
22442 let isExtended = 1;
22443 let isRestrictNoSlot1Store = 1;
22445 let CextOpcode = "S2_storerb";
22446 let BaseOpcode = "S2_storerbabs";
22447 let DecoderNamespace = "MustExtend";
22448 let isExtendable = 1;
22449 let opExtendable = 1;
22450 let isExtentSigned = 0;
22451 let opExtentBits = 6;
22452 let opExtentAlign = 0;
22453 let opNewValue = 2;
22455 def S4_pstorerbnewtnew_io : HInst<
22457 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22458 "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22459 tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
22460 let Inst{2-2} = 0b0;
22461 let Inst{12-11} = 0b00;
22462 let Inst{31-21} = 0b01000010101;
22463 let isPredicated = 1;
22464 let addrMode = BaseImmOffset;
22465 let accessSize = ByteAccess;
22467 let isPredicatedNew = 1;
22468 let isNewValue = 1;
22469 let isRestrictNoSlot1Store = 1;
22471 let CextOpcode = "S2_storerb";
22472 let InputType = "imm";
22473 let BaseOpcode = "S2_storerb_io";
22474 let isExtendable = 1;
22475 let opExtendable = 2;
22476 let isExtentSigned = 0;
22477 let opExtentBits = 6;
22478 let opExtentAlign = 0;
22479 let opNewValue = 3;
22481 def S4_pstorerbnewtnew_rr : HInst<
22483 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22484 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22485 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
22486 let Inst{4-3} = 0b00;
22487 let Inst{31-21} = 0b00110110101;
22488 let isPredicated = 1;
22489 let addrMode = BaseRegOffset;
22490 let accessSize = ByteAccess;
22492 let isPredicatedNew = 1;
22493 let isNewValue = 1;
22494 let isRestrictNoSlot1Store = 1;
22496 let CextOpcode = "S2_storerb";
22497 let InputType = "reg";
22498 let BaseOpcode = "S4_storerb_rr";
22499 let opNewValue = 4;
22501 def S4_pstorerbnewtnew_zomap : HInst<
22503 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22504 "if ($Pv4.new) memb($Rs32) = $Nt8.new",
22505 tc_e7d02c66, TypeMAPPING> {
22507 let isCodeGenOnly = 1;
22508 let opNewValue = 2;
22510 def S4_pstorerbt_abs : HInst<
22512 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22513 "if ($Pv4) memb(#$Ii) = $Rt32",
22514 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
22515 let Inst{2-2} = 0b0;
22516 let Inst{7-7} = 0b1;
22517 let Inst{13-13} = 0b0;
22518 let Inst{31-18} = 0b10101111000000;
22519 let isPredicated = 1;
22520 let addrMode = Absolute;
22521 let accessSize = ByteAccess;
22522 let isExtended = 1;
22524 let CextOpcode = "S2_storerb";
22525 let BaseOpcode = "S2_storerbabs";
22526 let isNVStorable = 1;
22527 let DecoderNamespace = "MustExtend";
22528 let isExtendable = 1;
22529 let opExtendable = 1;
22530 let isExtentSigned = 0;
22531 let opExtentBits = 6;
22532 let opExtentAlign = 0;
22534 def S4_pstorerbt_rr : HInst<
22536 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22537 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22538 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
22539 let Inst{31-21} = 0b00110100000;
22540 let isPredicated = 1;
22541 let addrMode = BaseRegOffset;
22542 let accessSize = ByteAccess;
22544 let CextOpcode = "S2_storerb";
22545 let InputType = "reg";
22546 let BaseOpcode = "S4_storerb_rr";
22547 let isNVStorable = 1;
22549 def S4_pstorerbtnew_abs : HInst<
22551 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22552 "if ($Pv4.new) memb(#$Ii) = $Rt32",
22553 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
22554 let Inst{2-2} = 0b0;
22555 let Inst{7-7} = 0b1;
22556 let Inst{13-13} = 0b1;
22557 let Inst{31-18} = 0b10101111000000;
22558 let isPredicated = 1;
22559 let addrMode = Absolute;
22560 let accessSize = ByteAccess;
22561 let isPredicatedNew = 1;
22562 let isExtended = 1;
22564 let CextOpcode = "S2_storerb";
22565 let BaseOpcode = "S2_storerbabs";
22566 let isNVStorable = 1;
22567 let DecoderNamespace = "MustExtend";
22568 let isExtendable = 1;
22569 let opExtendable = 1;
22570 let isExtentSigned = 0;
22571 let opExtentBits = 6;
22572 let opExtentAlign = 0;
22574 def S4_pstorerbtnew_io : HInst<
22576 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22577 "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22578 tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22579 let Inst{2-2} = 0b0;
22580 let Inst{31-21} = 0b01000010000;
22581 let isPredicated = 1;
22582 let addrMode = BaseImmOffset;
22583 let accessSize = ByteAccess;
22584 let isPredicatedNew = 1;
22586 let CextOpcode = "S2_storerb";
22587 let InputType = "imm";
22588 let BaseOpcode = "S2_storerb_io";
22589 let isNVStorable = 1;
22590 let isExtendable = 1;
22591 let opExtendable = 2;
22592 let isExtentSigned = 0;
22593 let opExtentBits = 6;
22594 let opExtentAlign = 0;
22596 def S4_pstorerbtnew_rr : HInst<
22598 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22599 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22600 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
22601 let Inst{31-21} = 0b00110110000;
22602 let isPredicated = 1;
22603 let addrMode = BaseRegOffset;
22604 let accessSize = ByteAccess;
22605 let isPredicatedNew = 1;
22607 let CextOpcode = "S2_storerb";
22608 let InputType = "reg";
22609 let BaseOpcode = "S4_storerb_rr";
22610 let isNVStorable = 1;
22612 def S4_pstorerbtnew_zomap : HInst<
22614 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22615 "if ($Pv4.new) memb($Rs32) = $Rt32",
22616 tc_f86c328a, TypeMAPPING> {
22618 let isCodeGenOnly = 1;
22620 def S4_pstorerdf_abs : HInst<
22622 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22623 "if (!$Pv4) memd(#$Ii) = $Rtt32",
22624 tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
22625 let Inst{2-2} = 0b1;
22626 let Inst{7-7} = 0b1;
22627 let Inst{13-13} = 0b0;
22628 let Inst{31-18} = 0b10101111110000;
22629 let isPredicated = 1;
22630 let isPredicatedFalse = 1;
22631 let addrMode = Absolute;
22632 let accessSize = DoubleWordAccess;
22633 let isExtended = 1;
22635 let CextOpcode = "S2_storerd";
22636 let BaseOpcode = "S2_storerdabs";
22637 let DecoderNamespace = "MustExtend";
22638 let isExtendable = 1;
22639 let opExtendable = 1;
22640 let isExtentSigned = 0;
22641 let opExtentBits = 6;
22642 let opExtentAlign = 0;
22644 def S4_pstorerdf_rr : HInst<
22646 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22647 "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22648 tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
22649 let Inst{31-21} = 0b00110101110;
22650 let isPredicated = 1;
22651 let isPredicatedFalse = 1;
22652 let addrMode = BaseRegOffset;
22653 let accessSize = DoubleWordAccess;
22655 let CextOpcode = "S2_storerd";
22656 let InputType = "reg";
22657 let BaseOpcode = "S2_storerd_rr";
22659 def S4_pstorerdfnew_abs : HInst<
22661 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22662 "if (!$Pv4.new) memd(#$Ii) = $Rtt32",
22663 tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
22664 let Inst{2-2} = 0b1;
22665 let Inst{7-7} = 0b1;
22666 let Inst{13-13} = 0b1;
22667 let Inst{31-18} = 0b10101111110000;
22668 let isPredicated = 1;
22669 let isPredicatedFalse = 1;
22670 let addrMode = Absolute;
22671 let accessSize = DoubleWordAccess;
22672 let isPredicatedNew = 1;
22673 let isExtended = 1;
22675 let CextOpcode = "S2_storerd";
22676 let BaseOpcode = "S2_storerdabs";
22677 let DecoderNamespace = "MustExtend";
22678 let isExtendable = 1;
22679 let opExtendable = 1;
22680 let isExtentSigned = 0;
22681 let opExtentBits = 6;
22682 let opExtentAlign = 0;
22684 def S4_pstorerdfnew_io : HInst<
22686 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
22687 "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
22688 tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
22689 let Inst{2-2} = 0b0;
22690 let Inst{31-21} = 0b01000110110;
22691 let isPredicated = 1;
22692 let isPredicatedFalse = 1;
22693 let addrMode = BaseImmOffset;
22694 let accessSize = DoubleWordAccess;
22695 let isPredicatedNew = 1;
22697 let CextOpcode = "S2_storerd";
22698 let InputType = "imm";
22699 let BaseOpcode = "S2_storerd_io";
22700 let isExtendable = 1;
22701 let opExtendable = 2;
22702 let isExtentSigned = 0;
22703 let opExtentBits = 9;
22704 let opExtentAlign = 3;
22706 def S4_pstorerdfnew_rr : HInst<
22708 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22709 "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22710 tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
22711 let Inst{31-21} = 0b00110111110;
22712 let isPredicated = 1;
22713 let isPredicatedFalse = 1;
22714 let addrMode = BaseRegOffset;
22715 let accessSize = DoubleWordAccess;
22716 let isPredicatedNew = 1;
22718 let CextOpcode = "S2_storerd";
22719 let InputType = "reg";
22720 let BaseOpcode = "S2_storerd_rr";
22722 def S4_pstorerdfnew_zomap : HInst<
22724 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
22725 "if (!$Pv4.new) memd($Rs32) = $Rtt32",
22726 tc_f86c328a, TypeMAPPING> {
22728 let isCodeGenOnly = 1;
22730 def S4_pstorerdt_abs : HInst<
22732 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22733 "if ($Pv4) memd(#$Ii) = $Rtt32",
22734 tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
22735 let Inst{2-2} = 0b0;
22736 let Inst{7-7} = 0b1;
22737 let Inst{13-13} = 0b0;
22738 let Inst{31-18} = 0b10101111110000;
22739 let isPredicated = 1;
22740 let addrMode = Absolute;
22741 let accessSize = DoubleWordAccess;
22742 let isExtended = 1;
22744 let CextOpcode = "S2_storerd";
22745 let BaseOpcode = "S2_storerdabs";
22746 let DecoderNamespace = "MustExtend";
22747 let isExtendable = 1;
22748 let opExtendable = 1;
22749 let isExtentSigned = 0;
22750 let opExtentBits = 6;
22751 let opExtentAlign = 0;
22753 def S4_pstorerdt_rr : HInst<
22755 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22756 "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22757 tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
22758 let Inst{31-21} = 0b00110100110;
22759 let isPredicated = 1;
22760 let addrMode = BaseRegOffset;
22761 let accessSize = DoubleWordAccess;
22763 let CextOpcode = "S2_storerd";
22764 let InputType = "reg";
22765 let BaseOpcode = "S2_storerd_rr";
22767 def S4_pstorerdtnew_abs : HInst<
22769 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22770 "if ($Pv4.new) memd(#$Ii) = $Rtt32",
22771 tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
22772 let Inst{2-2} = 0b0;
22773 let Inst{7-7} = 0b1;
22774 let Inst{13-13} = 0b1;
22775 let Inst{31-18} = 0b10101111110000;
22776 let isPredicated = 1;
22777 let addrMode = Absolute;
22778 let accessSize = DoubleWordAccess;
22779 let isPredicatedNew = 1;
22780 let isExtended = 1;
22782 let CextOpcode = "S2_storerd";
22783 let BaseOpcode = "S2_storerdabs";
22784 let DecoderNamespace = "MustExtend";
22785 let isExtendable = 1;
22786 let opExtendable = 1;
22787 let isExtentSigned = 0;
22788 let opExtentBits = 6;
22789 let opExtentAlign = 0;
22791 def S4_pstorerdtnew_io : HInst<
22793 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
22794 "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
22795 tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
22796 let Inst{2-2} = 0b0;
22797 let Inst{31-21} = 0b01000010110;
22798 let isPredicated = 1;
22799 let addrMode = BaseImmOffset;
22800 let accessSize = DoubleWordAccess;
22801 let isPredicatedNew = 1;
22803 let CextOpcode = "S2_storerd";
22804 let InputType = "imm";
22805 let BaseOpcode = "S2_storerd_io";
22806 let isExtendable = 1;
22807 let opExtendable = 2;
22808 let isExtentSigned = 0;
22809 let opExtentBits = 9;
22810 let opExtentAlign = 3;
22812 def S4_pstorerdtnew_rr : HInst<
22814 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22815 "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22816 tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
22817 let Inst{31-21} = 0b00110110110;
22818 let isPredicated = 1;
22819 let addrMode = BaseRegOffset;
22820 let accessSize = DoubleWordAccess;
22821 let isPredicatedNew = 1;
22823 let CextOpcode = "S2_storerd";
22824 let InputType = "reg";
22825 let BaseOpcode = "S2_storerd_rr";
22827 def S4_pstorerdtnew_zomap : HInst<
22829 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
22830 "if ($Pv4.new) memd($Rs32) = $Rtt32",
22831 tc_f86c328a, TypeMAPPING> {
22833 let isCodeGenOnly = 1;
22835 def S4_pstorerff_abs : HInst<
22837 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22838 "if (!$Pv4) memh(#$Ii) = $Rt32.h",
22839 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
22840 let Inst{2-2} = 0b1;
22841 let Inst{7-7} = 0b1;
22842 let Inst{13-13} = 0b0;
22843 let Inst{31-18} = 0b10101111011000;
22844 let isPredicated = 1;
22845 let isPredicatedFalse = 1;
22846 let addrMode = Absolute;
22847 let accessSize = HalfWordAccess;
22848 let isExtended = 1;
22850 let CextOpcode = "S2_storerf";
22851 let BaseOpcode = "S2_storerfabs";
22852 let DecoderNamespace = "MustExtend";
22853 let isExtendable = 1;
22854 let opExtendable = 1;
22855 let isExtentSigned = 0;
22856 let opExtentBits = 6;
22857 let opExtentAlign = 0;
22859 def S4_pstorerff_rr : HInst<
22861 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22862 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
22863 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
22864 let Inst{31-21} = 0b00110101011;
22865 let isPredicated = 1;
22866 let isPredicatedFalse = 1;
22867 let addrMode = BaseRegOffset;
22868 let accessSize = HalfWordAccess;
22870 let CextOpcode = "S2_storerf";
22871 let InputType = "reg";
22872 let BaseOpcode = "S4_storerf_rr";
22874 def S4_pstorerffnew_abs : HInst<
22876 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22877 "if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
22878 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
22879 let Inst{2-2} = 0b1;
22880 let Inst{7-7} = 0b1;
22881 let Inst{13-13} = 0b1;
22882 let Inst{31-18} = 0b10101111011000;
22883 let isPredicated = 1;
22884 let isPredicatedFalse = 1;
22885 let addrMode = Absolute;
22886 let accessSize = HalfWordAccess;
22887 let isPredicatedNew = 1;
22888 let isExtended = 1;
22890 let CextOpcode = "S2_storerf";
22891 let BaseOpcode = "S2_storerfabs";
22892 let DecoderNamespace = "MustExtend";
22893 let isExtendable = 1;
22894 let opExtendable = 1;
22895 let isExtentSigned = 0;
22896 let opExtentBits = 6;
22897 let opExtentAlign = 0;
22899 def S4_pstorerffnew_io : HInst<
22901 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
22902 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
22903 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
22904 let Inst{2-2} = 0b0;
22905 let Inst{31-21} = 0b01000110011;
22906 let isPredicated = 1;
22907 let isPredicatedFalse = 1;
22908 let addrMode = BaseImmOffset;
22909 let accessSize = HalfWordAccess;
22910 let isPredicatedNew = 1;
22912 let CextOpcode = "S2_storerf";
22913 let InputType = "imm";
22914 let BaseOpcode = "S2_storerf_io";
22915 let isExtendable = 1;
22916 let opExtendable = 2;
22917 let isExtentSigned = 0;
22918 let opExtentBits = 7;
22919 let opExtentAlign = 1;
22921 def S4_pstorerffnew_rr : HInst<
22923 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22924 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
22925 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
22926 let Inst{31-21} = 0b00110111011;
22927 let isPredicated = 1;
22928 let isPredicatedFalse = 1;
22929 let addrMode = BaseRegOffset;
22930 let accessSize = HalfWordAccess;
22931 let isPredicatedNew = 1;
22933 let CextOpcode = "S2_storerf";
22934 let InputType = "reg";
22935 let BaseOpcode = "S4_storerf_rr";
22937 def S4_pstorerffnew_zomap : HInst<
22939 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22940 "if (!$Pv4.new) memh($Rs32) = $Rt32.h",
22941 tc_f86c328a, TypeMAPPING> {
22943 let isCodeGenOnly = 1;
22945 def S4_pstorerft_abs : HInst<
22947 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22948 "if ($Pv4) memh(#$Ii) = $Rt32.h",
22949 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
22950 let Inst{2-2} = 0b0;
22951 let Inst{7-7} = 0b1;
22952 let Inst{13-13} = 0b0;
22953 let Inst{31-18} = 0b10101111011000;
22954 let isPredicated = 1;
22955 let addrMode = Absolute;
22956 let accessSize = HalfWordAccess;
22957 let isExtended = 1;
22959 let CextOpcode = "S2_storerf";
22960 let BaseOpcode = "S2_storerfabs";
22961 let DecoderNamespace = "MustExtend";
22962 let isExtendable = 1;
22963 let opExtendable = 1;
22964 let isExtentSigned = 0;
22965 let opExtentBits = 6;
22966 let opExtentAlign = 0;
22968 def S4_pstorerft_rr : HInst<
22970 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22971 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
22972 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
22973 let Inst{31-21} = 0b00110100011;
22974 let isPredicated = 1;
22975 let addrMode = BaseRegOffset;
22976 let accessSize = HalfWordAccess;
22978 let CextOpcode = "S2_storerf";
22979 let InputType = "reg";
22980 let BaseOpcode = "S4_storerf_rr";
22982 def S4_pstorerftnew_abs : HInst<
22984 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22985 "if ($Pv4.new) memh(#$Ii) = $Rt32.h",
22986 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
22987 let Inst{2-2} = 0b0;
22988 let Inst{7-7} = 0b1;
22989 let Inst{13-13} = 0b1;
22990 let Inst{31-18} = 0b10101111011000;
22991 let isPredicated = 1;
22992 let addrMode = Absolute;
22993 let accessSize = HalfWordAccess;
22994 let isPredicatedNew = 1;
22995 let isExtended = 1;
22997 let CextOpcode = "S2_storerf";
22998 let BaseOpcode = "S2_storerfabs";
22999 let DecoderNamespace = "MustExtend";
23000 let isExtendable = 1;
23001 let opExtendable = 1;
23002 let isExtentSigned = 0;
23003 let opExtentBits = 6;
23004 let opExtentAlign = 0;
23006 def S4_pstorerftnew_io : HInst<
23008 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23009 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23010 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23011 let Inst{2-2} = 0b0;
23012 let Inst{31-21} = 0b01000010011;
23013 let isPredicated = 1;
23014 let addrMode = BaseImmOffset;
23015 let accessSize = HalfWordAccess;
23016 let isPredicatedNew = 1;
23018 let CextOpcode = "S2_storerf";
23019 let InputType = "imm";
23020 let BaseOpcode = "S2_storerf_io";
23021 let isExtendable = 1;
23022 let opExtendable = 2;
23023 let isExtentSigned = 0;
23024 let opExtentBits = 7;
23025 let opExtentAlign = 1;
23027 def S4_pstorerftnew_rr : HInst<
23029 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23030 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23031 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
23032 let Inst{31-21} = 0b00110110011;
23033 let isPredicated = 1;
23034 let addrMode = BaseRegOffset;
23035 let accessSize = HalfWordAccess;
23036 let isPredicatedNew = 1;
23038 let CextOpcode = "S2_storerf";
23039 let InputType = "reg";
23040 let BaseOpcode = "S4_storerf_rr";
23042 def S4_pstorerftnew_zomap : HInst<
23044 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23045 "if ($Pv4.new) memh($Rs32) = $Rt32.h",
23046 tc_f86c328a, TypeMAPPING> {
23048 let isCodeGenOnly = 1;
23050 def S4_pstorerhf_abs : HInst<
23052 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23053 "if (!$Pv4) memh(#$Ii) = $Rt32",
23054 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
23055 let Inst{2-2} = 0b1;
23056 let Inst{7-7} = 0b1;
23057 let Inst{13-13} = 0b0;
23058 let Inst{31-18} = 0b10101111010000;
23059 let isPredicated = 1;
23060 let isPredicatedFalse = 1;
23061 let addrMode = Absolute;
23062 let accessSize = HalfWordAccess;
23063 let isExtended = 1;
23065 let CextOpcode = "S2_storerh";
23066 let BaseOpcode = "S2_storerhabs";
23067 let isNVStorable = 1;
23068 let DecoderNamespace = "MustExtend";
23069 let isExtendable = 1;
23070 let opExtendable = 1;
23071 let isExtentSigned = 0;
23072 let opExtentBits = 6;
23073 let opExtentAlign = 0;
23075 def S4_pstorerhf_rr : HInst<
23077 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23078 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23079 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
23080 let Inst{31-21} = 0b00110101010;
23081 let isPredicated = 1;
23082 let isPredicatedFalse = 1;
23083 let addrMode = BaseRegOffset;
23084 let accessSize = HalfWordAccess;
23086 let CextOpcode = "S2_storerh";
23087 let InputType = "reg";
23088 let BaseOpcode = "S2_storerh_rr";
23089 let isNVStorable = 1;
23091 def S4_pstorerhfnew_abs : HInst<
23093 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23094 "if (!$Pv4.new) memh(#$Ii) = $Rt32",
23095 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
23096 let Inst{2-2} = 0b1;
23097 let Inst{7-7} = 0b1;
23098 let Inst{13-13} = 0b1;
23099 let Inst{31-18} = 0b10101111010000;
23100 let isPredicated = 1;
23101 let isPredicatedFalse = 1;
23102 let addrMode = Absolute;
23103 let accessSize = HalfWordAccess;
23104 let isPredicatedNew = 1;
23105 let isExtended = 1;
23107 let CextOpcode = "S2_storerh";
23108 let BaseOpcode = "S2_storerhabs";
23109 let isNVStorable = 1;
23110 let DecoderNamespace = "MustExtend";
23111 let isExtendable = 1;
23112 let opExtendable = 1;
23113 let isExtentSigned = 0;
23114 let opExtentBits = 6;
23115 let opExtentAlign = 0;
23117 def S4_pstorerhfnew_io : HInst<
23119 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23120 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23121 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23122 let Inst{2-2} = 0b0;
23123 let Inst{31-21} = 0b01000110010;
23124 let isPredicated = 1;
23125 let isPredicatedFalse = 1;
23126 let addrMode = BaseImmOffset;
23127 let accessSize = HalfWordAccess;
23128 let isPredicatedNew = 1;
23130 let CextOpcode = "S2_storerh";
23131 let InputType = "imm";
23132 let BaseOpcode = "S2_storerh_io";
23133 let isNVStorable = 1;
23134 let isExtendable = 1;
23135 let opExtendable = 2;
23136 let isExtentSigned = 0;
23137 let opExtentBits = 7;
23138 let opExtentAlign = 1;
23140 def S4_pstorerhfnew_rr : HInst<
23142 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23143 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23144 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
23145 let Inst{31-21} = 0b00110111010;
23146 let isPredicated = 1;
23147 let isPredicatedFalse = 1;
23148 let addrMode = BaseRegOffset;
23149 let accessSize = HalfWordAccess;
23150 let isPredicatedNew = 1;
23152 let CextOpcode = "S2_storerh";
23153 let InputType = "reg";
23154 let BaseOpcode = "S2_storerh_rr";
23155 let isNVStorable = 1;
23157 def S4_pstorerhfnew_zomap : HInst<
23159 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23160 "if (!$Pv4.new) memh($Rs32) = $Rt32",
23161 tc_f86c328a, TypeMAPPING> {
23163 let isCodeGenOnly = 1;
23165 def S4_pstorerhnewf_abs : HInst<
23167 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23168 "if (!$Pv4) memh(#$Ii) = $Nt8.new",
23169 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
23170 let Inst{2-2} = 0b1;
23171 let Inst{7-7} = 0b1;
23172 let Inst{13-11} = 0b001;
23173 let Inst{31-18} = 0b10101111101000;
23174 let isPredicated = 1;
23175 let isPredicatedFalse = 1;
23176 let addrMode = Absolute;
23177 let accessSize = HalfWordAccess;
23179 let isNewValue = 1;
23180 let isExtended = 1;
23181 let isRestrictNoSlot1Store = 1;
23183 let CextOpcode = "S2_storerh";
23184 let BaseOpcode = "S2_storerhabs";
23185 let DecoderNamespace = "MustExtend";
23186 let isExtendable = 1;
23187 let opExtendable = 1;
23188 let isExtentSigned = 0;
23189 let opExtentBits = 6;
23190 let opExtentAlign = 0;
23191 let opNewValue = 2;
23193 def S4_pstorerhnewf_rr : HInst<
23195 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23196 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23197 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
23198 let Inst{4-3} = 0b01;
23199 let Inst{31-21} = 0b00110101101;
23200 let isPredicated = 1;
23201 let isPredicatedFalse = 1;
23202 let addrMode = BaseRegOffset;
23203 let accessSize = HalfWordAccess;
23205 let isNewValue = 1;
23206 let isRestrictNoSlot1Store = 1;
23208 let CextOpcode = "S2_storerh";
23209 let InputType = "reg";
23210 let BaseOpcode = "S2_storerh_rr";
23211 let opNewValue = 4;
23213 def S4_pstorerhnewfnew_abs : HInst<
23215 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23216 "if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23217 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
23218 let Inst{2-2} = 0b1;
23219 let Inst{7-7} = 0b1;
23220 let Inst{13-11} = 0b101;
23221 let Inst{31-18} = 0b10101111101000;
23222 let isPredicated = 1;
23223 let isPredicatedFalse = 1;
23224 let addrMode = Absolute;
23225 let accessSize = HalfWordAccess;
23227 let isPredicatedNew = 1;
23228 let isNewValue = 1;
23229 let isExtended = 1;
23230 let isRestrictNoSlot1Store = 1;
23232 let CextOpcode = "S2_storerh";
23233 let BaseOpcode = "S2_storerhabs";
23234 let DecoderNamespace = "MustExtend";
23235 let isExtendable = 1;
23236 let opExtendable = 1;
23237 let isExtentSigned = 0;
23238 let opExtentBits = 6;
23239 let opExtentAlign = 0;
23240 let opNewValue = 2;
23242 def S4_pstorerhnewfnew_io : HInst<
23244 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23245 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23246 tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
23247 let Inst{2-2} = 0b0;
23248 let Inst{12-11} = 0b01;
23249 let Inst{31-21} = 0b01000110101;
23250 let isPredicated = 1;
23251 let isPredicatedFalse = 1;
23252 let addrMode = BaseImmOffset;
23253 let accessSize = HalfWordAccess;
23255 let isPredicatedNew = 1;
23256 let isNewValue = 1;
23257 let isRestrictNoSlot1Store = 1;
23259 let CextOpcode = "S2_storerh";
23260 let InputType = "imm";
23261 let BaseOpcode = "S2_storerh_io";
23262 let isExtendable = 1;
23263 let opExtendable = 2;
23264 let isExtentSigned = 0;
23265 let opExtentBits = 7;
23266 let opExtentAlign = 1;
23267 let opNewValue = 3;
23269 def S4_pstorerhnewfnew_rr : HInst<
23271 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23272 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23273 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
23274 let Inst{4-3} = 0b01;
23275 let Inst{31-21} = 0b00110111101;
23276 let isPredicated = 1;
23277 let isPredicatedFalse = 1;
23278 let addrMode = BaseRegOffset;
23279 let accessSize = HalfWordAccess;
23281 let isPredicatedNew = 1;
23282 let isNewValue = 1;
23283 let isRestrictNoSlot1Store = 1;
23285 let CextOpcode = "S2_storerh";
23286 let InputType = "reg";
23287 let BaseOpcode = "S2_storerh_rr";
23288 let opNewValue = 4;
23290 def S4_pstorerhnewfnew_zomap : HInst<
23292 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23293 "if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23294 tc_e7d02c66, TypeMAPPING> {
23296 let isCodeGenOnly = 1;
23297 let opNewValue = 2;
23299 def S4_pstorerhnewt_abs : HInst<
23301 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23302 "if ($Pv4) memh(#$Ii) = $Nt8.new",
23303 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
23304 let Inst{2-2} = 0b0;
23305 let Inst{7-7} = 0b1;
23306 let Inst{13-11} = 0b001;
23307 let Inst{31-18} = 0b10101111101000;
23308 let isPredicated = 1;
23309 let addrMode = Absolute;
23310 let accessSize = HalfWordAccess;
23312 let isNewValue = 1;
23313 let isExtended = 1;
23314 let isRestrictNoSlot1Store = 1;
23316 let CextOpcode = "S2_storerh";
23317 let BaseOpcode = "S2_storerhabs";
23318 let DecoderNamespace = "MustExtend";
23319 let isExtendable = 1;
23320 let opExtendable = 1;
23321 let isExtentSigned = 0;
23322 let opExtentBits = 6;
23323 let opExtentAlign = 0;
23324 let opNewValue = 2;
23326 def S4_pstorerhnewt_rr : HInst<
23328 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23329 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23330 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
23331 let Inst{4-3} = 0b01;
23332 let Inst{31-21} = 0b00110100101;
23333 let isPredicated = 1;
23334 let addrMode = BaseRegOffset;
23335 let accessSize = HalfWordAccess;
23337 let isNewValue = 1;
23338 let isRestrictNoSlot1Store = 1;
23340 let CextOpcode = "S2_storerh";
23341 let InputType = "reg";
23342 let BaseOpcode = "S2_storerh_rr";
23343 let opNewValue = 4;
23345 def S4_pstorerhnewtnew_abs : HInst<
23347 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23348 "if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23349 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
23350 let Inst{2-2} = 0b0;
23351 let Inst{7-7} = 0b1;
23352 let Inst{13-11} = 0b101;
23353 let Inst{31-18} = 0b10101111101000;
23354 let isPredicated = 1;
23355 let addrMode = Absolute;
23356 let accessSize = HalfWordAccess;
23358 let isPredicatedNew = 1;
23359 let isNewValue = 1;
23360 let isExtended = 1;
23361 let isRestrictNoSlot1Store = 1;
23363 let CextOpcode = "S2_storerh";
23364 let BaseOpcode = "S2_storerhabs";
23365 let DecoderNamespace = "MustExtend";
23366 let isExtendable = 1;
23367 let opExtendable = 1;
23368 let isExtentSigned = 0;
23369 let opExtentBits = 6;
23370 let opExtentAlign = 0;
23371 let opNewValue = 2;
23373 def S4_pstorerhnewtnew_io : HInst<
23375 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23376 "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23377 tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
23378 let Inst{2-2} = 0b0;
23379 let Inst{12-11} = 0b01;
23380 let Inst{31-21} = 0b01000010101;
23381 let isPredicated = 1;
23382 let addrMode = BaseImmOffset;
23383 let accessSize = HalfWordAccess;
23385 let isPredicatedNew = 1;
23386 let isNewValue = 1;
23387 let isRestrictNoSlot1Store = 1;
23389 let CextOpcode = "S2_storerh";
23390 let InputType = "imm";
23391 let BaseOpcode = "S2_storerh_io";
23392 let isExtendable = 1;
23393 let opExtendable = 2;
23394 let isExtentSigned = 0;
23395 let opExtentBits = 7;
23396 let opExtentAlign = 1;
23397 let opNewValue = 3;
23399 def S4_pstorerhnewtnew_rr : HInst<
23401 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23402 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23403 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
23404 let Inst{4-3} = 0b01;
23405 let Inst{31-21} = 0b00110110101;
23406 let isPredicated = 1;
23407 let addrMode = BaseRegOffset;
23408 let accessSize = HalfWordAccess;
23410 let isPredicatedNew = 1;
23411 let isNewValue = 1;
23412 let isRestrictNoSlot1Store = 1;
23414 let CextOpcode = "S2_storerh";
23415 let InputType = "reg";
23416 let BaseOpcode = "S2_storerh_rr";
23417 let opNewValue = 4;
23419 def S4_pstorerhnewtnew_zomap : HInst<
23421 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23422 "if ($Pv4.new) memh($Rs32) = $Nt8.new",
23423 tc_e7d02c66, TypeMAPPING> {
23425 let isCodeGenOnly = 1;
23426 let opNewValue = 2;
23428 def S4_pstorerht_abs : HInst<
23430 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23431 "if ($Pv4) memh(#$Ii) = $Rt32",
23432 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
23433 let Inst{2-2} = 0b0;
23434 let Inst{7-7} = 0b1;
23435 let Inst{13-13} = 0b0;
23436 let Inst{31-18} = 0b10101111010000;
23437 let isPredicated = 1;
23438 let addrMode = Absolute;
23439 let accessSize = HalfWordAccess;
23440 let isExtended = 1;
23442 let CextOpcode = "S2_storerh";
23443 let BaseOpcode = "S2_storerhabs";
23444 let isNVStorable = 1;
23445 let DecoderNamespace = "MustExtend";
23446 let isExtendable = 1;
23447 let opExtendable = 1;
23448 let isExtentSigned = 0;
23449 let opExtentBits = 6;
23450 let opExtentAlign = 0;
23452 def S4_pstorerht_rr : HInst<
23454 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23455 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23456 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
23457 let Inst{31-21} = 0b00110100010;
23458 let isPredicated = 1;
23459 let addrMode = BaseRegOffset;
23460 let accessSize = HalfWordAccess;
23462 let CextOpcode = "S2_storerh";
23463 let InputType = "reg";
23464 let BaseOpcode = "S2_storerh_rr";
23465 let isNVStorable = 1;
23467 def S4_pstorerhtnew_abs : HInst<
23469 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23470 "if ($Pv4.new) memh(#$Ii) = $Rt32",
23471 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
23472 let Inst{2-2} = 0b0;
23473 let Inst{7-7} = 0b1;
23474 let Inst{13-13} = 0b1;
23475 let Inst{31-18} = 0b10101111010000;
23476 let isPredicated = 1;
23477 let addrMode = Absolute;
23478 let accessSize = HalfWordAccess;
23479 let isPredicatedNew = 1;
23480 let isExtended = 1;
23482 let CextOpcode = "S2_storerh";
23483 let BaseOpcode = "S2_storerhabs";
23484 let isNVStorable = 1;
23485 let DecoderNamespace = "MustExtend";
23486 let isExtendable = 1;
23487 let opExtendable = 1;
23488 let isExtentSigned = 0;
23489 let opExtentBits = 6;
23490 let opExtentAlign = 0;
23492 def S4_pstorerhtnew_io : HInst<
23494 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23495 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23496 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23497 let Inst{2-2} = 0b0;
23498 let Inst{31-21} = 0b01000010010;
23499 let isPredicated = 1;
23500 let addrMode = BaseImmOffset;
23501 let accessSize = HalfWordAccess;
23502 let isPredicatedNew = 1;
23504 let CextOpcode = "S2_storerh";
23505 let InputType = "imm";
23506 let BaseOpcode = "S2_storerh_io";
23507 let isNVStorable = 1;
23508 let isExtendable = 1;
23509 let opExtendable = 2;
23510 let isExtentSigned = 0;
23511 let opExtentBits = 7;
23512 let opExtentAlign = 1;
23514 def S4_pstorerhtnew_rr : HInst<
23516 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23517 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23518 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
23519 let Inst{31-21} = 0b00110110010;
23520 let isPredicated = 1;
23521 let addrMode = BaseRegOffset;
23522 let accessSize = HalfWordAccess;
23523 let isPredicatedNew = 1;
23525 let CextOpcode = "S2_storerh";
23526 let InputType = "reg";
23527 let BaseOpcode = "S2_storerh_rr";
23528 let isNVStorable = 1;
23530 def S4_pstorerhtnew_zomap : HInst<
23532 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23533 "if ($Pv4.new) memh($Rs32) = $Rt32",
23534 tc_f86c328a, TypeMAPPING> {
23536 let isCodeGenOnly = 1;
23538 def S4_pstorerif_abs : HInst<
23540 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23541 "if (!$Pv4) memw(#$Ii) = $Rt32",
23542 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
23543 let Inst{2-2} = 0b1;
23544 let Inst{7-7} = 0b1;
23545 let Inst{13-13} = 0b0;
23546 let Inst{31-18} = 0b10101111100000;
23547 let isPredicated = 1;
23548 let isPredicatedFalse = 1;
23549 let addrMode = Absolute;
23550 let accessSize = WordAccess;
23551 let isExtended = 1;
23553 let CextOpcode = "S2_storeri";
23554 let BaseOpcode = "S2_storeriabs";
23555 let isNVStorable = 1;
23556 let DecoderNamespace = "MustExtend";
23557 let isExtendable = 1;
23558 let opExtendable = 1;
23559 let isExtentSigned = 0;
23560 let opExtentBits = 6;
23561 let opExtentAlign = 0;
23563 def S4_pstorerif_rr : HInst<
23565 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23566 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
23567 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
23568 let Inst{31-21} = 0b00110101100;
23569 let isPredicated = 1;
23570 let isPredicatedFalse = 1;
23571 let addrMode = BaseRegOffset;
23572 let accessSize = WordAccess;
23574 let CextOpcode = "S2_storeri";
23575 let InputType = "reg";
23576 let BaseOpcode = "S2_storeri_rr";
23577 let isNVStorable = 1;
23579 def S4_pstorerifnew_abs : HInst<
23581 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23582 "if (!$Pv4.new) memw(#$Ii) = $Rt32",
23583 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
23584 let Inst{2-2} = 0b1;
23585 let Inst{7-7} = 0b1;
23586 let Inst{13-13} = 0b1;
23587 let Inst{31-18} = 0b10101111100000;
23588 let isPredicated = 1;
23589 let isPredicatedFalse = 1;
23590 let addrMode = Absolute;
23591 let accessSize = WordAccess;
23592 let isPredicatedNew = 1;
23593 let isExtended = 1;
23595 let CextOpcode = "S2_storeri";
23596 let BaseOpcode = "S2_storeriabs";
23597 let isNVStorable = 1;
23598 let DecoderNamespace = "MustExtend";
23599 let isExtendable = 1;
23600 let opExtendable = 1;
23601 let isExtentSigned = 0;
23602 let opExtentBits = 6;
23603 let opExtentAlign = 0;
23605 def S4_pstorerifnew_io : HInst<
23607 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
23608 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
23609 tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
23610 let Inst{2-2} = 0b0;
23611 let Inst{31-21} = 0b01000110100;
23612 let isPredicated = 1;
23613 let isPredicatedFalse = 1;
23614 let addrMode = BaseImmOffset;
23615 let accessSize = WordAccess;
23616 let isPredicatedNew = 1;
23618 let CextOpcode = "S2_storeri";
23619 let InputType = "imm";
23620 let BaseOpcode = "S2_storeri_io";
23621 let isNVStorable = 1;
23622 let isExtendable = 1;
23623 let opExtendable = 2;
23624 let isExtentSigned = 0;
23625 let opExtentBits = 8;
23626 let opExtentAlign = 2;
23628 def S4_pstorerifnew_rr : HInst<
23630 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23631 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
23632 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
23633 let Inst{31-21} = 0b00110111100;
23634 let isPredicated = 1;
23635 let isPredicatedFalse = 1;
23636 let addrMode = BaseRegOffset;
23637 let accessSize = WordAccess;
23638 let isPredicatedNew = 1;
23640 let CextOpcode = "S2_storeri";
23641 let InputType = "reg";
23642 let BaseOpcode = "S2_storeri_rr";
23643 let isNVStorable = 1;
23645 def S4_pstorerifnew_zomap : HInst<
23647 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23648 "if (!$Pv4.new) memw($Rs32) = $Rt32",
23649 tc_f86c328a, TypeMAPPING> {
23651 let isCodeGenOnly = 1;
23653 def S4_pstorerinewf_abs : HInst<
23655 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23656 "if (!$Pv4) memw(#$Ii) = $Nt8.new",
23657 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
23658 let Inst{2-2} = 0b1;
23659 let Inst{7-7} = 0b1;
23660 let Inst{13-11} = 0b010;
23661 let Inst{31-18} = 0b10101111101000;
23662 let isPredicated = 1;
23663 let isPredicatedFalse = 1;
23664 let addrMode = Absolute;
23665 let accessSize = WordAccess;
23667 let isNewValue = 1;
23668 let isExtended = 1;
23669 let isRestrictNoSlot1Store = 1;
23671 let CextOpcode = "S2_storeri";
23672 let BaseOpcode = "S2_storeriabs";
23673 let DecoderNamespace = "MustExtend";
23674 let isExtendable = 1;
23675 let opExtendable = 1;
23676 let isExtentSigned = 0;
23677 let opExtentBits = 6;
23678 let opExtentAlign = 0;
23679 let opNewValue = 2;
23681 def S4_pstorerinewf_rr : HInst<
23683 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23684 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23685 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
23686 let Inst{4-3} = 0b10;
23687 let Inst{31-21} = 0b00110101101;
23688 let isPredicated = 1;
23689 let isPredicatedFalse = 1;
23690 let addrMode = BaseRegOffset;
23691 let accessSize = WordAccess;
23693 let isNewValue = 1;
23694 let isRestrictNoSlot1Store = 1;
23696 let CextOpcode = "S2_storeri";
23697 let InputType = "reg";
23698 let BaseOpcode = "S2_storeri_rr";
23699 let opNewValue = 4;
23701 def S4_pstorerinewfnew_abs : HInst<
23703 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23704 "if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
23705 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
23706 let Inst{2-2} = 0b1;
23707 let Inst{7-7} = 0b1;
23708 let Inst{13-11} = 0b110;
23709 let Inst{31-18} = 0b10101111101000;
23710 let isPredicated = 1;
23711 let isPredicatedFalse = 1;
23712 let addrMode = Absolute;
23713 let accessSize = WordAccess;
23715 let isPredicatedNew = 1;
23716 let isNewValue = 1;
23717 let isExtended = 1;
23718 let isRestrictNoSlot1Store = 1;
23720 let CextOpcode = "S2_storeri";
23721 let BaseOpcode = "S2_storeriabs";
23722 let DecoderNamespace = "MustExtend";
23723 let isExtendable = 1;
23724 let opExtendable = 1;
23725 let isExtentSigned = 0;
23726 let opExtentBits = 6;
23727 let opExtentAlign = 0;
23728 let opNewValue = 2;
23730 def S4_pstorerinewfnew_io : HInst<
23732 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
23733 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
23734 tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
23735 let Inst{2-2} = 0b0;
23736 let Inst{12-11} = 0b10;
23737 let Inst{31-21} = 0b01000110101;
23738 let isPredicated = 1;
23739 let isPredicatedFalse = 1;
23740 let addrMode = BaseImmOffset;
23741 let accessSize = WordAccess;
23743 let isPredicatedNew = 1;
23744 let isNewValue = 1;
23745 let isRestrictNoSlot1Store = 1;
23747 let CextOpcode = "S2_storeri";
23748 let InputType = "imm";
23749 let BaseOpcode = "S2_storeri_io";
23750 let isExtendable = 1;
23751 let opExtendable = 2;
23752 let isExtentSigned = 0;
23753 let opExtentBits = 8;
23754 let opExtentAlign = 2;
23755 let opNewValue = 3;
23757 def S4_pstorerinewfnew_rr : HInst<
23759 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23760 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23761 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
23762 let Inst{4-3} = 0b10;
23763 let Inst{31-21} = 0b00110111101;
23764 let isPredicated = 1;
23765 let isPredicatedFalse = 1;
23766 let addrMode = BaseRegOffset;
23767 let accessSize = WordAccess;
23769 let isPredicatedNew = 1;
23770 let isNewValue = 1;
23771 let isRestrictNoSlot1Store = 1;
23773 let CextOpcode = "S2_storeri";
23774 let InputType = "reg";
23775 let BaseOpcode = "S2_storeri_rr";
23776 let opNewValue = 4;
23778 def S4_pstorerinewfnew_zomap : HInst<
23780 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23781 "if (!$Pv4.new) memw($Rs32) = $Nt8.new",
23782 tc_e7d02c66, TypeMAPPING> {
23784 let isCodeGenOnly = 1;
23785 let opNewValue = 2;
23787 def S4_pstorerinewt_abs : HInst<
23789 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23790 "if ($Pv4) memw(#$Ii) = $Nt8.new",
23791 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
23792 let Inst{2-2} = 0b0;
23793 let Inst{7-7} = 0b1;
23794 let Inst{13-11} = 0b010;
23795 let Inst{31-18} = 0b10101111101000;
23796 let isPredicated = 1;
23797 let addrMode = Absolute;
23798 let accessSize = WordAccess;
23800 let isNewValue = 1;
23801 let isExtended = 1;
23802 let isRestrictNoSlot1Store = 1;
23804 let CextOpcode = "S2_storeri";
23805 let BaseOpcode = "S2_storeriabs";
23806 let DecoderNamespace = "MustExtend";
23807 let isExtendable = 1;
23808 let opExtendable = 1;
23809 let isExtentSigned = 0;
23810 let opExtentBits = 6;
23811 let opExtentAlign = 0;
23812 let opNewValue = 2;
23814 def S4_pstorerinewt_rr : HInst<
23816 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23817 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23818 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
23819 let Inst{4-3} = 0b10;
23820 let Inst{31-21} = 0b00110100101;
23821 let isPredicated = 1;
23822 let addrMode = BaseRegOffset;
23823 let accessSize = WordAccess;
23825 let isNewValue = 1;
23826 let isRestrictNoSlot1Store = 1;
23828 let CextOpcode = "S2_storeri";
23829 let InputType = "reg";
23830 let BaseOpcode = "S2_storeri_rr";
23831 let opNewValue = 4;
23833 def S4_pstorerinewtnew_abs : HInst<
23835 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23836 "if ($Pv4.new) memw(#$Ii) = $Nt8.new",
23837 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
23838 let Inst{2-2} = 0b0;
23839 let Inst{7-7} = 0b1;
23840 let Inst{13-11} = 0b110;
23841 let Inst{31-18} = 0b10101111101000;
23842 let isPredicated = 1;
23843 let addrMode = Absolute;
23844 let accessSize = WordAccess;
23846 let isPredicatedNew = 1;
23847 let isNewValue = 1;
23848 let isExtended = 1;
23849 let isRestrictNoSlot1Store = 1;
23851 let CextOpcode = "S2_storeri";
23852 let BaseOpcode = "S2_storeriabs";
23853 let DecoderNamespace = "MustExtend";
23854 let isExtendable = 1;
23855 let opExtendable = 1;
23856 let isExtentSigned = 0;
23857 let opExtentBits = 6;
23858 let opExtentAlign = 0;
23859 let opNewValue = 2;
23861 def S4_pstorerinewtnew_io : HInst<
23863 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
23864 "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
23865 tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
23866 let Inst{2-2} = 0b0;
23867 let Inst{12-11} = 0b10;
23868 let Inst{31-21} = 0b01000010101;
23869 let isPredicated = 1;
23870 let addrMode = BaseImmOffset;
23871 let accessSize = WordAccess;
23873 let isPredicatedNew = 1;
23874 let isNewValue = 1;
23875 let isRestrictNoSlot1Store = 1;
23877 let CextOpcode = "S2_storeri";
23878 let InputType = "imm";
23879 let BaseOpcode = "S2_storeri_io";
23880 let isExtendable = 1;
23881 let opExtendable = 2;
23882 let isExtentSigned = 0;
23883 let opExtentBits = 8;
23884 let opExtentAlign = 2;
23885 let opNewValue = 3;
23887 def S4_pstorerinewtnew_rr : HInst<
23889 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23890 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23891 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
23892 let Inst{4-3} = 0b10;
23893 let Inst{31-21} = 0b00110110101;
23894 let isPredicated = 1;
23895 let addrMode = BaseRegOffset;
23896 let accessSize = WordAccess;
23898 let isPredicatedNew = 1;
23899 let isNewValue = 1;
23900 let isRestrictNoSlot1Store = 1;
23902 let CextOpcode = "S2_storeri";
23903 let InputType = "reg";
23904 let BaseOpcode = "S2_storeri_rr";
23905 let opNewValue = 4;
23907 def S4_pstorerinewtnew_zomap : HInst<
23909 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23910 "if ($Pv4.new) memw($Rs32) = $Nt8.new",
23911 tc_e7d02c66, TypeMAPPING> {
23913 let isCodeGenOnly = 1;
23914 let opNewValue = 2;
23916 def S4_pstorerit_abs : HInst<
23918 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23919 "if ($Pv4) memw(#$Ii) = $Rt32",
23920 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
23921 let Inst{2-2} = 0b0;
23922 let Inst{7-7} = 0b1;
23923 let Inst{13-13} = 0b0;
23924 let Inst{31-18} = 0b10101111100000;
23925 let isPredicated = 1;
23926 let addrMode = Absolute;
23927 let accessSize = WordAccess;
23928 let isExtended = 1;
23930 let CextOpcode = "S2_storeri";
23931 let BaseOpcode = "S2_storeriabs";
23932 let isNVStorable = 1;
23933 let DecoderNamespace = "MustExtend";
23934 let isExtendable = 1;
23935 let opExtendable = 1;
23936 let isExtentSigned = 0;
23937 let opExtentBits = 6;
23938 let opExtentAlign = 0;
23940 def S4_pstorerit_rr : HInst<
23942 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23943 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
23944 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
23945 let Inst{31-21} = 0b00110100100;
23946 let isPredicated = 1;
23947 let addrMode = BaseRegOffset;
23948 let accessSize = WordAccess;
23950 let CextOpcode = "S2_storeri";
23951 let InputType = "reg";
23952 let BaseOpcode = "S2_storeri_rr";
23953 let isNVStorable = 1;
23955 def S4_pstoreritnew_abs : HInst<
23957 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23958 "if ($Pv4.new) memw(#$Ii) = $Rt32",
23959 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
23960 let Inst{2-2} = 0b0;
23961 let Inst{7-7} = 0b1;
23962 let Inst{13-13} = 0b1;
23963 let Inst{31-18} = 0b10101111100000;
23964 let isPredicated = 1;
23965 let addrMode = Absolute;
23966 let accessSize = WordAccess;
23967 let isPredicatedNew = 1;
23968 let isExtended = 1;
23970 let CextOpcode = "S2_storeri";
23971 let BaseOpcode = "S2_storeriabs";
23972 let isNVStorable = 1;
23973 let DecoderNamespace = "MustExtend";
23974 let isExtendable = 1;
23975 let opExtendable = 1;
23976 let isExtentSigned = 0;
23977 let opExtentBits = 6;
23978 let opExtentAlign = 0;
23980 def S4_pstoreritnew_io : HInst<
23982 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
23983 "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
23984 tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
23985 let Inst{2-2} = 0b0;
23986 let Inst{31-21} = 0b01000010100;
23987 let isPredicated = 1;
23988 let addrMode = BaseImmOffset;
23989 let accessSize = WordAccess;
23990 let isPredicatedNew = 1;
23992 let CextOpcode = "S2_storeri";
23993 let InputType = "imm";
23994 let BaseOpcode = "S2_storeri_io";
23995 let isNVStorable = 1;
23996 let isExtendable = 1;
23997 let opExtendable = 2;
23998 let isExtentSigned = 0;
23999 let opExtentBits = 8;
24000 let opExtentAlign = 2;
24002 def S4_pstoreritnew_rr : HInst<
24004 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24005 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24006 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
24007 let Inst{31-21} = 0b00110110100;
24008 let isPredicated = 1;
24009 let addrMode = BaseRegOffset;
24010 let accessSize = WordAccess;
24011 let isPredicatedNew = 1;
24013 let CextOpcode = "S2_storeri";
24014 let InputType = "reg";
24015 let BaseOpcode = "S2_storeri_rr";
24016 let isNVStorable = 1;
24018 def S4_pstoreritnew_zomap : HInst<
24020 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24021 "if ($Pv4.new) memw($Rs32) = $Rt32",
24022 tc_f86c328a, TypeMAPPING> {
24024 let isCodeGenOnly = 1;
24026 def S4_stored_locked : HInst<
24027 (outs PredRegs:$Pd4),
24028 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24029 "memd_locked($Rs32,$Pd4) = $Rtt32",
24030 tc_1372bca1, TypeST>, Enc_d7dc10 {
24031 let Inst{7-2} = 0b000000;
24032 let Inst{13-13} = 0b0;
24033 let Inst{31-21} = 0b10100000111;
24034 let accessSize = DoubleWordAccess;
24035 let isPredicateLate = 1;
24039 def S4_storeirb_io : HInst<
24041 (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24042 "memb($Rs32+#$Ii) = #$II",
24043 tc_05b6c987, TypeST>, Enc_8203bb, PredNewRel {
24044 let Inst{31-21} = 0b00111100000;
24045 let addrMode = BaseImmOffset;
24046 let accessSize = ByteAccess;
24048 let CextOpcode = "S2_storerb";
24049 let InputType = "imm";
24050 let BaseOpcode = "S4_storeirb_io";
24051 let isPredicable = 1;
24052 let isExtendable = 1;
24053 let opExtendable = 2;
24054 let isExtentSigned = 1;
24055 let opExtentBits = 8;
24056 let opExtentAlign = 0;
24058 def S4_storeirb_zomap : HInst<
24060 (ins IntRegs:$Rs32, s8_0Imm:$II),
24061 "memb($Rs32) = #$II",
24062 tc_05b6c987, TypeMAPPING> {
24064 let isCodeGenOnly = 1;
24066 def S4_storeirbf_io : HInst<
24068 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24069 "if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24070 tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
24071 let Inst{31-21} = 0b00111000100;
24072 let isPredicated = 1;
24073 let isPredicatedFalse = 1;
24074 let addrMode = BaseImmOffset;
24075 let accessSize = ByteAccess;
24077 let CextOpcode = "S2_storerb";
24078 let InputType = "imm";
24079 let BaseOpcode = "S4_storeirb_io";
24080 let isExtendable = 1;
24081 let opExtendable = 3;
24082 let isExtentSigned = 1;
24083 let opExtentBits = 6;
24084 let opExtentAlign = 0;
24086 def S4_storeirbf_zomap : HInst<
24088 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24089 "if (!$Pv4) memb($Rs32) = #$II",
24090 tc_8b15472a, TypeMAPPING> {
24092 let isCodeGenOnly = 1;
24094 def S4_storeirbfnew_io : HInst<
24096 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24097 "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24098 tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
24099 let Inst{31-21} = 0b00111001100;
24100 let isPredicated = 1;
24101 let isPredicatedFalse = 1;
24102 let addrMode = BaseImmOffset;
24103 let accessSize = ByteAccess;
24104 let isPredicatedNew = 1;
24106 let CextOpcode = "S2_storerb";
24107 let InputType = "imm";
24108 let BaseOpcode = "S4_storeirb_io";
24109 let isExtendable = 1;
24110 let opExtendable = 3;
24111 let isExtentSigned = 1;
24112 let opExtentBits = 6;
24113 let opExtentAlign = 0;
24115 def S4_storeirbfnew_zomap : HInst<
24117 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24118 "if (!$Pv4.new) memb($Rs32) = #$II",
24119 tc_f86c328a, TypeMAPPING> {
24121 let isCodeGenOnly = 1;
24123 def S4_storeirbt_io : HInst<
24125 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24126 "if ($Pv4) memb($Rs32+#$Ii) = #$II",
24127 tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
24128 let Inst{31-21} = 0b00111000000;
24129 let isPredicated = 1;
24130 let addrMode = BaseImmOffset;
24131 let accessSize = ByteAccess;
24133 let CextOpcode = "S2_storerb";
24134 let InputType = "imm";
24135 let BaseOpcode = "S4_storeirb_io";
24136 let isExtendable = 1;
24137 let opExtendable = 3;
24138 let isExtentSigned = 1;
24139 let opExtentBits = 6;
24140 let opExtentAlign = 0;
24142 def S4_storeirbt_zomap : HInst<
24144 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24145 "if ($Pv4) memb($Rs32) = #$II",
24146 tc_8b15472a, TypeMAPPING> {
24148 let isCodeGenOnly = 1;
24150 def S4_storeirbtnew_io : HInst<
24152 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24153 "if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24154 tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
24155 let Inst{31-21} = 0b00111001000;
24156 let isPredicated = 1;
24157 let addrMode = BaseImmOffset;
24158 let accessSize = ByteAccess;
24159 let isPredicatedNew = 1;
24161 let CextOpcode = "S2_storerb";
24162 let InputType = "imm";
24163 let BaseOpcode = "S4_storeirb_io";
24164 let isExtendable = 1;
24165 let opExtendable = 3;
24166 let isExtentSigned = 1;
24167 let opExtentBits = 6;
24168 let opExtentAlign = 0;
24170 def S4_storeirbtnew_zomap : HInst<
24172 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24173 "if ($Pv4.new) memb($Rs32) = #$II",
24174 tc_f86c328a, TypeMAPPING> {
24176 let isCodeGenOnly = 1;
24178 def S4_storeirh_io : HInst<
24180 (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24181 "memh($Rs32+#$Ii) = #$II",
24182 tc_05b6c987, TypeST>, Enc_a803e0, PredNewRel {
24183 let Inst{31-21} = 0b00111100001;
24184 let addrMode = BaseImmOffset;
24185 let accessSize = HalfWordAccess;
24187 let CextOpcode = "S2_storerh";
24188 let InputType = "imm";
24189 let BaseOpcode = "S4_storeirh_io";
24190 let isPredicable = 1;
24191 let isExtendable = 1;
24192 let opExtendable = 2;
24193 let isExtentSigned = 1;
24194 let opExtentBits = 8;
24195 let opExtentAlign = 0;
24197 def S4_storeirh_zomap : HInst<
24199 (ins IntRegs:$Rs32, s8_0Imm:$II),
24200 "memh($Rs32) = #$II",
24201 tc_05b6c987, TypeMAPPING> {
24203 let isCodeGenOnly = 1;
24205 def S4_storeirhf_io : HInst<
24207 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24208 "if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24209 tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
24210 let Inst{31-21} = 0b00111000101;
24211 let isPredicated = 1;
24212 let isPredicatedFalse = 1;
24213 let addrMode = BaseImmOffset;
24214 let accessSize = HalfWordAccess;
24216 let CextOpcode = "S2_storerh";
24217 let InputType = "imm";
24218 let BaseOpcode = "S4_storeirh_io";
24219 let isExtendable = 1;
24220 let opExtendable = 3;
24221 let isExtentSigned = 1;
24222 let opExtentBits = 6;
24223 let opExtentAlign = 0;
24225 def S4_storeirhf_zomap : HInst<
24227 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24228 "if (!$Pv4) memh($Rs32) = #$II",
24229 tc_8b15472a, TypeMAPPING> {
24231 let isCodeGenOnly = 1;
24233 def S4_storeirhfnew_io : HInst<
24235 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24236 "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24237 tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
24238 let Inst{31-21} = 0b00111001101;
24239 let isPredicated = 1;
24240 let isPredicatedFalse = 1;
24241 let addrMode = BaseImmOffset;
24242 let accessSize = HalfWordAccess;
24243 let isPredicatedNew = 1;
24245 let CextOpcode = "S2_storerh";
24246 let InputType = "imm";
24247 let BaseOpcode = "S4_storeirh_io";
24248 let isExtendable = 1;
24249 let opExtendable = 3;
24250 let isExtentSigned = 1;
24251 let opExtentBits = 6;
24252 let opExtentAlign = 0;
24254 def S4_storeirhfnew_zomap : HInst<
24256 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24257 "if (!$Pv4.new) memh($Rs32) = #$II",
24258 tc_f86c328a, TypeMAPPING> {
24260 let isCodeGenOnly = 1;
24262 def S4_storeirht_io : HInst<
24264 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24265 "if ($Pv4) memh($Rs32+#$Ii) = #$II",
24266 tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
24267 let Inst{31-21} = 0b00111000001;
24268 let isPredicated = 1;
24269 let addrMode = BaseImmOffset;
24270 let accessSize = HalfWordAccess;
24272 let CextOpcode = "S2_storerh";
24273 let InputType = "imm";
24274 let BaseOpcode = "S4_storeirh_io";
24275 let isExtendable = 1;
24276 let opExtendable = 3;
24277 let isExtentSigned = 1;
24278 let opExtentBits = 6;
24279 let opExtentAlign = 0;
24281 def S4_storeirht_zomap : HInst<
24283 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24284 "if ($Pv4) memh($Rs32) = #$II",
24285 tc_8b15472a, TypeMAPPING> {
24287 let isCodeGenOnly = 1;
24289 def S4_storeirhtnew_io : HInst<
24291 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24292 "if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24293 tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
24294 let Inst{31-21} = 0b00111001001;
24295 let isPredicated = 1;
24296 let addrMode = BaseImmOffset;
24297 let accessSize = HalfWordAccess;
24298 let isPredicatedNew = 1;
24300 let CextOpcode = "S2_storerh";
24301 let InputType = "imm";
24302 let BaseOpcode = "S4_storeirh_io";
24303 let isExtendable = 1;
24304 let opExtendable = 3;
24305 let isExtentSigned = 1;
24306 let opExtentBits = 6;
24307 let opExtentAlign = 0;
24309 def S4_storeirhtnew_zomap : HInst<
24311 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24312 "if ($Pv4.new) memh($Rs32) = #$II",
24313 tc_f86c328a, TypeMAPPING> {
24315 let isCodeGenOnly = 1;
24317 def S4_storeiri_io : HInst<
24319 (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24320 "memw($Rs32+#$Ii) = #$II",
24321 tc_05b6c987, TypeST>, Enc_f37377, PredNewRel {
24322 let Inst{31-21} = 0b00111100010;
24323 let addrMode = BaseImmOffset;
24324 let accessSize = WordAccess;
24326 let CextOpcode = "S2_storeri";
24327 let InputType = "imm";
24328 let BaseOpcode = "S4_storeiri_io";
24329 let isPredicable = 1;
24330 let isExtendable = 1;
24331 let opExtendable = 2;
24332 let isExtentSigned = 1;
24333 let opExtentBits = 8;
24334 let opExtentAlign = 0;
24336 def S4_storeiri_zomap : HInst<
24338 (ins IntRegs:$Rs32, s8_0Imm:$II),
24339 "memw($Rs32) = #$II",
24340 tc_05b6c987, TypeMAPPING> {
24342 let isCodeGenOnly = 1;
24344 def S4_storeirif_io : HInst<
24346 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24347 "if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24348 tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
24349 let Inst{31-21} = 0b00111000110;
24350 let isPredicated = 1;
24351 let isPredicatedFalse = 1;
24352 let addrMode = BaseImmOffset;
24353 let accessSize = WordAccess;
24355 let CextOpcode = "S2_storeri";
24356 let InputType = "imm";
24357 let BaseOpcode = "S4_storeiri_io";
24358 let isExtendable = 1;
24359 let opExtendable = 3;
24360 let isExtentSigned = 1;
24361 let opExtentBits = 6;
24362 let opExtentAlign = 0;
24364 def S4_storeirif_zomap : HInst<
24366 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24367 "if (!$Pv4) memw($Rs32) = #$II",
24368 tc_8b15472a, TypeMAPPING> {
24370 let isCodeGenOnly = 1;
24372 def S4_storeirifnew_io : HInst<
24374 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24375 "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24376 tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
24377 let Inst{31-21} = 0b00111001110;
24378 let isPredicated = 1;
24379 let isPredicatedFalse = 1;
24380 let addrMode = BaseImmOffset;
24381 let accessSize = WordAccess;
24382 let isPredicatedNew = 1;
24384 let CextOpcode = "S2_storeri";
24385 let InputType = "imm";
24386 let BaseOpcode = "S4_storeiri_io";
24387 let isExtendable = 1;
24388 let opExtendable = 3;
24389 let isExtentSigned = 1;
24390 let opExtentBits = 6;
24391 let opExtentAlign = 0;
24393 def S4_storeirifnew_zomap : HInst<
24395 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24396 "if (!$Pv4.new) memw($Rs32) = #$II",
24397 tc_f86c328a, TypeMAPPING> {
24399 let isCodeGenOnly = 1;
24401 def S4_storeirit_io : HInst<
24403 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24404 "if ($Pv4) memw($Rs32+#$Ii) = #$II",
24405 tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
24406 let Inst{31-21} = 0b00111000010;
24407 let isPredicated = 1;
24408 let addrMode = BaseImmOffset;
24409 let accessSize = WordAccess;
24411 let CextOpcode = "S2_storeri";
24412 let InputType = "imm";
24413 let BaseOpcode = "S4_storeiri_io";
24414 let isExtendable = 1;
24415 let opExtendable = 3;
24416 let isExtentSigned = 1;
24417 let opExtentBits = 6;
24418 let opExtentAlign = 0;
24420 def S4_storeirit_zomap : HInst<
24422 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24423 "if ($Pv4) memw($Rs32) = #$II",
24424 tc_8b15472a, TypeMAPPING> {
24426 let isCodeGenOnly = 1;
24428 def S4_storeiritnew_io : HInst<
24430 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24431 "if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
24432 tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
24433 let Inst{31-21} = 0b00111001010;
24434 let isPredicated = 1;
24435 let addrMode = BaseImmOffset;
24436 let accessSize = WordAccess;
24437 let isPredicatedNew = 1;
24439 let CextOpcode = "S2_storeri";
24440 let InputType = "imm";
24441 let BaseOpcode = "S4_storeiri_io";
24442 let isExtendable = 1;
24443 let opExtendable = 3;
24444 let isExtentSigned = 1;
24445 let opExtentBits = 6;
24446 let opExtentAlign = 0;
24448 def S4_storeiritnew_zomap : HInst<
24450 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24451 "if ($Pv4.new) memw($Rs32) = #$II",
24452 tc_f86c328a, TypeMAPPING> {
24454 let isCodeGenOnly = 1;
24456 def S4_storerb_ap : HInst<
24457 (outs IntRegs:$Re32),
24458 (ins u32_0Imm:$II, IntRegs:$Rt32),
24459 "memb($Re32=#$II) = $Rt32",
24460 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
24461 let Inst{7-6} = 0b10;
24462 let Inst{13-13} = 0b0;
24463 let Inst{31-21} = 0b10101011000;
24464 let addrMode = AbsoluteSet;
24465 let accessSize = ByteAccess;
24466 let isExtended = 1;
24468 let BaseOpcode = "S2_storerb_ap";
24469 let isNVStorable = 1;
24470 let DecoderNamespace = "MustExtend";
24471 let isExtendable = 1;
24472 let opExtendable = 1;
24473 let isExtentSigned = 0;
24474 let opExtentBits = 6;
24475 let opExtentAlign = 0;
24477 def S4_storerb_rr : HInst<
24479 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24480 "memb($Rs32+$Ru32<<#$Ii) = $Rt32",
24481 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24482 let Inst{6-5} = 0b00;
24483 let Inst{31-21} = 0b00111011000;
24484 let addrMode = BaseRegOffset;
24485 let accessSize = ByteAccess;
24487 let CextOpcode = "S2_storerb";
24488 let InputType = "reg";
24489 let BaseOpcode = "S4_storerb_rr";
24490 let isNVStorable = 1;
24491 let isPredicable = 1;
24493 def S4_storerb_ur : HInst<
24495 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24496 "memb($Ru32<<#$Ii+#$II) = $Rt32",
24497 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24498 let Inst{7-7} = 0b1;
24499 let Inst{31-21} = 0b10101101000;
24500 let addrMode = BaseLongOffset;
24501 let accessSize = ByteAccess;
24502 let isExtended = 1;
24504 let CextOpcode = "S2_storerb";
24505 let InputType = "imm";
24506 let BaseOpcode = "S4_storerb_ur";
24507 let isNVStorable = 1;
24508 let DecoderNamespace = "MustExtend";
24509 let isExtendable = 1;
24510 let opExtendable = 2;
24511 let isExtentSigned = 0;
24512 let opExtentBits = 6;
24513 let opExtentAlign = 0;
24515 def S4_storerbnew_ap : HInst<
24516 (outs IntRegs:$Re32),
24517 (ins u32_0Imm:$II, IntRegs:$Nt8),
24518 "memb($Re32=#$II) = $Nt8.new",
24519 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
24520 let Inst{7-6} = 0b10;
24521 let Inst{13-11} = 0b000;
24522 let Inst{31-21} = 0b10101011101;
24523 let addrMode = AbsoluteSet;
24524 let accessSize = ByteAccess;
24526 let isNewValue = 1;
24527 let isExtended = 1;
24528 let isRestrictNoSlot1Store = 1;
24530 let BaseOpcode = "S2_storerb_ap";
24531 let DecoderNamespace = "MustExtend";
24532 let isExtendable = 1;
24533 let opExtendable = 1;
24534 let isExtentSigned = 0;
24535 let opExtentBits = 6;
24536 let opExtentAlign = 0;
24537 let opNewValue = 2;
24539 def S4_storerbnew_rr : HInst<
24541 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24542 "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24543 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
24544 let Inst{6-3} = 0b0000;
24545 let Inst{31-21} = 0b00111011101;
24546 let addrMode = BaseRegOffset;
24547 let accessSize = ByteAccess;
24549 let isNewValue = 1;
24550 let isRestrictNoSlot1Store = 1;
24552 let CextOpcode = "S2_storerb";
24553 let InputType = "reg";
24554 let BaseOpcode = "S4_storerb_rr";
24555 let isPredicable = 1;
24556 let opNewValue = 3;
24558 def S4_storerbnew_ur : HInst<
24560 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
24561 "memb($Ru32<<#$Ii+#$II) = $Nt8.new",
24562 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
24563 let Inst{7-7} = 0b1;
24564 let Inst{12-11} = 0b00;
24565 let Inst{31-21} = 0b10101101101;
24566 let addrMode = BaseLongOffset;
24567 let accessSize = ByteAccess;
24569 let isNewValue = 1;
24570 let isExtended = 1;
24571 let isRestrictNoSlot1Store = 1;
24573 let CextOpcode = "S2_storerb";
24574 let BaseOpcode = "S4_storerb_ur";
24575 let DecoderNamespace = "MustExtend";
24576 let isExtendable = 1;
24577 let opExtendable = 2;
24578 let isExtentSigned = 0;
24579 let opExtentBits = 6;
24580 let opExtentAlign = 0;
24581 let opNewValue = 3;
24583 def S4_storerd_ap : HInst<
24584 (outs IntRegs:$Re32),
24585 (ins u32_0Imm:$II, DoubleRegs:$Rtt32),
24586 "memd($Re32=#$II) = $Rtt32",
24587 tc_66888ded, TypeST>, Enc_c7a204 {
24588 let Inst{7-6} = 0b10;
24589 let Inst{13-13} = 0b0;
24590 let Inst{31-21} = 0b10101011110;
24591 let addrMode = AbsoluteSet;
24592 let accessSize = DoubleWordAccess;
24593 let isExtended = 1;
24595 let BaseOpcode = "S4_storerd_ap";
24596 let DecoderNamespace = "MustExtend";
24597 let isExtendable = 1;
24598 let opExtendable = 1;
24599 let isExtentSigned = 0;
24600 let opExtentBits = 6;
24601 let opExtentAlign = 0;
24603 def S4_storerd_rr : HInst<
24605 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
24606 "memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
24607 tc_d9709180, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
24608 let Inst{6-5} = 0b00;
24609 let Inst{31-21} = 0b00111011110;
24610 let addrMode = BaseRegOffset;
24611 let accessSize = DoubleWordAccess;
24613 let CextOpcode = "S2_storerd";
24614 let InputType = "reg";
24615 let BaseOpcode = "S2_storerd_rr";
24616 let isPredicable = 1;
24618 def S4_storerd_ur : HInst<
24620 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
24621 "memd($Ru32<<#$Ii+#$II) = $Rtt32",
24622 tc_0dc560de, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
24623 let Inst{7-7} = 0b1;
24624 let Inst{31-21} = 0b10101101110;
24625 let addrMode = BaseLongOffset;
24626 let accessSize = DoubleWordAccess;
24627 let isExtended = 1;
24629 let CextOpcode = "S2_storerd";
24630 let InputType = "imm";
24631 let BaseOpcode = "S2_storerd_ur";
24632 let DecoderNamespace = "MustExtend";
24633 let isExtendable = 1;
24634 let opExtendable = 2;
24635 let isExtentSigned = 0;
24636 let opExtentBits = 6;
24637 let opExtentAlign = 0;
24639 def S4_storerf_ap : HInst<
24640 (outs IntRegs:$Re32),
24641 (ins u32_0Imm:$II, IntRegs:$Rt32),
24642 "memh($Re32=#$II) = $Rt32.h",
24643 tc_66888ded, TypeST>, Enc_8bcba4 {
24644 let Inst{7-6} = 0b10;
24645 let Inst{13-13} = 0b0;
24646 let Inst{31-21} = 0b10101011011;
24647 let addrMode = AbsoluteSet;
24648 let accessSize = HalfWordAccess;
24649 let isExtended = 1;
24651 let BaseOpcode = "S4_storerf_ap";
24652 let DecoderNamespace = "MustExtend";
24653 let isExtendable = 1;
24654 let opExtendable = 1;
24655 let isExtentSigned = 0;
24656 let opExtentBits = 6;
24657 let opExtentAlign = 0;
24659 def S4_storerf_rr : HInst<
24661 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24662 "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
24663 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24664 let Inst{6-5} = 0b00;
24665 let Inst{31-21} = 0b00111011011;
24666 let addrMode = BaseRegOffset;
24667 let accessSize = HalfWordAccess;
24669 let CextOpcode = "S2_storerf";
24670 let InputType = "reg";
24671 let BaseOpcode = "S4_storerf_rr";
24672 let isPredicable = 1;
24674 def S4_storerf_ur : HInst<
24676 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24677 "memh($Ru32<<#$Ii+#$II) = $Rt32.h",
24678 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24679 let Inst{7-7} = 0b1;
24680 let Inst{31-21} = 0b10101101011;
24681 let addrMode = BaseLongOffset;
24682 let accessSize = HalfWordAccess;
24683 let isExtended = 1;
24685 let CextOpcode = "S2_storerf";
24686 let InputType = "imm";
24687 let BaseOpcode = "S4_storerf_rr";
24688 let DecoderNamespace = "MustExtend";
24689 let isExtendable = 1;
24690 let opExtendable = 2;
24691 let isExtentSigned = 0;
24692 let opExtentBits = 6;
24693 let opExtentAlign = 0;
24695 def S4_storerh_ap : HInst<
24696 (outs IntRegs:$Re32),
24697 (ins u32_0Imm:$II, IntRegs:$Rt32),
24698 "memh($Re32=#$II) = $Rt32",
24699 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
24700 let Inst{7-6} = 0b10;
24701 let Inst{13-13} = 0b0;
24702 let Inst{31-21} = 0b10101011010;
24703 let addrMode = AbsoluteSet;
24704 let accessSize = HalfWordAccess;
24705 let isExtended = 1;
24707 let BaseOpcode = "S2_storerh_ap";
24708 let isNVStorable = 1;
24709 let DecoderNamespace = "MustExtend";
24710 let isExtendable = 1;
24711 let opExtendable = 1;
24712 let isExtentSigned = 0;
24713 let opExtentBits = 6;
24714 let opExtentAlign = 0;
24716 def S4_storerh_rr : HInst<
24718 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24719 "memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24720 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24721 let Inst{6-5} = 0b00;
24722 let Inst{31-21} = 0b00111011010;
24723 let addrMode = BaseRegOffset;
24724 let accessSize = HalfWordAccess;
24726 let CextOpcode = "S2_storerh";
24727 let InputType = "reg";
24728 let BaseOpcode = "S2_storerh_rr";
24729 let isNVStorable = 1;
24730 let isPredicable = 1;
24732 def S4_storerh_ur : HInst<
24734 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24735 "memh($Ru32<<#$Ii+#$II) = $Rt32",
24736 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24737 let Inst{7-7} = 0b1;
24738 let Inst{31-21} = 0b10101101010;
24739 let addrMode = BaseLongOffset;
24740 let accessSize = HalfWordAccess;
24741 let isExtended = 1;
24743 let CextOpcode = "S2_storerh";
24744 let InputType = "imm";
24745 let BaseOpcode = "S2_storerh_ur";
24746 let isNVStorable = 1;
24747 let DecoderNamespace = "MustExtend";
24748 let isExtendable = 1;
24749 let opExtendable = 2;
24750 let isExtentSigned = 0;
24751 let opExtentBits = 6;
24752 let opExtentAlign = 0;
24754 def S4_storerhnew_ap : HInst<
24755 (outs IntRegs:$Re32),
24756 (ins u32_0Imm:$II, IntRegs:$Nt8),
24757 "memh($Re32=#$II) = $Nt8.new",
24758 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
24759 let Inst{7-6} = 0b10;
24760 let Inst{13-11} = 0b001;
24761 let Inst{31-21} = 0b10101011101;
24762 let addrMode = AbsoluteSet;
24763 let accessSize = HalfWordAccess;
24765 let isNewValue = 1;
24766 let isExtended = 1;
24767 let isRestrictNoSlot1Store = 1;
24769 let BaseOpcode = "S2_storerh_ap";
24770 let DecoderNamespace = "MustExtend";
24771 let isExtendable = 1;
24772 let opExtendable = 1;
24773 let isExtentSigned = 0;
24774 let opExtentBits = 6;
24775 let opExtentAlign = 0;
24776 let opNewValue = 2;
24778 def S4_storerhnew_rr : HInst<
24780 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24781 "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24782 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
24783 let Inst{6-3} = 0b0001;
24784 let Inst{31-21} = 0b00111011101;
24785 let addrMode = BaseRegOffset;
24786 let accessSize = HalfWordAccess;
24788 let isNewValue = 1;
24789 let isRestrictNoSlot1Store = 1;
24791 let CextOpcode = "S2_storerh";
24792 let InputType = "reg";
24793 let BaseOpcode = "S2_storerh_rr";
24794 let isPredicable = 1;
24795 let opNewValue = 3;
24797 def S4_storerhnew_ur : HInst<
24799 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
24800 "memh($Ru32<<#$Ii+#$II) = $Nt8.new",
24801 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
24802 let Inst{7-7} = 0b1;
24803 let Inst{12-11} = 0b01;
24804 let Inst{31-21} = 0b10101101101;
24805 let addrMode = BaseLongOffset;
24806 let accessSize = HalfWordAccess;
24808 let isNewValue = 1;
24809 let isExtended = 1;
24810 let isRestrictNoSlot1Store = 1;
24812 let CextOpcode = "S2_storerh";
24813 let BaseOpcode = "S2_storerh_ur";
24814 let DecoderNamespace = "MustExtend";
24815 let isExtendable = 1;
24816 let opExtendable = 2;
24817 let isExtentSigned = 0;
24818 let opExtentBits = 6;
24819 let opExtentAlign = 0;
24820 let opNewValue = 3;
24822 def S4_storeri_ap : HInst<
24823 (outs IntRegs:$Re32),
24824 (ins u32_0Imm:$II, IntRegs:$Rt32),
24825 "memw($Re32=#$II) = $Rt32",
24826 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
24827 let Inst{7-6} = 0b10;
24828 let Inst{13-13} = 0b0;
24829 let Inst{31-21} = 0b10101011100;
24830 let addrMode = AbsoluteSet;
24831 let accessSize = WordAccess;
24832 let isExtended = 1;
24834 let BaseOpcode = "S2_storeri_ap";
24835 let isNVStorable = 1;
24836 let DecoderNamespace = "MustExtend";
24837 let isExtendable = 1;
24838 let opExtendable = 1;
24839 let isExtentSigned = 0;
24840 let opExtentBits = 6;
24841 let opExtentAlign = 0;
24843 def S4_storeri_rr : HInst<
24845 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24846 "memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24847 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24848 let Inst{6-5} = 0b00;
24849 let Inst{31-21} = 0b00111011100;
24850 let addrMode = BaseRegOffset;
24851 let accessSize = WordAccess;
24853 let CextOpcode = "S2_storeri";
24854 let InputType = "reg";
24855 let BaseOpcode = "S2_storeri_rr";
24856 let isNVStorable = 1;
24857 let isPredicable = 1;
24859 def S4_storeri_ur : HInst<
24861 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24862 "memw($Ru32<<#$Ii+#$II) = $Rt32",
24863 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24864 let Inst{7-7} = 0b1;
24865 let Inst{31-21} = 0b10101101100;
24866 let addrMode = BaseLongOffset;
24867 let accessSize = WordAccess;
24868 let isExtended = 1;
24870 let CextOpcode = "S2_storeri";
24871 let InputType = "imm";
24872 let BaseOpcode = "S2_storeri_ur";
24873 let isNVStorable = 1;
24874 let DecoderNamespace = "MustExtend";
24875 let isExtendable = 1;
24876 let opExtendable = 2;
24877 let isExtentSigned = 0;
24878 let opExtentBits = 6;
24879 let opExtentAlign = 0;
24881 def S4_storerinew_ap : HInst<
24882 (outs IntRegs:$Re32),
24883 (ins u32_0Imm:$II, IntRegs:$Nt8),
24884 "memw($Re32=#$II) = $Nt8.new",
24885 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
24886 let Inst{7-6} = 0b10;
24887 let Inst{13-11} = 0b010;
24888 let Inst{31-21} = 0b10101011101;
24889 let addrMode = AbsoluteSet;
24890 let accessSize = WordAccess;
24892 let isNewValue = 1;
24893 let isExtended = 1;
24894 let isRestrictNoSlot1Store = 1;
24896 let BaseOpcode = "S2_storeri_ap";
24897 let DecoderNamespace = "MustExtend";
24898 let isExtendable = 1;
24899 let opExtendable = 1;
24900 let isExtentSigned = 0;
24901 let opExtentBits = 6;
24902 let opExtentAlign = 0;
24903 let opNewValue = 2;
24905 def S4_storerinew_rr : HInst<
24907 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24908 "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24909 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
24910 let Inst{6-3} = 0b0010;
24911 let Inst{31-21} = 0b00111011101;
24912 let addrMode = BaseRegOffset;
24913 let accessSize = WordAccess;
24915 let isNewValue = 1;
24916 let isRestrictNoSlot1Store = 1;
24918 let CextOpcode = "S2_storeri";
24919 let InputType = "reg";
24920 let BaseOpcode = "S2_storeri_rr";
24921 let isPredicable = 1;
24922 let opNewValue = 3;
24924 def S4_storerinew_ur : HInst<
24926 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
24927 "memw($Ru32<<#$Ii+#$II) = $Nt8.new",
24928 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
24929 let Inst{7-7} = 0b1;
24930 let Inst{12-11} = 0b10;
24931 let Inst{31-21} = 0b10101101101;
24932 let addrMode = BaseLongOffset;
24933 let accessSize = WordAccess;
24935 let isNewValue = 1;
24936 let isExtended = 1;
24937 let isRestrictNoSlot1Store = 1;
24939 let CextOpcode = "S2_storeri";
24940 let BaseOpcode = "S2_storeri_ur";
24941 let DecoderNamespace = "MustExtend";
24942 let isExtendable = 1;
24943 let opExtendable = 2;
24944 let isExtentSigned = 0;
24945 let opExtentBits = 6;
24946 let opExtentAlign = 0;
24947 let opNewValue = 3;
24949 def S4_subaddi : HInst<
24950 (outs IntRegs:$Rd32),
24951 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
24952 "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
24953 tc_c74f796f, TypeALU64>, Enc_8b8d61 {
24954 let Inst{31-23} = 0b110110111;
24955 let hasNewValue = 1;
24956 let opNewValue = 0;
24957 let prefersSlot3 = 1;
24958 let isExtendable = 1;
24959 let opExtendable = 2;
24960 let isExtentSigned = 1;
24961 let opExtentBits = 6;
24962 let opExtentAlign = 0;
24964 def S4_subi_asl_ri : HInst<
24965 (outs IntRegs:$Rx32),
24966 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
24967 "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
24968 tc_c74f796f, TypeALU64>, Enc_c31910 {
24969 let Inst{2-0} = 0b110;
24970 let Inst{4-4} = 0b0;
24971 let Inst{31-24} = 0b11011110;
24972 let hasNewValue = 1;
24973 let opNewValue = 0;
24974 let prefersSlot3 = 1;
24975 let isExtendable = 1;
24976 let opExtendable = 1;
24977 let isExtentSigned = 0;
24978 let opExtentBits = 8;
24979 let opExtentAlign = 0;
24980 let Constraints = "$Rx32 = $Rx32in";
24982 def S4_subi_lsr_ri : HInst<
24983 (outs IntRegs:$Rx32),
24984 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
24985 "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
24986 tc_c74f796f, TypeALU64>, Enc_c31910 {
24987 let Inst{2-0} = 0b110;
24988 let Inst{4-4} = 0b1;
24989 let Inst{31-24} = 0b11011110;
24990 let hasNewValue = 1;
24991 let opNewValue = 0;
24992 let prefersSlot3 = 1;
24993 let isExtendable = 1;
24994 let opExtendable = 1;
24995 let isExtentSigned = 0;
24996 let opExtentBits = 8;
24997 let opExtentAlign = 0;
24998 let Constraints = "$Rx32 = $Rx32in";
25000 def S4_vrcrotate : HInst<
25001 (outs DoubleRegs:$Rdd32),
25002 (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25003 "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25004 tc_b9c0b731, TypeS_3op>, Enc_645d54 {
25005 let Inst{7-6} = 0b11;
25006 let Inst{31-21} = 0b11000011110;
25007 let prefersSlot3 = 1;
25009 def S4_vrcrotate_acc : HInst<
25010 (outs DoubleRegs:$Rxx32),
25011 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25012 "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25013 tc_60571023, TypeS_3op>, Enc_b72622 {
25014 let Inst{7-6} = 0b00;
25015 let Inst{31-21} = 0b11001011101;
25016 let prefersSlot3 = 1;
25017 let Constraints = "$Rxx32 = $Rxx32in";
25019 def S4_vxaddsubh : HInst<
25020 (outs DoubleRegs:$Rdd32),
25021 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25022 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25023 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
25024 let Inst{7-5} = 0b100;
25025 let Inst{13-13} = 0b0;
25026 let Inst{31-21} = 0b11000001010;
25027 let prefersSlot3 = 1;
25028 let Defs = [USR_OVF];
25030 def S4_vxaddsubhr : HInst<
25031 (outs DoubleRegs:$Rdd32),
25032 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25033 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25034 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
25035 let Inst{7-5} = 0b000;
25036 let Inst{13-13} = 0b0;
25037 let Inst{31-21} = 0b11000001110;
25038 let prefersSlot3 = 1;
25039 let Defs = [USR_OVF];
25041 def S4_vxaddsubw : HInst<
25042 (outs DoubleRegs:$Rdd32),
25043 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25044 "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25045 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
25046 let Inst{7-5} = 0b000;
25047 let Inst{13-13} = 0b0;
25048 let Inst{31-21} = 0b11000001010;
25049 let prefersSlot3 = 1;
25050 let Defs = [USR_OVF];
25052 def S4_vxsubaddh : HInst<
25053 (outs DoubleRegs:$Rdd32),
25054 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25055 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25056 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
25057 let Inst{7-5} = 0b110;
25058 let Inst{13-13} = 0b0;
25059 let Inst{31-21} = 0b11000001010;
25060 let prefersSlot3 = 1;
25061 let Defs = [USR_OVF];
25063 def S4_vxsubaddhr : HInst<
25064 (outs DoubleRegs:$Rdd32),
25065 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25066 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25067 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
25068 let Inst{7-5} = 0b010;
25069 let Inst{13-13} = 0b0;
25070 let Inst{31-21} = 0b11000001110;
25071 let prefersSlot3 = 1;
25072 let Defs = [USR_OVF];
25074 def S4_vxsubaddw : HInst<
25075 (outs DoubleRegs:$Rdd32),
25076 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25077 "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25078 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
25079 let Inst{7-5} = 0b010;
25080 let Inst{13-13} = 0b0;
25081 let Inst{31-21} = 0b11000001010;
25082 let prefersSlot3 = 1;
25083 let Defs = [USR_OVF];
25085 def S5_asrhub_rnd_sat : HInst<
25086 (outs IntRegs:$Rd32),
25087 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25088 "$Rd32 = vasrhub($Rss32,#$Ii):raw",
25089 tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
25090 let Inst{7-5} = 0b100;
25091 let Inst{13-12} = 0b00;
25092 let Inst{31-21} = 0b10001000011;
25093 let hasNewValue = 1;
25094 let opNewValue = 0;
25095 let prefersSlot3 = 1;
25096 let Defs = [USR_OVF];
25098 def S5_asrhub_rnd_sat_goodsyntax : HInst<
25099 (outs IntRegs:$Rd32),
25100 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25101 "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25102 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
25103 let hasNewValue = 1;
25104 let opNewValue = 0;
25107 def S5_asrhub_sat : HInst<
25108 (outs IntRegs:$Rd32),
25109 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25110 "$Rd32 = vasrhub($Rss32,#$Ii):sat",
25111 tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
25112 let Inst{7-5} = 0b101;
25113 let Inst{13-12} = 0b00;
25114 let Inst{31-21} = 0b10001000011;
25115 let hasNewValue = 1;
25116 let opNewValue = 0;
25117 let prefersSlot3 = 1;
25118 let Defs = [USR_OVF];
25120 def S5_popcountp : HInst<
25121 (outs IntRegs:$Rd32),
25122 (ins DoubleRegs:$Rss32),
25123 "$Rd32 = popcount($Rss32)",
25124 tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
25125 let Inst{13-5} = 0b000000011;
25126 let Inst{31-21} = 0b10001000011;
25127 let hasNewValue = 1;
25128 let opNewValue = 0;
25129 let prefersSlot3 = 1;
25131 def S5_vasrhrnd : HInst<
25132 (outs DoubleRegs:$Rdd32),
25133 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25134 "$Rdd32 = vasrh($Rss32,#$Ii):raw",
25135 tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> {
25136 let Inst{7-5} = 0b000;
25137 let Inst{13-12} = 0b00;
25138 let Inst{31-21} = 0b10000000001;
25139 let prefersSlot3 = 1;
25141 def S5_vasrhrnd_goodsyntax : HInst<
25142 (outs DoubleRegs:$Rdd32),
25143 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25144 "$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25145 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
25148 def S6_allocframe_to_raw : HInst<
25150 (ins u11_3Imm:$Ii),
25151 "allocframe(#$Ii)",
25152 tc_e216a5db, TypeMAPPING>, Requires<[HasV65T]> {
25154 let isCodeGenOnly = 1;
25156 def S6_rol_i_p : HInst<
25157 (outs DoubleRegs:$Rdd32),
25158 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25159 "$Rdd32 = rol($Rss32,#$Ii)",
25160 tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> {
25161 let Inst{7-5} = 0b011;
25162 let Inst{31-21} = 0b10000000000;
25164 def S6_rol_i_p_acc : HInst<
25165 (outs DoubleRegs:$Rxx32),
25166 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25167 "$Rxx32 += rol($Rss32,#$Ii)",
25168 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
25169 let Inst{7-5} = 0b111;
25170 let Inst{31-21} = 0b10000010000;
25171 let prefersSlot3 = 1;
25172 let Constraints = "$Rxx32 = $Rxx32in";
25174 def S6_rol_i_p_and : HInst<
25175 (outs DoubleRegs:$Rxx32),
25176 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25177 "$Rxx32 &= rol($Rss32,#$Ii)",
25178 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
25179 let Inst{7-5} = 0b011;
25180 let Inst{31-21} = 0b10000010010;
25181 let prefersSlot3 = 1;
25182 let Constraints = "$Rxx32 = $Rxx32in";
25184 def S6_rol_i_p_nac : HInst<
25185 (outs DoubleRegs:$Rxx32),
25186 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25187 "$Rxx32 -= rol($Rss32,#$Ii)",
25188 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
25189 let Inst{7-5} = 0b011;
25190 let Inst{31-21} = 0b10000010000;
25191 let prefersSlot3 = 1;
25192 let Constraints = "$Rxx32 = $Rxx32in";
25194 def S6_rol_i_p_or : HInst<
25195 (outs DoubleRegs:$Rxx32),
25196 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25197 "$Rxx32 |= rol($Rss32,#$Ii)",
25198 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
25199 let Inst{7-5} = 0b111;
25200 let Inst{31-21} = 0b10000010010;
25201 let prefersSlot3 = 1;
25202 let Constraints = "$Rxx32 = $Rxx32in";
25204 def S6_rol_i_p_xacc : HInst<
25205 (outs DoubleRegs:$Rxx32),
25206 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25207 "$Rxx32 ^= rol($Rss32,#$Ii)",
25208 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
25209 let Inst{7-5} = 0b011;
25210 let Inst{31-21} = 0b10000010100;
25211 let prefersSlot3 = 1;
25212 let Constraints = "$Rxx32 = $Rxx32in";
25214 def S6_rol_i_r : HInst<
25215 (outs IntRegs:$Rd32),
25216 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
25217 "$Rd32 = rol($Rs32,#$Ii)",
25218 tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> {
25219 let Inst{7-5} = 0b011;
25220 let Inst{13-13} = 0b0;
25221 let Inst{31-21} = 0b10001100000;
25222 let hasNewValue = 1;
25223 let opNewValue = 0;
25225 def S6_rol_i_r_acc : HInst<
25226 (outs IntRegs:$Rx32),
25227 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25228 "$Rx32 += rol($Rs32,#$Ii)",
25229 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
25230 let Inst{7-5} = 0b111;
25231 let Inst{13-13} = 0b0;
25232 let Inst{31-21} = 0b10001110000;
25233 let hasNewValue = 1;
25234 let opNewValue = 0;
25235 let prefersSlot3 = 1;
25236 let Constraints = "$Rx32 = $Rx32in";
25238 def S6_rol_i_r_and : HInst<
25239 (outs IntRegs:$Rx32),
25240 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25241 "$Rx32 &= rol($Rs32,#$Ii)",
25242 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
25243 let Inst{7-5} = 0b011;
25244 let Inst{13-13} = 0b0;
25245 let Inst{31-21} = 0b10001110010;
25246 let hasNewValue = 1;
25247 let opNewValue = 0;
25248 let prefersSlot3 = 1;
25249 let Constraints = "$Rx32 = $Rx32in";
25251 def S6_rol_i_r_nac : HInst<
25252 (outs IntRegs:$Rx32),
25253 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25254 "$Rx32 -= rol($Rs32,#$Ii)",
25255 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
25256 let Inst{7-5} = 0b011;
25257 let Inst{13-13} = 0b0;
25258 let Inst{31-21} = 0b10001110000;
25259 let hasNewValue = 1;
25260 let opNewValue = 0;
25261 let prefersSlot3 = 1;
25262 let Constraints = "$Rx32 = $Rx32in";
25264 def S6_rol_i_r_or : HInst<
25265 (outs IntRegs:$Rx32),
25266 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25267 "$Rx32 |= rol($Rs32,#$Ii)",
25268 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
25269 let Inst{7-5} = 0b111;
25270 let Inst{13-13} = 0b0;
25271 let Inst{31-21} = 0b10001110010;
25272 let hasNewValue = 1;
25273 let opNewValue = 0;
25274 let prefersSlot3 = 1;
25275 let Constraints = "$Rx32 = $Rx32in";
25277 def S6_rol_i_r_xacc : HInst<
25278 (outs IntRegs:$Rx32),
25279 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25280 "$Rx32 ^= rol($Rs32,#$Ii)",
25281 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
25282 let Inst{7-5} = 0b011;
25283 let Inst{13-13} = 0b0;
25284 let Inst{31-21} = 0b10001110100;
25285 let hasNewValue = 1;
25286 let opNewValue = 0;
25287 let prefersSlot3 = 1;
25288 let Constraints = "$Rx32 = $Rx32in";
25290 def S6_vsplatrbp : HInst<
25291 (outs DoubleRegs:$Rdd32),
25292 (ins IntRegs:$Rs32),
25293 "$Rdd32 = vsplatb($Rs32)",
25294 tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> {
25295 let Inst{13-5} = 0b000000100;
25296 let Inst{31-21} = 0b10000100010;
25298 def S6_vtrunehb_ppp : HInst<
25299 (outs DoubleRegs:$Rdd32),
25300 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25301 "$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25302 tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
25303 let Inst{7-5} = 0b011;
25304 let Inst{13-13} = 0b0;
25305 let Inst{31-21} = 0b11000001100;
25307 def S6_vtrunohb_ppp : HInst<
25308 (outs DoubleRegs:$Rdd32),
25309 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25310 "$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25311 tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
25312 let Inst{7-5} = 0b101;
25313 let Inst{13-13} = 0b0;
25314 let Inst{31-21} = 0b11000001100;
25316 def SA1_addi : HInst<
25317 (outs GeneralSubRegs:$Rx16),
25318 (ins IntRegs:$Rx16in, s32_0Imm:$Ii),
25319 "$Rx16 = add($Rx16in,#$Ii)",
25320 tc_609d2efe, TypeSUBINSN>, Enc_93af4c {
25321 let Inst{12-11} = 0b00;
25322 let hasNewValue = 1;
25323 let opNewValue = 0;
25324 let AsmVariantName = "NonParsable";
25325 let DecoderNamespace = "SUBINSN_A";
25326 let isExtendable = 1;
25327 let opExtendable = 2;
25328 let isExtentSigned = 1;
25329 let opExtentBits = 7;
25330 let opExtentAlign = 0;
25331 let Constraints = "$Rx16 = $Rx16in";
25333 def SA1_addrx : HInst<
25334 (outs GeneralSubRegs:$Rx16),
25335 (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16),
25336 "$Rx16 = add($Rx16in,$Rs16)",
25337 tc_609d2efe, TypeSUBINSN>, Enc_0527db {
25338 let Inst{12-8} = 0b11000;
25339 let hasNewValue = 1;
25340 let opNewValue = 0;
25341 let AsmVariantName = "NonParsable";
25342 let DecoderNamespace = "SUBINSN_A";
25343 let Constraints = "$Rx16 = $Rx16in";
25345 def SA1_addsp : HInst<
25346 (outs GeneralSubRegs:$Rd16),
25348 "$Rd16 = add(r29,#$Ii)",
25349 tc_a904d137, TypeSUBINSN>, Enc_2df31d {
25350 let Inst{12-10} = 0b011;
25351 let hasNewValue = 1;
25352 let opNewValue = 0;
25353 let AsmVariantName = "NonParsable";
25355 let DecoderNamespace = "SUBINSN_A";
25357 def SA1_and1 : HInst<
25358 (outs GeneralSubRegs:$Rd16),
25359 (ins GeneralSubRegs:$Rs16),
25360 "$Rd16 = and($Rs16,#1)",
25361 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25362 let Inst{12-8} = 0b10010;
25363 let hasNewValue = 1;
25364 let opNewValue = 0;
25365 let AsmVariantName = "NonParsable";
25366 let DecoderNamespace = "SUBINSN_A";
25368 def SA1_clrf : HInst<
25369 (outs GeneralSubRegs:$Rd16),
25371 "if (!p0) $Rd16 = #0",
25372 tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
25373 let Inst{12-4} = 0b110100111;
25374 let isPredicated = 1;
25375 let isPredicatedFalse = 1;
25376 let hasNewValue = 1;
25377 let opNewValue = 0;
25378 let AsmVariantName = "NonParsable";
25380 let DecoderNamespace = "SUBINSN_A";
25382 def SA1_clrfnew : HInst<
25383 (outs GeneralSubRegs:$Rd16),
25385 "if (!p0.new) $Rd16 = #0",
25386 tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
25387 let Inst{12-4} = 0b110100101;
25388 let isPredicated = 1;
25389 let isPredicatedFalse = 1;
25390 let hasNewValue = 1;
25391 let opNewValue = 0;
25392 let AsmVariantName = "NonParsable";
25393 let isPredicatedNew = 1;
25395 let DecoderNamespace = "SUBINSN_A";
25397 def SA1_clrt : HInst<
25398 (outs GeneralSubRegs:$Rd16),
25400 "if (p0) $Rd16 = #0",
25401 tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
25402 let Inst{12-4} = 0b110100110;
25403 let isPredicated = 1;
25404 let hasNewValue = 1;
25405 let opNewValue = 0;
25406 let AsmVariantName = "NonParsable";
25408 let DecoderNamespace = "SUBINSN_A";
25410 def SA1_clrtnew : HInst<
25411 (outs GeneralSubRegs:$Rd16),
25413 "if (p0.new) $Rd16 = #0",
25414 tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
25415 let Inst{12-4} = 0b110100100;
25416 let isPredicated = 1;
25417 let hasNewValue = 1;
25418 let opNewValue = 0;
25419 let AsmVariantName = "NonParsable";
25420 let isPredicatedNew = 1;
25422 let DecoderNamespace = "SUBINSN_A";
25424 def SA1_cmpeqi : HInst<
25426 (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
25427 "p0 = cmp.eq($Rs16,#$Ii)",
25428 tc_90f3e30c, TypeSUBINSN>, Enc_63eaeb {
25429 let Inst{3-2} = 0b00;
25430 let Inst{12-8} = 0b11001;
25431 let AsmVariantName = "NonParsable";
25433 let DecoderNamespace = "SUBINSN_A";
25435 def SA1_combine0i : HInst<
25436 (outs GeneralDoubleLow8Regs:$Rdd8),
25438 "$Rdd8 = combine(#0,#$Ii)",
25439 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
25440 let Inst{4-3} = 0b00;
25441 let Inst{12-7} = 0b111000;
25442 let hasNewValue = 1;
25443 let opNewValue = 0;
25444 let AsmVariantName = "NonParsable";
25445 let DecoderNamespace = "SUBINSN_A";
25447 def SA1_combine1i : HInst<
25448 (outs GeneralDoubleLow8Regs:$Rdd8),
25450 "$Rdd8 = combine(#1,#$Ii)",
25451 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
25452 let Inst{4-3} = 0b01;
25453 let Inst{12-7} = 0b111000;
25454 let hasNewValue = 1;
25455 let opNewValue = 0;
25456 let AsmVariantName = "NonParsable";
25457 let DecoderNamespace = "SUBINSN_A";
25459 def SA1_combine2i : HInst<
25460 (outs GeneralDoubleLow8Regs:$Rdd8),
25462 "$Rdd8 = combine(#2,#$Ii)",
25463 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
25464 let Inst{4-3} = 0b10;
25465 let Inst{12-7} = 0b111000;
25466 let hasNewValue = 1;
25467 let opNewValue = 0;
25468 let AsmVariantName = "NonParsable";
25469 let DecoderNamespace = "SUBINSN_A";
25471 def SA1_combine3i : HInst<
25472 (outs GeneralDoubleLow8Regs:$Rdd8),
25474 "$Rdd8 = combine(#3,#$Ii)",
25475 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
25476 let Inst{4-3} = 0b11;
25477 let Inst{12-7} = 0b111000;
25478 let hasNewValue = 1;
25479 let opNewValue = 0;
25480 let AsmVariantName = "NonParsable";
25481 let DecoderNamespace = "SUBINSN_A";
25483 def SA1_combinerz : HInst<
25484 (outs GeneralDoubleLow8Regs:$Rdd8),
25485 (ins GeneralSubRegs:$Rs16),
25486 "$Rdd8 = combine($Rs16,#0)",
25487 tc_a904d137, TypeSUBINSN>, Enc_399e12 {
25488 let Inst{3-3} = 0b1;
25489 let Inst{12-8} = 0b11101;
25490 let hasNewValue = 1;
25491 let opNewValue = 0;
25492 let AsmVariantName = "NonParsable";
25493 let DecoderNamespace = "SUBINSN_A";
25495 def SA1_combinezr : HInst<
25496 (outs GeneralDoubleLow8Regs:$Rdd8),
25497 (ins GeneralSubRegs:$Rs16),
25498 "$Rdd8 = combine(#0,$Rs16)",
25499 tc_a904d137, TypeSUBINSN>, Enc_399e12 {
25500 let Inst{3-3} = 0b0;
25501 let Inst{12-8} = 0b11101;
25502 let hasNewValue = 1;
25503 let opNewValue = 0;
25504 let AsmVariantName = "NonParsable";
25505 let DecoderNamespace = "SUBINSN_A";
25507 def SA1_dec : HInst<
25508 (outs GeneralSubRegs:$Rd16),
25509 (ins GeneralSubRegs:$Rs16, n1Const:$n1),
25510 "$Rd16 = add($Rs16,#$n1)",
25511 tc_609d2efe, TypeSUBINSN>, Enc_ee5ed0 {
25512 let Inst{12-8} = 0b10011;
25513 let hasNewValue = 1;
25514 let opNewValue = 0;
25515 let AsmVariantName = "NonParsable";
25516 let DecoderNamespace = "SUBINSN_A";
25518 def SA1_inc : HInst<
25519 (outs GeneralSubRegs:$Rd16),
25520 (ins GeneralSubRegs:$Rs16),
25521 "$Rd16 = add($Rs16,#1)",
25522 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25523 let Inst{12-8} = 0b10001;
25524 let hasNewValue = 1;
25525 let opNewValue = 0;
25526 let AsmVariantName = "NonParsable";
25527 let DecoderNamespace = "SUBINSN_A";
25529 def SA1_seti : HInst<
25530 (outs GeneralSubRegs:$Rd16),
25531 (ins u32_0Imm:$Ii),
25533 tc_a904d137, TypeSUBINSN>, Enc_e39bb2 {
25534 let Inst{12-10} = 0b010;
25535 let hasNewValue = 1;
25536 let opNewValue = 0;
25537 let AsmVariantName = "NonParsable";
25538 let DecoderNamespace = "SUBINSN_A";
25539 let isExtendable = 1;
25540 let opExtendable = 1;
25541 let isExtentSigned = 0;
25542 let opExtentBits = 6;
25543 let opExtentAlign = 0;
25545 def SA1_setin1 : HInst<
25546 (outs GeneralSubRegs:$Rd16),
25549 tc_a904d137, TypeSUBINSN>, Enc_7a0ea6 {
25550 let Inst{12-4} = 0b110100000;
25551 let hasNewValue = 1;
25552 let opNewValue = 0;
25553 let AsmVariantName = "NonParsable";
25554 let DecoderNamespace = "SUBINSN_A";
25556 def SA1_sxtb : HInst<
25557 (outs GeneralSubRegs:$Rd16),
25558 (ins GeneralSubRegs:$Rs16),
25559 "$Rd16 = sxtb($Rs16)",
25560 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25561 let Inst{12-8} = 0b10101;
25562 let hasNewValue = 1;
25563 let opNewValue = 0;
25564 let AsmVariantName = "NonParsable";
25565 let DecoderNamespace = "SUBINSN_A";
25567 def SA1_sxth : HInst<
25568 (outs GeneralSubRegs:$Rd16),
25569 (ins GeneralSubRegs:$Rs16),
25570 "$Rd16 = sxth($Rs16)",
25571 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25572 let Inst{12-8} = 0b10100;
25573 let hasNewValue = 1;
25574 let opNewValue = 0;
25575 let AsmVariantName = "NonParsable";
25576 let DecoderNamespace = "SUBINSN_A";
25578 def SA1_tfr : HInst<
25579 (outs GeneralSubRegs:$Rd16),
25580 (ins GeneralSubRegs:$Rs16),
25582 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25583 let Inst{12-8} = 0b10000;
25584 let hasNewValue = 1;
25585 let opNewValue = 0;
25586 let AsmVariantName = "NonParsable";
25587 let DecoderNamespace = "SUBINSN_A";
25589 def SA1_zxtb : HInst<
25590 (outs GeneralSubRegs:$Rd16),
25591 (ins GeneralSubRegs:$Rs16),
25592 "$Rd16 = and($Rs16,#255)",
25593 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25594 let Inst{12-8} = 0b10111;
25595 let hasNewValue = 1;
25596 let opNewValue = 0;
25597 let AsmVariantName = "NonParsable";
25598 let DecoderNamespace = "SUBINSN_A";
25600 def SA1_zxth : HInst<
25601 (outs GeneralSubRegs:$Rd16),
25602 (ins GeneralSubRegs:$Rs16),
25603 "$Rd16 = zxth($Rs16)",
25604 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
25605 let Inst{12-8} = 0b10110;
25606 let hasNewValue = 1;
25607 let opNewValue = 0;
25608 let AsmVariantName = "NonParsable";
25609 let DecoderNamespace = "SUBINSN_A";
25611 def SL1_loadri_io : HInst<
25612 (outs GeneralSubRegs:$Rd16),
25613 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
25614 "$Rd16 = memw($Rs16+#$Ii)",
25615 tc_7f881c76, TypeSUBINSN>, Enc_53dca9 {
25616 let Inst{12-12} = 0b0;
25617 let hasNewValue = 1;
25618 let opNewValue = 0;
25619 let addrMode = BaseImmOffset;
25620 let accessSize = WordAccess;
25621 let AsmVariantName = "NonParsable";
25623 let DecoderNamespace = "SUBINSN_L1";
25625 def SL1_loadrub_io : HInst<
25626 (outs GeneralSubRegs:$Rd16),
25627 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
25628 "$Rd16 = memub($Rs16+#$Ii)",
25629 tc_7f881c76, TypeSUBINSN>, Enc_c175d0 {
25630 let Inst{12-12} = 0b1;
25631 let hasNewValue = 1;
25632 let opNewValue = 0;
25633 let addrMode = BaseImmOffset;
25634 let accessSize = ByteAccess;
25635 let AsmVariantName = "NonParsable";
25637 let DecoderNamespace = "SUBINSN_L1";
25639 def SL2_deallocframe : HInst<
25643 tc_36c68ad1, TypeSUBINSN>, Enc_e3b0c4 {
25644 let Inst{12-0} = 0b1111100000000;
25645 let accessSize = DoubleWordAccess;
25646 let AsmVariantName = "NonParsable";
25648 let Uses = [FRAMEKEY, R30];
25649 let Defs = [R30, R29, R31];
25650 let DecoderNamespace = "SUBINSN_L2";
25652 def SL2_jumpr31 : HInst<
25656 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
25657 let Inst{12-0} = 0b1111111000000;
25658 let isTerminator = 1;
25659 let isIndirectBranch = 1;
25660 let AsmVariantName = "NonParsable";
25665 let DecoderNamespace = "SUBINSN_L2";
25667 def SL2_jumpr31_f : HInst<
25670 "if (!p0) jumpr r31",
25671 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
25672 let Inst{12-0} = 0b1111111000101;
25673 let isPredicated = 1;
25674 let isPredicatedFalse = 1;
25675 let isTerminator = 1;
25676 let isIndirectBranch = 1;
25677 let AsmVariantName = "NonParsable";
25680 let Uses = [P0, R31];
25682 let isTaken = Inst{4};
25683 let DecoderNamespace = "SUBINSN_L2";
25685 def SL2_jumpr31_fnew : HInst<
25688 "if (!p0.new) jumpr:nt r31",
25689 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
25690 let Inst{12-0} = 0b1111111000111;
25691 let isPredicated = 1;
25692 let isPredicatedFalse = 1;
25693 let isTerminator = 1;
25694 let isIndirectBranch = 1;
25695 let AsmVariantName = "NonParsable";
25696 let isPredicatedNew = 1;
25699 let Uses = [P0, R31];
25701 let isTaken = Inst{4};
25702 let DecoderNamespace = "SUBINSN_L2";
25704 def SL2_jumpr31_t : HInst<
25707 "if (p0) jumpr r31",
25708 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
25709 let Inst{12-0} = 0b1111111000100;
25710 let isPredicated = 1;
25711 let isTerminator = 1;
25712 let isIndirectBranch = 1;
25713 let AsmVariantName = "NonParsable";
25716 let Uses = [P0, R31];
25718 let isTaken = Inst{4};
25719 let DecoderNamespace = "SUBINSN_L2";
25721 def SL2_jumpr31_tnew : HInst<
25724 "if (p0.new) jumpr:nt r31",
25725 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
25726 let Inst{12-0} = 0b1111111000110;
25727 let isPredicated = 1;
25728 let isTerminator = 1;
25729 let isIndirectBranch = 1;
25730 let AsmVariantName = "NonParsable";
25731 let isPredicatedNew = 1;
25734 let Uses = [P0, R31];
25736 let isTaken = Inst{4};
25737 let DecoderNamespace = "SUBINSN_L2";
25739 def SL2_loadrb_io : HInst<
25740 (outs GeneralSubRegs:$Rd16),
25741 (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
25742 "$Rd16 = memb($Rs16+#$Ii)",
25743 tc_7f881c76, TypeSUBINSN>, Enc_2fbf3c {
25744 let Inst{12-11} = 0b10;
25745 let hasNewValue = 1;
25746 let opNewValue = 0;
25747 let addrMode = BaseImmOffset;
25748 let accessSize = ByteAccess;
25749 let AsmVariantName = "NonParsable";
25751 let DecoderNamespace = "SUBINSN_L2";
25753 def SL2_loadrd_sp : HInst<
25754 (outs GeneralDoubleLow8Regs:$Rdd8),
25756 "$Rdd8 = memd(r29+#$Ii)",
25757 tc_9c98e8af, TypeSUBINSN>, Enc_86a14b {
25758 let Inst{12-8} = 0b11110;
25759 let hasNewValue = 1;
25760 let opNewValue = 0;
25761 let addrMode = BaseImmOffset;
25762 let accessSize = DoubleWordAccess;
25763 let AsmVariantName = "NonParsable";
25766 let DecoderNamespace = "SUBINSN_L2";
25768 def SL2_loadrh_io : HInst<
25769 (outs GeneralSubRegs:$Rd16),
25770 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
25771 "$Rd16 = memh($Rs16+#$Ii)",
25772 tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
25773 let Inst{12-11} = 0b00;
25774 let hasNewValue = 1;
25775 let opNewValue = 0;
25776 let addrMode = BaseImmOffset;
25777 let accessSize = HalfWordAccess;
25778 let AsmVariantName = "NonParsable";
25780 let DecoderNamespace = "SUBINSN_L2";
25782 def SL2_loadri_sp : HInst<
25783 (outs GeneralSubRegs:$Rd16),
25785 "$Rd16 = memw(r29+#$Ii)",
25786 tc_9c98e8af, TypeSUBINSN>, Enc_51635c {
25787 let Inst{12-9} = 0b1110;
25788 let hasNewValue = 1;
25789 let opNewValue = 0;
25790 let addrMode = BaseImmOffset;
25791 let accessSize = WordAccess;
25792 let AsmVariantName = "NonParsable";
25795 let DecoderNamespace = "SUBINSN_L2";
25797 def SL2_loadruh_io : HInst<
25798 (outs GeneralSubRegs:$Rd16),
25799 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
25800 "$Rd16 = memuh($Rs16+#$Ii)",
25801 tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
25802 let Inst{12-11} = 0b01;
25803 let hasNewValue = 1;
25804 let opNewValue = 0;
25805 let addrMode = BaseImmOffset;
25806 let accessSize = HalfWordAccess;
25807 let AsmVariantName = "NonParsable";
25809 let DecoderNamespace = "SUBINSN_L2";
25811 def SL2_return : HInst<
25815 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
25816 let Inst{12-0} = 0b1111101000000;
25817 let isTerminator = 1;
25818 let isIndirectBranch = 1;
25819 let accessSize = DoubleWordAccess;
25820 let AsmVariantName = "NonParsable";
25823 let isRestrictNoSlot1Store = 1;
25825 let Uses = [FRAMEKEY, R30];
25826 let Defs = [PC, R30, R29, R31];
25827 let DecoderNamespace = "SUBINSN_L2";
25829 def SL2_return_f : HInst<
25832 "if (!p0) dealloc_return",
25833 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
25834 let Inst{12-0} = 0b1111101000101;
25835 let isPredicated = 1;
25836 let isPredicatedFalse = 1;
25837 let isTerminator = 1;
25838 let isIndirectBranch = 1;
25839 let accessSize = DoubleWordAccess;
25840 let AsmVariantName = "NonParsable";
25843 let isRestrictNoSlot1Store = 1;
25845 let Uses = [FRAMEKEY, P0, R30];
25846 let Defs = [PC, R30, R29, R31];
25847 let isTaken = Inst{4};
25848 let DecoderNamespace = "SUBINSN_L2";
25850 def SL2_return_fnew : HInst<
25853 "if (!p0.new) dealloc_return:nt",
25854 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
25855 let Inst{12-0} = 0b1111101000111;
25856 let isPredicated = 1;
25857 let isPredicatedFalse = 1;
25858 let isTerminator = 1;
25859 let isIndirectBranch = 1;
25860 let accessSize = DoubleWordAccess;
25861 let AsmVariantName = "NonParsable";
25862 let isPredicatedNew = 1;
25865 let isRestrictNoSlot1Store = 1;
25867 let Uses = [FRAMEKEY, P0, R30];
25868 let Defs = [PC, R30, R29, R31];
25869 let isTaken = Inst{4};
25870 let DecoderNamespace = "SUBINSN_L2";
25872 def SL2_return_t : HInst<
25875 "if (p0) dealloc_return",
25876 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
25877 let Inst{12-0} = 0b1111101000100;
25878 let isPredicated = 1;
25879 let isTerminator = 1;
25880 let isIndirectBranch = 1;
25881 let accessSize = DoubleWordAccess;
25882 let AsmVariantName = "NonParsable";
25885 let isRestrictNoSlot1Store = 1;
25887 let Uses = [FRAMEKEY, P0, R30];
25888 let Defs = [PC, R30, R29, R31];
25889 let isTaken = Inst{4};
25890 let DecoderNamespace = "SUBINSN_L2";
25892 def SL2_return_tnew : HInst<
25895 "if (p0.new) dealloc_return:nt",
25896 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
25897 let Inst{12-0} = 0b1111101000110;
25898 let isPredicated = 1;
25899 let isTerminator = 1;
25900 let isIndirectBranch = 1;
25901 let accessSize = DoubleWordAccess;
25902 let AsmVariantName = "NonParsable";
25903 let isPredicatedNew = 1;
25906 let isRestrictNoSlot1Store = 1;
25908 let Uses = [FRAMEKEY, P0, R30];
25909 let Defs = [PC, R30, R29, R31];
25910 let isTaken = Inst{4};
25911 let DecoderNamespace = "SUBINSN_L2";
25913 def SS1_storeb_io : HInst<
25915 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
25916 "memb($Rs16+#$Ii) = $Rt16",
25917 tc_05b6c987, TypeSUBINSN>, Enc_b38ffc {
25918 let Inst{12-12} = 0b1;
25919 let addrMode = BaseImmOffset;
25920 let accessSize = ByteAccess;
25921 let AsmVariantName = "NonParsable";
25923 let DecoderNamespace = "SUBINSN_S1";
25925 def SS1_storew_io : HInst<
25927 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
25928 "memw($Rs16+#$Ii) = $Rt16",
25929 tc_05b6c987, TypeSUBINSN>, Enc_f55a0c {
25930 let Inst{12-12} = 0b0;
25931 let addrMode = BaseImmOffset;
25932 let accessSize = WordAccess;
25933 let AsmVariantName = "NonParsable";
25935 let DecoderNamespace = "SUBINSN_S1";
25937 def SS2_allocframe : HInst<
25940 "allocframe(#$Ii)",
25941 tc_0fc1ae07, TypeSUBINSN>, Enc_6f70ca {
25942 let Inst{3-0} = 0b0000;
25943 let Inst{12-9} = 0b1110;
25944 let addrMode = BaseImmOffset;
25945 let accessSize = DoubleWordAccess;
25946 let AsmVariantName = "NonParsable";
25948 let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31];
25949 let Defs = [R30, R29];
25950 let DecoderNamespace = "SUBINSN_S2";
25952 def SS2_storebi0 : HInst<
25954 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
25955 "memb($Rs16+#$Ii) = #0",
25956 tc_57288781, TypeSUBINSN>, Enc_84d359 {
25957 let Inst{12-8} = 0b10010;
25958 let addrMode = BaseImmOffset;
25959 let accessSize = ByteAccess;
25960 let AsmVariantName = "NonParsable";
25962 let DecoderNamespace = "SUBINSN_S2";
25964 def SS2_storebi1 : HInst<
25966 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
25967 "memb($Rs16+#$Ii) = #1",
25968 tc_57288781, TypeSUBINSN>, Enc_84d359 {
25969 let Inst{12-8} = 0b10011;
25970 let addrMode = BaseImmOffset;
25971 let accessSize = ByteAccess;
25972 let AsmVariantName = "NonParsable";
25974 let DecoderNamespace = "SUBINSN_S2";
25976 def SS2_stored_sp : HInst<
25978 (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
25979 "memd(r29+#$Ii) = $Rtt8",
25980 tc_a788683e, TypeSUBINSN>, Enc_b8309d {
25981 let Inst{12-9} = 0b0101;
25982 let addrMode = BaseImmOffset;
25983 let accessSize = DoubleWordAccess;
25984 let AsmVariantName = "NonParsable";
25987 let DecoderNamespace = "SUBINSN_S2";
25989 def SS2_storeh_io : HInst<
25991 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
25992 "memh($Rs16+#$Ii) = $Rt16",
25993 tc_05b6c987, TypeSUBINSN>, Enc_625deb {
25994 let Inst{12-11} = 0b00;
25995 let addrMode = BaseImmOffset;
25996 let accessSize = HalfWordAccess;
25997 let AsmVariantName = "NonParsable";
25999 let DecoderNamespace = "SUBINSN_S2";
26001 def SS2_storew_sp : HInst<
26003 (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26004 "memw(r29+#$Ii) = $Rt16",
26005 tc_a788683e, TypeSUBINSN>, Enc_87c142 {
26006 let Inst{12-9} = 0b0100;
26007 let addrMode = BaseImmOffset;
26008 let accessSize = WordAccess;
26009 let AsmVariantName = "NonParsable";
26012 let DecoderNamespace = "SUBINSN_S2";
26014 def SS2_storewi0 : HInst<
26016 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26017 "memw($Rs16+#$Ii) = #0",
26018 tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
26019 let Inst{12-8} = 0b10000;
26020 let addrMode = BaseImmOffset;
26021 let accessSize = WordAccess;
26022 let AsmVariantName = "NonParsable";
26024 let DecoderNamespace = "SUBINSN_S2";
26026 def SS2_storewi1 : HInst<
26028 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26029 "memw($Rs16+#$Ii) = #1",
26030 tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
26031 let Inst{12-8} = 0b10001;
26032 let addrMode = BaseImmOffset;
26033 let accessSize = WordAccess;
26034 let AsmVariantName = "NonParsable";
26036 let DecoderNamespace = "SUBINSN_S2";
26038 def V6_MAP_equb : HInst<
26040 (ins HvxVR:$Vu32, HvxVR:$Vv32),
26041 "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26042 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26043 let hasNewValue = 1;
26044 let opNewValue = 0;
26046 let isCodeGenOnly = 1;
26047 let DecoderNamespace = "EXT_mmvec";
26049 def V6_MAP_equb_and : HInst<
26051 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26052 "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26053 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26055 let isCodeGenOnly = 1;
26056 let DecoderNamespace = "EXT_mmvec";
26057 let Constraints = "$Qx4 = $Qx4in";
26059 def V6_MAP_equb_ior : HInst<
26061 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26062 "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26063 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26064 let isAccumulator = 1;
26066 let isCodeGenOnly = 1;
26067 let DecoderNamespace = "EXT_mmvec";
26068 let Constraints = "$Qx4 = $Qx4in";
26070 def V6_MAP_equb_xor : HInst<
26072 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26073 "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26074 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26076 let isCodeGenOnly = 1;
26077 let DecoderNamespace = "EXT_mmvec";
26078 let Constraints = "$Qx4 = $Qx4in";
26080 def V6_MAP_equh : HInst<
26082 (ins HvxVR:$Vu32, HvxVR:$Vv32),
26083 "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26084 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26085 let hasNewValue = 1;
26086 let opNewValue = 0;
26088 let isCodeGenOnly = 1;
26089 let DecoderNamespace = "EXT_mmvec";
26091 def V6_MAP_equh_and : HInst<
26093 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26094 "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26095 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26097 let isCodeGenOnly = 1;
26098 let DecoderNamespace = "EXT_mmvec";
26099 let Constraints = "$Qx4 = $Qx4in";
26101 def V6_MAP_equh_ior : HInst<
26103 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26104 "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26105 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26106 let isAccumulator = 1;
26108 let isCodeGenOnly = 1;
26109 let DecoderNamespace = "EXT_mmvec";
26110 let Constraints = "$Qx4 = $Qx4in";
26112 def V6_MAP_equh_xor : HInst<
26114 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26115 "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26116 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26118 let isCodeGenOnly = 1;
26119 let DecoderNamespace = "EXT_mmvec";
26120 let Constraints = "$Qx4 = $Qx4in";
26122 def V6_MAP_equw : HInst<
26124 (ins HvxVR:$Vu32, HvxVR:$Vv32),
26125 "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26126 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26127 let hasNewValue = 1;
26128 let opNewValue = 0;
26130 let isCodeGenOnly = 1;
26131 let DecoderNamespace = "EXT_mmvec";
26133 def V6_MAP_equw_and : HInst<
26135 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26136 "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26137 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26139 let isCodeGenOnly = 1;
26140 let DecoderNamespace = "EXT_mmvec";
26141 let Constraints = "$Qx4 = $Qx4in";
26143 def V6_MAP_equw_ior : HInst<
26145 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26146 "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26147 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26148 let isAccumulator = 1;
26150 let isCodeGenOnly = 1;
26151 let DecoderNamespace = "EXT_mmvec";
26152 let Constraints = "$Qx4 = $Qx4in";
26154 def V6_MAP_equw_xor : HInst<
26156 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26157 "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26158 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26160 let isCodeGenOnly = 1;
26161 let DecoderNamespace = "EXT_mmvec";
26162 let Constraints = "$Qx4 = $Qx4in";
26164 def V6_extractw : HInst<
26165 (outs IntRegs:$Rd32),
26166 (ins HvxVR:$Vu32, IntRegs:$Rs32),
26167 "$Rd32 = vextract($Vu32,$Rs32)",
26168 tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26169 let Inst{7-5} = 0b001;
26170 let Inst{13-13} = 0b0;
26171 let Inst{31-21} = 0b10010010000;
26172 let hasNewValue = 1;
26173 let opNewValue = 0;
26176 let DecoderNamespace = "EXT_mmvec";
26178 def V6_extractw_alt : HInst<
26179 (outs IntRegs:$Rd32),
26180 (ins HvxVR:$Vu32, IntRegs:$Rs32),
26181 "$Rd32.w = vextract($Vu32,$Rs32)",
26182 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26183 let hasNewValue = 1;
26184 let opNewValue = 0;
26186 let isCodeGenOnly = 1;
26187 let DecoderNamespace = "EXT_mmvec";
26190 (outs HvxVR:$Vd32),
26191 (ins HvxWR:$Vss32),
26192 "$Vd32 = hi($Vss32)",
26193 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26194 let hasNewValue = 1;
26195 let opNewValue = 0;
26197 let DecoderNamespace = "EXT_mmvec";
26199 def V6_ld0 : HInst<
26200 (outs HvxVR:$Vd32),
26201 (ins IntRegs:$Rt32),
26202 "$Vd32 = vmem($Rt32)",
26203 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26204 let hasNewValue = 1;
26205 let opNewValue = 0;
26207 let isCodeGenOnly = 1;
26208 let DecoderNamespace = "EXT_mmvec";
26210 def V6_ldcnp0 : HInst<
26211 (outs HvxVR:$Vd32),
26212 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26213 "if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26214 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26215 let hasNewValue = 1;
26216 let opNewValue = 0;
26218 let isCodeGenOnly = 1;
26219 let DecoderNamespace = "EXT_mmvec";
26221 def V6_ldcnpnt0 : HInst<
26222 (outs HvxVR:$Vd32),
26223 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26224 "if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26225 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26226 let hasNewValue = 1;
26227 let opNewValue = 0;
26229 let isCodeGenOnly = 1;
26230 let DecoderNamespace = "EXT_mmvec";
26232 def V6_ldcp0 : HInst<
26233 (outs HvxVR:$Vd32),
26234 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26235 "if ($Pv4) $Vd32.cur = vmem($Rt32)",
26236 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26237 let hasNewValue = 1;
26238 let opNewValue = 0;
26240 let isCodeGenOnly = 1;
26241 let DecoderNamespace = "EXT_mmvec";
26243 def V6_ldcpnt0 : HInst<
26244 (outs HvxVR:$Vd32),
26245 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26246 "if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26247 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26248 let hasNewValue = 1;
26249 let opNewValue = 0;
26251 let isCodeGenOnly = 1;
26252 let DecoderNamespace = "EXT_mmvec";
26254 def V6_ldnp0 : HInst<
26255 (outs HvxVR:$Vd32),
26256 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26257 "if (!$Pv4) $Vd32 = vmem($Rt32)",
26258 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26259 let hasNewValue = 1;
26260 let opNewValue = 0;
26262 let isCodeGenOnly = 1;
26263 let DecoderNamespace = "EXT_mmvec";
26265 def V6_ldnpnt0 : HInst<
26266 (outs HvxVR:$Vd32),
26267 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26268 "if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26269 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26270 let hasNewValue = 1;
26271 let opNewValue = 0;
26273 let isCodeGenOnly = 1;
26274 let DecoderNamespace = "EXT_mmvec";
26276 def V6_ldnt0 : HInst<
26277 (outs HvxVR:$Vd32),
26278 (ins IntRegs:$Rt32),
26279 "$Vd32 = vmem($Rt32):nt",
26280 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26281 let hasNewValue = 1;
26282 let opNewValue = 0;
26284 let isCodeGenOnly = 1;
26285 let DecoderNamespace = "EXT_mmvec";
26287 def V6_ldntnt0 : HInst<
26288 (outs HvxVR:$Vd32),
26289 (ins IntRegs:$Rt32),
26290 "$Vd32 = vmem($Rt32):nt",
26291 PSEUDO, TypeMAPPING>, Requires<[HasV62T]> {
26292 let hasNewValue = 1;
26293 let opNewValue = 0;
26295 let isCodeGenOnly = 1;
26296 let DecoderNamespace = "EXT_mmvec";
26298 def V6_ldp0 : HInst<
26299 (outs HvxVR:$Vd32),
26300 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26301 "if ($Pv4) $Vd32 = vmem($Rt32)",
26302 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26303 let hasNewValue = 1;
26304 let opNewValue = 0;
26306 let isCodeGenOnly = 1;
26307 let DecoderNamespace = "EXT_mmvec";
26309 def V6_ldpnt0 : HInst<
26310 (outs HvxVR:$Vd32),
26311 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26312 "if ($Pv4) $Vd32 = vmem($Rt32):nt",
26313 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26314 let hasNewValue = 1;
26315 let opNewValue = 0;
26317 let isCodeGenOnly = 1;
26318 let DecoderNamespace = "EXT_mmvec";
26320 def V6_ldtnp0 : HInst<
26321 (outs HvxVR:$Vd32),
26322 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26323 "if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26324 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26325 let hasNewValue = 1;
26326 let opNewValue = 0;
26328 let isCodeGenOnly = 1;
26329 let DecoderNamespace = "EXT_mmvec";
26331 def V6_ldtnpnt0 : HInst<
26332 (outs HvxVR:$Vd32),
26333 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26334 "if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26335 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26336 let hasNewValue = 1;
26337 let opNewValue = 0;
26339 let isCodeGenOnly = 1;
26340 let DecoderNamespace = "EXT_mmvec";
26342 def V6_ldtp0 : HInst<
26343 (outs HvxVR:$Vd32),
26344 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26345 "if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26346 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26347 let hasNewValue = 1;
26348 let opNewValue = 0;
26350 let isCodeGenOnly = 1;
26351 let DecoderNamespace = "EXT_mmvec";
26353 def V6_ldtpnt0 : HInst<
26354 (outs HvxVR:$Vd32),
26355 (ins PredRegs:$Pv4, IntRegs:$Rt32),
26356 "if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
26357 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26358 let hasNewValue = 1;
26359 let opNewValue = 0;
26361 let isCodeGenOnly = 1;
26362 let DecoderNamespace = "EXT_mmvec";
26364 def V6_ldu0 : HInst<
26365 (outs HvxVR:$Vd32),
26366 (ins IntRegs:$Rt32),
26367 "$Vd32 = vmemu($Rt32)",
26368 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26369 let hasNewValue = 1;
26370 let opNewValue = 0;
26372 let isCodeGenOnly = 1;
26373 let DecoderNamespace = "EXT_mmvec";
26376 (outs HvxVR:$Vd32),
26377 (ins HvxWR:$Vss32),
26378 "$Vd32 = lo($Vss32)",
26379 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26380 let hasNewValue = 1;
26381 let opNewValue = 0;
26383 let DecoderNamespace = "EXT_mmvec";
26385 def V6_lvsplatb : HInst<
26386 (outs HvxVR:$Vd32),
26387 (ins IntRegs:$Rt32),
26388 "$Vd32.b = vsplat($Rt32)",
26389 tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26390 let Inst{13-5} = 0b000000010;
26391 let Inst{31-21} = 0b00011001110;
26392 let hasNewValue = 1;
26393 let opNewValue = 0;
26394 let DecoderNamespace = "EXT_mmvec";
26396 def V6_lvsplath : HInst<
26397 (outs HvxVR:$Vd32),
26398 (ins IntRegs:$Rt32),
26399 "$Vd32.h = vsplat($Rt32)",
26400 tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26401 let Inst{13-5} = 0b000000001;
26402 let Inst{31-21} = 0b00011001110;
26403 let hasNewValue = 1;
26404 let opNewValue = 0;
26405 let DecoderNamespace = "EXT_mmvec";
26407 def V6_lvsplatw : HInst<
26408 (outs HvxVR:$Vd32),
26409 (ins IntRegs:$Rt32),
26410 "$Vd32 = vsplat($Rt32)",
26411 tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
26412 let Inst{13-5} = 0b000000001;
26413 let Inst{31-21} = 0b00011001101;
26414 let hasNewValue = 1;
26415 let opNewValue = 0;
26416 let DecoderNamespace = "EXT_mmvec";
26418 def V6_pred_and : HInst<
26420 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26421 "$Qd4 = and($Qs4,$Qt4)",
26422 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26423 let Inst{7-2} = 0b000000;
26424 let Inst{13-10} = 0b0000;
26425 let Inst{21-16} = 0b000011;
26426 let Inst{31-24} = 0b00011110;
26427 let hasNewValue = 1;
26428 let opNewValue = 0;
26429 let DecoderNamespace = "EXT_mmvec";
26431 def V6_pred_and_n : HInst<
26433 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26434 "$Qd4 = and($Qs4,!$Qt4)",
26435 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26436 let Inst{7-2} = 0b000101;
26437 let Inst{13-10} = 0b0000;
26438 let Inst{21-16} = 0b000011;
26439 let Inst{31-24} = 0b00011110;
26440 let hasNewValue = 1;
26441 let opNewValue = 0;
26442 let DecoderNamespace = "EXT_mmvec";
26444 def V6_pred_not : HInst<
26447 "$Qd4 = not($Qs4)",
26448 tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
26449 let Inst{7-2} = 0b000010;
26450 let Inst{13-10} = 0b0000;
26451 let Inst{31-16} = 0b0001111000000011;
26452 let hasNewValue = 1;
26453 let opNewValue = 0;
26454 let DecoderNamespace = "EXT_mmvec";
26456 def V6_pred_or : HInst<
26458 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26459 "$Qd4 = or($Qs4,$Qt4)",
26460 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26461 let Inst{7-2} = 0b000001;
26462 let Inst{13-10} = 0b0000;
26463 let Inst{21-16} = 0b000011;
26464 let Inst{31-24} = 0b00011110;
26465 let hasNewValue = 1;
26466 let opNewValue = 0;
26467 let DecoderNamespace = "EXT_mmvec";
26469 def V6_pred_or_n : HInst<
26471 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26472 "$Qd4 = or($Qs4,!$Qt4)",
26473 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26474 let Inst{7-2} = 0b000100;
26475 let Inst{13-10} = 0b0000;
26476 let Inst{21-16} = 0b000011;
26477 let Inst{31-24} = 0b00011110;
26478 let hasNewValue = 1;
26479 let opNewValue = 0;
26480 let DecoderNamespace = "EXT_mmvec";
26482 def V6_pred_scalar2 : HInst<
26484 (ins IntRegs:$Rt32),
26485 "$Qd4 = vsetq($Rt32)",
26486 tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
26487 let Inst{13-2} = 0b000000010001;
26488 let Inst{31-21} = 0b00011001101;
26489 let hasNewValue = 1;
26490 let opNewValue = 0;
26491 let DecoderNamespace = "EXT_mmvec";
26493 def V6_pred_scalar2v2 : HInst<
26495 (ins IntRegs:$Rt32),
26496 "$Qd4 = vsetq2($Rt32)",
26497 tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
26498 let Inst{13-2} = 0b000000010011;
26499 let Inst{31-21} = 0b00011001101;
26500 let hasNewValue = 1;
26501 let opNewValue = 0;
26502 let DecoderNamespace = "EXT_mmvec";
26504 def V6_pred_xor : HInst<
26506 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26507 "$Qd4 = xor($Qs4,$Qt4)",
26508 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26509 let Inst{7-2} = 0b000011;
26510 let Inst{13-10} = 0b0000;
26511 let Inst{21-16} = 0b000011;
26512 let Inst{31-24} = 0b00011110;
26513 let hasNewValue = 1;
26514 let opNewValue = 0;
26515 let DecoderNamespace = "EXT_mmvec";
26517 def V6_shuffeqh : HInst<
26519 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26520 "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
26521 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
26522 let Inst{7-2} = 0b000110;
26523 let Inst{13-10} = 0b0000;
26524 let Inst{21-16} = 0b000011;
26525 let Inst{31-24} = 0b00011110;
26526 let hasNewValue = 1;
26527 let opNewValue = 0;
26528 let DecoderNamespace = "EXT_mmvec";
26530 def V6_shuffeqw : HInst<
26532 (ins HvxQR:$Qs4, HvxQR:$Qt4),
26533 "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
26534 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
26535 let Inst{7-2} = 0b000111;
26536 let Inst{13-10} = 0b0000;
26537 let Inst{21-16} = 0b000011;
26538 let Inst{31-24} = 0b00011110;
26539 let hasNewValue = 1;
26540 let opNewValue = 0;
26541 let DecoderNamespace = "EXT_mmvec";
26543 def V6_st0 : HInst<
26545 (ins IntRegs:$Rt32, HvxVR:$Vs32),
26546 "vmem($Rt32) = $Vs32",
26547 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26549 let isCodeGenOnly = 1;
26550 let DecoderNamespace = "EXT_mmvec";
26552 def V6_stn0 : HInst<
26554 (ins IntRegs:$Rt32, HvxVR:$Os8),
26555 "vmem($Rt32) = $Os8.new",
26556 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26558 let isCodeGenOnly = 1;
26559 let DecoderNamespace = "EXT_mmvec";
26560 let opNewValue = 1;
26562 def V6_stnnt0 : HInst<
26564 (ins IntRegs:$Rt32, HvxVR:$Os8),
26565 "vmem($Rt32):nt = $Os8.new",
26566 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26568 let isCodeGenOnly = 1;
26569 let DecoderNamespace = "EXT_mmvec";
26570 let opNewValue = 1;
26572 def V6_stnp0 : HInst<
26574 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26575 "if (!$Pv4) vmem($Rt32) = $Vs32",
26576 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26578 let isCodeGenOnly = 1;
26579 let DecoderNamespace = "EXT_mmvec";
26581 def V6_stnpnt0 : HInst<
26583 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26584 "if (!$Pv4) vmem($Rt32):nt = $Vs32",
26585 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26587 let isCodeGenOnly = 1;
26588 let DecoderNamespace = "EXT_mmvec";
26590 def V6_stnq0 : HInst<
26592 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26593 "if (!$Qv4) vmem($Rt32) = $Vs32",
26594 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26596 let isCodeGenOnly = 1;
26597 let DecoderNamespace = "EXT_mmvec";
26599 def V6_stnqnt0 : HInst<
26601 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26602 "if (!$Qv4) vmem($Rt32):nt = $Vs32",
26603 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26605 let isCodeGenOnly = 1;
26606 let DecoderNamespace = "EXT_mmvec";
26608 def V6_stnt0 : HInst<
26610 (ins IntRegs:$Rt32, HvxVR:$Vs32),
26611 "vmem($Rt32):nt = $Vs32",
26612 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26614 let isCodeGenOnly = 1;
26615 let DecoderNamespace = "EXT_mmvec";
26617 def V6_stp0 : HInst<
26619 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26620 "if ($Pv4) vmem($Rt32) = $Vs32",
26621 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26623 let isCodeGenOnly = 1;
26624 let DecoderNamespace = "EXT_mmvec";
26626 def V6_stpnt0 : HInst<
26628 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26629 "if ($Pv4) vmem($Rt32):nt = $Vs32",
26630 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26632 let isCodeGenOnly = 1;
26633 let DecoderNamespace = "EXT_mmvec";
26635 def V6_stq0 : HInst<
26637 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26638 "if ($Qv4) vmem($Rt32) = $Vs32",
26639 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26641 let isCodeGenOnly = 1;
26642 let DecoderNamespace = "EXT_mmvec";
26644 def V6_stqnt0 : HInst<
26646 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26647 "if ($Qv4) vmem($Rt32):nt = $Vs32",
26648 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26650 let isCodeGenOnly = 1;
26651 let DecoderNamespace = "EXT_mmvec";
26653 def V6_stu0 : HInst<
26655 (ins IntRegs:$Rt32, HvxVR:$Vs32),
26656 "vmemu($Rt32) = $Vs32",
26657 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26659 let isCodeGenOnly = 1;
26660 let DecoderNamespace = "EXT_mmvec";
26662 def V6_stunp0 : HInst<
26664 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26665 "if (!$Pv4) vmemu($Rt32) = $Vs32",
26666 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26668 let isCodeGenOnly = 1;
26669 let DecoderNamespace = "EXT_mmvec";
26671 def V6_stup0 : HInst<
26673 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26674 "if ($Pv4) vmemu($Rt32) = $Vs32",
26675 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26677 let isCodeGenOnly = 1;
26678 let DecoderNamespace = "EXT_mmvec";
26680 def V6_vL32Ub_ai : HInst<
26681 (outs HvxVR:$Vd32),
26682 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
26683 "$Vd32 = vmemu($Rt32+#$Ii)",
26684 tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
26685 let Inst{7-5} = 0b111;
26686 let Inst{12-11} = 0b00;
26687 let Inst{31-21} = 0b00101000000;
26688 let hasNewValue = 1;
26689 let opNewValue = 0;
26690 let addrMode = BaseImmOffset;
26691 let accessSize = HVXVectorAccess;
26694 let isRestrictNoSlot1Store = 1;
26695 let DecoderNamespace = "EXT_mmvec";
26697 def V6_vL32Ub_pi : HInst<
26698 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26699 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
26700 "$Vd32 = vmemu($Rx32++#$Ii)",
26701 tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
26702 let Inst{7-5} = 0b111;
26703 let Inst{13-11} = 0b000;
26704 let Inst{31-21} = 0b00101001000;
26705 let hasNewValue = 1;
26706 let opNewValue = 0;
26707 let addrMode = PostInc;
26708 let accessSize = HVXVectorAccess;
26711 let isRestrictNoSlot1Store = 1;
26712 let BaseOpcode = "V6_vL32b_pi";
26713 let DecoderNamespace = "EXT_mmvec";
26714 let Constraints = "$Rx32 = $Rx32in";
26716 def V6_vL32Ub_ppu : HInst<
26717 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26718 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
26719 "$Vd32 = vmemu($Rx32++$Mu2)",
26720 tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
26721 let Inst{12-5} = 0b00000111;
26722 let Inst{31-21} = 0b00101011000;
26723 let hasNewValue = 1;
26724 let opNewValue = 0;
26725 let addrMode = PostInc;
26726 let accessSize = HVXVectorAccess;
26729 let isRestrictNoSlot1Store = 1;
26730 let DecoderNamespace = "EXT_mmvec";
26731 let Constraints = "$Rx32 = $Rx32in";
26733 def V6_vL32b_ai : HInst<
26734 (outs HvxVR:$Vd32),
26735 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
26736 "$Vd32 = vmem($Rt32+#$Ii)",
26737 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
26738 let Inst{7-5} = 0b000;
26739 let Inst{12-11} = 0b00;
26740 let Inst{31-21} = 0b00101000000;
26741 let hasNewValue = 1;
26742 let opNewValue = 0;
26743 let addrMode = BaseImmOffset;
26744 let accessSize = HVXVectorAccess;
26747 let isRestrictNoSlot1Store = 1;
26748 let BaseOpcode = "V6_vL32b_ai";
26749 let isCVLoadable = 1;
26750 let isPredicable = 1;
26751 let DecoderNamespace = "EXT_mmvec";
26753 def V6_vL32b_cur_ai : HInst<
26754 (outs HvxVR:$Vd32),
26755 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
26756 "$Vd32.cur = vmem($Rt32+#$Ii)",
26757 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
26758 let Inst{7-5} = 0b001;
26759 let Inst{12-11} = 0b00;
26760 let Inst{31-21} = 0b00101000000;
26761 let hasNewValue = 1;
26762 let opNewValue = 0;
26763 let addrMode = BaseImmOffset;
26764 let accessSize = HVXVectorAccess;
26768 let isRestrictNoSlot1Store = 1;
26769 let BaseOpcode = "V6_vL32b_cur_ai";
26770 let isPredicable = 1;
26771 let DecoderNamespace = "EXT_mmvec";
26773 def V6_vL32b_cur_npred_ai : HInst<
26774 (outs HvxVR:$Vd32),
26775 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
26776 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
26777 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
26778 let Inst{7-5} = 0b101;
26779 let Inst{31-21} = 0b00101000100;
26780 let isPredicated = 1;
26781 let isPredicatedFalse = 1;
26782 let hasNewValue = 1;
26783 let opNewValue = 0;
26784 let addrMode = BaseImmOffset;
26785 let accessSize = HVXVectorAccess;
26789 let isRestrictNoSlot1Store = 1;
26790 let BaseOpcode = "V6_vL32b_cur_ai";
26791 let DecoderNamespace = "EXT_mmvec";
26793 def V6_vL32b_cur_npred_pi : HInst<
26794 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26795 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
26796 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
26797 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
26798 let Inst{7-5} = 0b101;
26799 let Inst{13-13} = 0b0;
26800 let Inst{31-21} = 0b00101001100;
26801 let isPredicated = 1;
26802 let isPredicatedFalse = 1;
26803 let hasNewValue = 1;
26804 let opNewValue = 0;
26805 let addrMode = PostInc;
26806 let accessSize = HVXVectorAccess;
26810 let isRestrictNoSlot1Store = 1;
26811 let BaseOpcode = "V6_vL32b_cur_pi";
26812 let DecoderNamespace = "EXT_mmvec";
26813 let Constraints = "$Rx32 = $Rx32in";
26815 def V6_vL32b_cur_npred_ppu : HInst<
26816 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26817 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
26818 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
26819 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
26820 let Inst{10-5} = 0b000101;
26821 let Inst{31-21} = 0b00101011100;
26822 let isPredicated = 1;
26823 let isPredicatedFalse = 1;
26824 let hasNewValue = 1;
26825 let opNewValue = 0;
26826 let addrMode = PostInc;
26827 let accessSize = HVXVectorAccess;
26831 let isRestrictNoSlot1Store = 1;
26832 let BaseOpcode = "V6_vL32b_cur_ppu";
26833 let DecoderNamespace = "EXT_mmvec";
26834 let Constraints = "$Rx32 = $Rx32in";
26836 def V6_vL32b_cur_pi : HInst<
26837 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26838 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
26839 "$Vd32.cur = vmem($Rx32++#$Ii)",
26840 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
26841 let Inst{7-5} = 0b001;
26842 let Inst{13-11} = 0b000;
26843 let Inst{31-21} = 0b00101001000;
26844 let hasNewValue = 1;
26845 let opNewValue = 0;
26846 let addrMode = PostInc;
26847 let accessSize = HVXVectorAccess;
26851 let isRestrictNoSlot1Store = 1;
26852 let BaseOpcode = "V6_vL32b_cur_pi";
26853 let isPredicable = 1;
26854 let DecoderNamespace = "EXT_mmvec";
26855 let Constraints = "$Rx32 = $Rx32in";
26857 def V6_vL32b_cur_ppu : HInst<
26858 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26859 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
26860 "$Vd32.cur = vmem($Rx32++$Mu2)",
26861 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
26862 let Inst{12-5} = 0b00000001;
26863 let Inst{31-21} = 0b00101011000;
26864 let hasNewValue = 1;
26865 let opNewValue = 0;
26866 let addrMode = PostInc;
26867 let accessSize = HVXVectorAccess;
26871 let isRestrictNoSlot1Store = 1;
26872 let BaseOpcode = "V6_vL32b_cur_ppu";
26873 let isPredicable = 1;
26874 let DecoderNamespace = "EXT_mmvec";
26875 let Constraints = "$Rx32 = $Rx32in";
26877 def V6_vL32b_cur_pred_ai : HInst<
26878 (outs HvxVR:$Vd32),
26879 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
26880 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
26881 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
26882 let Inst{7-5} = 0b100;
26883 let Inst{31-21} = 0b00101000100;
26884 let isPredicated = 1;
26885 let hasNewValue = 1;
26886 let opNewValue = 0;
26887 let addrMode = BaseImmOffset;
26888 let accessSize = HVXVectorAccess;
26892 let isRestrictNoSlot1Store = 1;
26893 let BaseOpcode = "V6_vL32b_cur_ai";
26894 let DecoderNamespace = "EXT_mmvec";
26896 def V6_vL32b_cur_pred_pi : HInst<
26897 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26898 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
26899 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
26900 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
26901 let Inst{7-5} = 0b100;
26902 let Inst{13-13} = 0b0;
26903 let Inst{31-21} = 0b00101001100;
26904 let isPredicated = 1;
26905 let hasNewValue = 1;
26906 let opNewValue = 0;
26907 let addrMode = PostInc;
26908 let accessSize = HVXVectorAccess;
26912 let isRestrictNoSlot1Store = 1;
26913 let BaseOpcode = "V6_vL32b_cur_pi";
26914 let DecoderNamespace = "EXT_mmvec";
26915 let Constraints = "$Rx32 = $Rx32in";
26917 def V6_vL32b_cur_pred_ppu : HInst<
26918 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26919 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
26920 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
26921 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
26922 let Inst{10-5} = 0b000100;
26923 let Inst{31-21} = 0b00101011100;
26924 let isPredicated = 1;
26925 let hasNewValue = 1;
26926 let opNewValue = 0;
26927 let addrMode = PostInc;
26928 let accessSize = HVXVectorAccess;
26932 let isRestrictNoSlot1Store = 1;
26933 let BaseOpcode = "V6_vL32b_cur_ppu";
26934 let DecoderNamespace = "EXT_mmvec";
26935 let Constraints = "$Rx32 = $Rx32in";
26937 def V6_vL32b_npred_ai : HInst<
26938 (outs HvxVR:$Vd32),
26939 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
26940 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
26941 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
26942 let Inst{7-5} = 0b011;
26943 let Inst{31-21} = 0b00101000100;
26944 let isPredicated = 1;
26945 let isPredicatedFalse = 1;
26946 let hasNewValue = 1;
26947 let opNewValue = 0;
26948 let addrMode = BaseImmOffset;
26949 let accessSize = HVXVectorAccess;
26952 let isRestrictNoSlot1Store = 1;
26953 let BaseOpcode = "V6_vL32b_ai";
26954 let DecoderNamespace = "EXT_mmvec";
26956 def V6_vL32b_npred_pi : HInst<
26957 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26958 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
26959 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
26960 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
26961 let Inst{7-5} = 0b011;
26962 let Inst{13-13} = 0b0;
26963 let Inst{31-21} = 0b00101001100;
26964 let isPredicated = 1;
26965 let isPredicatedFalse = 1;
26966 let hasNewValue = 1;
26967 let opNewValue = 0;
26968 let addrMode = PostInc;
26969 let accessSize = HVXVectorAccess;
26972 let isRestrictNoSlot1Store = 1;
26973 let BaseOpcode = "V6_vL32b_pi";
26974 let DecoderNamespace = "EXT_mmvec";
26975 let Constraints = "$Rx32 = $Rx32in";
26977 def V6_vL32b_npred_ppu : HInst<
26978 (outs HvxVR:$Vd32, IntRegs:$Rx32),
26979 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
26980 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
26981 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
26982 let Inst{10-5} = 0b000011;
26983 let Inst{31-21} = 0b00101011100;
26984 let isPredicated = 1;
26985 let isPredicatedFalse = 1;
26986 let hasNewValue = 1;
26987 let opNewValue = 0;
26988 let addrMode = PostInc;
26989 let accessSize = HVXVectorAccess;
26992 let isRestrictNoSlot1Store = 1;
26993 let BaseOpcode = "V6_vL32b_ppu";
26994 let DecoderNamespace = "EXT_mmvec";
26995 let Constraints = "$Rx32 = $Rx32in";
26997 def V6_vL32b_nt_ai : HInst<
26998 (outs HvxVR:$Vd32),
26999 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
27000 "$Vd32 = vmem($Rt32+#$Ii):nt",
27001 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27002 let Inst{7-5} = 0b000;
27003 let Inst{12-11} = 0b00;
27004 let Inst{31-21} = 0b00101000010;
27005 let hasNewValue = 1;
27006 let opNewValue = 0;
27007 let addrMode = BaseImmOffset;
27008 let accessSize = HVXVectorAccess;
27011 let isNonTemporal = 1;
27012 let isRestrictNoSlot1Store = 1;
27013 let BaseOpcode = "V6_vL32b_nt_ai";
27014 let isCVLoadable = 1;
27015 let isPredicable = 1;
27016 let DecoderNamespace = "EXT_mmvec";
27018 def V6_vL32b_nt_cur_ai : HInst<
27019 (outs HvxVR:$Vd32),
27020 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
27021 "$Vd32.cur = vmem($Rt32+#$Ii):nt",
27022 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27023 let Inst{7-5} = 0b001;
27024 let Inst{12-11} = 0b00;
27025 let Inst{31-21} = 0b00101000010;
27026 let hasNewValue = 1;
27027 let opNewValue = 0;
27028 let addrMode = BaseImmOffset;
27029 let accessSize = HVXVectorAccess;
27033 let isNonTemporal = 1;
27034 let isRestrictNoSlot1Store = 1;
27035 let BaseOpcode = "V6_vL32b_nt_cur_ai";
27036 let isPredicable = 1;
27037 let DecoderNamespace = "EXT_mmvec";
27039 def V6_vL32b_nt_cur_npred_ai : HInst<
27040 (outs HvxVR:$Vd32),
27041 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27042 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27043 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27044 let Inst{7-5} = 0b101;
27045 let Inst{31-21} = 0b00101000110;
27046 let isPredicated = 1;
27047 let isPredicatedFalse = 1;
27048 let hasNewValue = 1;
27049 let opNewValue = 0;
27050 let addrMode = BaseImmOffset;
27051 let accessSize = HVXVectorAccess;
27055 let isNonTemporal = 1;
27056 let isRestrictNoSlot1Store = 1;
27057 let BaseOpcode = "V6_vL32b_nt_cur_ai";
27058 let DecoderNamespace = "EXT_mmvec";
27060 def V6_vL32b_nt_cur_npred_pi : HInst<
27061 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27062 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27063 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27064 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27065 let Inst{7-5} = 0b101;
27066 let Inst{13-13} = 0b0;
27067 let Inst{31-21} = 0b00101001110;
27068 let isPredicated = 1;
27069 let isPredicatedFalse = 1;
27070 let hasNewValue = 1;
27071 let opNewValue = 0;
27072 let addrMode = PostInc;
27073 let accessSize = HVXVectorAccess;
27077 let isNonTemporal = 1;
27078 let isRestrictNoSlot1Store = 1;
27079 let BaseOpcode = "V6_vL32b_nt_cur_pi";
27080 let DecoderNamespace = "EXT_mmvec";
27081 let Constraints = "$Rx32 = $Rx32in";
27083 def V6_vL32b_nt_cur_npred_ppu : HInst<
27084 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27085 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27086 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27087 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27088 let Inst{10-5} = 0b000101;
27089 let Inst{31-21} = 0b00101011110;
27090 let isPredicated = 1;
27091 let isPredicatedFalse = 1;
27092 let hasNewValue = 1;
27093 let opNewValue = 0;
27094 let addrMode = PostInc;
27095 let accessSize = HVXVectorAccess;
27099 let isNonTemporal = 1;
27100 let isRestrictNoSlot1Store = 1;
27101 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27102 let DecoderNamespace = "EXT_mmvec";
27103 let Constraints = "$Rx32 = $Rx32in";
27105 def V6_vL32b_nt_cur_pi : HInst<
27106 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27107 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27108 "$Vd32.cur = vmem($Rx32++#$Ii):nt",
27109 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27110 let Inst{7-5} = 0b001;
27111 let Inst{13-11} = 0b000;
27112 let Inst{31-21} = 0b00101001010;
27113 let hasNewValue = 1;
27114 let opNewValue = 0;
27115 let addrMode = PostInc;
27116 let accessSize = HVXVectorAccess;
27120 let isNonTemporal = 1;
27121 let isRestrictNoSlot1Store = 1;
27122 let BaseOpcode = "V6_vL32b_nt_cur_pi";
27123 let isPredicable = 1;
27124 let DecoderNamespace = "EXT_mmvec";
27125 let Constraints = "$Rx32 = $Rx32in";
27127 def V6_vL32b_nt_cur_ppu : HInst<
27128 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27129 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
27130 "$Vd32.cur = vmem($Rx32++$Mu2):nt",
27131 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27132 let Inst{12-5} = 0b00000001;
27133 let Inst{31-21} = 0b00101011010;
27134 let hasNewValue = 1;
27135 let opNewValue = 0;
27136 let addrMode = PostInc;
27137 let accessSize = HVXVectorAccess;
27141 let isNonTemporal = 1;
27142 let isRestrictNoSlot1Store = 1;
27143 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27144 let isPredicable = 1;
27145 let DecoderNamespace = "EXT_mmvec";
27146 let Constraints = "$Rx32 = $Rx32in";
27148 def V6_vL32b_nt_cur_pred_ai : HInst<
27149 (outs HvxVR:$Vd32),
27150 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27151 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27152 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27153 let Inst{7-5} = 0b100;
27154 let Inst{31-21} = 0b00101000110;
27155 let isPredicated = 1;
27156 let hasNewValue = 1;
27157 let opNewValue = 0;
27158 let addrMode = BaseImmOffset;
27159 let accessSize = HVXVectorAccess;
27163 let isNonTemporal = 1;
27164 let isRestrictNoSlot1Store = 1;
27165 let BaseOpcode = "V6_vL32b_nt_cur_ai";
27166 let DecoderNamespace = "EXT_mmvec";
27168 def V6_vL32b_nt_cur_pred_pi : HInst<
27169 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27170 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27171 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27172 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27173 let Inst{7-5} = 0b100;
27174 let Inst{13-13} = 0b0;
27175 let Inst{31-21} = 0b00101001110;
27176 let isPredicated = 1;
27177 let hasNewValue = 1;
27178 let opNewValue = 0;
27179 let addrMode = PostInc;
27180 let accessSize = HVXVectorAccess;
27184 let isNonTemporal = 1;
27185 let isRestrictNoSlot1Store = 1;
27186 let BaseOpcode = "V6_vL32b_nt_cur_pi";
27187 let DecoderNamespace = "EXT_mmvec";
27188 let Constraints = "$Rx32 = $Rx32in";
27190 def V6_vL32b_nt_cur_pred_ppu : HInst<
27191 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27192 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27193 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27194 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27195 let Inst{10-5} = 0b000100;
27196 let Inst{31-21} = 0b00101011110;
27197 let isPredicated = 1;
27198 let hasNewValue = 1;
27199 let opNewValue = 0;
27200 let addrMode = PostInc;
27201 let accessSize = HVXVectorAccess;
27205 let isNonTemporal = 1;
27206 let isRestrictNoSlot1Store = 1;
27207 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27208 let DecoderNamespace = "EXT_mmvec";
27209 let Constraints = "$Rx32 = $Rx32in";
27211 def V6_vL32b_nt_npred_ai : HInst<
27212 (outs HvxVR:$Vd32),
27213 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27214 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27215 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27216 let Inst{7-5} = 0b011;
27217 let Inst{31-21} = 0b00101000110;
27218 let isPredicated = 1;
27219 let isPredicatedFalse = 1;
27220 let hasNewValue = 1;
27221 let opNewValue = 0;
27222 let addrMode = BaseImmOffset;
27223 let accessSize = HVXVectorAccess;
27226 let isNonTemporal = 1;
27227 let isRestrictNoSlot1Store = 1;
27228 let BaseOpcode = "V6_vL32b_nt_ai";
27229 let DecoderNamespace = "EXT_mmvec";
27231 def V6_vL32b_nt_npred_pi : HInst<
27232 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27233 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27234 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27235 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27236 let Inst{7-5} = 0b011;
27237 let Inst{13-13} = 0b0;
27238 let Inst{31-21} = 0b00101001110;
27239 let isPredicated = 1;
27240 let isPredicatedFalse = 1;
27241 let hasNewValue = 1;
27242 let opNewValue = 0;
27243 let addrMode = PostInc;
27244 let accessSize = HVXVectorAccess;
27247 let isNonTemporal = 1;
27248 let isRestrictNoSlot1Store = 1;
27249 let BaseOpcode = "V6_vL32b_nt_pi";
27250 let DecoderNamespace = "EXT_mmvec";
27251 let Constraints = "$Rx32 = $Rx32in";
27253 def V6_vL32b_nt_npred_ppu : HInst<
27254 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27255 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27256 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27257 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27258 let Inst{10-5} = 0b000011;
27259 let Inst{31-21} = 0b00101011110;
27260 let isPredicated = 1;
27261 let isPredicatedFalse = 1;
27262 let hasNewValue = 1;
27263 let opNewValue = 0;
27264 let addrMode = PostInc;
27265 let accessSize = HVXVectorAccess;
27268 let isNonTemporal = 1;
27269 let isRestrictNoSlot1Store = 1;
27270 let BaseOpcode = "V6_vL32b_nt_ppu";
27271 let DecoderNamespace = "EXT_mmvec";
27272 let Constraints = "$Rx32 = $Rx32in";
27274 def V6_vL32b_nt_pi : HInst<
27275 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27276 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27277 "$Vd32 = vmem($Rx32++#$Ii):nt",
27278 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27279 let Inst{7-5} = 0b000;
27280 let Inst{13-11} = 0b000;
27281 let Inst{31-21} = 0b00101001010;
27282 let hasNewValue = 1;
27283 let opNewValue = 0;
27284 let addrMode = PostInc;
27285 let accessSize = HVXVectorAccess;
27288 let isNonTemporal = 1;
27289 let isRestrictNoSlot1Store = 1;
27290 let BaseOpcode = "V6_vL32b_nt_pi";
27291 let isCVLoadable = 1;
27292 let isPredicable = 1;
27293 let DecoderNamespace = "EXT_mmvec";
27294 let Constraints = "$Rx32 = $Rx32in";
27296 def V6_vL32b_nt_ppu : HInst<
27297 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27298 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
27299 "$Vd32 = vmem($Rx32++$Mu2):nt",
27300 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27301 let Inst{12-5} = 0b00000000;
27302 let Inst{31-21} = 0b00101011010;
27303 let hasNewValue = 1;
27304 let opNewValue = 0;
27305 let addrMode = PostInc;
27306 let accessSize = HVXVectorAccess;
27309 let isNonTemporal = 1;
27310 let isRestrictNoSlot1Store = 1;
27311 let BaseOpcode = "V6_vL32b_nt_ppu";
27312 let isCVLoadable = 1;
27313 let isPredicable = 1;
27314 let DecoderNamespace = "EXT_mmvec";
27315 let Constraints = "$Rx32 = $Rx32in";
27317 def V6_vL32b_nt_pred_ai : HInst<
27318 (outs HvxVR:$Vd32),
27319 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27320 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27321 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27322 let Inst{7-5} = 0b010;
27323 let Inst{31-21} = 0b00101000110;
27324 let isPredicated = 1;
27325 let hasNewValue = 1;
27326 let opNewValue = 0;
27327 let addrMode = BaseImmOffset;
27328 let accessSize = HVXVectorAccess;
27331 let isNonTemporal = 1;
27332 let isRestrictNoSlot1Store = 1;
27333 let BaseOpcode = "V6_vL32b_nt_ai";
27334 let DecoderNamespace = "EXT_mmvec";
27336 def V6_vL32b_nt_pred_pi : HInst<
27337 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27338 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27339 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27340 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27341 let Inst{7-5} = 0b010;
27342 let Inst{13-13} = 0b0;
27343 let Inst{31-21} = 0b00101001110;
27344 let isPredicated = 1;
27345 let hasNewValue = 1;
27346 let opNewValue = 0;
27347 let addrMode = PostInc;
27348 let accessSize = HVXVectorAccess;
27351 let isNonTemporal = 1;
27352 let isRestrictNoSlot1Store = 1;
27353 let BaseOpcode = "V6_vL32b_nt_pi";
27354 let DecoderNamespace = "EXT_mmvec";
27355 let Constraints = "$Rx32 = $Rx32in";
27357 def V6_vL32b_nt_pred_ppu : HInst<
27358 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27359 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27360 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27361 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27362 let Inst{10-5} = 0b000010;
27363 let Inst{31-21} = 0b00101011110;
27364 let isPredicated = 1;
27365 let hasNewValue = 1;
27366 let opNewValue = 0;
27367 let addrMode = PostInc;
27368 let accessSize = HVXVectorAccess;
27371 let isNonTemporal = 1;
27372 let isRestrictNoSlot1Store = 1;
27373 let BaseOpcode = "V6_vL32b_nt_ppu";
27374 let DecoderNamespace = "EXT_mmvec";
27375 let Constraints = "$Rx32 = $Rx32in";
27377 def V6_vL32b_nt_tmp_ai : HInst<
27378 (outs HvxVR:$Vd32),
27379 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
27380 "$Vd32.tmp = vmem($Rt32+#$Ii):nt",
27381 tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27382 let Inst{7-5} = 0b010;
27383 let Inst{12-11} = 0b00;
27384 let Inst{31-21} = 0b00101000010;
27385 let hasNewValue = 1;
27386 let opNewValue = 0;
27387 let addrMode = BaseImmOffset;
27388 let accessSize = HVXVectorAccess;
27391 let isNonTemporal = 1;
27392 let isRestrictNoSlot1Store = 1;
27393 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27394 let isPredicable = 1;
27395 let DecoderNamespace = "EXT_mmvec";
27397 def V6_vL32b_nt_tmp_npred_ai : HInst<
27398 (outs HvxVR:$Vd32),
27399 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27400 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
27401 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27402 let Inst{7-5} = 0b111;
27403 let Inst{31-21} = 0b00101000110;
27404 let isPredicated = 1;
27405 let isPredicatedFalse = 1;
27406 let hasNewValue = 1;
27407 let opNewValue = 0;
27408 let addrMode = BaseImmOffset;
27409 let accessSize = HVXVectorAccess;
27412 let isNonTemporal = 1;
27413 let isRestrictNoSlot1Store = 1;
27414 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27415 let DecoderNamespace = "EXT_mmvec";
27417 def V6_vL32b_nt_tmp_npred_pi : HInst<
27418 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27419 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27420 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
27421 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27422 let Inst{7-5} = 0b111;
27423 let Inst{13-13} = 0b0;
27424 let Inst{31-21} = 0b00101001110;
27425 let isPredicated = 1;
27426 let isPredicatedFalse = 1;
27427 let hasNewValue = 1;
27428 let opNewValue = 0;
27429 let addrMode = PostInc;
27430 let accessSize = HVXVectorAccess;
27433 let isNonTemporal = 1;
27434 let isRestrictNoSlot1Store = 1;
27435 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27436 let DecoderNamespace = "EXT_mmvec";
27437 let Constraints = "$Rx32 = $Rx32in";
27439 def V6_vL32b_nt_tmp_npred_ppu : HInst<
27440 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27441 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27442 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
27443 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27444 let Inst{10-5} = 0b000111;
27445 let Inst{31-21} = 0b00101011110;
27446 let isPredicated = 1;
27447 let isPredicatedFalse = 1;
27448 let hasNewValue = 1;
27449 let opNewValue = 0;
27450 let addrMode = PostInc;
27451 let accessSize = HVXVectorAccess;
27454 let isNonTemporal = 1;
27455 let isRestrictNoSlot1Store = 1;
27456 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27457 let DecoderNamespace = "EXT_mmvec";
27458 let Constraints = "$Rx32 = $Rx32in";
27460 def V6_vL32b_nt_tmp_pi : HInst<
27461 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27462 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27463 "$Vd32.tmp = vmem($Rx32++#$Ii):nt",
27464 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27465 let Inst{7-5} = 0b010;
27466 let Inst{13-11} = 0b000;
27467 let Inst{31-21} = 0b00101001010;
27468 let hasNewValue = 1;
27469 let opNewValue = 0;
27470 let addrMode = PostInc;
27471 let accessSize = HVXVectorAccess;
27474 let isNonTemporal = 1;
27475 let isRestrictNoSlot1Store = 1;
27476 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27477 let isPredicable = 1;
27478 let DecoderNamespace = "EXT_mmvec";
27479 let Constraints = "$Rx32 = $Rx32in";
27481 def V6_vL32b_nt_tmp_ppu : HInst<
27482 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27483 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
27484 "$Vd32.tmp = vmem($Rx32++$Mu2):nt",
27485 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27486 let Inst{12-5} = 0b00000010;
27487 let Inst{31-21} = 0b00101011010;
27488 let hasNewValue = 1;
27489 let opNewValue = 0;
27490 let addrMode = PostInc;
27491 let accessSize = HVXVectorAccess;
27494 let isNonTemporal = 1;
27495 let isRestrictNoSlot1Store = 1;
27496 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27497 let isPredicable = 1;
27498 let DecoderNamespace = "EXT_mmvec";
27499 let Constraints = "$Rx32 = $Rx32in";
27501 def V6_vL32b_nt_tmp_pred_ai : HInst<
27502 (outs HvxVR:$Vd32),
27503 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27504 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
27505 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27506 let Inst{7-5} = 0b110;
27507 let Inst{31-21} = 0b00101000110;
27508 let isPredicated = 1;
27509 let hasNewValue = 1;
27510 let opNewValue = 0;
27511 let addrMode = BaseImmOffset;
27512 let accessSize = HVXVectorAccess;
27515 let isNonTemporal = 1;
27516 let isRestrictNoSlot1Store = 1;
27517 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27518 let DecoderNamespace = "EXT_mmvec";
27520 def V6_vL32b_nt_tmp_pred_pi : HInst<
27521 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27522 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27523 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
27524 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27525 let Inst{7-5} = 0b110;
27526 let Inst{13-13} = 0b0;
27527 let Inst{31-21} = 0b00101001110;
27528 let isPredicated = 1;
27529 let hasNewValue = 1;
27530 let opNewValue = 0;
27531 let addrMode = PostInc;
27532 let accessSize = HVXVectorAccess;
27535 let isNonTemporal = 1;
27536 let isRestrictNoSlot1Store = 1;
27537 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27538 let DecoderNamespace = "EXT_mmvec";
27539 let Constraints = "$Rx32 = $Rx32in";
27541 def V6_vL32b_nt_tmp_pred_ppu : HInst<
27542 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27543 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27544 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
27545 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27546 let Inst{10-5} = 0b000110;
27547 let Inst{31-21} = 0b00101011110;
27548 let isPredicated = 1;
27549 let hasNewValue = 1;
27550 let opNewValue = 0;
27551 let addrMode = PostInc;
27552 let accessSize = HVXVectorAccess;
27555 let isNonTemporal = 1;
27556 let isRestrictNoSlot1Store = 1;
27557 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27558 let DecoderNamespace = "EXT_mmvec";
27559 let Constraints = "$Rx32 = $Rx32in";
27561 def V6_vL32b_pi : HInst<
27562 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27563 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27564 "$Vd32 = vmem($Rx32++#$Ii)",
27565 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27566 let Inst{7-5} = 0b000;
27567 let Inst{13-11} = 0b000;
27568 let Inst{31-21} = 0b00101001000;
27569 let hasNewValue = 1;
27570 let opNewValue = 0;
27571 let addrMode = PostInc;
27572 let accessSize = HVXVectorAccess;
27575 let isRestrictNoSlot1Store = 1;
27576 let BaseOpcode = "V6_vL32b_pi";
27577 let isCVLoadable = 1;
27578 let isPredicable = 1;
27579 let DecoderNamespace = "EXT_mmvec";
27580 let Constraints = "$Rx32 = $Rx32in";
27582 def V6_vL32b_ppu : HInst<
27583 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27584 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
27585 "$Vd32 = vmem($Rx32++$Mu2)",
27586 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27587 let Inst{12-5} = 0b00000000;
27588 let Inst{31-21} = 0b00101011000;
27589 let hasNewValue = 1;
27590 let opNewValue = 0;
27591 let addrMode = PostInc;
27592 let accessSize = HVXVectorAccess;
27595 let isRestrictNoSlot1Store = 1;
27596 let BaseOpcode = "V6_vL32b_ppu";
27597 let isCVLoadable = 1;
27598 let isPredicable = 1;
27599 let DecoderNamespace = "EXT_mmvec";
27600 let Constraints = "$Rx32 = $Rx32in";
27602 def V6_vL32b_pred_ai : HInst<
27603 (outs HvxVR:$Vd32),
27604 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27605 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27606 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27607 let Inst{7-5} = 0b010;
27608 let Inst{31-21} = 0b00101000100;
27609 let isPredicated = 1;
27610 let hasNewValue = 1;
27611 let opNewValue = 0;
27612 let addrMode = BaseImmOffset;
27613 let accessSize = HVXVectorAccess;
27616 let isRestrictNoSlot1Store = 1;
27617 let BaseOpcode = "V6_vL32b_ai";
27618 let DecoderNamespace = "EXT_mmvec";
27620 def V6_vL32b_pred_pi : HInst<
27621 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27622 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27623 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27624 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27625 let Inst{7-5} = 0b010;
27626 let Inst{13-13} = 0b0;
27627 let Inst{31-21} = 0b00101001100;
27628 let isPredicated = 1;
27629 let hasNewValue = 1;
27630 let opNewValue = 0;
27631 let addrMode = PostInc;
27632 let accessSize = HVXVectorAccess;
27635 let isRestrictNoSlot1Store = 1;
27636 let BaseOpcode = "V6_vL32b_pi";
27637 let DecoderNamespace = "EXT_mmvec";
27638 let Constraints = "$Rx32 = $Rx32in";
27640 def V6_vL32b_pred_ppu : HInst<
27641 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27642 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27643 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27644 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27645 let Inst{10-5} = 0b000010;
27646 let Inst{31-21} = 0b00101011100;
27647 let isPredicated = 1;
27648 let hasNewValue = 1;
27649 let opNewValue = 0;
27650 let addrMode = PostInc;
27651 let accessSize = HVXVectorAccess;
27654 let isRestrictNoSlot1Store = 1;
27655 let BaseOpcode = "V6_vL32b_ppu";
27656 let DecoderNamespace = "EXT_mmvec";
27657 let Constraints = "$Rx32 = $Rx32in";
27659 def V6_vL32b_tmp_ai : HInst<
27660 (outs HvxVR:$Vd32),
27661 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
27662 "$Vd32.tmp = vmem($Rt32+#$Ii)",
27663 tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27664 let Inst{7-5} = 0b010;
27665 let Inst{12-11} = 0b00;
27666 let Inst{31-21} = 0b00101000000;
27667 let hasNewValue = 1;
27668 let opNewValue = 0;
27669 let addrMode = BaseImmOffset;
27670 let accessSize = HVXVectorAccess;
27673 let isRestrictNoSlot1Store = 1;
27674 let BaseOpcode = "V6_vL32b_tmp_ai";
27675 let isPredicable = 1;
27676 let DecoderNamespace = "EXT_mmvec";
27678 def V6_vL32b_tmp_npred_ai : HInst<
27679 (outs HvxVR:$Vd32),
27680 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27681 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
27682 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27683 let Inst{7-5} = 0b111;
27684 let Inst{31-21} = 0b00101000100;
27685 let isPredicated = 1;
27686 let isPredicatedFalse = 1;
27687 let hasNewValue = 1;
27688 let opNewValue = 0;
27689 let addrMode = BaseImmOffset;
27690 let accessSize = HVXVectorAccess;
27693 let isRestrictNoSlot1Store = 1;
27694 let BaseOpcode = "V6_vL32b_tmp_ai";
27695 let DecoderNamespace = "EXT_mmvec";
27697 def V6_vL32b_tmp_npred_pi : HInst<
27698 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27699 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27700 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
27701 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27702 let Inst{7-5} = 0b111;
27703 let Inst{13-13} = 0b0;
27704 let Inst{31-21} = 0b00101001100;
27705 let isPredicated = 1;
27706 let isPredicatedFalse = 1;
27707 let hasNewValue = 1;
27708 let opNewValue = 0;
27709 let addrMode = PostInc;
27710 let accessSize = HVXVectorAccess;
27713 let isRestrictNoSlot1Store = 1;
27714 let BaseOpcode = "V6_vL32b_tmp_pi";
27715 let DecoderNamespace = "EXT_mmvec";
27716 let Constraints = "$Rx32 = $Rx32in";
27718 def V6_vL32b_tmp_npred_ppu : HInst<
27719 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27720 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27721 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
27722 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27723 let Inst{10-5} = 0b000111;
27724 let Inst{31-21} = 0b00101011100;
27725 let isPredicated = 1;
27726 let isPredicatedFalse = 1;
27727 let hasNewValue = 1;
27728 let opNewValue = 0;
27729 let addrMode = PostInc;
27730 let accessSize = HVXVectorAccess;
27733 let isRestrictNoSlot1Store = 1;
27734 let BaseOpcode = "V6_vL32b_tmp_ppu";
27735 let DecoderNamespace = "EXT_mmvec";
27736 let Constraints = "$Rx32 = $Rx32in";
27738 def V6_vL32b_tmp_pi : HInst<
27739 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27740 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27741 "$Vd32.tmp = vmem($Rx32++#$Ii)",
27742 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27743 let Inst{7-5} = 0b010;
27744 let Inst{13-11} = 0b000;
27745 let Inst{31-21} = 0b00101001000;
27746 let hasNewValue = 1;
27747 let opNewValue = 0;
27748 let addrMode = PostInc;
27749 let accessSize = HVXVectorAccess;
27752 let isRestrictNoSlot1Store = 1;
27753 let BaseOpcode = "V6_vL32b_tmp_pi";
27754 let isPredicable = 1;
27755 let DecoderNamespace = "EXT_mmvec";
27756 let Constraints = "$Rx32 = $Rx32in";
27758 def V6_vL32b_tmp_ppu : HInst<
27759 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27760 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
27761 "$Vd32.tmp = vmem($Rx32++$Mu2)",
27762 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27763 let Inst{12-5} = 0b00000010;
27764 let Inst{31-21} = 0b00101011000;
27765 let hasNewValue = 1;
27766 let opNewValue = 0;
27767 let addrMode = PostInc;
27768 let accessSize = HVXVectorAccess;
27771 let isRestrictNoSlot1Store = 1;
27772 let BaseOpcode = "V6_vL32b_tmp_ppu";
27773 let isPredicable = 1;
27774 let DecoderNamespace = "EXT_mmvec";
27775 let Constraints = "$Rx32 = $Rx32in";
27777 def V6_vL32b_tmp_pred_ai : HInst<
27778 (outs HvxVR:$Vd32),
27779 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27780 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
27781 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27782 let Inst{7-5} = 0b110;
27783 let Inst{31-21} = 0b00101000100;
27784 let isPredicated = 1;
27785 let hasNewValue = 1;
27786 let opNewValue = 0;
27787 let addrMode = BaseImmOffset;
27788 let accessSize = HVXVectorAccess;
27791 let isRestrictNoSlot1Store = 1;
27792 let BaseOpcode = "V6_vL32b_tmp_ai";
27793 let DecoderNamespace = "EXT_mmvec";
27795 def V6_vL32b_tmp_pred_pi : HInst<
27796 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27797 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27798 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
27799 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27800 let Inst{7-5} = 0b110;
27801 let Inst{13-13} = 0b0;
27802 let Inst{31-21} = 0b00101001100;
27803 let isPredicated = 1;
27804 let hasNewValue = 1;
27805 let opNewValue = 0;
27806 let addrMode = PostInc;
27807 let accessSize = HVXVectorAccess;
27810 let isRestrictNoSlot1Store = 1;
27811 let BaseOpcode = "V6_vL32b_tmp_pi";
27812 let DecoderNamespace = "EXT_mmvec";
27813 let Constraints = "$Rx32 = $Rx32in";
27815 def V6_vL32b_tmp_pred_ppu : HInst<
27816 (outs HvxVR:$Vd32, IntRegs:$Rx32),
27817 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27818 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
27819 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27820 let Inst{10-5} = 0b000110;
27821 let Inst{31-21} = 0b00101011100;
27822 let isPredicated = 1;
27823 let hasNewValue = 1;
27824 let opNewValue = 0;
27825 let addrMode = PostInc;
27826 let accessSize = HVXVectorAccess;
27829 let isRestrictNoSlot1Store = 1;
27830 let BaseOpcode = "V6_vL32b_tmp_ppu";
27831 let DecoderNamespace = "EXT_mmvec";
27832 let Constraints = "$Rx32 = $Rx32in";
27834 def V6_vS32Ub_ai : HInst<
27836 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
27837 "vmemu($Rt32+#$Ii) = $Vs32",
27838 tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
27839 let Inst{7-5} = 0b111;
27840 let Inst{12-11} = 0b00;
27841 let Inst{31-21} = 0b00101000001;
27842 let addrMode = BaseImmOffset;
27843 let accessSize = HVXVectorAccess;
27845 let BaseOpcode = "V6_vS32Ub_ai";
27846 let isPredicable = 1;
27847 let DecoderNamespace = "EXT_mmvec";
27849 def V6_vS32Ub_npred_ai : HInst<
27851 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
27852 "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
27853 tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
27854 let Inst{7-5} = 0b111;
27855 let Inst{31-21} = 0b00101000101;
27856 let isPredicated = 1;
27857 let isPredicatedFalse = 1;
27858 let addrMode = BaseImmOffset;
27859 let accessSize = HVXVectorAccess;
27861 let BaseOpcode = "V6_vS32Ub_ai";
27862 let DecoderNamespace = "EXT_mmvec";
27864 def V6_vS32Ub_npred_pi : HInst<
27865 (outs IntRegs:$Rx32),
27866 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
27867 "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
27868 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
27869 let Inst{7-5} = 0b111;
27870 let Inst{13-13} = 0b0;
27871 let Inst{31-21} = 0b00101001101;
27872 let isPredicated = 1;
27873 let isPredicatedFalse = 1;
27874 let addrMode = PostInc;
27875 let accessSize = HVXVectorAccess;
27877 let BaseOpcode = "V6_vS32Ub_pi";
27878 let DecoderNamespace = "EXT_mmvec";
27879 let Constraints = "$Rx32 = $Rx32in";
27881 def V6_vS32Ub_npred_ppu : HInst<
27882 (outs IntRegs:$Rx32),
27883 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
27884 "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
27885 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
27886 let Inst{10-5} = 0b000111;
27887 let Inst{31-21} = 0b00101011101;
27888 let isPredicated = 1;
27889 let isPredicatedFalse = 1;
27890 let addrMode = PostInc;
27891 let accessSize = HVXVectorAccess;
27893 let BaseOpcode = "V6_vS32Ub_ppu";
27894 let DecoderNamespace = "EXT_mmvec";
27895 let Constraints = "$Rx32 = $Rx32in";
27897 def V6_vS32Ub_pi : HInst<
27898 (outs IntRegs:$Rx32),
27899 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
27900 "vmemu($Rx32++#$Ii) = $Vs32",
27901 tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
27902 let Inst{7-5} = 0b111;
27903 let Inst{13-11} = 0b000;
27904 let Inst{31-21} = 0b00101001001;
27905 let addrMode = PostInc;
27906 let accessSize = HVXVectorAccess;
27908 let BaseOpcode = "V6_vS32Ub_pi";
27909 let isPredicable = 1;
27910 let DecoderNamespace = "EXT_mmvec";
27911 let Constraints = "$Rx32 = $Rx32in";
27913 def V6_vS32Ub_ppu : HInst<
27914 (outs IntRegs:$Rx32),
27915 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
27916 "vmemu($Rx32++$Mu2) = $Vs32",
27917 tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
27918 let Inst{12-5} = 0b00000111;
27919 let Inst{31-21} = 0b00101011001;
27920 let addrMode = PostInc;
27921 let accessSize = HVXVectorAccess;
27923 let BaseOpcode = "V6_vS32Ub_ppu";
27924 let isPredicable = 1;
27925 let DecoderNamespace = "EXT_mmvec";
27926 let Constraints = "$Rx32 = $Rx32in";
27928 def V6_vS32Ub_pred_ai : HInst<
27930 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
27931 "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
27932 tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
27933 let Inst{7-5} = 0b110;
27934 let Inst{31-21} = 0b00101000101;
27935 let isPredicated = 1;
27936 let addrMode = BaseImmOffset;
27937 let accessSize = HVXVectorAccess;
27939 let BaseOpcode = "V6_vS32Ub_ai";
27940 let DecoderNamespace = "EXT_mmvec";
27942 def V6_vS32Ub_pred_pi : HInst<
27943 (outs IntRegs:$Rx32),
27944 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
27945 "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
27946 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
27947 let Inst{7-5} = 0b110;
27948 let Inst{13-13} = 0b0;
27949 let Inst{31-21} = 0b00101001101;
27950 let isPredicated = 1;
27951 let addrMode = PostInc;
27952 let accessSize = HVXVectorAccess;
27954 let BaseOpcode = "V6_vS32Ub_pi";
27955 let DecoderNamespace = "EXT_mmvec";
27956 let Constraints = "$Rx32 = $Rx32in";
27958 def V6_vS32Ub_pred_ppu : HInst<
27959 (outs IntRegs:$Rx32),
27960 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
27961 "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
27962 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
27963 let Inst{10-5} = 0b000110;
27964 let Inst{31-21} = 0b00101011101;
27965 let isPredicated = 1;
27966 let addrMode = PostInc;
27967 let accessSize = HVXVectorAccess;
27969 let BaseOpcode = "V6_vS32Ub_ppu";
27970 let DecoderNamespace = "EXT_mmvec";
27971 let Constraints = "$Rx32 = $Rx32in";
27973 def V6_vS32b_ai : HInst<
27975 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
27976 "vmem($Rt32+#$Ii) = $Vs32",
27977 tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
27978 let Inst{7-5} = 0b000;
27979 let Inst{12-11} = 0b00;
27980 let Inst{31-21} = 0b00101000001;
27981 let addrMode = BaseImmOffset;
27982 let accessSize = HVXVectorAccess;
27984 let BaseOpcode = "V6_vS32b_ai";
27985 let isNVStorable = 1;
27986 let isPredicable = 1;
27987 let DecoderNamespace = "EXT_mmvec";
27989 def V6_vS32b_new_ai : HInst<
27991 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
27992 "vmem($Rt32+#$Ii) = $Os8.new",
27993 tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
27994 let Inst{7-3} = 0b00100;
27995 let Inst{12-11} = 0b00;
27996 let Inst{31-21} = 0b00101000001;
27997 let addrMode = BaseImmOffset;
27998 let accessSize = HVXVectorAccess;
28001 let isNewValue = 1;
28003 let BaseOpcode = "V6_vS32b_ai";
28004 let isPredicable = 1;
28005 let DecoderNamespace = "EXT_mmvec";
28006 let opNewValue = 2;
28008 def V6_vS32b_new_npred_ai : HInst<
28010 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28011 "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28012 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28013 let Inst{7-3} = 0b01101;
28014 let Inst{31-21} = 0b00101000101;
28015 let isPredicated = 1;
28016 let isPredicatedFalse = 1;
28017 let addrMode = BaseImmOffset;
28018 let accessSize = HVXVectorAccess;
28021 let isNewValue = 1;
28023 let BaseOpcode = "V6_vS32b_ai";
28024 let DecoderNamespace = "EXT_mmvec";
28025 let opNewValue = 3;
28027 def V6_vS32b_new_npred_pi : HInst<
28028 (outs IntRegs:$Rx32),
28029 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28030 "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28031 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28032 let Inst{7-3} = 0b01101;
28033 let Inst{13-13} = 0b0;
28034 let Inst{31-21} = 0b00101001101;
28035 let isPredicated = 1;
28036 let isPredicatedFalse = 1;
28037 let addrMode = PostInc;
28038 let accessSize = HVXVectorAccess;
28041 let isNewValue = 1;
28043 let BaseOpcode = "V6_vS32b_pi";
28044 let DecoderNamespace = "EXT_mmvec";
28045 let opNewValue = 4;
28046 let Constraints = "$Rx32 = $Rx32in";
28048 def V6_vS32b_new_npred_ppu : HInst<
28049 (outs IntRegs:$Rx32),
28050 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28051 "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28052 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28053 let Inst{10-3} = 0b00001101;
28054 let Inst{31-21} = 0b00101011101;
28055 let isPredicated = 1;
28056 let isPredicatedFalse = 1;
28057 let addrMode = PostInc;
28058 let accessSize = HVXVectorAccess;
28061 let isNewValue = 1;
28063 let BaseOpcode = "V6_vS32b_ppu";
28064 let DecoderNamespace = "EXT_mmvec";
28065 let opNewValue = 4;
28066 let Constraints = "$Rx32 = $Rx32in";
28068 def V6_vS32b_new_pi : HInst<
28069 (outs IntRegs:$Rx32),
28070 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28071 "vmem($Rx32++#$Ii) = $Os8.new",
28072 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28073 let Inst{7-3} = 0b00100;
28074 let Inst{13-11} = 0b000;
28075 let Inst{31-21} = 0b00101001001;
28076 let addrMode = PostInc;
28077 let accessSize = HVXVectorAccess;
28080 let isNewValue = 1;
28082 let BaseOpcode = "V6_vS32b_pi";
28083 let isPredicable = 1;
28084 let DecoderNamespace = "EXT_mmvec";
28085 let opNewValue = 3;
28086 let Constraints = "$Rx32 = $Rx32in";
28088 def V6_vS32b_new_ppu : HInst<
28089 (outs IntRegs:$Rx32),
28090 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28091 "vmem($Rx32++$Mu2) = $Os8.new",
28092 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28093 let Inst{12-3} = 0b0000000100;
28094 let Inst{31-21} = 0b00101011001;
28095 let addrMode = PostInc;
28096 let accessSize = HVXVectorAccess;
28099 let isNewValue = 1;
28101 let BaseOpcode = "V6_vS32b_ppu";
28102 let isPredicable = 1;
28103 let DecoderNamespace = "EXT_mmvec";
28104 let opNewValue = 3;
28105 let Constraints = "$Rx32 = $Rx32in";
28107 def V6_vS32b_new_pred_ai : HInst<
28109 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28110 "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28111 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28112 let Inst{7-3} = 0b01000;
28113 let Inst{31-21} = 0b00101000101;
28114 let isPredicated = 1;
28115 let addrMode = BaseImmOffset;
28116 let accessSize = HVXVectorAccess;
28119 let isNewValue = 1;
28121 let BaseOpcode = "V6_vS32b_ai";
28122 let DecoderNamespace = "EXT_mmvec";
28123 let opNewValue = 3;
28125 def V6_vS32b_new_pred_pi : HInst<
28126 (outs IntRegs:$Rx32),
28127 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28128 "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28129 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28130 let Inst{7-3} = 0b01000;
28131 let Inst{13-13} = 0b0;
28132 let Inst{31-21} = 0b00101001101;
28133 let isPredicated = 1;
28134 let addrMode = PostInc;
28135 let accessSize = HVXVectorAccess;
28138 let isNewValue = 1;
28140 let BaseOpcode = "V6_vS32b_pi";
28141 let DecoderNamespace = "EXT_mmvec";
28142 let opNewValue = 4;
28143 let Constraints = "$Rx32 = $Rx32in";
28145 def V6_vS32b_new_pred_ppu : HInst<
28146 (outs IntRegs:$Rx32),
28147 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28148 "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28149 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28150 let Inst{10-3} = 0b00001000;
28151 let Inst{31-21} = 0b00101011101;
28152 let isPredicated = 1;
28153 let addrMode = PostInc;
28154 let accessSize = HVXVectorAccess;
28157 let isNewValue = 1;
28159 let BaseOpcode = "V6_vS32b_ppu";
28160 let DecoderNamespace = "EXT_mmvec";
28161 let opNewValue = 4;
28162 let Constraints = "$Rx32 = $Rx32in";
28164 def V6_vS32b_npred_ai : HInst<
28166 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28167 "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
28168 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28169 let Inst{7-5} = 0b001;
28170 let Inst{31-21} = 0b00101000101;
28171 let isPredicated = 1;
28172 let isPredicatedFalse = 1;
28173 let addrMode = BaseImmOffset;
28174 let accessSize = HVXVectorAccess;
28176 let BaseOpcode = "V6_vS32b_ai";
28177 let isNVStorable = 1;
28178 let DecoderNamespace = "EXT_mmvec";
28180 def V6_vS32b_npred_pi : HInst<
28181 (outs IntRegs:$Rx32),
28182 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28183 "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
28184 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28185 let Inst{7-5} = 0b001;
28186 let Inst{13-13} = 0b0;
28187 let Inst{31-21} = 0b00101001101;
28188 let isPredicated = 1;
28189 let isPredicatedFalse = 1;
28190 let addrMode = PostInc;
28191 let accessSize = HVXVectorAccess;
28193 let BaseOpcode = "V6_vS32b_pi";
28194 let isNVStorable = 1;
28195 let DecoderNamespace = "EXT_mmvec";
28196 let Constraints = "$Rx32 = $Rx32in";
28198 def V6_vS32b_npred_ppu : HInst<
28199 (outs IntRegs:$Rx32),
28200 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28201 "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
28202 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28203 let Inst{10-5} = 0b000001;
28204 let Inst{31-21} = 0b00101011101;
28205 let isPredicated = 1;
28206 let isPredicatedFalse = 1;
28207 let addrMode = PostInc;
28208 let accessSize = HVXVectorAccess;
28210 let BaseOpcode = "V6_vS32b_ppu";
28211 let isNVStorable = 1;
28212 let DecoderNamespace = "EXT_mmvec";
28213 let Constraints = "$Rx32 = $Rx32in";
28215 def V6_vS32b_nqpred_ai : HInst<
28217 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28218 "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
28219 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28220 let Inst{7-5} = 0b001;
28221 let Inst{31-21} = 0b00101000100;
28222 let addrMode = BaseImmOffset;
28223 let accessSize = HVXVectorAccess;
28225 let DecoderNamespace = "EXT_mmvec";
28227 def V6_vS32b_nqpred_pi : HInst<
28228 (outs IntRegs:$Rx32),
28229 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28230 "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
28231 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28232 let Inst{7-5} = 0b001;
28233 let Inst{13-13} = 0b0;
28234 let Inst{31-21} = 0b00101001100;
28235 let addrMode = PostInc;
28236 let accessSize = HVXVectorAccess;
28238 let DecoderNamespace = "EXT_mmvec";
28239 let Constraints = "$Rx32 = $Rx32in";
28241 def V6_vS32b_nqpred_ppu : HInst<
28242 (outs IntRegs:$Rx32),
28243 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28244 "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
28245 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28246 let Inst{10-5} = 0b000001;
28247 let Inst{31-21} = 0b00101011100;
28248 let addrMode = PostInc;
28249 let accessSize = HVXVectorAccess;
28251 let DecoderNamespace = "EXT_mmvec";
28252 let Constraints = "$Rx32 = $Rx32in";
28254 def V6_vS32b_nt_ai : HInst<
28256 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28257 "vmem($Rt32+#$Ii):nt = $Vs32",
28258 tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28259 let Inst{7-5} = 0b000;
28260 let Inst{12-11} = 0b00;
28261 let Inst{31-21} = 0b00101000011;
28262 let addrMode = BaseImmOffset;
28263 let accessSize = HVXVectorAccess;
28264 let isNonTemporal = 1;
28266 let BaseOpcode = "V6_vS32b_ai";
28267 let isNVStorable = 1;
28268 let isPredicable = 1;
28269 let DecoderNamespace = "EXT_mmvec";
28271 def V6_vS32b_nt_new_ai : HInst<
28273 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28274 "vmem($Rt32+#$Ii):nt = $Os8.new",
28275 tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28276 let Inst{7-3} = 0b00100;
28277 let Inst{12-11} = 0b00;
28278 let Inst{31-21} = 0b00101000011;
28279 let addrMode = BaseImmOffset;
28280 let accessSize = HVXVectorAccess;
28283 let isNewValue = 1;
28284 let isNonTemporal = 1;
28286 let BaseOpcode = "V6_vS32b_ai";
28287 let isPredicable = 1;
28288 let DecoderNamespace = "EXT_mmvec";
28289 let opNewValue = 2;
28291 def V6_vS32b_nt_new_npred_ai : HInst<
28293 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28294 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
28295 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28296 let Inst{7-3} = 0b01111;
28297 let Inst{31-21} = 0b00101000111;
28298 let isPredicated = 1;
28299 let isPredicatedFalse = 1;
28300 let addrMode = BaseImmOffset;
28301 let accessSize = HVXVectorAccess;
28304 let isNewValue = 1;
28305 let isNonTemporal = 1;
28307 let BaseOpcode = "V6_vS32b_ai";
28308 let DecoderNamespace = "EXT_mmvec";
28309 let opNewValue = 3;
28311 def V6_vS32b_nt_new_npred_pi : HInst<
28312 (outs IntRegs:$Rx32),
28313 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28314 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
28315 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28316 let Inst{7-3} = 0b01111;
28317 let Inst{13-13} = 0b0;
28318 let Inst{31-21} = 0b00101001111;
28319 let isPredicated = 1;
28320 let isPredicatedFalse = 1;
28321 let addrMode = PostInc;
28322 let accessSize = HVXVectorAccess;
28325 let isNewValue = 1;
28326 let isNonTemporal = 1;
28328 let BaseOpcode = "V6_vS32b_pi";
28329 let DecoderNamespace = "EXT_mmvec";
28330 let opNewValue = 4;
28331 let Constraints = "$Rx32 = $Rx32in";
28333 def V6_vS32b_nt_new_npred_ppu : HInst<
28334 (outs IntRegs:$Rx32),
28335 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28336 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
28337 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28338 let Inst{10-3} = 0b00001111;
28339 let Inst{31-21} = 0b00101011111;
28340 let isPredicated = 1;
28341 let isPredicatedFalse = 1;
28342 let addrMode = PostInc;
28343 let accessSize = HVXVectorAccess;
28346 let isNewValue = 1;
28347 let isNonTemporal = 1;
28349 let BaseOpcode = "V6_vS32b_ppu";
28350 let DecoderNamespace = "EXT_mmvec";
28351 let opNewValue = 4;
28352 let Constraints = "$Rx32 = $Rx32in";
28354 def V6_vS32b_nt_new_pi : HInst<
28355 (outs IntRegs:$Rx32),
28356 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28357 "vmem($Rx32++#$Ii):nt = $Os8.new",
28358 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28359 let Inst{7-3} = 0b00100;
28360 let Inst{13-11} = 0b000;
28361 let Inst{31-21} = 0b00101001011;
28362 let addrMode = PostInc;
28363 let accessSize = HVXVectorAccess;
28366 let isNewValue = 1;
28367 let isNonTemporal = 1;
28369 let BaseOpcode = "V6_vS32b_pi";
28370 let isPredicable = 1;
28371 let DecoderNamespace = "EXT_mmvec";
28372 let opNewValue = 3;
28373 let Constraints = "$Rx32 = $Rx32in";
28375 def V6_vS32b_nt_new_ppu : HInst<
28376 (outs IntRegs:$Rx32),
28377 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28378 "vmem($Rx32++$Mu2):nt = $Os8.new",
28379 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28380 let Inst{12-3} = 0b0000000100;
28381 let Inst{31-21} = 0b00101011011;
28382 let addrMode = PostInc;
28383 let accessSize = HVXVectorAccess;
28386 let isNewValue = 1;
28387 let isNonTemporal = 1;
28389 let BaseOpcode = "V6_vS32b_ppu";
28390 let isPredicable = 1;
28391 let DecoderNamespace = "EXT_mmvec";
28392 let opNewValue = 3;
28393 let Constraints = "$Rx32 = $Rx32in";
28395 def V6_vS32b_nt_new_pred_ai : HInst<
28397 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28398 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
28399 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28400 let Inst{7-3} = 0b01010;
28401 let Inst{31-21} = 0b00101000111;
28402 let isPredicated = 1;
28403 let addrMode = BaseImmOffset;
28404 let accessSize = HVXVectorAccess;
28407 let isNewValue = 1;
28408 let isNonTemporal = 1;
28410 let BaseOpcode = "V6_vS32b_ai";
28411 let DecoderNamespace = "EXT_mmvec";
28412 let opNewValue = 3;
28414 def V6_vS32b_nt_new_pred_pi : HInst<
28415 (outs IntRegs:$Rx32),
28416 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28417 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
28418 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28419 let Inst{7-3} = 0b01010;
28420 let Inst{13-13} = 0b0;
28421 let Inst{31-21} = 0b00101001111;
28422 let isPredicated = 1;
28423 let addrMode = PostInc;
28424 let accessSize = HVXVectorAccess;
28427 let isNewValue = 1;
28428 let isNonTemporal = 1;
28430 let BaseOpcode = "V6_vS32b_pi";
28431 let DecoderNamespace = "EXT_mmvec";
28432 let opNewValue = 4;
28433 let Constraints = "$Rx32 = $Rx32in";
28435 def V6_vS32b_nt_new_pred_ppu : HInst<
28436 (outs IntRegs:$Rx32),
28437 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28438 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
28439 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28440 let Inst{10-3} = 0b00001010;
28441 let Inst{31-21} = 0b00101011111;
28442 let isPredicated = 1;
28443 let addrMode = PostInc;
28444 let accessSize = HVXVectorAccess;
28447 let isNewValue = 1;
28448 let isNonTemporal = 1;
28450 let BaseOpcode = "V6_vS32b_ppu";
28451 let DecoderNamespace = "EXT_mmvec";
28452 let opNewValue = 4;
28453 let Constraints = "$Rx32 = $Rx32in";
28455 def V6_vS32b_nt_npred_ai : HInst<
28457 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28458 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
28459 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28460 let Inst{7-5} = 0b001;
28461 let Inst{31-21} = 0b00101000111;
28462 let isPredicated = 1;
28463 let isPredicatedFalse = 1;
28464 let addrMode = BaseImmOffset;
28465 let accessSize = HVXVectorAccess;
28466 let isNonTemporal = 1;
28468 let BaseOpcode = "V6_vS32b_ai";
28469 let isNVStorable = 1;
28470 let DecoderNamespace = "EXT_mmvec";
28472 def V6_vS32b_nt_npred_pi : HInst<
28473 (outs IntRegs:$Rx32),
28474 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28475 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
28476 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28477 let Inst{7-5} = 0b001;
28478 let Inst{13-13} = 0b0;
28479 let Inst{31-21} = 0b00101001111;
28480 let isPredicated = 1;
28481 let isPredicatedFalse = 1;
28482 let addrMode = PostInc;
28483 let accessSize = HVXVectorAccess;
28484 let isNonTemporal = 1;
28486 let BaseOpcode = "V6_vS32b_pi";
28487 let isNVStorable = 1;
28488 let DecoderNamespace = "EXT_mmvec";
28489 let Constraints = "$Rx32 = $Rx32in";
28491 def V6_vS32b_nt_npred_ppu : HInst<
28492 (outs IntRegs:$Rx32),
28493 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28494 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
28495 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28496 let Inst{10-5} = 0b000001;
28497 let Inst{31-21} = 0b00101011111;
28498 let isPredicated = 1;
28499 let isPredicatedFalse = 1;
28500 let addrMode = PostInc;
28501 let accessSize = HVXVectorAccess;
28502 let isNonTemporal = 1;
28504 let BaseOpcode = "V6_vS32b_ppu";
28505 let isNVStorable = 1;
28506 let DecoderNamespace = "EXT_mmvec";
28507 let Constraints = "$Rx32 = $Rx32in";
28509 def V6_vS32b_nt_nqpred_ai : HInst<
28511 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28512 "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
28513 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28514 let Inst{7-5} = 0b001;
28515 let Inst{31-21} = 0b00101000110;
28516 let addrMode = BaseImmOffset;
28517 let accessSize = HVXVectorAccess;
28518 let isNonTemporal = 1;
28520 let DecoderNamespace = "EXT_mmvec";
28522 def V6_vS32b_nt_nqpred_pi : HInst<
28523 (outs IntRegs:$Rx32),
28524 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28525 "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
28526 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28527 let Inst{7-5} = 0b001;
28528 let Inst{13-13} = 0b0;
28529 let Inst{31-21} = 0b00101001110;
28530 let addrMode = PostInc;
28531 let accessSize = HVXVectorAccess;
28532 let isNonTemporal = 1;
28534 let DecoderNamespace = "EXT_mmvec";
28535 let Constraints = "$Rx32 = $Rx32in";
28537 def V6_vS32b_nt_nqpred_ppu : HInst<
28538 (outs IntRegs:$Rx32),
28539 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28540 "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
28541 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28542 let Inst{10-5} = 0b000001;
28543 let Inst{31-21} = 0b00101011110;
28544 let addrMode = PostInc;
28545 let accessSize = HVXVectorAccess;
28546 let isNonTemporal = 1;
28548 let DecoderNamespace = "EXT_mmvec";
28549 let Constraints = "$Rx32 = $Rx32in";
28551 def V6_vS32b_nt_pi : HInst<
28552 (outs IntRegs:$Rx32),
28553 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28554 "vmem($Rx32++#$Ii):nt = $Vs32",
28555 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28556 let Inst{7-5} = 0b000;
28557 let Inst{13-11} = 0b000;
28558 let Inst{31-21} = 0b00101001011;
28559 let addrMode = PostInc;
28560 let accessSize = HVXVectorAccess;
28561 let isNonTemporal = 1;
28563 let BaseOpcode = "V6_vS32b_pi";
28564 let isNVStorable = 1;
28565 let isPredicable = 1;
28566 let DecoderNamespace = "EXT_mmvec";
28567 let Constraints = "$Rx32 = $Rx32in";
28569 def V6_vS32b_nt_ppu : HInst<
28570 (outs IntRegs:$Rx32),
28571 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28572 "vmem($Rx32++$Mu2):nt = $Vs32",
28573 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28574 let Inst{12-5} = 0b00000000;
28575 let Inst{31-21} = 0b00101011011;
28576 let addrMode = PostInc;
28577 let accessSize = HVXVectorAccess;
28578 let isNonTemporal = 1;
28580 let BaseOpcode = "V6_vS32b_ppu";
28581 let isNVStorable = 1;
28582 let isPredicable = 1;
28583 let DecoderNamespace = "EXT_mmvec";
28584 let Constraints = "$Rx32 = $Rx32in";
28586 def V6_vS32b_nt_pred_ai : HInst<
28588 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28589 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
28590 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28591 let Inst{7-5} = 0b000;
28592 let Inst{31-21} = 0b00101000111;
28593 let isPredicated = 1;
28594 let addrMode = BaseImmOffset;
28595 let accessSize = HVXVectorAccess;
28596 let isNonTemporal = 1;
28598 let BaseOpcode = "V6_vS32b_ai";
28599 let isNVStorable = 1;
28600 let DecoderNamespace = "EXT_mmvec";
28602 def V6_vS32b_nt_pred_pi : HInst<
28603 (outs IntRegs:$Rx32),
28604 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28605 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
28606 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28607 let Inst{7-5} = 0b000;
28608 let Inst{13-13} = 0b0;
28609 let Inst{31-21} = 0b00101001111;
28610 let isPredicated = 1;
28611 let addrMode = PostInc;
28612 let accessSize = HVXVectorAccess;
28613 let isNonTemporal = 1;
28615 let BaseOpcode = "V6_vS32b_pi";
28616 let isNVStorable = 1;
28617 let DecoderNamespace = "EXT_mmvec";
28618 let Constraints = "$Rx32 = $Rx32in";
28620 def V6_vS32b_nt_pred_ppu : HInst<
28621 (outs IntRegs:$Rx32),
28622 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28623 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
28624 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28625 let Inst{10-5} = 0b000000;
28626 let Inst{31-21} = 0b00101011111;
28627 let isPredicated = 1;
28628 let addrMode = PostInc;
28629 let accessSize = HVXVectorAccess;
28630 let isNonTemporal = 1;
28632 let BaseOpcode = "V6_vS32b_ppu";
28633 let isNVStorable = 1;
28634 let DecoderNamespace = "EXT_mmvec";
28635 let Constraints = "$Rx32 = $Rx32in";
28637 def V6_vS32b_nt_qpred_ai : HInst<
28639 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28640 "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
28641 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28642 let Inst{7-5} = 0b000;
28643 let Inst{31-21} = 0b00101000110;
28644 let addrMode = BaseImmOffset;
28645 let accessSize = HVXVectorAccess;
28646 let isNonTemporal = 1;
28648 let DecoderNamespace = "EXT_mmvec";
28650 def V6_vS32b_nt_qpred_pi : HInst<
28651 (outs IntRegs:$Rx32),
28652 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28653 "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
28654 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28655 let Inst{7-5} = 0b000;
28656 let Inst{13-13} = 0b0;
28657 let Inst{31-21} = 0b00101001110;
28658 let addrMode = PostInc;
28659 let accessSize = HVXVectorAccess;
28660 let isNonTemporal = 1;
28662 let DecoderNamespace = "EXT_mmvec";
28663 let Constraints = "$Rx32 = $Rx32in";
28665 def V6_vS32b_nt_qpred_ppu : HInst<
28666 (outs IntRegs:$Rx32),
28667 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28668 "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
28669 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28670 let Inst{10-5} = 0b000000;
28671 let Inst{31-21} = 0b00101011110;
28672 let addrMode = PostInc;
28673 let accessSize = HVXVectorAccess;
28674 let isNonTemporal = 1;
28676 let DecoderNamespace = "EXT_mmvec";
28677 let Constraints = "$Rx32 = $Rx32in";
28679 def V6_vS32b_pi : HInst<
28680 (outs IntRegs:$Rx32),
28681 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28682 "vmem($Rx32++#$Ii) = $Vs32",
28683 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28684 let Inst{7-5} = 0b000;
28685 let Inst{13-11} = 0b000;
28686 let Inst{31-21} = 0b00101001001;
28687 let addrMode = PostInc;
28688 let accessSize = HVXVectorAccess;
28690 let BaseOpcode = "V6_vS32b_pi";
28691 let isNVStorable = 1;
28692 let isPredicable = 1;
28693 let DecoderNamespace = "EXT_mmvec";
28694 let Constraints = "$Rx32 = $Rx32in";
28696 def V6_vS32b_ppu : HInst<
28697 (outs IntRegs:$Rx32),
28698 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28699 "vmem($Rx32++$Mu2) = $Vs32",
28700 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28701 let Inst{12-5} = 0b00000000;
28702 let Inst{31-21} = 0b00101011001;
28703 let addrMode = PostInc;
28704 let accessSize = HVXVectorAccess;
28706 let isNVStorable = 1;
28707 let isPredicable = 1;
28708 let DecoderNamespace = "EXT_mmvec";
28709 let Constraints = "$Rx32 = $Rx32in";
28711 def V6_vS32b_pred_ai : HInst<
28713 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28714 "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
28715 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28716 let Inst{7-5} = 0b000;
28717 let Inst{31-21} = 0b00101000101;
28718 let isPredicated = 1;
28719 let addrMode = BaseImmOffset;
28720 let accessSize = HVXVectorAccess;
28722 let BaseOpcode = "V6_vS32b_ai";
28723 let isNVStorable = 1;
28724 let DecoderNamespace = "EXT_mmvec";
28726 def V6_vS32b_pred_pi : HInst<
28727 (outs IntRegs:$Rx32),
28728 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28729 "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
28730 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28731 let Inst{7-5} = 0b000;
28732 let Inst{13-13} = 0b0;
28733 let Inst{31-21} = 0b00101001101;
28734 let isPredicated = 1;
28735 let addrMode = PostInc;
28736 let accessSize = HVXVectorAccess;
28738 let BaseOpcode = "V6_vS32b_pi";
28739 let isNVStorable = 1;
28740 let DecoderNamespace = "EXT_mmvec";
28741 let Constraints = "$Rx32 = $Rx32in";
28743 def V6_vS32b_pred_ppu : HInst<
28744 (outs IntRegs:$Rx32),
28745 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28746 "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
28747 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28748 let Inst{10-5} = 0b000000;
28749 let Inst{31-21} = 0b00101011101;
28750 let isPredicated = 1;
28751 let addrMode = PostInc;
28752 let accessSize = HVXVectorAccess;
28754 let BaseOpcode = "V6_vS32b_ppu";
28755 let isNVStorable = 1;
28756 let DecoderNamespace = "EXT_mmvec";
28757 let Constraints = "$Rx32 = $Rx32in";
28759 def V6_vS32b_qpred_ai : HInst<
28761 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28762 "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
28763 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28764 let Inst{7-5} = 0b000;
28765 let Inst{31-21} = 0b00101000100;
28766 let addrMode = BaseImmOffset;
28767 let accessSize = HVXVectorAccess;
28769 let DecoderNamespace = "EXT_mmvec";
28771 def V6_vS32b_qpred_pi : HInst<
28772 (outs IntRegs:$Rx32),
28773 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28774 "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
28775 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28776 let Inst{7-5} = 0b000;
28777 let Inst{13-13} = 0b0;
28778 let Inst{31-21} = 0b00101001100;
28779 let addrMode = PostInc;
28780 let accessSize = HVXVectorAccess;
28782 let DecoderNamespace = "EXT_mmvec";
28783 let Constraints = "$Rx32 = $Rx32in";
28785 def V6_vS32b_qpred_ppu : HInst<
28786 (outs IntRegs:$Rx32),
28787 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28788 "if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
28789 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28790 let Inst{10-5} = 0b000000;
28791 let Inst{31-21} = 0b00101011100;
28792 let addrMode = PostInc;
28793 let accessSize = HVXVectorAccess;
28795 let DecoderNamespace = "EXT_mmvec";
28796 let Constraints = "$Rx32 = $Rx32in";
28798 def V6_vS32b_srls_ai : HInst<
28800 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
28801 "vmem($Rt32+#$Ii):scatter_release",
28802 tc_29841470, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
28803 let Inst{7-0} = 0b00101000;
28804 let Inst{12-11} = 0b00;
28805 let Inst{31-21} = 0b00101000001;
28806 let addrMode = BaseImmOffset;
28807 let accessSize = HVXVectorAccess;
28810 let DecoderNamespace = "EXT_mmvec";
28812 def V6_vS32b_srls_pi : HInst<
28813 (outs IntRegs:$Rx32),
28814 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28815 "vmem($Rx32++#$Ii):scatter_release",
28816 tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
28817 let Inst{7-0} = 0b00101000;
28818 let Inst{13-11} = 0b000;
28819 let Inst{31-21} = 0b00101001001;
28820 let addrMode = PostInc;
28821 let accessSize = HVXVectorAccess;
28824 let DecoderNamespace = "EXT_mmvec";
28825 let Constraints = "$Rx32 = $Rx32in";
28827 def V6_vS32b_srls_ppu : HInst<
28828 (outs IntRegs:$Rx32),
28829 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
28830 "vmem($Rx32++$Mu2):scatter_release",
28831 tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
28832 let Inst{12-0} = 0b0000000101000;
28833 let Inst{31-21} = 0b00101011001;
28834 let addrMode = PostInc;
28835 let accessSize = HVXVectorAccess;
28838 let DecoderNamespace = "EXT_mmvec";
28839 let Constraints = "$Rx32 = $Rx32in";
28841 def V6_vabsb : HInst<
28842 (outs HvxVR:$Vd32),
28844 "$Vd32.b = vabs($Vu32.b)",
28845 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
28846 let Inst{7-5} = 0b100;
28847 let Inst{13-13} = 0b0;
28848 let Inst{31-16} = 0b0001111000000001;
28849 let hasNewValue = 1;
28850 let opNewValue = 0;
28851 let DecoderNamespace = "EXT_mmvec";
28853 def V6_vabsb_alt : HInst<
28854 (outs HvxVR:$Vd32),
28856 "$Vd32 = vabsb($Vu32)",
28857 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
28858 let hasNewValue = 1;
28859 let opNewValue = 0;
28861 let isCodeGenOnly = 1;
28862 let DecoderNamespace = "EXT_mmvec";
28864 def V6_vabsb_sat : HInst<
28865 (outs HvxVR:$Vd32),
28867 "$Vd32.b = vabs($Vu32.b):sat",
28868 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
28869 let Inst{7-5} = 0b101;
28870 let Inst{13-13} = 0b0;
28871 let Inst{31-16} = 0b0001111000000001;
28872 let hasNewValue = 1;
28873 let opNewValue = 0;
28874 let DecoderNamespace = "EXT_mmvec";
28876 def V6_vabsb_sat_alt : HInst<
28877 (outs HvxVR:$Vd32),
28879 "$Vd32 = vabsb($Vu32):sat",
28880 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
28881 let hasNewValue = 1;
28882 let opNewValue = 0;
28884 let isCodeGenOnly = 1;
28885 let DecoderNamespace = "EXT_mmvec";
28887 def V6_vabsdiffh : HInst<
28888 (outs HvxVR:$Vd32),
28889 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28890 "$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
28891 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
28892 let Inst{7-5} = 0b001;
28893 let Inst{13-13} = 0b0;
28894 let Inst{31-21} = 0b00011100110;
28895 let hasNewValue = 1;
28896 let opNewValue = 0;
28897 let DecoderNamespace = "EXT_mmvec";
28899 def V6_vabsdiffh_alt : HInst<
28900 (outs HvxVR:$Vd32),
28901 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28902 "$Vd32 = vabsdiffh($Vu32,$Vv32)",
28903 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
28904 let hasNewValue = 1;
28905 let opNewValue = 0;
28907 let isCodeGenOnly = 1;
28908 let DecoderNamespace = "EXT_mmvec";
28910 def V6_vabsdiffub : HInst<
28911 (outs HvxVR:$Vd32),
28912 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28913 "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
28914 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
28915 let Inst{7-5} = 0b000;
28916 let Inst{13-13} = 0b0;
28917 let Inst{31-21} = 0b00011100110;
28918 let hasNewValue = 1;
28919 let opNewValue = 0;
28920 let DecoderNamespace = "EXT_mmvec";
28922 def V6_vabsdiffub_alt : HInst<
28923 (outs HvxVR:$Vd32),
28924 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28925 "$Vd32 = vabsdiffub($Vu32,$Vv32)",
28926 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
28927 let hasNewValue = 1;
28928 let opNewValue = 0;
28930 let isCodeGenOnly = 1;
28931 let DecoderNamespace = "EXT_mmvec";
28933 def V6_vabsdiffuh : HInst<
28934 (outs HvxVR:$Vd32),
28935 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28936 "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
28937 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
28938 let Inst{7-5} = 0b010;
28939 let Inst{13-13} = 0b0;
28940 let Inst{31-21} = 0b00011100110;
28941 let hasNewValue = 1;
28942 let opNewValue = 0;
28943 let DecoderNamespace = "EXT_mmvec";
28945 def V6_vabsdiffuh_alt : HInst<
28946 (outs HvxVR:$Vd32),
28947 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28948 "$Vd32 = vabsdiffuh($Vu32,$Vv32)",
28949 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
28950 let hasNewValue = 1;
28951 let opNewValue = 0;
28953 let isCodeGenOnly = 1;
28954 let DecoderNamespace = "EXT_mmvec";
28956 def V6_vabsdiffw : HInst<
28957 (outs HvxVR:$Vd32),
28958 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28959 "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
28960 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
28961 let Inst{7-5} = 0b011;
28962 let Inst{13-13} = 0b0;
28963 let Inst{31-21} = 0b00011100110;
28964 let hasNewValue = 1;
28965 let opNewValue = 0;
28966 let DecoderNamespace = "EXT_mmvec";
28968 def V6_vabsdiffw_alt : HInst<
28969 (outs HvxVR:$Vd32),
28970 (ins HvxVR:$Vu32, HvxVR:$Vv32),
28971 "$Vd32 = vabsdiffw($Vu32,$Vv32)",
28972 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
28973 let hasNewValue = 1;
28974 let opNewValue = 0;
28976 let isCodeGenOnly = 1;
28977 let DecoderNamespace = "EXT_mmvec";
28979 def V6_vabsh : HInst<
28980 (outs HvxVR:$Vd32),
28982 "$Vd32.h = vabs($Vu32.h)",
28983 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
28984 let Inst{7-5} = 0b000;
28985 let Inst{13-13} = 0b0;
28986 let Inst{31-16} = 0b0001111000000000;
28987 let hasNewValue = 1;
28988 let opNewValue = 0;
28989 let DecoderNamespace = "EXT_mmvec";
28991 def V6_vabsh_alt : HInst<
28992 (outs HvxVR:$Vd32),
28994 "$Vd32 = vabsh($Vu32)",
28995 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
28996 let hasNewValue = 1;
28997 let opNewValue = 0;
28999 let isCodeGenOnly = 1;
29000 let DecoderNamespace = "EXT_mmvec";
29002 def V6_vabsh_sat : HInst<
29003 (outs HvxVR:$Vd32),
29005 "$Vd32.h = vabs($Vu32.h):sat",
29006 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29007 let Inst{7-5} = 0b001;
29008 let Inst{13-13} = 0b0;
29009 let Inst{31-16} = 0b0001111000000000;
29010 let hasNewValue = 1;
29011 let opNewValue = 0;
29012 let DecoderNamespace = "EXT_mmvec";
29014 def V6_vabsh_sat_alt : HInst<
29015 (outs HvxVR:$Vd32),
29017 "$Vd32 = vabsh($Vu32):sat",
29018 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29019 let hasNewValue = 1;
29020 let opNewValue = 0;
29022 let isCodeGenOnly = 1;
29023 let DecoderNamespace = "EXT_mmvec";
29025 def V6_vabsub_alt : HInst<
29026 (outs HvxVR:$Vd32),
29028 "$Vd32.ub = vabs($Vu32.b)",
29029 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
29030 let hasNewValue = 1;
29031 let opNewValue = 0;
29033 let isCodeGenOnly = 1;
29034 let DecoderNamespace = "EXT_mmvec";
29036 def V6_vabsuh_alt : HInst<
29037 (outs HvxVR:$Vd32),
29039 "$Vd32.uh = vabs($Vu32.h)",
29040 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
29041 let hasNewValue = 1;
29042 let opNewValue = 0;
29044 let isCodeGenOnly = 1;
29045 let DecoderNamespace = "EXT_mmvec";
29047 def V6_vabsuw_alt : HInst<
29048 (outs HvxVR:$Vd32),
29050 "$Vd32.uw = vabs($Vu32.w)",
29051 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
29052 let hasNewValue = 1;
29053 let opNewValue = 0;
29055 let isCodeGenOnly = 1;
29056 let DecoderNamespace = "EXT_mmvec";
29058 def V6_vabsw : HInst<
29059 (outs HvxVR:$Vd32),
29061 "$Vd32.w = vabs($Vu32.w)",
29062 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29063 let Inst{7-5} = 0b010;
29064 let Inst{13-13} = 0b0;
29065 let Inst{31-16} = 0b0001111000000000;
29066 let hasNewValue = 1;
29067 let opNewValue = 0;
29068 let DecoderNamespace = "EXT_mmvec";
29070 def V6_vabsw_alt : HInst<
29071 (outs HvxVR:$Vd32),
29073 "$Vd32 = vabsw($Vu32)",
29074 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29075 let hasNewValue = 1;
29076 let opNewValue = 0;
29078 let isCodeGenOnly = 1;
29079 let DecoderNamespace = "EXT_mmvec";
29081 def V6_vabsw_sat : HInst<
29082 (outs HvxVR:$Vd32),
29084 "$Vd32.w = vabs($Vu32.w):sat",
29085 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29086 let Inst{7-5} = 0b011;
29087 let Inst{13-13} = 0b0;
29088 let Inst{31-16} = 0b0001111000000000;
29089 let hasNewValue = 1;
29090 let opNewValue = 0;
29091 let DecoderNamespace = "EXT_mmvec";
29093 def V6_vabsw_sat_alt : HInst<
29094 (outs HvxVR:$Vd32),
29096 "$Vd32 = vabsw($Vu32):sat",
29097 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29098 let hasNewValue = 1;
29099 let opNewValue = 0;
29101 let isCodeGenOnly = 1;
29102 let DecoderNamespace = "EXT_mmvec";
29104 def V6_vaddb : HInst<
29105 (outs HvxVR:$Vd32),
29106 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29107 "$Vd32.b = vadd($Vu32.b,$Vv32.b)",
29108 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29109 let Inst{7-5} = 0b110;
29110 let Inst{13-13} = 0b0;
29111 let Inst{31-21} = 0b00011111101;
29112 let hasNewValue = 1;
29113 let opNewValue = 0;
29114 let DecoderNamespace = "EXT_mmvec";
29116 def V6_vaddb_alt : HInst<
29117 (outs HvxVR:$Vd32),
29118 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29119 "$Vd32 = vaddb($Vu32,$Vv32)",
29120 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29121 let hasNewValue = 1;
29122 let opNewValue = 0;
29124 let isCodeGenOnly = 1;
29125 let DecoderNamespace = "EXT_mmvec";
29127 def V6_vaddb_dv : HInst<
29128 (outs HvxWR:$Vdd32),
29129 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29130 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
29131 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29132 let Inst{7-5} = 0b100;
29133 let Inst{13-13} = 0b0;
29134 let Inst{31-21} = 0b00011100011;
29135 let hasNewValue = 1;
29136 let opNewValue = 0;
29137 let DecoderNamespace = "EXT_mmvec";
29139 def V6_vaddb_dv_alt : HInst<
29140 (outs HvxWR:$Vdd32),
29141 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29142 "$Vdd32 = vaddb($Vuu32,$Vvv32)",
29143 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29144 let hasNewValue = 1;
29145 let opNewValue = 0;
29147 let isCodeGenOnly = 1;
29148 let DecoderNamespace = "EXT_mmvec";
29150 def V6_vaddbnq : HInst<
29151 (outs HvxVR:$Vx32),
29152 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29153 "if (!$Qv4) $Vx32.b += $Vu32.b",
29154 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29155 let Inst{7-5} = 0b011;
29156 let Inst{13-13} = 0b1;
29157 let Inst{21-16} = 0b000001;
29158 let Inst{31-24} = 0b00011110;
29159 let hasNewValue = 1;
29160 let opNewValue = 0;
29161 let isAccumulator = 1;
29162 let DecoderNamespace = "EXT_mmvec";
29163 let Constraints = "$Vx32 = $Vx32in";
29165 def V6_vaddbnq_alt : HInst<
29166 (outs HvxVR:$Vx32),
29167 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29168 "if (!$Qv4.b) $Vx32.b += $Vu32.b",
29169 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29170 let hasNewValue = 1;
29171 let opNewValue = 0;
29172 let isAccumulator = 1;
29174 let isCodeGenOnly = 1;
29175 let DecoderNamespace = "EXT_mmvec";
29176 let Constraints = "$Vx32 = $Vx32in";
29178 def V6_vaddbq : HInst<
29179 (outs HvxVR:$Vx32),
29180 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29181 "if ($Qv4) $Vx32.b += $Vu32.b",
29182 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29183 let Inst{7-5} = 0b000;
29184 let Inst{13-13} = 0b1;
29185 let Inst{21-16} = 0b000001;
29186 let Inst{31-24} = 0b00011110;
29187 let hasNewValue = 1;
29188 let opNewValue = 0;
29189 let isAccumulator = 1;
29190 let DecoderNamespace = "EXT_mmvec";
29191 let Constraints = "$Vx32 = $Vx32in";
29193 def V6_vaddbq_alt : HInst<
29194 (outs HvxVR:$Vx32),
29195 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29196 "if ($Qv4.b) $Vx32.b += $Vu32.b",
29197 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29198 let hasNewValue = 1;
29199 let opNewValue = 0;
29200 let isAccumulator = 1;
29202 let isCodeGenOnly = 1;
29203 let DecoderNamespace = "EXT_mmvec";
29204 let Constraints = "$Vx32 = $Vx32in";
29206 def V6_vaddbsat : HInst<
29207 (outs HvxVR:$Vd32),
29208 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29209 "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
29210 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29211 let Inst{7-5} = 0b000;
29212 let Inst{13-13} = 0b0;
29213 let Inst{31-21} = 0b00011111000;
29214 let hasNewValue = 1;
29215 let opNewValue = 0;
29216 let DecoderNamespace = "EXT_mmvec";
29218 def V6_vaddbsat_alt : HInst<
29219 (outs HvxVR:$Vd32),
29220 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29221 "$Vd32 = vaddb($Vu32,$Vv32):sat",
29222 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29223 let hasNewValue = 1;
29224 let opNewValue = 0;
29226 let isCodeGenOnly = 1;
29227 let DecoderNamespace = "EXT_mmvec";
29229 def V6_vaddbsat_dv : HInst<
29230 (outs HvxWR:$Vdd32),
29231 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29232 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
29233 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
29234 let Inst{7-5} = 0b000;
29235 let Inst{13-13} = 0b0;
29236 let Inst{31-21} = 0b00011110101;
29237 let hasNewValue = 1;
29238 let opNewValue = 0;
29239 let DecoderNamespace = "EXT_mmvec";
29241 def V6_vaddbsat_dv_alt : HInst<
29242 (outs HvxWR:$Vdd32),
29243 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29244 "$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
29245 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29246 let hasNewValue = 1;
29247 let opNewValue = 0;
29249 let isCodeGenOnly = 1;
29250 let DecoderNamespace = "EXT_mmvec";
29252 def V6_vaddcarry : HInst<
29253 (outs HvxVR:$Vd32, HvxQR:$Qx4),
29254 (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
29255 "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
29256 tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
29257 let Inst{7-7} = 0b0;
29258 let Inst{13-13} = 0b1;
29259 let Inst{31-21} = 0b00011100101;
29260 let hasNewValue = 1;
29261 let opNewValue = 0;
29262 let DecoderNamespace = "EXT_mmvec";
29263 let Constraints = "$Qx4 = $Qx4in";
29265 def V6_vaddclbh : HInst<
29266 (outs HvxVR:$Vd32),
29267 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29268 "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
29269 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
29270 let Inst{7-5} = 0b000;
29271 let Inst{13-13} = 0b1;
29272 let Inst{31-21} = 0b00011111000;
29273 let hasNewValue = 1;
29274 let opNewValue = 0;
29275 let DecoderNamespace = "EXT_mmvec";
29277 def V6_vaddclbw : HInst<
29278 (outs HvxVR:$Vd32),
29279 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29280 "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
29281 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
29282 let Inst{7-5} = 0b001;
29283 let Inst{13-13} = 0b1;
29284 let Inst{31-21} = 0b00011111000;
29285 let hasNewValue = 1;
29286 let opNewValue = 0;
29287 let DecoderNamespace = "EXT_mmvec";
29289 def V6_vaddh : HInst<
29290 (outs HvxVR:$Vd32),
29291 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29292 "$Vd32.h = vadd($Vu32.h,$Vv32.h)",
29293 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29294 let Inst{7-5} = 0b111;
29295 let Inst{13-13} = 0b0;
29296 let Inst{31-21} = 0b00011111101;
29297 let hasNewValue = 1;
29298 let opNewValue = 0;
29299 let DecoderNamespace = "EXT_mmvec";
29301 def V6_vaddh_alt : HInst<
29302 (outs HvxVR:$Vd32),
29303 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29304 "$Vd32 = vaddh($Vu32,$Vv32)",
29305 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29306 let hasNewValue = 1;
29307 let opNewValue = 0;
29309 let isCodeGenOnly = 1;
29310 let DecoderNamespace = "EXT_mmvec";
29312 def V6_vaddh_dv : HInst<
29313 (outs HvxWR:$Vdd32),
29314 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29315 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
29316 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29317 let Inst{7-5} = 0b101;
29318 let Inst{13-13} = 0b0;
29319 let Inst{31-21} = 0b00011100011;
29320 let hasNewValue = 1;
29321 let opNewValue = 0;
29322 let DecoderNamespace = "EXT_mmvec";
29324 def V6_vaddh_dv_alt : HInst<
29325 (outs HvxWR:$Vdd32),
29326 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29327 "$Vdd32 = vaddh($Vuu32,$Vvv32)",
29328 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29329 let hasNewValue = 1;
29330 let opNewValue = 0;
29332 let isCodeGenOnly = 1;
29333 let DecoderNamespace = "EXT_mmvec";
29335 def V6_vaddhnq : HInst<
29336 (outs HvxVR:$Vx32),
29337 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29338 "if (!$Qv4) $Vx32.h += $Vu32.h",
29339 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29340 let Inst{7-5} = 0b100;
29341 let Inst{13-13} = 0b1;
29342 let Inst{21-16} = 0b000001;
29343 let Inst{31-24} = 0b00011110;
29344 let hasNewValue = 1;
29345 let opNewValue = 0;
29346 let isAccumulator = 1;
29347 let DecoderNamespace = "EXT_mmvec";
29348 let Constraints = "$Vx32 = $Vx32in";
29350 def V6_vaddhnq_alt : HInst<
29351 (outs HvxVR:$Vx32),
29352 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29353 "if (!$Qv4.h) $Vx32.h += $Vu32.h",
29354 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29355 let hasNewValue = 1;
29356 let opNewValue = 0;
29357 let isAccumulator = 1;
29359 let isCodeGenOnly = 1;
29360 let DecoderNamespace = "EXT_mmvec";
29361 let Constraints = "$Vx32 = $Vx32in";
29363 def V6_vaddhq : HInst<
29364 (outs HvxVR:$Vx32),
29365 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29366 "if ($Qv4) $Vx32.h += $Vu32.h",
29367 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29368 let Inst{7-5} = 0b001;
29369 let Inst{13-13} = 0b1;
29370 let Inst{21-16} = 0b000001;
29371 let Inst{31-24} = 0b00011110;
29372 let hasNewValue = 1;
29373 let opNewValue = 0;
29374 let isAccumulator = 1;
29375 let DecoderNamespace = "EXT_mmvec";
29376 let Constraints = "$Vx32 = $Vx32in";
29378 def V6_vaddhq_alt : HInst<
29379 (outs HvxVR:$Vx32),
29380 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29381 "if ($Qv4.h) $Vx32.h += $Vu32.h",
29382 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29383 let hasNewValue = 1;
29384 let opNewValue = 0;
29385 let isAccumulator = 1;
29387 let isCodeGenOnly = 1;
29388 let DecoderNamespace = "EXT_mmvec";
29389 let Constraints = "$Vx32 = $Vx32in";
29391 def V6_vaddhsat : HInst<
29392 (outs HvxVR:$Vd32),
29393 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29394 "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
29395 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29396 let Inst{7-5} = 0b011;
29397 let Inst{13-13} = 0b0;
29398 let Inst{31-21} = 0b00011100010;
29399 let hasNewValue = 1;
29400 let opNewValue = 0;
29401 let DecoderNamespace = "EXT_mmvec";
29403 def V6_vaddhsat_alt : HInst<
29404 (outs HvxVR:$Vd32),
29405 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29406 "$Vd32 = vaddh($Vu32,$Vv32):sat",
29407 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29408 let hasNewValue = 1;
29409 let opNewValue = 0;
29411 let isCodeGenOnly = 1;
29412 let DecoderNamespace = "EXT_mmvec";
29414 def V6_vaddhsat_dv : HInst<
29415 (outs HvxWR:$Vdd32),
29416 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29417 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
29418 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29419 let Inst{7-5} = 0b001;
29420 let Inst{13-13} = 0b0;
29421 let Inst{31-21} = 0b00011100100;
29422 let hasNewValue = 1;
29423 let opNewValue = 0;
29424 let DecoderNamespace = "EXT_mmvec";
29426 def V6_vaddhsat_dv_alt : HInst<
29427 (outs HvxWR:$Vdd32),
29428 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29429 "$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
29430 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29431 let hasNewValue = 1;
29432 let opNewValue = 0;
29434 let isCodeGenOnly = 1;
29435 let DecoderNamespace = "EXT_mmvec";
29437 def V6_vaddhw : HInst<
29438 (outs HvxWR:$Vdd32),
29439 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29440 "$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
29441 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29442 let Inst{7-5} = 0b100;
29443 let Inst{13-13} = 0b0;
29444 let Inst{31-21} = 0b00011100101;
29445 let hasNewValue = 1;
29446 let opNewValue = 0;
29447 let DecoderNamespace = "EXT_mmvec";
29449 def V6_vaddhw_acc : HInst<
29450 (outs HvxWR:$Vxx32),
29451 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29452 "$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
29453 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29454 let Inst{7-5} = 0b010;
29455 let Inst{13-13} = 0b1;
29456 let Inst{31-21} = 0b00011100001;
29457 let hasNewValue = 1;
29458 let opNewValue = 0;
29459 let isAccumulator = 1;
29460 let DecoderNamespace = "EXT_mmvec";
29461 let Constraints = "$Vxx32 = $Vxx32in";
29463 def V6_vaddhw_acc_alt : HInst<
29464 (outs HvxWR:$Vxx32),
29465 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29466 "$Vxx32 += vaddh($Vu32,$Vv32)",
29467 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29468 let hasNewValue = 1;
29469 let opNewValue = 0;
29470 let isAccumulator = 1;
29472 let isCodeGenOnly = 1;
29473 let DecoderNamespace = "EXT_mmvec";
29474 let Constraints = "$Vxx32 = $Vxx32in";
29476 def V6_vaddhw_alt : HInst<
29477 (outs HvxWR:$Vdd32),
29478 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29479 "$Vdd32 = vaddh($Vu32,$Vv32)",
29480 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29481 let hasNewValue = 1;
29482 let opNewValue = 0;
29484 let isCodeGenOnly = 1;
29485 let DecoderNamespace = "EXT_mmvec";
29487 def V6_vaddubh : HInst<
29488 (outs HvxWR:$Vdd32),
29489 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29490 "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
29491 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29492 let Inst{7-5} = 0b010;
29493 let Inst{13-13} = 0b0;
29494 let Inst{31-21} = 0b00011100101;
29495 let hasNewValue = 1;
29496 let opNewValue = 0;
29497 let DecoderNamespace = "EXT_mmvec";
29499 def V6_vaddubh_acc : HInst<
29500 (outs HvxWR:$Vxx32),
29501 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29502 "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
29503 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29504 let Inst{7-5} = 0b101;
29505 let Inst{13-13} = 0b1;
29506 let Inst{31-21} = 0b00011100010;
29507 let hasNewValue = 1;
29508 let opNewValue = 0;
29509 let isAccumulator = 1;
29510 let DecoderNamespace = "EXT_mmvec";
29511 let Constraints = "$Vxx32 = $Vxx32in";
29513 def V6_vaddubh_acc_alt : HInst<
29514 (outs HvxWR:$Vxx32),
29515 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29516 "$Vxx32 += vaddub($Vu32,$Vv32)",
29517 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29518 let hasNewValue = 1;
29519 let opNewValue = 0;
29520 let isAccumulator = 1;
29522 let isCodeGenOnly = 1;
29523 let DecoderNamespace = "EXT_mmvec";
29524 let Constraints = "$Vxx32 = $Vxx32in";
29526 def V6_vaddubh_alt : HInst<
29527 (outs HvxWR:$Vdd32),
29528 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29529 "$Vdd32 = vaddub($Vu32,$Vv32)",
29530 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29531 let hasNewValue = 1;
29532 let opNewValue = 0;
29534 let isCodeGenOnly = 1;
29535 let DecoderNamespace = "EXT_mmvec";
29537 def V6_vaddubsat : HInst<
29538 (outs HvxVR:$Vd32),
29539 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29540 "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
29541 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29542 let Inst{7-5} = 0b001;
29543 let Inst{13-13} = 0b0;
29544 let Inst{31-21} = 0b00011100010;
29545 let hasNewValue = 1;
29546 let opNewValue = 0;
29547 let DecoderNamespace = "EXT_mmvec";
29549 def V6_vaddubsat_alt : HInst<
29550 (outs HvxVR:$Vd32),
29551 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29552 "$Vd32 = vaddub($Vu32,$Vv32):sat",
29553 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29554 let hasNewValue = 1;
29555 let opNewValue = 0;
29557 let isCodeGenOnly = 1;
29558 let DecoderNamespace = "EXT_mmvec";
29560 def V6_vaddubsat_dv : HInst<
29561 (outs HvxWR:$Vdd32),
29562 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29563 "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
29564 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29565 let Inst{7-5} = 0b111;
29566 let Inst{13-13} = 0b0;
29567 let Inst{31-21} = 0b00011100011;
29568 let hasNewValue = 1;
29569 let opNewValue = 0;
29570 let DecoderNamespace = "EXT_mmvec";
29572 def V6_vaddubsat_dv_alt : HInst<
29573 (outs HvxWR:$Vdd32),
29574 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29575 "$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
29576 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29577 let hasNewValue = 1;
29578 let opNewValue = 0;
29580 let isCodeGenOnly = 1;
29581 let DecoderNamespace = "EXT_mmvec";
29583 def V6_vaddububb_sat : HInst<
29584 (outs HvxVR:$Vd32),
29585 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29586 "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
29587 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29588 let Inst{7-5} = 0b100;
29589 let Inst{13-13} = 0b0;
29590 let Inst{31-21} = 0b00011110101;
29591 let hasNewValue = 1;
29592 let opNewValue = 0;
29593 let DecoderNamespace = "EXT_mmvec";
29595 def V6_vadduhsat : HInst<
29596 (outs HvxVR:$Vd32),
29597 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29598 "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
29599 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29600 let Inst{7-5} = 0b010;
29601 let Inst{13-13} = 0b0;
29602 let Inst{31-21} = 0b00011100010;
29603 let hasNewValue = 1;
29604 let opNewValue = 0;
29605 let DecoderNamespace = "EXT_mmvec";
29607 def V6_vadduhsat_alt : HInst<
29608 (outs HvxVR:$Vd32),
29609 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29610 "$Vd32 = vadduh($Vu32,$Vv32):sat",
29611 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29612 let hasNewValue = 1;
29613 let opNewValue = 0;
29615 let isCodeGenOnly = 1;
29616 let DecoderNamespace = "EXT_mmvec";
29618 def V6_vadduhsat_dv : HInst<
29619 (outs HvxWR:$Vdd32),
29620 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29621 "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
29622 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29623 let Inst{7-5} = 0b000;
29624 let Inst{13-13} = 0b0;
29625 let Inst{31-21} = 0b00011100100;
29626 let hasNewValue = 1;
29627 let opNewValue = 0;
29628 let DecoderNamespace = "EXT_mmvec";
29630 def V6_vadduhsat_dv_alt : HInst<
29631 (outs HvxWR:$Vdd32),
29632 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29633 "$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
29634 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29635 let hasNewValue = 1;
29636 let opNewValue = 0;
29638 let isCodeGenOnly = 1;
29639 let DecoderNamespace = "EXT_mmvec";
29641 def V6_vadduhw : HInst<
29642 (outs HvxWR:$Vdd32),
29643 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29644 "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
29645 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29646 let Inst{7-5} = 0b011;
29647 let Inst{13-13} = 0b0;
29648 let Inst{31-21} = 0b00011100101;
29649 let hasNewValue = 1;
29650 let opNewValue = 0;
29651 let DecoderNamespace = "EXT_mmvec";
29653 def V6_vadduhw_acc : HInst<
29654 (outs HvxWR:$Vxx32),
29655 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29656 "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
29657 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29658 let Inst{7-5} = 0b100;
29659 let Inst{13-13} = 0b1;
29660 let Inst{31-21} = 0b00011100010;
29661 let hasNewValue = 1;
29662 let opNewValue = 0;
29663 let isAccumulator = 1;
29664 let DecoderNamespace = "EXT_mmvec";
29665 let Constraints = "$Vxx32 = $Vxx32in";
29667 def V6_vadduhw_acc_alt : HInst<
29668 (outs HvxWR:$Vxx32),
29669 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29670 "$Vxx32 += vadduh($Vu32,$Vv32)",
29671 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29672 let hasNewValue = 1;
29673 let opNewValue = 0;
29674 let isAccumulator = 1;
29676 let isCodeGenOnly = 1;
29677 let DecoderNamespace = "EXT_mmvec";
29678 let Constraints = "$Vxx32 = $Vxx32in";
29680 def V6_vadduhw_alt : HInst<
29681 (outs HvxWR:$Vdd32),
29682 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29683 "$Vdd32 = vadduh($Vu32,$Vv32)",
29684 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29685 let hasNewValue = 1;
29686 let opNewValue = 0;
29688 let isCodeGenOnly = 1;
29689 let DecoderNamespace = "EXT_mmvec";
29691 def V6_vadduwsat : HInst<
29692 (outs HvxVR:$Vd32),
29693 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29694 "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
29695 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29696 let Inst{7-5} = 0b001;
29697 let Inst{13-13} = 0b0;
29698 let Inst{31-21} = 0b00011111011;
29699 let hasNewValue = 1;
29700 let opNewValue = 0;
29701 let DecoderNamespace = "EXT_mmvec";
29703 def V6_vadduwsat_alt : HInst<
29704 (outs HvxVR:$Vd32),
29705 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29706 "$Vd32 = vadduw($Vu32,$Vv32):sat",
29707 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29708 let hasNewValue = 1;
29709 let opNewValue = 0;
29711 let isCodeGenOnly = 1;
29712 let DecoderNamespace = "EXT_mmvec";
29714 def V6_vadduwsat_dv : HInst<
29715 (outs HvxWR:$Vdd32),
29716 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29717 "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
29718 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
29719 let Inst{7-5} = 0b010;
29720 let Inst{13-13} = 0b0;
29721 let Inst{31-21} = 0b00011110101;
29722 let hasNewValue = 1;
29723 let opNewValue = 0;
29724 let DecoderNamespace = "EXT_mmvec";
29726 def V6_vadduwsat_dv_alt : HInst<
29727 (outs HvxWR:$Vdd32),
29728 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29729 "$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
29730 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29731 let hasNewValue = 1;
29732 let opNewValue = 0;
29734 let isCodeGenOnly = 1;
29735 let DecoderNamespace = "EXT_mmvec";
29737 def V6_vaddw : HInst<
29738 (outs HvxVR:$Vd32),
29739 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29740 "$Vd32.w = vadd($Vu32.w,$Vv32.w)",
29741 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29742 let Inst{7-5} = 0b000;
29743 let Inst{13-13} = 0b0;
29744 let Inst{31-21} = 0b00011100010;
29745 let hasNewValue = 1;
29746 let opNewValue = 0;
29747 let DecoderNamespace = "EXT_mmvec";
29749 def V6_vaddw_alt : HInst<
29750 (outs HvxVR:$Vd32),
29751 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29752 "$Vd32 = vaddw($Vu32,$Vv32)",
29753 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29754 let hasNewValue = 1;
29755 let opNewValue = 0;
29757 let isCodeGenOnly = 1;
29758 let DecoderNamespace = "EXT_mmvec";
29760 def V6_vaddw_dv : HInst<
29761 (outs HvxWR:$Vdd32),
29762 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29763 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
29764 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29765 let Inst{7-5} = 0b110;
29766 let Inst{13-13} = 0b0;
29767 let Inst{31-21} = 0b00011100011;
29768 let hasNewValue = 1;
29769 let opNewValue = 0;
29770 let DecoderNamespace = "EXT_mmvec";
29772 def V6_vaddw_dv_alt : HInst<
29773 (outs HvxWR:$Vdd32),
29774 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29775 "$Vdd32 = vaddw($Vuu32,$Vvv32)",
29776 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29777 let hasNewValue = 1;
29778 let opNewValue = 0;
29780 let isCodeGenOnly = 1;
29781 let DecoderNamespace = "EXT_mmvec";
29783 def V6_vaddwnq : HInst<
29784 (outs HvxVR:$Vx32),
29785 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29786 "if (!$Qv4) $Vx32.w += $Vu32.w",
29787 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29788 let Inst{7-5} = 0b101;
29789 let Inst{13-13} = 0b1;
29790 let Inst{21-16} = 0b000001;
29791 let Inst{31-24} = 0b00011110;
29792 let hasNewValue = 1;
29793 let opNewValue = 0;
29794 let isAccumulator = 1;
29795 let DecoderNamespace = "EXT_mmvec";
29796 let Constraints = "$Vx32 = $Vx32in";
29798 def V6_vaddwnq_alt : HInst<
29799 (outs HvxVR:$Vx32),
29800 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29801 "if (!$Qv4.w) $Vx32.w += $Vu32.w",
29802 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29803 let hasNewValue = 1;
29804 let opNewValue = 0;
29805 let isAccumulator = 1;
29807 let isCodeGenOnly = 1;
29808 let DecoderNamespace = "EXT_mmvec";
29809 let Constraints = "$Vx32 = $Vx32in";
29811 def V6_vaddwq : HInst<
29812 (outs HvxVR:$Vx32),
29813 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29814 "if ($Qv4) $Vx32.w += $Vu32.w",
29815 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29816 let Inst{7-5} = 0b010;
29817 let Inst{13-13} = 0b1;
29818 let Inst{21-16} = 0b000001;
29819 let Inst{31-24} = 0b00011110;
29820 let hasNewValue = 1;
29821 let opNewValue = 0;
29822 let isAccumulator = 1;
29823 let DecoderNamespace = "EXT_mmvec";
29824 let Constraints = "$Vx32 = $Vx32in";
29826 def V6_vaddwq_alt : HInst<
29827 (outs HvxVR:$Vx32),
29828 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29829 "if ($Qv4.w) $Vx32.w += $Vu32.w",
29830 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29831 let hasNewValue = 1;
29832 let opNewValue = 0;
29833 let isAccumulator = 1;
29835 let isCodeGenOnly = 1;
29836 let DecoderNamespace = "EXT_mmvec";
29837 let Constraints = "$Vx32 = $Vx32in";
29839 def V6_vaddwsat : HInst<
29840 (outs HvxVR:$Vd32),
29841 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29842 "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
29843 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29844 let Inst{7-5} = 0b100;
29845 let Inst{13-13} = 0b0;
29846 let Inst{31-21} = 0b00011100010;
29847 let hasNewValue = 1;
29848 let opNewValue = 0;
29849 let DecoderNamespace = "EXT_mmvec";
29851 def V6_vaddwsat_alt : HInst<
29852 (outs HvxVR:$Vd32),
29853 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29854 "$Vd32 = vaddw($Vu32,$Vv32):sat",
29855 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29856 let hasNewValue = 1;
29857 let opNewValue = 0;
29859 let isCodeGenOnly = 1;
29860 let DecoderNamespace = "EXT_mmvec";
29862 def V6_vaddwsat_dv : HInst<
29863 (outs HvxWR:$Vdd32),
29864 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29865 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
29866 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29867 let Inst{7-5} = 0b010;
29868 let Inst{13-13} = 0b0;
29869 let Inst{31-21} = 0b00011100100;
29870 let hasNewValue = 1;
29871 let opNewValue = 0;
29872 let DecoderNamespace = "EXT_mmvec";
29874 def V6_vaddwsat_dv_alt : HInst<
29875 (outs HvxWR:$Vdd32),
29876 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29877 "$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
29878 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29879 let hasNewValue = 1;
29880 let opNewValue = 0;
29882 let isCodeGenOnly = 1;
29883 let DecoderNamespace = "EXT_mmvec";
29885 def V6_valignb : HInst<
29886 (outs HvxVR:$Vd32),
29887 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
29888 "$Vd32 = valign($Vu32,$Vv32,$Rt8)",
29889 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
29890 let Inst{7-5} = 0b000;
29891 let Inst{13-13} = 0b0;
29892 let Inst{31-24} = 0b00011011;
29893 let hasNewValue = 1;
29894 let opNewValue = 0;
29895 let DecoderNamespace = "EXT_mmvec";
29897 def V6_valignbi : HInst<
29898 (outs HvxVR:$Vd32),
29899 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
29900 "$Vd32 = valign($Vu32,$Vv32,#$Ii)",
29901 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
29902 let Inst{13-13} = 0b1;
29903 let Inst{31-21} = 0b00011110001;
29904 let hasNewValue = 1;
29905 let opNewValue = 0;
29906 let DecoderNamespace = "EXT_mmvec";
29908 def V6_vand : HInst<
29909 (outs HvxVR:$Vd32),
29910 (ins HvxVR:$Vu32, HvxVR:$Vv32),
29911 "$Vd32 = vand($Vu32,$Vv32)",
29912 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29913 let Inst{7-5} = 0b101;
29914 let Inst{13-13} = 0b0;
29915 let Inst{31-21} = 0b00011100001;
29916 let hasNewValue = 1;
29917 let opNewValue = 0;
29918 let DecoderNamespace = "EXT_mmvec";
29920 def V6_vandnqrt : HInst<
29921 (outs HvxVR:$Vd32),
29922 (ins HvxQR:$Qu4, IntRegs:$Rt32),
29923 "$Vd32 = vand(!$Qu4,$Rt32)",
29924 tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> {
29925 let Inst{7-5} = 0b101;
29926 let Inst{13-10} = 0b0001;
29927 let Inst{31-21} = 0b00011001101;
29928 let hasNewValue = 1;
29929 let opNewValue = 0;
29930 let DecoderNamespace = "EXT_mmvec";
29932 def V6_vandnqrt_acc : HInst<
29933 (outs HvxVR:$Vx32),
29934 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
29935 "$Vx32 |= vand(!$Qu4,$Rt32)",
29936 tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> {
29937 let Inst{7-5} = 0b011;
29938 let Inst{13-10} = 0b1001;
29939 let Inst{31-21} = 0b00011001011;
29940 let hasNewValue = 1;
29941 let opNewValue = 0;
29942 let isAccumulator = 1;
29943 let DecoderNamespace = "EXT_mmvec";
29944 let Constraints = "$Vx32 = $Vx32in";
29946 def V6_vandnqrt_acc_alt : HInst<
29947 (outs HvxVR:$Vx32),
29948 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
29949 "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
29950 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29951 let hasNewValue = 1;
29952 let opNewValue = 0;
29953 let isAccumulator = 1;
29955 let isCodeGenOnly = 1;
29956 let DecoderNamespace = "EXT_mmvec";
29957 let Constraints = "$Vx32 = $Vx32in";
29959 def V6_vandnqrt_alt : HInst<
29960 (outs HvxVR:$Vd32),
29961 (ins HvxQR:$Qu4, IntRegs:$Rt32),
29962 "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
29963 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29964 let hasNewValue = 1;
29965 let opNewValue = 0;
29967 let isCodeGenOnly = 1;
29968 let DecoderNamespace = "EXT_mmvec";
29970 def V6_vandqrt : HInst<
29971 (outs HvxVR:$Vd32),
29972 (ins HvxQR:$Qu4, IntRegs:$Rt32),
29973 "$Vd32 = vand($Qu4,$Rt32)",
29974 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
29975 let Inst{7-5} = 0b101;
29976 let Inst{13-10} = 0b0000;
29977 let Inst{31-21} = 0b00011001101;
29978 let hasNewValue = 1;
29979 let opNewValue = 0;
29980 let DecoderNamespace = "EXT_mmvec";
29982 def V6_vandqrt_acc : HInst<
29983 (outs HvxVR:$Vx32),
29984 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
29985 "$Vx32 |= vand($Qu4,$Rt32)",
29986 tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
29987 let Inst{7-5} = 0b011;
29988 let Inst{13-10} = 0b1000;
29989 let Inst{31-21} = 0b00011001011;
29990 let hasNewValue = 1;
29991 let opNewValue = 0;
29992 let isAccumulator = 1;
29993 let DecoderNamespace = "EXT_mmvec";
29994 let Constraints = "$Vx32 = $Vx32in";
29996 def V6_vandqrt_acc_alt : HInst<
29997 (outs HvxVR:$Vx32),
29998 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
29999 "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
30000 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30001 let hasNewValue = 1;
30002 let opNewValue = 0;
30003 let isAccumulator = 1;
30005 let isCodeGenOnly = 1;
30006 let DecoderNamespace = "EXT_mmvec";
30007 let Constraints = "$Vx32 = $Vx32in";
30009 def V6_vandqrt_alt : HInst<
30010 (outs HvxVR:$Vd32),
30011 (ins HvxQR:$Qu4, IntRegs:$Rt32),
30012 "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
30013 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30014 let hasNewValue = 1;
30015 let opNewValue = 0;
30017 let isCodeGenOnly = 1;
30018 let DecoderNamespace = "EXT_mmvec";
30020 def V6_vandvnqv : HInst<
30021 (outs HvxVR:$Vd32),
30022 (ins HvxQR:$Qv4, HvxVR:$Vu32),
30023 "$Vd32 = vand(!$Qv4,$Vu32)",
30024 tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30025 let Inst{7-5} = 0b001;
30026 let Inst{13-13} = 0b1;
30027 let Inst{21-16} = 0b000011;
30028 let Inst{31-24} = 0b00011110;
30029 let hasNewValue = 1;
30030 let opNewValue = 0;
30031 let DecoderNamespace = "EXT_mmvec";
30033 def V6_vandvqv : HInst<
30034 (outs HvxVR:$Vd32),
30035 (ins HvxQR:$Qv4, HvxVR:$Vu32),
30036 "$Vd32 = vand($Qv4,$Vu32)",
30037 tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30038 let Inst{7-5} = 0b000;
30039 let Inst{13-13} = 0b1;
30040 let Inst{21-16} = 0b000011;
30041 let Inst{31-24} = 0b00011110;
30042 let hasNewValue = 1;
30043 let opNewValue = 0;
30044 let DecoderNamespace = "EXT_mmvec";
30046 def V6_vandvrt : HInst<
30048 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30049 "$Qd4 = vand($Vu32,$Rt32)",
30050 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
30051 let Inst{7-2} = 0b010010;
30052 let Inst{13-13} = 0b0;
30053 let Inst{31-21} = 0b00011001101;
30054 let hasNewValue = 1;
30055 let opNewValue = 0;
30056 let DecoderNamespace = "EXT_mmvec";
30058 def V6_vandvrt_acc : HInst<
30060 (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30061 "$Qx4 |= vand($Vu32,$Rt32)",
30062 tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
30063 let Inst{7-2} = 0b100000;
30064 let Inst{13-13} = 0b1;
30065 let Inst{31-21} = 0b00011001011;
30066 let isAccumulator = 1;
30067 let DecoderNamespace = "EXT_mmvec";
30068 let Constraints = "$Qx4 = $Qx4in";
30070 def V6_vandvrt_acc_alt : HInst<
30072 (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30073 "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
30074 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30075 let isAccumulator = 1;
30077 let isCodeGenOnly = 1;
30078 let DecoderNamespace = "EXT_mmvec";
30079 let Constraints = "$Qx4 = $Qx4in";
30081 def V6_vandvrt_alt : HInst<
30083 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30084 "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
30085 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30086 let hasNewValue = 1;
30087 let opNewValue = 0;
30089 let isCodeGenOnly = 1;
30090 let DecoderNamespace = "EXT_mmvec";
30092 def V6_vaslh : HInst<
30093 (outs HvxVR:$Vd32),
30094 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30095 "$Vd32.h = vasl($Vu32.h,$Rt32)",
30096 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30097 let Inst{7-5} = 0b000;
30098 let Inst{13-13} = 0b0;
30099 let Inst{31-21} = 0b00011001100;
30100 let hasNewValue = 1;
30101 let opNewValue = 0;
30102 let DecoderNamespace = "EXT_mmvec";
30104 def V6_vaslh_acc : HInst<
30105 (outs HvxVR:$Vx32),
30106 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30107 "$Vx32.h += vasl($Vu32.h,$Rt32)",
30108 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
30109 let Inst{7-5} = 0b101;
30110 let Inst{13-13} = 0b1;
30111 let Inst{31-21} = 0b00011001101;
30112 let hasNewValue = 1;
30113 let opNewValue = 0;
30114 let isAccumulator = 1;
30115 let DecoderNamespace = "EXT_mmvec";
30116 let Constraints = "$Vx32 = $Vx32in";
30118 def V6_vaslh_acc_alt : HInst<
30119 (outs HvxVR:$Vx32),
30120 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30121 "$Vx32 += vaslh($Vu32,$Rt32)",
30122 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30123 let hasNewValue = 1;
30124 let opNewValue = 0;
30125 let isAccumulator = 1;
30127 let isCodeGenOnly = 1;
30128 let DecoderNamespace = "EXT_mmvec";
30129 let Constraints = "$Vx32 = $Vx32in";
30131 def V6_vaslh_alt : HInst<
30132 (outs HvxVR:$Vd32),
30133 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30134 "$Vd32 = vaslh($Vu32,$Rt32)",
30135 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30136 let hasNewValue = 1;
30137 let opNewValue = 0;
30139 let isCodeGenOnly = 1;
30140 let DecoderNamespace = "EXT_mmvec";
30142 def V6_vaslhv : HInst<
30143 (outs HvxVR:$Vd32),
30144 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30145 "$Vd32.h = vasl($Vu32.h,$Vv32.h)",
30146 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30147 let Inst{7-5} = 0b101;
30148 let Inst{13-13} = 0b0;
30149 let Inst{31-21} = 0b00011111101;
30150 let hasNewValue = 1;
30151 let opNewValue = 0;
30152 let DecoderNamespace = "EXT_mmvec";
30154 def V6_vaslhv_alt : HInst<
30155 (outs HvxVR:$Vd32),
30156 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30157 "$Vd32 = vaslh($Vu32,$Vv32)",
30158 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30159 let hasNewValue = 1;
30160 let opNewValue = 0;
30162 let isCodeGenOnly = 1;
30163 let DecoderNamespace = "EXT_mmvec";
30165 def V6_vaslw : HInst<
30166 (outs HvxVR:$Vd32),
30167 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30168 "$Vd32.w = vasl($Vu32.w,$Rt32)",
30169 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30170 let Inst{7-5} = 0b111;
30171 let Inst{13-13} = 0b0;
30172 let Inst{31-21} = 0b00011001011;
30173 let hasNewValue = 1;
30174 let opNewValue = 0;
30175 let DecoderNamespace = "EXT_mmvec";
30177 def V6_vaslw_acc : HInst<
30178 (outs HvxVR:$Vx32),
30179 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30180 "$Vx32.w += vasl($Vu32.w,$Rt32)",
30181 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
30182 let Inst{7-5} = 0b010;
30183 let Inst{13-13} = 0b1;
30184 let Inst{31-21} = 0b00011001011;
30185 let hasNewValue = 1;
30186 let opNewValue = 0;
30187 let isAccumulator = 1;
30188 let DecoderNamespace = "EXT_mmvec";
30189 let Constraints = "$Vx32 = $Vx32in";
30191 def V6_vaslw_acc_alt : HInst<
30192 (outs HvxVR:$Vx32),
30193 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30194 "$Vx32 += vaslw($Vu32,$Rt32)",
30195 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30196 let hasNewValue = 1;
30197 let opNewValue = 0;
30198 let isAccumulator = 1;
30200 let isCodeGenOnly = 1;
30201 let DecoderNamespace = "EXT_mmvec";
30202 let Constraints = "$Vx32 = $Vx32in";
30204 def V6_vaslw_alt : HInst<
30205 (outs HvxVR:$Vd32),
30206 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30207 "$Vd32 = vaslw($Vu32,$Rt32)",
30208 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30209 let hasNewValue = 1;
30210 let opNewValue = 0;
30212 let isCodeGenOnly = 1;
30213 let DecoderNamespace = "EXT_mmvec";
30215 def V6_vaslwv : HInst<
30216 (outs HvxVR:$Vd32),
30217 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30218 "$Vd32.w = vasl($Vu32.w,$Vv32.w)",
30219 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30220 let Inst{7-5} = 0b100;
30221 let Inst{13-13} = 0b0;
30222 let Inst{31-21} = 0b00011111101;
30223 let hasNewValue = 1;
30224 let opNewValue = 0;
30225 let DecoderNamespace = "EXT_mmvec";
30227 def V6_vaslwv_alt : HInst<
30228 (outs HvxVR:$Vd32),
30229 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30230 "$Vd32 = vaslw($Vu32,$Vv32)",
30231 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30232 let hasNewValue = 1;
30233 let opNewValue = 0;
30235 let isCodeGenOnly = 1;
30236 let DecoderNamespace = "EXT_mmvec";
30238 def V6_vasrh : HInst<
30239 (outs HvxVR:$Vd32),
30240 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30241 "$Vd32.h = vasr($Vu32.h,$Rt32)",
30242 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30243 let Inst{7-5} = 0b110;
30244 let Inst{13-13} = 0b0;
30245 let Inst{31-21} = 0b00011001011;
30246 let hasNewValue = 1;
30247 let opNewValue = 0;
30248 let DecoderNamespace = "EXT_mmvec";
30250 def V6_vasrh_acc : HInst<
30251 (outs HvxVR:$Vx32),
30252 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30253 "$Vx32.h += vasr($Vu32.h,$Rt32)",
30254 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
30255 let Inst{7-5} = 0b111;
30256 let Inst{13-13} = 0b1;
30257 let Inst{31-21} = 0b00011001100;
30258 let hasNewValue = 1;
30259 let opNewValue = 0;
30260 let isAccumulator = 1;
30261 let DecoderNamespace = "EXT_mmvec";
30262 let Constraints = "$Vx32 = $Vx32in";
30264 def V6_vasrh_acc_alt : HInst<
30265 (outs HvxVR:$Vx32),
30266 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30267 "$Vx32 += vasrh($Vu32,$Rt32)",
30268 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30269 let hasNewValue = 1;
30270 let opNewValue = 0;
30271 let isAccumulator = 1;
30273 let isCodeGenOnly = 1;
30274 let DecoderNamespace = "EXT_mmvec";
30275 let Constraints = "$Vx32 = $Vx32in";
30277 def V6_vasrh_alt : HInst<
30278 (outs HvxVR:$Vd32),
30279 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30280 "$Vd32 = vasrh($Vu32,$Rt32)",
30281 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30282 let hasNewValue = 1;
30283 let opNewValue = 0;
30285 let isCodeGenOnly = 1;
30286 let DecoderNamespace = "EXT_mmvec";
30288 def V6_vasrhbrndsat : HInst<
30289 (outs HvxVR:$Vd32),
30290 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30291 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
30292 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30293 let Inst{7-5} = 0b000;
30294 let Inst{13-13} = 0b1;
30295 let Inst{31-24} = 0b00011011;
30296 let hasNewValue = 1;
30297 let opNewValue = 0;
30298 let DecoderNamespace = "EXT_mmvec";
30300 def V6_vasrhbrndsat_alt : HInst<
30301 (outs HvxVR:$Vd32),
30302 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30303 "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat",
30304 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30305 let hasNewValue = 1;
30306 let opNewValue = 0;
30308 let isCodeGenOnly = 1;
30310 def V6_vasrhbsat : HInst<
30311 (outs HvxVR:$Vd32),
30312 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30313 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
30314 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30315 let Inst{7-5} = 0b000;
30316 let Inst{13-13} = 0b0;
30317 let Inst{31-24} = 0b00011000;
30318 let hasNewValue = 1;
30319 let opNewValue = 0;
30320 let DecoderNamespace = "EXT_mmvec";
30322 def V6_vasrhubrndsat : HInst<
30323 (outs HvxVR:$Vd32),
30324 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30325 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
30326 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30327 let Inst{7-5} = 0b111;
30328 let Inst{13-13} = 0b0;
30329 let Inst{31-24} = 0b00011011;
30330 let hasNewValue = 1;
30331 let opNewValue = 0;
30332 let DecoderNamespace = "EXT_mmvec";
30334 def V6_vasrhubrndsat_alt : HInst<
30335 (outs HvxVR:$Vd32),
30336 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30337 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat",
30338 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30339 let hasNewValue = 1;
30340 let opNewValue = 0;
30342 let isCodeGenOnly = 1;
30344 def V6_vasrhubsat : HInst<
30345 (outs HvxVR:$Vd32),
30346 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30347 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
30348 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30349 let Inst{7-5} = 0b110;
30350 let Inst{13-13} = 0b0;
30351 let Inst{31-24} = 0b00011011;
30352 let hasNewValue = 1;
30353 let opNewValue = 0;
30354 let DecoderNamespace = "EXT_mmvec";
30356 def V6_vasrhubsat_alt : HInst<
30357 (outs HvxVR:$Vd32),
30358 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30359 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat",
30360 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30361 let hasNewValue = 1;
30362 let opNewValue = 0;
30364 let isCodeGenOnly = 1;
30366 def V6_vasrhv : HInst<
30367 (outs HvxVR:$Vd32),
30368 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30369 "$Vd32.h = vasr($Vu32.h,$Vv32.h)",
30370 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30371 let Inst{7-5} = 0b011;
30372 let Inst{13-13} = 0b0;
30373 let Inst{31-21} = 0b00011111101;
30374 let hasNewValue = 1;
30375 let opNewValue = 0;
30376 let DecoderNamespace = "EXT_mmvec";
30378 def V6_vasrhv_alt : HInst<
30379 (outs HvxVR:$Vd32),
30380 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30381 "$Vd32 = vasrh($Vu32,$Vv32)",
30382 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30383 let hasNewValue = 1;
30384 let opNewValue = 0;
30386 let isCodeGenOnly = 1;
30387 let DecoderNamespace = "EXT_mmvec";
30389 def V6_vasruhubrndsat : HInst<
30390 (outs HvxVR:$Vd32),
30391 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30392 "$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
30393 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30394 let Inst{7-5} = 0b111;
30395 let Inst{13-13} = 0b0;
30396 let Inst{31-24} = 0b00011000;
30397 let hasNewValue = 1;
30398 let opNewValue = 0;
30399 let DecoderNamespace = "EXT_mmvec";
30401 def V6_vasruhubsat : HInst<
30402 (outs HvxVR:$Vd32),
30403 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30404 "$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
30405 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30406 let Inst{7-5} = 0b101;
30407 let Inst{13-13} = 0b1;
30408 let Inst{31-24} = 0b00011000;
30409 let hasNewValue = 1;
30410 let opNewValue = 0;
30411 let DecoderNamespace = "EXT_mmvec";
30413 def V6_vasruwuhrndsat : HInst<
30414 (outs HvxVR:$Vd32),
30415 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30416 "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
30417 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30418 let Inst{7-5} = 0b001;
30419 let Inst{13-13} = 0b0;
30420 let Inst{31-24} = 0b00011000;
30421 let hasNewValue = 1;
30422 let opNewValue = 0;
30423 let DecoderNamespace = "EXT_mmvec";
30425 def V6_vasruwuhsat : HInst<
30426 (outs HvxVR:$Vd32),
30427 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30428 "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
30429 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30430 let Inst{7-5} = 0b100;
30431 let Inst{13-13} = 0b1;
30432 let Inst{31-24} = 0b00011000;
30433 let hasNewValue = 1;
30434 let opNewValue = 0;
30435 let DecoderNamespace = "EXT_mmvec";
30437 def V6_vasrw : HInst<
30438 (outs HvxVR:$Vd32),
30439 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30440 "$Vd32.w = vasr($Vu32.w,$Rt32)",
30441 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30442 let Inst{7-5} = 0b101;
30443 let Inst{13-13} = 0b0;
30444 let Inst{31-21} = 0b00011001011;
30445 let hasNewValue = 1;
30446 let opNewValue = 0;
30447 let DecoderNamespace = "EXT_mmvec";
30449 def V6_vasrw_acc : HInst<
30450 (outs HvxVR:$Vx32),
30451 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30452 "$Vx32.w += vasr($Vu32.w,$Rt32)",
30453 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
30454 let Inst{7-5} = 0b101;
30455 let Inst{13-13} = 0b1;
30456 let Inst{31-21} = 0b00011001011;
30457 let hasNewValue = 1;
30458 let opNewValue = 0;
30459 let isAccumulator = 1;
30460 let DecoderNamespace = "EXT_mmvec";
30461 let Constraints = "$Vx32 = $Vx32in";
30463 def V6_vasrw_acc_alt : HInst<
30464 (outs HvxVR:$Vx32),
30465 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30466 "$Vx32 += vasrw($Vu32,$Rt32)",
30467 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30468 let hasNewValue = 1;
30469 let opNewValue = 0;
30470 let isAccumulator = 1;
30472 let isCodeGenOnly = 1;
30473 let DecoderNamespace = "EXT_mmvec";
30474 let Constraints = "$Vx32 = $Vx32in";
30476 def V6_vasrw_alt : HInst<
30477 (outs HvxVR:$Vd32),
30478 (ins HvxVR:$Vu32, IntRegs:$Rt32),
30479 "$Vd32 = vasrw($Vu32,$Rt32)",
30480 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30481 let hasNewValue = 1;
30482 let opNewValue = 0;
30484 let isCodeGenOnly = 1;
30485 let DecoderNamespace = "EXT_mmvec";
30487 def V6_vasrwh : HInst<
30488 (outs HvxVR:$Vd32),
30489 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30490 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
30491 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30492 let Inst{7-5} = 0b010;
30493 let Inst{13-13} = 0b0;
30494 let Inst{31-24} = 0b00011011;
30495 let hasNewValue = 1;
30496 let opNewValue = 0;
30497 let DecoderNamespace = "EXT_mmvec";
30499 def V6_vasrwh_alt : HInst<
30500 (outs HvxVR:$Vd32),
30501 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30502 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)",
30503 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30504 let hasNewValue = 1;
30505 let opNewValue = 0;
30507 let isCodeGenOnly = 1;
30509 def V6_vasrwhrndsat : HInst<
30510 (outs HvxVR:$Vd32),
30511 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30512 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
30513 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30514 let Inst{7-5} = 0b100;
30515 let Inst{13-13} = 0b0;
30516 let Inst{31-24} = 0b00011011;
30517 let hasNewValue = 1;
30518 let opNewValue = 0;
30519 let DecoderNamespace = "EXT_mmvec";
30521 def V6_vasrwhrndsat_alt : HInst<
30522 (outs HvxVR:$Vd32),
30523 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30524 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat",
30525 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30526 let hasNewValue = 1;
30527 let opNewValue = 0;
30529 let isCodeGenOnly = 1;
30531 def V6_vasrwhsat : HInst<
30532 (outs HvxVR:$Vd32),
30533 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30534 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
30535 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30536 let Inst{7-5} = 0b011;
30537 let Inst{13-13} = 0b0;
30538 let Inst{31-24} = 0b00011011;
30539 let hasNewValue = 1;
30540 let opNewValue = 0;
30541 let DecoderNamespace = "EXT_mmvec";
30543 def V6_vasrwhsat_alt : HInst<
30544 (outs HvxVR:$Vd32),
30545 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30546 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat",
30547 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30548 let hasNewValue = 1;
30549 let opNewValue = 0;
30551 let isCodeGenOnly = 1;
30553 def V6_vasrwuhrndsat : HInst<
30554 (outs HvxVR:$Vd32),
30555 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30556 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
30557 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30558 let Inst{7-5} = 0b010;
30559 let Inst{13-13} = 0b0;
30560 let Inst{31-24} = 0b00011000;
30561 let hasNewValue = 1;
30562 let opNewValue = 0;
30563 let DecoderNamespace = "EXT_mmvec";
30565 def V6_vasrwuhsat : HInst<
30566 (outs HvxVR:$Vd32),
30567 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30568 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
30569 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30570 let Inst{7-5} = 0b101;
30571 let Inst{13-13} = 0b0;
30572 let Inst{31-24} = 0b00011011;
30573 let hasNewValue = 1;
30574 let opNewValue = 0;
30575 let DecoderNamespace = "EXT_mmvec";
30577 def V6_vasrwuhsat_alt : HInst<
30578 (outs HvxVR:$Vd32),
30579 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30580 "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat",
30581 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
30582 let hasNewValue = 1;
30583 let opNewValue = 0;
30585 let isCodeGenOnly = 1;
30587 def V6_vasrwv : HInst<
30588 (outs HvxVR:$Vd32),
30589 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30590 "$Vd32.w = vasr($Vu32.w,$Vv32.w)",
30591 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30592 let Inst{7-5} = 0b000;
30593 let Inst{13-13} = 0b0;
30594 let Inst{31-21} = 0b00011111101;
30595 let hasNewValue = 1;
30596 let opNewValue = 0;
30597 let DecoderNamespace = "EXT_mmvec";
30599 def V6_vasrwv_alt : HInst<
30600 (outs HvxVR:$Vd32),
30601 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30602 "$Vd32 = vasrw($Vu32,$Vv32)",
30603 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30604 let hasNewValue = 1;
30605 let opNewValue = 0;
30607 let isCodeGenOnly = 1;
30608 let DecoderNamespace = "EXT_mmvec";
30610 def V6_vassign : HInst<
30611 (outs HvxVR:$Vd32),
30614 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30615 let Inst{7-5} = 0b111;
30616 let Inst{13-13} = 0b1;
30617 let Inst{31-16} = 0b0001111000000011;
30618 let hasNewValue = 1;
30619 let opNewValue = 0;
30620 let DecoderNamespace = "EXT_mmvec";
30622 def V6_vassignp : HInst<
30623 (outs HvxWR:$Vdd32),
30624 (ins HvxWR:$Vuu32),
30626 CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
30627 let hasNewValue = 1;
30628 let opNewValue = 0;
30630 let DecoderNamespace = "EXT_mmvec";
30632 def V6_vavgb : HInst<
30633 (outs HvxVR:$Vd32),
30634 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30635 "$Vd32.b = vavg($Vu32.b,$Vv32.b)",
30636 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30637 let Inst{7-5} = 0b100;
30638 let Inst{13-13} = 0b1;
30639 let Inst{31-21} = 0b00011111000;
30640 let hasNewValue = 1;
30641 let opNewValue = 0;
30642 let DecoderNamespace = "EXT_mmvec";
30644 def V6_vavgb_alt : HInst<
30645 (outs HvxVR:$Vd32),
30646 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30647 "$Vd32 = vavgb($Vu32,$Vv32)",
30648 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30649 let hasNewValue = 1;
30650 let opNewValue = 0;
30652 let isCodeGenOnly = 1;
30653 let DecoderNamespace = "EXT_mmvec";
30655 def V6_vavgbrnd : HInst<
30656 (outs HvxVR:$Vd32),
30657 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30658 "$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
30659 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30660 let Inst{7-5} = 0b101;
30661 let Inst{13-13} = 0b1;
30662 let Inst{31-21} = 0b00011111000;
30663 let hasNewValue = 1;
30664 let opNewValue = 0;
30665 let DecoderNamespace = "EXT_mmvec";
30667 def V6_vavgbrnd_alt : HInst<
30668 (outs HvxVR:$Vd32),
30669 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30670 "$Vd32 = vavgb($Vu32,$Vv32):rnd",
30671 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30672 let hasNewValue = 1;
30673 let opNewValue = 0;
30675 let isCodeGenOnly = 1;
30676 let DecoderNamespace = "EXT_mmvec";
30678 def V6_vavgh : HInst<
30679 (outs HvxVR:$Vd32),
30680 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30681 "$Vd32.h = vavg($Vu32.h,$Vv32.h)",
30682 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30683 let Inst{7-5} = 0b110;
30684 let Inst{13-13} = 0b0;
30685 let Inst{31-21} = 0b00011100110;
30686 let hasNewValue = 1;
30687 let opNewValue = 0;
30688 let DecoderNamespace = "EXT_mmvec";
30690 def V6_vavgh_alt : HInst<
30691 (outs HvxVR:$Vd32),
30692 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30693 "$Vd32 = vavgh($Vu32,$Vv32)",
30694 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30695 let hasNewValue = 1;
30696 let opNewValue = 0;
30698 let isCodeGenOnly = 1;
30699 let DecoderNamespace = "EXT_mmvec";
30701 def V6_vavghrnd : HInst<
30702 (outs HvxVR:$Vd32),
30703 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30704 "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
30705 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30706 let Inst{7-5} = 0b101;
30707 let Inst{13-13} = 0b0;
30708 let Inst{31-21} = 0b00011100111;
30709 let hasNewValue = 1;
30710 let opNewValue = 0;
30711 let DecoderNamespace = "EXT_mmvec";
30713 def V6_vavghrnd_alt : HInst<
30714 (outs HvxVR:$Vd32),
30715 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30716 "$Vd32 = vavgh($Vu32,$Vv32):rnd",
30717 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30718 let hasNewValue = 1;
30719 let opNewValue = 0;
30721 let isCodeGenOnly = 1;
30722 let DecoderNamespace = "EXT_mmvec";
30724 def V6_vavgub : HInst<
30725 (outs HvxVR:$Vd32),
30726 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30727 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
30728 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30729 let Inst{7-5} = 0b100;
30730 let Inst{13-13} = 0b0;
30731 let Inst{31-21} = 0b00011100110;
30732 let hasNewValue = 1;
30733 let opNewValue = 0;
30734 let DecoderNamespace = "EXT_mmvec";
30736 def V6_vavgub_alt : HInst<
30737 (outs HvxVR:$Vd32),
30738 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30739 "$Vd32 = vavgub($Vu32,$Vv32)",
30740 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30741 let hasNewValue = 1;
30742 let opNewValue = 0;
30744 let isCodeGenOnly = 1;
30745 let DecoderNamespace = "EXT_mmvec";
30747 def V6_vavgubrnd : HInst<
30748 (outs HvxVR:$Vd32),
30749 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30750 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
30751 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30752 let Inst{7-5} = 0b011;
30753 let Inst{13-13} = 0b0;
30754 let Inst{31-21} = 0b00011100111;
30755 let hasNewValue = 1;
30756 let opNewValue = 0;
30757 let DecoderNamespace = "EXT_mmvec";
30759 def V6_vavgubrnd_alt : HInst<
30760 (outs HvxVR:$Vd32),
30761 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30762 "$Vd32 = vavgub($Vu32,$Vv32):rnd",
30763 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30764 let hasNewValue = 1;
30765 let opNewValue = 0;
30767 let isCodeGenOnly = 1;
30768 let DecoderNamespace = "EXT_mmvec";
30770 def V6_vavguh : HInst<
30771 (outs HvxVR:$Vd32),
30772 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30773 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
30774 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30775 let Inst{7-5} = 0b101;
30776 let Inst{13-13} = 0b0;
30777 let Inst{31-21} = 0b00011100110;
30778 let hasNewValue = 1;
30779 let opNewValue = 0;
30780 let DecoderNamespace = "EXT_mmvec";
30782 def V6_vavguh_alt : HInst<
30783 (outs HvxVR:$Vd32),
30784 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30785 "$Vd32 = vavguh($Vu32,$Vv32)",
30786 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30787 let hasNewValue = 1;
30788 let opNewValue = 0;
30790 let isCodeGenOnly = 1;
30791 let DecoderNamespace = "EXT_mmvec";
30793 def V6_vavguhrnd : HInst<
30794 (outs HvxVR:$Vd32),
30795 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30796 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
30797 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30798 let Inst{7-5} = 0b100;
30799 let Inst{13-13} = 0b0;
30800 let Inst{31-21} = 0b00011100111;
30801 let hasNewValue = 1;
30802 let opNewValue = 0;
30803 let DecoderNamespace = "EXT_mmvec";
30805 def V6_vavguhrnd_alt : HInst<
30806 (outs HvxVR:$Vd32),
30807 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30808 "$Vd32 = vavguh($Vu32,$Vv32):rnd",
30809 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30810 let hasNewValue = 1;
30811 let opNewValue = 0;
30813 let isCodeGenOnly = 1;
30814 let DecoderNamespace = "EXT_mmvec";
30816 def V6_vavguw : HInst<
30817 (outs HvxVR:$Vd32),
30818 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30819 "$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
30820 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30821 let Inst{7-5} = 0b010;
30822 let Inst{13-13} = 0b1;
30823 let Inst{31-21} = 0b00011111000;
30824 let hasNewValue = 1;
30825 let opNewValue = 0;
30826 let DecoderNamespace = "EXT_mmvec";
30828 def V6_vavguw_alt : HInst<
30829 (outs HvxVR:$Vd32),
30830 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30831 "$Vd32 = vavguw($Vu32,$Vv32)",
30832 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30833 let hasNewValue = 1;
30834 let opNewValue = 0;
30836 let isCodeGenOnly = 1;
30837 let DecoderNamespace = "EXT_mmvec";
30839 def V6_vavguwrnd : HInst<
30840 (outs HvxVR:$Vd32),
30841 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30842 "$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
30843 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30844 let Inst{7-5} = 0b011;
30845 let Inst{13-13} = 0b1;
30846 let Inst{31-21} = 0b00011111000;
30847 let hasNewValue = 1;
30848 let opNewValue = 0;
30849 let DecoderNamespace = "EXT_mmvec";
30851 def V6_vavguwrnd_alt : HInst<
30852 (outs HvxVR:$Vd32),
30853 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30854 "$Vd32 = vavguw($Vu32,$Vv32):rnd",
30855 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30856 let hasNewValue = 1;
30857 let opNewValue = 0;
30859 let isCodeGenOnly = 1;
30860 let DecoderNamespace = "EXT_mmvec";
30862 def V6_vavgw : HInst<
30863 (outs HvxVR:$Vd32),
30864 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30865 "$Vd32.w = vavg($Vu32.w,$Vv32.w)",
30866 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30867 let Inst{7-5} = 0b111;
30868 let Inst{13-13} = 0b0;
30869 let Inst{31-21} = 0b00011100110;
30870 let hasNewValue = 1;
30871 let opNewValue = 0;
30872 let DecoderNamespace = "EXT_mmvec";
30874 def V6_vavgw_alt : HInst<
30875 (outs HvxVR:$Vd32),
30876 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30877 "$Vd32 = vavgw($Vu32,$Vv32)",
30878 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30879 let hasNewValue = 1;
30880 let opNewValue = 0;
30882 let isCodeGenOnly = 1;
30883 let DecoderNamespace = "EXT_mmvec";
30885 def V6_vavgwrnd : HInst<
30886 (outs HvxVR:$Vd32),
30887 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30888 "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
30889 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30890 let Inst{7-5} = 0b110;
30891 let Inst{13-13} = 0b0;
30892 let Inst{31-21} = 0b00011100111;
30893 let hasNewValue = 1;
30894 let opNewValue = 0;
30895 let DecoderNamespace = "EXT_mmvec";
30897 def V6_vavgwrnd_alt : HInst<
30898 (outs HvxVR:$Vd32),
30899 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30900 "$Vd32 = vavgw($Vu32,$Vv32):rnd",
30901 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30902 let hasNewValue = 1;
30903 let opNewValue = 0;
30905 let isCodeGenOnly = 1;
30906 let DecoderNamespace = "EXT_mmvec";
30908 def V6_vccombine : HInst<
30909 (outs HvxWR:$Vdd32),
30910 (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
30911 "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
30912 tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
30913 let Inst{7-7} = 0b0;
30914 let Inst{13-13} = 0b0;
30915 let Inst{31-21} = 0b00011010011;
30916 let isPredicated = 1;
30917 let hasNewValue = 1;
30918 let opNewValue = 0;
30919 let DecoderNamespace = "EXT_mmvec";
30921 def V6_vcl0h : HInst<
30922 (outs HvxVR:$Vd32),
30924 "$Vd32.uh = vcl0($Vu32.uh)",
30925 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
30926 let Inst{7-5} = 0b111;
30927 let Inst{13-13} = 0b0;
30928 let Inst{31-16} = 0b0001111000000010;
30929 let hasNewValue = 1;
30930 let opNewValue = 0;
30931 let DecoderNamespace = "EXT_mmvec";
30933 def V6_vcl0h_alt : HInst<
30934 (outs HvxVR:$Vd32),
30936 "$Vd32 = vcl0h($Vu32)",
30937 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30938 let hasNewValue = 1;
30939 let opNewValue = 0;
30941 let isCodeGenOnly = 1;
30942 let DecoderNamespace = "EXT_mmvec";
30944 def V6_vcl0w : HInst<
30945 (outs HvxVR:$Vd32),
30947 "$Vd32.uw = vcl0($Vu32.uw)",
30948 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
30949 let Inst{7-5} = 0b101;
30950 let Inst{13-13} = 0b0;
30951 let Inst{31-16} = 0b0001111000000010;
30952 let hasNewValue = 1;
30953 let opNewValue = 0;
30954 let DecoderNamespace = "EXT_mmvec";
30956 def V6_vcl0w_alt : HInst<
30957 (outs HvxVR:$Vd32),
30959 "$Vd32 = vcl0w($Vu32)",
30960 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30961 let hasNewValue = 1;
30962 let opNewValue = 0;
30964 let isCodeGenOnly = 1;
30965 let DecoderNamespace = "EXT_mmvec";
30967 def V6_vcmov : HInst<
30968 (outs HvxVR:$Vd32),
30969 (ins PredRegs:$Ps4, HvxVR:$Vu32),
30970 "if ($Ps4) $Vd32 = $Vu32",
30971 tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
30972 let Inst{7-7} = 0b0;
30973 let Inst{13-13} = 0b0;
30974 let Inst{31-16} = 0b0001101000000000;
30975 let isPredicated = 1;
30976 let hasNewValue = 1;
30977 let opNewValue = 0;
30978 let DecoderNamespace = "EXT_mmvec";
30980 def V6_vcombine : HInst<
30981 (outs HvxWR:$Vdd32),
30982 (ins HvxVR:$Vu32, HvxVR:$Vv32),
30983 "$Vdd32 = vcombine($Vu32,$Vv32)",
30984 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30985 let Inst{7-5} = 0b111;
30986 let Inst{13-13} = 0b0;
30987 let Inst{31-21} = 0b00011111010;
30988 let hasNewValue = 1;
30989 let opNewValue = 0;
30990 let isRegSequence = 1;
30991 let DecoderNamespace = "EXT_mmvec";
30993 def V6_vd0 : HInst<
30994 (outs HvxVR:$Vd32),
30997 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
30998 let hasNewValue = 1;
30999 let opNewValue = 0;
31001 let isCodeGenOnly = 1;
31002 let DecoderNamespace = "EXT_mmvec";
31004 def V6_vdd0 : HInst<
31005 (outs HvxWR:$Vdd32),
31008 tc_8a6eb39a, TypeMAPPING>, Requires<[UseHVXV65]> {
31009 let hasNewValue = 1;
31010 let opNewValue = 0;
31012 let isCodeGenOnly = 1;
31013 let DecoderNamespace = "EXT_mmvec";
31015 def V6_vdeal : HInst<
31016 (outs HvxVR:$Vy32, HvxVR:$Vx32),
31017 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
31018 "vdeal($Vy32,$Vx32,$Rt32)",
31019 tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
31020 let Inst{7-5} = 0b010;
31021 let Inst{13-13} = 0b1;
31022 let Inst{31-21} = 0b00011001111;
31023 let hasNewValue = 1;
31024 let opNewValue = 0;
31025 let hasNewValue2 = 1;
31026 let opNewValue2 = 1;
31027 let DecoderNamespace = "EXT_mmvec";
31028 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
31030 def V6_vdealb : HInst<
31031 (outs HvxVR:$Vd32),
31033 "$Vd32.b = vdeal($Vu32.b)",
31034 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31035 let Inst{7-5} = 0b111;
31036 let Inst{13-13} = 0b0;
31037 let Inst{31-16} = 0b0001111000000000;
31038 let hasNewValue = 1;
31039 let opNewValue = 0;
31040 let DecoderNamespace = "EXT_mmvec";
31042 def V6_vdealb4w : HInst<
31043 (outs HvxVR:$Vd32),
31044 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31045 "$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
31046 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31047 let Inst{7-5} = 0b111;
31048 let Inst{13-13} = 0b0;
31049 let Inst{31-21} = 0b00011111001;
31050 let hasNewValue = 1;
31051 let opNewValue = 0;
31052 let DecoderNamespace = "EXT_mmvec";
31054 def V6_vdealb4w_alt : HInst<
31055 (outs HvxVR:$Vd32),
31056 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31057 "$Vd32 = vdealb4w($Vu32,$Vv32)",
31058 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31059 let hasNewValue = 1;
31060 let opNewValue = 0;
31062 let isCodeGenOnly = 1;
31063 let DecoderNamespace = "EXT_mmvec";
31065 def V6_vdealb_alt : HInst<
31066 (outs HvxVR:$Vd32),
31068 "$Vd32 = vdealb($Vu32)",
31069 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31070 let hasNewValue = 1;
31071 let opNewValue = 0;
31073 let isCodeGenOnly = 1;
31074 let DecoderNamespace = "EXT_mmvec";
31076 def V6_vdealh : HInst<
31077 (outs HvxVR:$Vd32),
31079 "$Vd32.h = vdeal($Vu32.h)",
31080 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31081 let Inst{7-5} = 0b110;
31082 let Inst{13-13} = 0b0;
31083 let Inst{31-16} = 0b0001111000000000;
31084 let hasNewValue = 1;
31085 let opNewValue = 0;
31086 let DecoderNamespace = "EXT_mmvec";
31088 def V6_vdealh_alt : HInst<
31089 (outs HvxVR:$Vd32),
31091 "$Vd32 = vdealh($Vu32)",
31092 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31093 let hasNewValue = 1;
31094 let opNewValue = 0;
31096 let isCodeGenOnly = 1;
31097 let DecoderNamespace = "EXT_mmvec";
31099 def V6_vdealvdd : HInst<
31100 (outs HvxWR:$Vdd32),
31101 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31102 "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
31103 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
31104 let Inst{7-5} = 0b100;
31105 let Inst{13-13} = 0b1;
31106 let Inst{31-24} = 0b00011011;
31107 let hasNewValue = 1;
31108 let opNewValue = 0;
31109 let DecoderNamespace = "EXT_mmvec";
31111 def V6_vdelta : HInst<
31112 (outs HvxVR:$Vd32),
31113 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31114 "$Vd32 = vdelta($Vu32,$Vv32)",
31115 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31116 let Inst{7-5} = 0b001;
31117 let Inst{13-13} = 0b0;
31118 let Inst{31-21} = 0b00011111001;
31119 let hasNewValue = 1;
31120 let opNewValue = 0;
31121 let DecoderNamespace = "EXT_mmvec";
31123 def V6_vdmpybus : HInst<
31124 (outs HvxVR:$Vd32),
31125 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31126 "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
31127 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
31128 let Inst{7-5} = 0b110;
31129 let Inst{13-13} = 0b0;
31130 let Inst{31-21} = 0b00011001000;
31131 let hasNewValue = 1;
31132 let opNewValue = 0;
31133 let DecoderNamespace = "EXT_mmvec";
31135 def V6_vdmpybus_acc : HInst<
31136 (outs HvxVR:$Vx32),
31137 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31138 "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
31139 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
31140 let Inst{7-5} = 0b110;
31141 let Inst{13-13} = 0b1;
31142 let Inst{31-21} = 0b00011001000;
31143 let hasNewValue = 1;
31144 let opNewValue = 0;
31145 let isAccumulator = 1;
31146 let DecoderNamespace = "EXT_mmvec";
31147 let Constraints = "$Vx32 = $Vx32in";
31149 def V6_vdmpybus_acc_alt : HInst<
31150 (outs HvxVR:$Vx32),
31151 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31152 "$Vx32 += vdmpybus($Vu32,$Rt32)",
31153 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31154 let hasNewValue = 1;
31155 let opNewValue = 0;
31156 let isAccumulator = 1;
31158 let isCodeGenOnly = 1;
31159 let DecoderNamespace = "EXT_mmvec";
31160 let Constraints = "$Vx32 = $Vx32in";
31162 def V6_vdmpybus_alt : HInst<
31163 (outs HvxVR:$Vd32),
31164 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31165 "$Vd32 = vdmpybus($Vu32,$Rt32)",
31166 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31167 let hasNewValue = 1;
31168 let opNewValue = 0;
31170 let isCodeGenOnly = 1;
31171 let DecoderNamespace = "EXT_mmvec";
31173 def V6_vdmpybus_dv : HInst<
31174 (outs HvxWR:$Vdd32),
31175 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31176 "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
31177 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31178 let Inst{7-5} = 0b111;
31179 let Inst{13-13} = 0b0;
31180 let Inst{31-21} = 0b00011001000;
31181 let hasNewValue = 1;
31182 let opNewValue = 0;
31183 let DecoderNamespace = "EXT_mmvec";
31185 def V6_vdmpybus_dv_acc : HInst<
31186 (outs HvxWR:$Vxx32),
31187 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31188 "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
31189 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31190 let Inst{7-5} = 0b111;
31191 let Inst{13-13} = 0b1;
31192 let Inst{31-21} = 0b00011001000;
31193 let hasNewValue = 1;
31194 let opNewValue = 0;
31195 let isAccumulator = 1;
31196 let DecoderNamespace = "EXT_mmvec";
31197 let Constraints = "$Vxx32 = $Vxx32in";
31199 def V6_vdmpybus_dv_acc_alt : HInst<
31200 (outs HvxWR:$Vxx32),
31201 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31202 "$Vxx32 += vdmpybus($Vuu32,$Rt32)",
31203 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31204 let hasNewValue = 1;
31205 let opNewValue = 0;
31206 let isAccumulator = 1;
31208 let isCodeGenOnly = 1;
31209 let DecoderNamespace = "EXT_mmvec";
31210 let Constraints = "$Vxx32 = $Vxx32in";
31212 def V6_vdmpybus_dv_alt : HInst<
31213 (outs HvxWR:$Vdd32),
31214 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31215 "$Vdd32 = vdmpybus($Vuu32,$Rt32)",
31216 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31217 let hasNewValue = 1;
31218 let opNewValue = 0;
31220 let isCodeGenOnly = 1;
31221 let DecoderNamespace = "EXT_mmvec";
31223 def V6_vdmpyhb : HInst<
31224 (outs HvxVR:$Vd32),
31225 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31226 "$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
31227 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
31228 let Inst{7-5} = 0b010;
31229 let Inst{13-13} = 0b0;
31230 let Inst{31-21} = 0b00011001000;
31231 let hasNewValue = 1;
31232 let opNewValue = 0;
31233 let DecoderNamespace = "EXT_mmvec";
31235 def V6_vdmpyhb_acc : HInst<
31236 (outs HvxVR:$Vx32),
31237 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31238 "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
31239 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
31240 let Inst{7-5} = 0b011;
31241 let Inst{13-13} = 0b1;
31242 let Inst{31-21} = 0b00011001000;
31243 let hasNewValue = 1;
31244 let opNewValue = 0;
31245 let isAccumulator = 1;
31246 let DecoderNamespace = "EXT_mmvec";
31247 let Constraints = "$Vx32 = $Vx32in";
31249 def V6_vdmpyhb_acc_alt : HInst<
31250 (outs HvxVR:$Vx32),
31251 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31252 "$Vx32 += vdmpyhb($Vu32,$Rt32)",
31253 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31254 let hasNewValue = 1;
31255 let opNewValue = 0;
31256 let isAccumulator = 1;
31258 let isCodeGenOnly = 1;
31259 let DecoderNamespace = "EXT_mmvec";
31260 let Constraints = "$Vx32 = $Vx32in";
31262 def V6_vdmpyhb_alt : HInst<
31263 (outs HvxVR:$Vd32),
31264 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31265 "$Vd32 = vdmpyhb($Vu32,$Rt32)",
31266 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31267 let hasNewValue = 1;
31268 let opNewValue = 0;
31270 let isCodeGenOnly = 1;
31271 let DecoderNamespace = "EXT_mmvec";
31273 def V6_vdmpyhb_dv : HInst<
31274 (outs HvxWR:$Vdd32),
31275 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31276 "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
31277 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31278 let Inst{7-5} = 0b100;
31279 let Inst{13-13} = 0b0;
31280 let Inst{31-21} = 0b00011001001;
31281 let hasNewValue = 1;
31282 let opNewValue = 0;
31283 let DecoderNamespace = "EXT_mmvec";
31285 def V6_vdmpyhb_dv_acc : HInst<
31286 (outs HvxWR:$Vxx32),
31287 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31288 "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
31289 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31290 let Inst{7-5} = 0b100;
31291 let Inst{13-13} = 0b1;
31292 let Inst{31-21} = 0b00011001001;
31293 let hasNewValue = 1;
31294 let opNewValue = 0;
31295 let isAccumulator = 1;
31296 let DecoderNamespace = "EXT_mmvec";
31297 let Constraints = "$Vxx32 = $Vxx32in";
31299 def V6_vdmpyhb_dv_acc_alt : HInst<
31300 (outs HvxWR:$Vxx32),
31301 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31302 "$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
31303 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31304 let hasNewValue = 1;
31305 let opNewValue = 0;
31306 let isAccumulator = 1;
31308 let isCodeGenOnly = 1;
31309 let DecoderNamespace = "EXT_mmvec";
31310 let Constraints = "$Vxx32 = $Vxx32in";
31312 def V6_vdmpyhb_dv_alt : HInst<
31313 (outs HvxWR:$Vdd32),
31314 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31315 "$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
31316 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31317 let hasNewValue = 1;
31318 let opNewValue = 0;
31320 let isCodeGenOnly = 1;
31321 let DecoderNamespace = "EXT_mmvec";
31323 def V6_vdmpyhisat : HInst<
31324 (outs HvxVR:$Vd32),
31325 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31326 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
31327 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
31328 let Inst{7-5} = 0b011;
31329 let Inst{13-13} = 0b0;
31330 let Inst{31-21} = 0b00011001001;
31331 let hasNewValue = 1;
31332 let opNewValue = 0;
31333 let DecoderNamespace = "EXT_mmvec";
31335 def V6_vdmpyhisat_acc : HInst<
31336 (outs HvxVR:$Vx32),
31337 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31338 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
31339 tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
31340 let Inst{7-5} = 0b010;
31341 let Inst{13-13} = 0b1;
31342 let Inst{31-21} = 0b00011001001;
31343 let hasNewValue = 1;
31344 let opNewValue = 0;
31345 let isAccumulator = 1;
31346 let DecoderNamespace = "EXT_mmvec";
31347 let Constraints = "$Vx32 = $Vx32in";
31349 def V6_vdmpyhisat_acc_alt : HInst<
31350 (outs HvxVR:$Vx32),
31351 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31352 "$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
31353 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31354 let hasNewValue = 1;
31355 let opNewValue = 0;
31356 let isAccumulator = 1;
31358 let isCodeGenOnly = 1;
31359 let DecoderNamespace = "EXT_mmvec";
31360 let Constraints = "$Vx32 = $Vx32in";
31362 def V6_vdmpyhisat_alt : HInst<
31363 (outs HvxVR:$Vd32),
31364 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31365 "$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
31366 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31367 let hasNewValue = 1;
31368 let opNewValue = 0;
31370 let isCodeGenOnly = 1;
31371 let DecoderNamespace = "EXT_mmvec";
31373 def V6_vdmpyhsat : HInst<
31374 (outs HvxVR:$Vd32),
31375 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31376 "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
31377 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
31378 let Inst{7-5} = 0b010;
31379 let Inst{13-13} = 0b0;
31380 let Inst{31-21} = 0b00011001001;
31381 let hasNewValue = 1;
31382 let opNewValue = 0;
31383 let DecoderNamespace = "EXT_mmvec";
31385 def V6_vdmpyhsat_acc : HInst<
31386 (outs HvxVR:$Vx32),
31387 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31388 "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
31389 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
31390 let Inst{7-5} = 0b011;
31391 let Inst{13-13} = 0b1;
31392 let Inst{31-21} = 0b00011001001;
31393 let hasNewValue = 1;
31394 let opNewValue = 0;
31395 let isAccumulator = 1;
31396 let DecoderNamespace = "EXT_mmvec";
31397 let Constraints = "$Vx32 = $Vx32in";
31399 def V6_vdmpyhsat_acc_alt : HInst<
31400 (outs HvxVR:$Vx32),
31401 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31402 "$Vx32 += vdmpyh($Vu32,$Rt32):sat",
31403 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31404 let hasNewValue = 1;
31405 let opNewValue = 0;
31406 let isAccumulator = 1;
31408 let isCodeGenOnly = 1;
31409 let DecoderNamespace = "EXT_mmvec";
31410 let Constraints = "$Vx32 = $Vx32in";
31412 def V6_vdmpyhsat_alt : HInst<
31413 (outs HvxVR:$Vd32),
31414 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31415 "$Vd32 = vdmpyh($Vu32,$Rt32):sat",
31416 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31417 let hasNewValue = 1;
31418 let opNewValue = 0;
31420 let isCodeGenOnly = 1;
31421 let DecoderNamespace = "EXT_mmvec";
31423 def V6_vdmpyhsuisat : HInst<
31424 (outs HvxVR:$Vd32),
31425 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31426 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
31427 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
31428 let Inst{7-5} = 0b001;
31429 let Inst{13-13} = 0b0;
31430 let Inst{31-21} = 0b00011001001;
31431 let hasNewValue = 1;
31432 let opNewValue = 0;
31433 let DecoderNamespace = "EXT_mmvec";
31435 def V6_vdmpyhsuisat_acc : HInst<
31436 (outs HvxVR:$Vx32),
31437 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31438 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
31439 tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
31440 let Inst{7-5} = 0b001;
31441 let Inst{13-13} = 0b1;
31442 let Inst{31-21} = 0b00011001001;
31443 let hasNewValue = 1;
31444 let opNewValue = 0;
31445 let isAccumulator = 1;
31446 let DecoderNamespace = "EXT_mmvec";
31447 let Constraints = "$Vx32 = $Vx32in";
31449 def V6_vdmpyhsuisat_acc_alt : HInst<
31450 (outs HvxVR:$Vx32),
31451 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31452 "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
31453 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31454 let hasNewValue = 1;
31455 let opNewValue = 0;
31456 let isAccumulator = 1;
31458 let isCodeGenOnly = 1;
31459 let DecoderNamespace = "EXT_mmvec";
31460 let Constraints = "$Vx32 = $Vx32in";
31462 def V6_vdmpyhsuisat_alt : HInst<
31463 (outs HvxVR:$Vd32),
31464 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31465 "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
31466 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31467 let hasNewValue = 1;
31468 let opNewValue = 0;
31470 let isCodeGenOnly = 1;
31471 let DecoderNamespace = "EXT_mmvec";
31473 def V6_vdmpyhsusat : HInst<
31474 (outs HvxVR:$Vd32),
31475 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31476 "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
31477 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
31478 let Inst{7-5} = 0b000;
31479 let Inst{13-13} = 0b0;
31480 let Inst{31-21} = 0b00011001001;
31481 let hasNewValue = 1;
31482 let opNewValue = 0;
31483 let DecoderNamespace = "EXT_mmvec";
31485 def V6_vdmpyhsusat_acc : HInst<
31486 (outs HvxVR:$Vx32),
31487 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31488 "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
31489 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
31490 let Inst{7-5} = 0b000;
31491 let Inst{13-13} = 0b1;
31492 let Inst{31-21} = 0b00011001001;
31493 let hasNewValue = 1;
31494 let opNewValue = 0;
31495 let isAccumulator = 1;
31496 let DecoderNamespace = "EXT_mmvec";
31497 let Constraints = "$Vx32 = $Vx32in";
31499 def V6_vdmpyhsusat_acc_alt : HInst<
31500 (outs HvxVR:$Vx32),
31501 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31502 "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
31503 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31504 let hasNewValue = 1;
31505 let opNewValue = 0;
31506 let isAccumulator = 1;
31508 let isCodeGenOnly = 1;
31509 let DecoderNamespace = "EXT_mmvec";
31510 let Constraints = "$Vx32 = $Vx32in";
31512 def V6_vdmpyhsusat_alt : HInst<
31513 (outs HvxVR:$Vd32),
31514 (ins HvxVR:$Vu32, IntRegs:$Rt32),
31515 "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
31516 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31517 let hasNewValue = 1;
31518 let opNewValue = 0;
31520 let isCodeGenOnly = 1;
31521 let DecoderNamespace = "EXT_mmvec";
31523 def V6_vdmpyhvsat : HInst<
31524 (outs HvxVR:$Vd32),
31525 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31526 "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
31527 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
31528 let Inst{7-5} = 0b011;
31529 let Inst{13-13} = 0b0;
31530 let Inst{31-21} = 0b00011100000;
31531 let hasNewValue = 1;
31532 let opNewValue = 0;
31533 let DecoderNamespace = "EXT_mmvec";
31535 def V6_vdmpyhvsat_acc : HInst<
31536 (outs HvxVR:$Vx32),
31537 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31538 "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
31539 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
31540 let Inst{7-5} = 0b011;
31541 let Inst{13-13} = 0b1;
31542 let Inst{31-21} = 0b00011100000;
31543 let hasNewValue = 1;
31544 let opNewValue = 0;
31545 let isAccumulator = 1;
31546 let DecoderNamespace = "EXT_mmvec";
31547 let Constraints = "$Vx32 = $Vx32in";
31549 def V6_vdmpyhvsat_acc_alt : HInst<
31550 (outs HvxVR:$Vx32),
31551 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31552 "$Vx32 += vdmpyh($Vu32,$Vv32):sat",
31553 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31554 let hasNewValue = 1;
31555 let opNewValue = 0;
31556 let isAccumulator = 1;
31558 let isCodeGenOnly = 1;
31559 let DecoderNamespace = "EXT_mmvec";
31560 let Constraints = "$Vx32 = $Vx32in";
31562 def V6_vdmpyhvsat_alt : HInst<
31563 (outs HvxVR:$Vd32),
31564 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31565 "$Vd32 = vdmpyh($Vu32,$Vv32):sat",
31566 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31567 let hasNewValue = 1;
31568 let opNewValue = 0;
31570 let isCodeGenOnly = 1;
31571 let DecoderNamespace = "EXT_mmvec";
31573 def V6_vdsaduh : HInst<
31574 (outs HvxWR:$Vdd32),
31575 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31576 "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
31577 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31578 let Inst{7-5} = 0b101;
31579 let Inst{13-13} = 0b0;
31580 let Inst{31-21} = 0b00011001000;
31581 let hasNewValue = 1;
31582 let opNewValue = 0;
31583 let DecoderNamespace = "EXT_mmvec";
31585 def V6_vdsaduh_acc : HInst<
31586 (outs HvxWR:$Vxx32),
31587 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31588 "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
31589 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31590 let Inst{7-5} = 0b000;
31591 let Inst{13-13} = 0b1;
31592 let Inst{31-21} = 0b00011001011;
31593 let hasNewValue = 1;
31594 let opNewValue = 0;
31595 let isAccumulator = 1;
31596 let DecoderNamespace = "EXT_mmvec";
31597 let Constraints = "$Vxx32 = $Vxx32in";
31599 def V6_vdsaduh_acc_alt : HInst<
31600 (outs HvxWR:$Vxx32),
31601 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31602 "$Vxx32 += vdsaduh($Vuu32,$Rt32)",
31603 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31604 let hasNewValue = 1;
31605 let opNewValue = 0;
31606 let isAccumulator = 1;
31608 let isCodeGenOnly = 1;
31609 let DecoderNamespace = "EXT_mmvec";
31610 let Constraints = "$Vxx32 = $Vxx32in";
31612 def V6_vdsaduh_alt : HInst<
31613 (outs HvxWR:$Vdd32),
31614 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
31615 "$Vdd32 = vdsaduh($Vuu32,$Rt32)",
31616 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31617 let hasNewValue = 1;
31618 let opNewValue = 0;
31620 let isCodeGenOnly = 1;
31621 let DecoderNamespace = "EXT_mmvec";
31623 def V6_veqb : HInst<
31625 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31626 "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
31627 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31628 let Inst{7-2} = 0b000000;
31629 let Inst{13-13} = 0b0;
31630 let Inst{31-21} = 0b00011111100;
31631 let hasNewValue = 1;
31632 let opNewValue = 0;
31633 let DecoderNamespace = "EXT_mmvec";
31635 def V6_veqb_and : HInst<
31637 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31638 "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
31639 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31640 let Inst{7-2} = 0b000000;
31641 let Inst{13-13} = 0b1;
31642 let Inst{31-21} = 0b00011100100;
31643 let DecoderNamespace = "EXT_mmvec";
31644 let Constraints = "$Qx4 = $Qx4in";
31646 def V6_veqb_or : HInst<
31648 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31649 "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
31650 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31651 let Inst{7-2} = 0b010000;
31652 let Inst{13-13} = 0b1;
31653 let Inst{31-21} = 0b00011100100;
31654 let isAccumulator = 1;
31655 let DecoderNamespace = "EXT_mmvec";
31656 let Constraints = "$Qx4 = $Qx4in";
31658 def V6_veqb_xor : HInst<
31660 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31661 "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
31662 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31663 let Inst{7-2} = 0b100000;
31664 let Inst{13-13} = 0b1;
31665 let Inst{31-21} = 0b00011100100;
31666 let DecoderNamespace = "EXT_mmvec";
31667 let Constraints = "$Qx4 = $Qx4in";
31669 def V6_veqh : HInst<
31671 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31672 "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
31673 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31674 let Inst{7-2} = 0b000001;
31675 let Inst{13-13} = 0b0;
31676 let Inst{31-21} = 0b00011111100;
31677 let hasNewValue = 1;
31678 let opNewValue = 0;
31679 let DecoderNamespace = "EXT_mmvec";
31681 def V6_veqh_and : HInst<
31683 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31684 "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
31685 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31686 let Inst{7-2} = 0b000001;
31687 let Inst{13-13} = 0b1;
31688 let Inst{31-21} = 0b00011100100;
31689 let DecoderNamespace = "EXT_mmvec";
31690 let Constraints = "$Qx4 = $Qx4in";
31692 def V6_veqh_or : HInst<
31694 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31695 "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
31696 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31697 let Inst{7-2} = 0b010001;
31698 let Inst{13-13} = 0b1;
31699 let Inst{31-21} = 0b00011100100;
31700 let isAccumulator = 1;
31701 let DecoderNamespace = "EXT_mmvec";
31702 let Constraints = "$Qx4 = $Qx4in";
31704 def V6_veqh_xor : HInst<
31706 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31707 "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
31708 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31709 let Inst{7-2} = 0b100001;
31710 let Inst{13-13} = 0b1;
31711 let Inst{31-21} = 0b00011100100;
31712 let DecoderNamespace = "EXT_mmvec";
31713 let Constraints = "$Qx4 = $Qx4in";
31715 def V6_veqw : HInst<
31717 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31718 "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
31719 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31720 let Inst{7-2} = 0b000010;
31721 let Inst{13-13} = 0b0;
31722 let Inst{31-21} = 0b00011111100;
31723 let hasNewValue = 1;
31724 let opNewValue = 0;
31725 let DecoderNamespace = "EXT_mmvec";
31727 def V6_veqw_and : HInst<
31729 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31730 "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
31731 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31732 let Inst{7-2} = 0b000010;
31733 let Inst{13-13} = 0b1;
31734 let Inst{31-21} = 0b00011100100;
31735 let DecoderNamespace = "EXT_mmvec";
31736 let Constraints = "$Qx4 = $Qx4in";
31738 def V6_veqw_or : HInst<
31740 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31741 "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
31742 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31743 let Inst{7-2} = 0b010010;
31744 let Inst{13-13} = 0b1;
31745 let Inst{31-21} = 0b00011100100;
31746 let isAccumulator = 1;
31747 let DecoderNamespace = "EXT_mmvec";
31748 let Constraints = "$Qx4 = $Qx4in";
31750 def V6_veqw_xor : HInst<
31752 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31753 "$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
31754 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31755 let Inst{7-2} = 0b100010;
31756 let Inst{13-13} = 0b1;
31757 let Inst{31-21} = 0b00011100100;
31758 let DecoderNamespace = "EXT_mmvec";
31759 let Constraints = "$Qx4 = $Qx4in";
31761 def V6_vgathermh : HInst<
31763 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31764 "vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
31765 tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
31766 let Inst{12-5} = 0b00001000;
31767 let Inst{31-21} = 0b00101111000;
31768 let hasNewValue = 1;
31769 let opNewValue = 0;
31770 let accessSize = HalfWordAccess;
31775 let DecoderNamespace = "EXT_mmvec";
31777 def V6_vgathermhq : HInst<
31779 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31780 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
31781 tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
31782 let Inst{12-7} = 0b001010;
31783 let Inst{31-21} = 0b00101111000;
31784 let hasNewValue = 1;
31785 let opNewValue = 0;
31786 let accessSize = HalfWordAccess;
31791 let DecoderNamespace = "EXT_mmvec";
31793 def V6_vgathermhw : HInst<
31795 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
31796 "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
31797 tc_bfe309d5, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> {
31798 let Inst{12-5} = 0b00010000;
31799 let Inst{31-21} = 0b00101111000;
31800 let hasNewValue = 1;
31801 let opNewValue = 0;
31802 let accessSize = HalfWordAccess;
31807 let DecoderNamespace = "EXT_mmvec";
31809 def V6_vgathermhwq : HInst<
31811 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
31812 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
31813 tc_98733e9d, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> {
31814 let Inst{12-7} = 0b001100;
31815 let Inst{31-21} = 0b00101111000;
31816 let hasNewValue = 1;
31817 let opNewValue = 0;
31818 let accessSize = HalfWordAccess;
31823 let DecoderNamespace = "EXT_mmvec";
31825 def V6_vgathermw : HInst<
31827 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31828 "vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
31829 tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
31830 let Inst{12-5} = 0b00000000;
31831 let Inst{31-21} = 0b00101111000;
31832 let hasNewValue = 1;
31833 let opNewValue = 0;
31834 let accessSize = WordAccess;
31839 let DecoderNamespace = "EXT_mmvec";
31841 def V6_vgathermwq : HInst<
31843 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31844 "if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
31845 tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
31846 let Inst{12-7} = 0b001000;
31847 let Inst{31-21} = 0b00101111000;
31848 let hasNewValue = 1;
31849 let opNewValue = 0;
31850 let accessSize = WordAccess;
31855 let DecoderNamespace = "EXT_mmvec";
31857 def V6_vgtb : HInst<
31859 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31860 "$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
31861 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31862 let Inst{7-2} = 0b000100;
31863 let Inst{13-13} = 0b0;
31864 let Inst{31-21} = 0b00011111100;
31865 let hasNewValue = 1;
31866 let opNewValue = 0;
31867 let DecoderNamespace = "EXT_mmvec";
31869 def V6_vgtb_and : HInst<
31871 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31872 "$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
31873 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31874 let Inst{7-2} = 0b000100;
31875 let Inst{13-13} = 0b1;
31876 let Inst{31-21} = 0b00011100100;
31877 let DecoderNamespace = "EXT_mmvec";
31878 let Constraints = "$Qx4 = $Qx4in";
31880 def V6_vgtb_or : HInst<
31882 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31883 "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
31884 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31885 let Inst{7-2} = 0b010100;
31886 let Inst{13-13} = 0b1;
31887 let Inst{31-21} = 0b00011100100;
31888 let isAccumulator = 1;
31889 let DecoderNamespace = "EXT_mmvec";
31890 let Constraints = "$Qx4 = $Qx4in";
31892 def V6_vgtb_xor : HInst<
31894 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31895 "$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
31896 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31897 let Inst{7-2} = 0b100100;
31898 let Inst{13-13} = 0b1;
31899 let Inst{31-21} = 0b00011100100;
31900 let DecoderNamespace = "EXT_mmvec";
31901 let Constraints = "$Qx4 = $Qx4in";
31903 def V6_vgth : HInst<
31905 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31906 "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
31907 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31908 let Inst{7-2} = 0b000101;
31909 let Inst{13-13} = 0b0;
31910 let Inst{31-21} = 0b00011111100;
31911 let hasNewValue = 1;
31912 let opNewValue = 0;
31913 let DecoderNamespace = "EXT_mmvec";
31915 def V6_vgth_and : HInst<
31917 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31918 "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
31919 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31920 let Inst{7-2} = 0b000101;
31921 let Inst{13-13} = 0b1;
31922 let Inst{31-21} = 0b00011100100;
31923 let DecoderNamespace = "EXT_mmvec";
31924 let Constraints = "$Qx4 = $Qx4in";
31926 def V6_vgth_or : HInst<
31928 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31929 "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
31930 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31931 let Inst{7-2} = 0b010101;
31932 let Inst{13-13} = 0b1;
31933 let Inst{31-21} = 0b00011100100;
31934 let isAccumulator = 1;
31935 let DecoderNamespace = "EXT_mmvec";
31936 let Constraints = "$Qx4 = $Qx4in";
31938 def V6_vgth_xor : HInst<
31940 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31941 "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
31942 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31943 let Inst{7-2} = 0b100101;
31944 let Inst{13-13} = 0b1;
31945 let Inst{31-21} = 0b00011100100;
31946 let DecoderNamespace = "EXT_mmvec";
31947 let Constraints = "$Qx4 = $Qx4in";
31949 def V6_vgtub : HInst<
31951 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31952 "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
31953 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31954 let Inst{7-2} = 0b001000;
31955 let Inst{13-13} = 0b0;
31956 let Inst{31-21} = 0b00011111100;
31957 let hasNewValue = 1;
31958 let opNewValue = 0;
31959 let DecoderNamespace = "EXT_mmvec";
31961 def V6_vgtub_and : HInst<
31963 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31964 "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
31965 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31966 let Inst{7-2} = 0b001000;
31967 let Inst{13-13} = 0b1;
31968 let Inst{31-21} = 0b00011100100;
31969 let DecoderNamespace = "EXT_mmvec";
31970 let Constraints = "$Qx4 = $Qx4in";
31972 def V6_vgtub_or : HInst<
31974 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31975 "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
31976 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31977 let Inst{7-2} = 0b011000;
31978 let Inst{13-13} = 0b1;
31979 let Inst{31-21} = 0b00011100100;
31980 let isAccumulator = 1;
31981 let DecoderNamespace = "EXT_mmvec";
31982 let Constraints = "$Qx4 = $Qx4in";
31984 def V6_vgtub_xor : HInst<
31986 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31987 "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
31988 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31989 let Inst{7-2} = 0b101000;
31990 let Inst{13-13} = 0b1;
31991 let Inst{31-21} = 0b00011100100;
31992 let DecoderNamespace = "EXT_mmvec";
31993 let Constraints = "$Qx4 = $Qx4in";
31995 def V6_vgtuh : HInst<
31997 (ins HvxVR:$Vu32, HvxVR:$Vv32),
31998 "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
31999 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32000 let Inst{7-2} = 0b001001;
32001 let Inst{13-13} = 0b0;
32002 let Inst{31-21} = 0b00011111100;
32003 let hasNewValue = 1;
32004 let opNewValue = 0;
32005 let DecoderNamespace = "EXT_mmvec";
32007 def V6_vgtuh_and : HInst<
32009 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32010 "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
32011 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32012 let Inst{7-2} = 0b001001;
32013 let Inst{13-13} = 0b1;
32014 let Inst{31-21} = 0b00011100100;
32015 let DecoderNamespace = "EXT_mmvec";
32016 let Constraints = "$Qx4 = $Qx4in";
32018 def V6_vgtuh_or : HInst<
32020 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32021 "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
32022 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32023 let Inst{7-2} = 0b011001;
32024 let Inst{13-13} = 0b1;
32025 let Inst{31-21} = 0b00011100100;
32026 let isAccumulator = 1;
32027 let DecoderNamespace = "EXT_mmvec";
32028 let Constraints = "$Qx4 = $Qx4in";
32030 def V6_vgtuh_xor : HInst<
32032 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32033 "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
32034 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32035 let Inst{7-2} = 0b101001;
32036 let Inst{13-13} = 0b1;
32037 let Inst{31-21} = 0b00011100100;
32038 let DecoderNamespace = "EXT_mmvec";
32039 let Constraints = "$Qx4 = $Qx4in";
32041 def V6_vgtuw : HInst<
32043 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32044 "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
32045 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32046 let Inst{7-2} = 0b001010;
32047 let Inst{13-13} = 0b0;
32048 let Inst{31-21} = 0b00011111100;
32049 let hasNewValue = 1;
32050 let opNewValue = 0;
32051 let DecoderNamespace = "EXT_mmvec";
32053 def V6_vgtuw_and : HInst<
32055 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32056 "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
32057 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32058 let Inst{7-2} = 0b001010;
32059 let Inst{13-13} = 0b1;
32060 let Inst{31-21} = 0b00011100100;
32061 let DecoderNamespace = "EXT_mmvec";
32062 let Constraints = "$Qx4 = $Qx4in";
32064 def V6_vgtuw_or : HInst<
32066 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32067 "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
32068 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32069 let Inst{7-2} = 0b011010;
32070 let Inst{13-13} = 0b1;
32071 let Inst{31-21} = 0b00011100100;
32072 let isAccumulator = 1;
32073 let DecoderNamespace = "EXT_mmvec";
32074 let Constraints = "$Qx4 = $Qx4in";
32076 def V6_vgtuw_xor : HInst<
32078 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32079 "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
32080 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32081 let Inst{7-2} = 0b101010;
32082 let Inst{13-13} = 0b1;
32083 let Inst{31-21} = 0b00011100100;
32084 let DecoderNamespace = "EXT_mmvec";
32085 let Constraints = "$Qx4 = $Qx4in";
32087 def V6_vgtw : HInst<
32089 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32090 "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
32091 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32092 let Inst{7-2} = 0b000110;
32093 let Inst{13-13} = 0b0;
32094 let Inst{31-21} = 0b00011111100;
32095 let hasNewValue = 1;
32096 let opNewValue = 0;
32097 let DecoderNamespace = "EXT_mmvec";
32099 def V6_vgtw_and : HInst<
32101 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32102 "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
32103 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32104 let Inst{7-2} = 0b000110;
32105 let Inst{13-13} = 0b1;
32106 let Inst{31-21} = 0b00011100100;
32107 let DecoderNamespace = "EXT_mmvec";
32108 let Constraints = "$Qx4 = $Qx4in";
32110 def V6_vgtw_or : HInst<
32112 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32113 "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
32114 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32115 let Inst{7-2} = 0b010110;
32116 let Inst{13-13} = 0b1;
32117 let Inst{31-21} = 0b00011100100;
32118 let isAccumulator = 1;
32119 let DecoderNamespace = "EXT_mmvec";
32120 let Constraints = "$Qx4 = $Qx4in";
32122 def V6_vgtw_xor : HInst<
32124 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32125 "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
32126 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32127 let Inst{7-2} = 0b100110;
32128 let Inst{13-13} = 0b1;
32129 let Inst{31-21} = 0b00011100100;
32130 let DecoderNamespace = "EXT_mmvec";
32131 let Constraints = "$Qx4 = $Qx4in";
32133 def V6_vhist : HInst<
32137 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
32138 let Inst{13-0} = 0b10000010000000;
32139 let Inst{31-16} = 0b0001111000000000;
32140 let DecoderNamespace = "EXT_mmvec";
32142 def V6_vhistq : HInst<
32146 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
32147 let Inst{13-0} = 0b10000010000000;
32148 let Inst{21-16} = 0b000010;
32149 let Inst{31-24} = 0b00011110;
32150 let DecoderNamespace = "EXT_mmvec";
32152 def V6_vinsertwr : HInst<
32153 (outs HvxVR:$Vx32),
32154 (ins HvxVR:$Vx32in, IntRegs:$Rt32),
32155 "$Vx32.w = vinsert($Rt32)",
32156 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
32157 let Inst{13-5} = 0b100000001;
32158 let Inst{31-21} = 0b00011001101;
32159 let hasNewValue = 1;
32160 let opNewValue = 0;
32161 let DecoderNamespace = "EXT_mmvec";
32162 let Constraints = "$Vx32 = $Vx32in";
32164 def V6_vlalignb : HInst<
32165 (outs HvxVR:$Vd32),
32166 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32167 "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
32168 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
32169 let Inst{7-5} = 0b001;
32170 let Inst{13-13} = 0b0;
32171 let Inst{31-24} = 0b00011011;
32172 let hasNewValue = 1;
32173 let opNewValue = 0;
32174 let DecoderNamespace = "EXT_mmvec";
32176 def V6_vlalignbi : HInst<
32177 (outs HvxVR:$Vd32),
32178 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32179 "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
32180 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
32181 let Inst{13-13} = 0b1;
32182 let Inst{31-21} = 0b00011110011;
32183 let hasNewValue = 1;
32184 let opNewValue = 0;
32185 let DecoderNamespace = "EXT_mmvec";
32187 def V6_vlsrb : HInst<
32188 (outs HvxVR:$Vd32),
32189 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32190 "$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
32191 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
32192 let Inst{7-5} = 0b011;
32193 let Inst{13-13} = 0b0;
32194 let Inst{31-21} = 0b00011001100;
32195 let hasNewValue = 1;
32196 let opNewValue = 0;
32197 let DecoderNamespace = "EXT_mmvec";
32199 def V6_vlsrh : HInst<
32200 (outs HvxVR:$Vd32),
32201 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32202 "$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
32203 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
32204 let Inst{7-5} = 0b010;
32205 let Inst{13-13} = 0b0;
32206 let Inst{31-21} = 0b00011001100;
32207 let hasNewValue = 1;
32208 let opNewValue = 0;
32209 let DecoderNamespace = "EXT_mmvec";
32211 def V6_vlsrh_alt : HInst<
32212 (outs HvxVR:$Vd32),
32213 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32214 "$Vd32 = vlsrh($Vu32,$Rt32)",
32215 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32216 let hasNewValue = 1;
32217 let opNewValue = 0;
32219 let isCodeGenOnly = 1;
32220 let DecoderNamespace = "EXT_mmvec";
32222 def V6_vlsrhv : HInst<
32223 (outs HvxVR:$Vd32),
32224 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32225 "$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
32226 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
32227 let Inst{7-5} = 0b010;
32228 let Inst{13-13} = 0b0;
32229 let Inst{31-21} = 0b00011111101;
32230 let hasNewValue = 1;
32231 let opNewValue = 0;
32232 let DecoderNamespace = "EXT_mmvec";
32234 def V6_vlsrhv_alt : HInst<
32235 (outs HvxVR:$Vd32),
32236 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32237 "$Vd32 = vlsrh($Vu32,$Vv32)",
32238 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32239 let hasNewValue = 1;
32240 let opNewValue = 0;
32242 let isCodeGenOnly = 1;
32243 let DecoderNamespace = "EXT_mmvec";
32245 def V6_vlsrw : HInst<
32246 (outs HvxVR:$Vd32),
32247 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32248 "$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
32249 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
32250 let Inst{7-5} = 0b001;
32251 let Inst{13-13} = 0b0;
32252 let Inst{31-21} = 0b00011001100;
32253 let hasNewValue = 1;
32254 let opNewValue = 0;
32255 let DecoderNamespace = "EXT_mmvec";
32257 def V6_vlsrw_alt : HInst<
32258 (outs HvxVR:$Vd32),
32259 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32260 "$Vd32 = vlsrw($Vu32,$Rt32)",
32261 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32262 let hasNewValue = 1;
32263 let opNewValue = 0;
32265 let isCodeGenOnly = 1;
32266 let DecoderNamespace = "EXT_mmvec";
32268 def V6_vlsrwv : HInst<
32269 (outs HvxVR:$Vd32),
32270 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32271 "$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
32272 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
32273 let Inst{7-5} = 0b001;
32274 let Inst{13-13} = 0b0;
32275 let Inst{31-21} = 0b00011111101;
32276 let hasNewValue = 1;
32277 let opNewValue = 0;
32278 let DecoderNamespace = "EXT_mmvec";
32280 def V6_vlsrwv_alt : HInst<
32281 (outs HvxVR:$Vd32),
32282 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32283 "$Vd32 = vlsrw($Vu32,$Vv32)",
32284 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32285 let hasNewValue = 1;
32286 let opNewValue = 0;
32288 let isCodeGenOnly = 1;
32289 let DecoderNamespace = "EXT_mmvec";
32291 def V6_vlut4 : HInst<
32292 (outs HvxVR:$Vd32),
32293 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
32294 "$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
32295 tc_fa99dc24, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
32296 let Inst{7-5} = 0b100;
32297 let Inst{13-13} = 0b0;
32298 let Inst{31-21} = 0b00011001011;
32299 let hasNewValue = 1;
32300 let opNewValue = 0;
32301 let DecoderNamespace = "EXT_mmvec";
32303 def V6_vlutvvb : HInst<
32304 (outs HvxVR:$Vd32),
32305 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32306 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
32307 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
32308 let Inst{7-5} = 0b001;
32309 let Inst{13-13} = 0b1;
32310 let Inst{31-24} = 0b00011011;
32311 let hasNewValue = 1;
32312 let opNewValue = 0;
32313 let DecoderNamespace = "EXT_mmvec";
32315 def V6_vlutvvb_nm : HInst<
32316 (outs HvxVR:$Vd32),
32317 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32318 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
32319 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
32320 let Inst{7-5} = 0b011;
32321 let Inst{13-13} = 0b0;
32322 let Inst{31-24} = 0b00011000;
32323 let hasNewValue = 1;
32324 let opNewValue = 0;
32325 let DecoderNamespace = "EXT_mmvec";
32327 def V6_vlutvvb_oracc : HInst<
32328 (outs HvxVR:$Vx32),
32329 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32330 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
32331 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
32332 let Inst{7-5} = 0b101;
32333 let Inst{13-13} = 0b1;
32334 let Inst{31-24} = 0b00011011;
32335 let hasNewValue = 1;
32336 let opNewValue = 0;
32337 let isAccumulator = 1;
32338 let DecoderNamespace = "EXT_mmvec";
32339 let Constraints = "$Vx32 = $Vx32in";
32341 def V6_vlutvvb_oracci : HInst<
32342 (outs HvxVR:$Vx32),
32343 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32344 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
32345 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
32346 let Inst{13-13} = 0b1;
32347 let Inst{31-21} = 0b00011100110;
32348 let hasNewValue = 1;
32349 let opNewValue = 0;
32350 let isAccumulator = 1;
32351 let DecoderNamespace = "EXT_mmvec";
32352 let Constraints = "$Vx32 = $Vx32in";
32354 def V6_vlutvvbi : HInst<
32355 (outs HvxVR:$Vd32),
32356 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32357 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
32358 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
32359 let Inst{13-13} = 0b0;
32360 let Inst{31-21} = 0b00011110001;
32361 let hasNewValue = 1;
32362 let opNewValue = 0;
32363 let DecoderNamespace = "EXT_mmvec";
32365 def V6_vlutvwh : HInst<
32366 (outs HvxWR:$Vdd32),
32367 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32368 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
32369 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32370 let Inst{7-5} = 0b110;
32371 let Inst{13-13} = 0b1;
32372 let Inst{31-24} = 0b00011011;
32373 let hasNewValue = 1;
32374 let opNewValue = 0;
32375 let DecoderNamespace = "EXT_mmvec";
32377 def V6_vlutvwh_nm : HInst<
32378 (outs HvxWR:$Vdd32),
32379 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32380 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
32381 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
32382 let Inst{7-5} = 0b100;
32383 let Inst{13-13} = 0b0;
32384 let Inst{31-24} = 0b00011000;
32385 let hasNewValue = 1;
32386 let opNewValue = 0;
32387 let DecoderNamespace = "EXT_mmvec";
32389 def V6_vlutvwh_oracc : HInst<
32390 (outs HvxWR:$Vxx32),
32391 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32392 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
32393 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
32394 let Inst{7-5} = 0b111;
32395 let Inst{13-13} = 0b1;
32396 let Inst{31-24} = 0b00011011;
32397 let hasNewValue = 1;
32398 let opNewValue = 0;
32399 let isAccumulator = 1;
32400 let DecoderNamespace = "EXT_mmvec";
32401 let Constraints = "$Vxx32 = $Vxx32in";
32403 def V6_vlutvwh_oracci : HInst<
32404 (outs HvxWR:$Vxx32),
32405 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32406 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
32407 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
32408 let Inst{13-13} = 0b1;
32409 let Inst{31-21} = 0b00011100111;
32410 let hasNewValue = 1;
32411 let opNewValue = 0;
32412 let isAccumulator = 1;
32413 let DecoderNamespace = "EXT_mmvec";
32414 let Constraints = "$Vxx32 = $Vxx32in";
32416 def V6_vlutvwhi : HInst<
32417 (outs HvxWR:$Vdd32),
32418 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32419 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
32420 tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
32421 let Inst{13-13} = 0b0;
32422 let Inst{31-21} = 0b00011110011;
32423 let hasNewValue = 1;
32424 let opNewValue = 0;
32425 let DecoderNamespace = "EXT_mmvec";
32427 def V6_vmaxb : HInst<
32428 (outs HvxVR:$Vd32),
32429 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32430 "$Vd32.b = vmax($Vu32.b,$Vv32.b)",
32431 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
32432 let Inst{7-5} = 0b101;
32433 let Inst{13-13} = 0b0;
32434 let Inst{31-21} = 0b00011111001;
32435 let hasNewValue = 1;
32436 let opNewValue = 0;
32437 let DecoderNamespace = "EXT_mmvec";
32439 def V6_vmaxb_alt : HInst<
32440 (outs HvxVR:$Vd32),
32441 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32442 "$Vd32 = vmaxb($Vu32,$Vv32)",
32443 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32444 let hasNewValue = 1;
32445 let opNewValue = 0;
32447 let isCodeGenOnly = 1;
32448 let DecoderNamespace = "EXT_mmvec";
32450 def V6_vmaxh : HInst<
32451 (outs HvxVR:$Vd32),
32452 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32453 "$Vd32.h = vmax($Vu32.h,$Vv32.h)",
32454 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32455 let Inst{7-5} = 0b111;
32456 let Inst{13-13} = 0b0;
32457 let Inst{31-21} = 0b00011111000;
32458 let hasNewValue = 1;
32459 let opNewValue = 0;
32460 let DecoderNamespace = "EXT_mmvec";
32462 def V6_vmaxh_alt : HInst<
32463 (outs HvxVR:$Vd32),
32464 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32465 "$Vd32 = vmaxh($Vu32,$Vv32)",
32466 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32467 let hasNewValue = 1;
32468 let opNewValue = 0;
32470 let isCodeGenOnly = 1;
32471 let DecoderNamespace = "EXT_mmvec";
32473 def V6_vmaxub : HInst<
32474 (outs HvxVR:$Vd32),
32475 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32476 "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
32477 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32478 let Inst{7-5} = 0b101;
32479 let Inst{13-13} = 0b0;
32480 let Inst{31-21} = 0b00011111000;
32481 let hasNewValue = 1;
32482 let opNewValue = 0;
32483 let DecoderNamespace = "EXT_mmvec";
32485 def V6_vmaxub_alt : HInst<
32486 (outs HvxVR:$Vd32),
32487 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32488 "$Vd32 = vmaxub($Vu32,$Vv32)",
32489 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32490 let hasNewValue = 1;
32491 let opNewValue = 0;
32493 let isCodeGenOnly = 1;
32494 let DecoderNamespace = "EXT_mmvec";
32496 def V6_vmaxuh : HInst<
32497 (outs HvxVR:$Vd32),
32498 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32499 "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
32500 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32501 let Inst{7-5} = 0b110;
32502 let Inst{13-13} = 0b0;
32503 let Inst{31-21} = 0b00011111000;
32504 let hasNewValue = 1;
32505 let opNewValue = 0;
32506 let DecoderNamespace = "EXT_mmvec";
32508 def V6_vmaxuh_alt : HInst<
32509 (outs HvxVR:$Vd32),
32510 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32511 "$Vd32 = vmaxuh($Vu32,$Vv32)",
32512 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32513 let hasNewValue = 1;
32514 let opNewValue = 0;
32516 let isCodeGenOnly = 1;
32517 let DecoderNamespace = "EXT_mmvec";
32519 def V6_vmaxw : HInst<
32520 (outs HvxVR:$Vd32),
32521 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32522 "$Vd32.w = vmax($Vu32.w,$Vv32.w)",
32523 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32524 let Inst{7-5} = 0b000;
32525 let Inst{13-13} = 0b0;
32526 let Inst{31-21} = 0b00011111001;
32527 let hasNewValue = 1;
32528 let opNewValue = 0;
32529 let DecoderNamespace = "EXT_mmvec";
32531 def V6_vmaxw_alt : HInst<
32532 (outs HvxVR:$Vd32),
32533 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32534 "$Vd32 = vmaxw($Vu32,$Vv32)",
32535 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32536 let hasNewValue = 1;
32537 let opNewValue = 0;
32539 let isCodeGenOnly = 1;
32540 let DecoderNamespace = "EXT_mmvec";
32542 def V6_vminb : HInst<
32543 (outs HvxVR:$Vd32),
32544 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32545 "$Vd32.b = vmin($Vu32.b,$Vv32.b)",
32546 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
32547 let Inst{7-5} = 0b100;
32548 let Inst{13-13} = 0b0;
32549 let Inst{31-21} = 0b00011111001;
32550 let hasNewValue = 1;
32551 let opNewValue = 0;
32552 let DecoderNamespace = "EXT_mmvec";
32554 def V6_vminb_alt : HInst<
32555 (outs HvxVR:$Vd32),
32556 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32557 "$Vd32 = vminb($Vu32,$Vv32)",
32558 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32559 let hasNewValue = 1;
32560 let opNewValue = 0;
32562 let isCodeGenOnly = 1;
32563 let DecoderNamespace = "EXT_mmvec";
32565 def V6_vminh : HInst<
32566 (outs HvxVR:$Vd32),
32567 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32568 "$Vd32.h = vmin($Vu32.h,$Vv32.h)",
32569 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32570 let Inst{7-5} = 0b011;
32571 let Inst{13-13} = 0b0;
32572 let Inst{31-21} = 0b00011111000;
32573 let hasNewValue = 1;
32574 let opNewValue = 0;
32575 let DecoderNamespace = "EXT_mmvec";
32577 def V6_vminh_alt : HInst<
32578 (outs HvxVR:$Vd32),
32579 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32580 "$Vd32 = vminh($Vu32,$Vv32)",
32581 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32582 let hasNewValue = 1;
32583 let opNewValue = 0;
32585 let isCodeGenOnly = 1;
32586 let DecoderNamespace = "EXT_mmvec";
32588 def V6_vminub : HInst<
32589 (outs HvxVR:$Vd32),
32590 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32591 "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
32592 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32593 let Inst{7-5} = 0b001;
32594 let Inst{13-13} = 0b0;
32595 let Inst{31-21} = 0b00011111000;
32596 let hasNewValue = 1;
32597 let opNewValue = 0;
32598 let DecoderNamespace = "EXT_mmvec";
32600 def V6_vminub_alt : HInst<
32601 (outs HvxVR:$Vd32),
32602 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32603 "$Vd32 = vminub($Vu32,$Vv32)",
32604 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32605 let hasNewValue = 1;
32606 let opNewValue = 0;
32608 let isCodeGenOnly = 1;
32609 let DecoderNamespace = "EXT_mmvec";
32611 def V6_vminuh : HInst<
32612 (outs HvxVR:$Vd32),
32613 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32614 "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
32615 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32616 let Inst{7-5} = 0b010;
32617 let Inst{13-13} = 0b0;
32618 let Inst{31-21} = 0b00011111000;
32619 let hasNewValue = 1;
32620 let opNewValue = 0;
32621 let DecoderNamespace = "EXT_mmvec";
32623 def V6_vminuh_alt : HInst<
32624 (outs HvxVR:$Vd32),
32625 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32626 "$Vd32 = vminuh($Vu32,$Vv32)",
32627 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32628 let hasNewValue = 1;
32629 let opNewValue = 0;
32631 let isCodeGenOnly = 1;
32632 let DecoderNamespace = "EXT_mmvec";
32634 def V6_vminw : HInst<
32635 (outs HvxVR:$Vd32),
32636 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32637 "$Vd32.w = vmin($Vu32.w,$Vv32.w)",
32638 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32639 let Inst{7-5} = 0b100;
32640 let Inst{13-13} = 0b0;
32641 let Inst{31-21} = 0b00011111000;
32642 let hasNewValue = 1;
32643 let opNewValue = 0;
32644 let DecoderNamespace = "EXT_mmvec";
32646 def V6_vminw_alt : HInst<
32647 (outs HvxVR:$Vd32),
32648 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32649 "$Vd32 = vminw($Vu32,$Vv32)",
32650 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32651 let hasNewValue = 1;
32652 let opNewValue = 0;
32654 let isCodeGenOnly = 1;
32655 let DecoderNamespace = "EXT_mmvec";
32657 def V6_vmpabus : HInst<
32658 (outs HvxWR:$Vdd32),
32659 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32660 "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
32661 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32662 let Inst{7-5} = 0b110;
32663 let Inst{13-13} = 0b0;
32664 let Inst{31-21} = 0b00011001001;
32665 let hasNewValue = 1;
32666 let opNewValue = 0;
32667 let DecoderNamespace = "EXT_mmvec";
32669 def V6_vmpabus_acc : HInst<
32670 (outs HvxWR:$Vxx32),
32671 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32672 "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
32673 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32674 let Inst{7-5} = 0b110;
32675 let Inst{13-13} = 0b1;
32676 let Inst{31-21} = 0b00011001001;
32677 let hasNewValue = 1;
32678 let opNewValue = 0;
32679 let isAccumulator = 1;
32680 let DecoderNamespace = "EXT_mmvec";
32681 let Constraints = "$Vxx32 = $Vxx32in";
32683 def V6_vmpabus_acc_alt : HInst<
32684 (outs HvxWR:$Vxx32),
32685 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32686 "$Vxx32 += vmpabus($Vuu32,$Rt32)",
32687 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32688 let hasNewValue = 1;
32689 let opNewValue = 0;
32690 let isAccumulator = 1;
32692 let isCodeGenOnly = 1;
32693 let DecoderNamespace = "EXT_mmvec";
32694 let Constraints = "$Vxx32 = $Vxx32in";
32696 def V6_vmpabus_alt : HInst<
32697 (outs HvxWR:$Vdd32),
32698 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32699 "$Vdd32 = vmpabus($Vuu32,$Rt32)",
32700 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32701 let hasNewValue = 1;
32702 let opNewValue = 0;
32704 let isCodeGenOnly = 1;
32705 let DecoderNamespace = "EXT_mmvec";
32707 def V6_vmpabusv : HInst<
32708 (outs HvxWR:$Vdd32),
32709 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32710 "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
32711 tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
32712 let Inst{7-5} = 0b011;
32713 let Inst{13-13} = 0b0;
32714 let Inst{31-21} = 0b00011100001;
32715 let hasNewValue = 1;
32716 let opNewValue = 0;
32717 let DecoderNamespace = "EXT_mmvec";
32719 def V6_vmpabusv_alt : HInst<
32720 (outs HvxWR:$Vdd32),
32721 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32722 "$Vdd32 = vmpabus($Vuu32,$Vvv32)",
32723 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32724 let hasNewValue = 1;
32725 let opNewValue = 0;
32727 let isCodeGenOnly = 1;
32728 let DecoderNamespace = "EXT_mmvec";
32730 def V6_vmpabuu : HInst<
32731 (outs HvxWR:$Vdd32),
32732 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32733 "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
32734 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
32735 let Inst{7-5} = 0b011;
32736 let Inst{13-13} = 0b0;
32737 let Inst{31-21} = 0b00011001011;
32738 let hasNewValue = 1;
32739 let opNewValue = 0;
32740 let DecoderNamespace = "EXT_mmvec";
32742 def V6_vmpabuu_acc : HInst<
32743 (outs HvxWR:$Vxx32),
32744 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32745 "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
32746 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
32747 let Inst{7-5} = 0b100;
32748 let Inst{13-13} = 0b1;
32749 let Inst{31-21} = 0b00011001101;
32750 let hasNewValue = 1;
32751 let opNewValue = 0;
32752 let isAccumulator = 1;
32753 let DecoderNamespace = "EXT_mmvec";
32754 let Constraints = "$Vxx32 = $Vxx32in";
32756 def V6_vmpabuu_acc_alt : HInst<
32757 (outs HvxWR:$Vxx32),
32758 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32759 "$Vxx32 += vmpabuu($Vuu32,$Rt32)",
32760 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32761 let hasNewValue = 1;
32762 let opNewValue = 0;
32763 let isAccumulator = 1;
32765 let isCodeGenOnly = 1;
32766 let DecoderNamespace = "EXT_mmvec";
32767 let Constraints = "$Vxx32 = $Vxx32in";
32769 def V6_vmpabuu_alt : HInst<
32770 (outs HvxWR:$Vdd32),
32771 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32772 "$Vdd32 = vmpabuu($Vuu32,$Rt32)",
32773 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32774 let hasNewValue = 1;
32775 let opNewValue = 0;
32777 let isCodeGenOnly = 1;
32778 let DecoderNamespace = "EXT_mmvec";
32780 def V6_vmpabuuv : HInst<
32781 (outs HvxWR:$Vdd32),
32782 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32783 "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
32784 tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
32785 let Inst{7-5} = 0b111;
32786 let Inst{13-13} = 0b0;
32787 let Inst{31-21} = 0b00011100111;
32788 let hasNewValue = 1;
32789 let opNewValue = 0;
32790 let DecoderNamespace = "EXT_mmvec";
32792 def V6_vmpabuuv_alt : HInst<
32793 (outs HvxWR:$Vdd32),
32794 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32795 "$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
32796 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32797 let hasNewValue = 1;
32798 let opNewValue = 0;
32800 let isCodeGenOnly = 1;
32801 let DecoderNamespace = "EXT_mmvec";
32803 def V6_vmpahb : HInst<
32804 (outs HvxWR:$Vdd32),
32805 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32806 "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
32807 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32808 let Inst{7-5} = 0b111;
32809 let Inst{13-13} = 0b0;
32810 let Inst{31-21} = 0b00011001001;
32811 let hasNewValue = 1;
32812 let opNewValue = 0;
32813 let DecoderNamespace = "EXT_mmvec";
32815 def V6_vmpahb_acc : HInst<
32816 (outs HvxWR:$Vxx32),
32817 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32818 "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
32819 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32820 let Inst{7-5} = 0b111;
32821 let Inst{13-13} = 0b1;
32822 let Inst{31-21} = 0b00011001001;
32823 let hasNewValue = 1;
32824 let opNewValue = 0;
32825 let isAccumulator = 1;
32826 let DecoderNamespace = "EXT_mmvec";
32827 let Constraints = "$Vxx32 = $Vxx32in";
32829 def V6_vmpahb_acc_alt : HInst<
32830 (outs HvxWR:$Vxx32),
32831 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32832 "$Vxx32 += vmpahb($Vuu32,$Rt32)",
32833 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32834 let hasNewValue = 1;
32835 let opNewValue = 0;
32836 let isAccumulator = 1;
32838 let isCodeGenOnly = 1;
32839 let DecoderNamespace = "EXT_mmvec";
32840 let Constraints = "$Vxx32 = $Vxx32in";
32842 def V6_vmpahb_alt : HInst<
32843 (outs HvxWR:$Vdd32),
32844 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32845 "$Vdd32 = vmpahb($Vuu32,$Rt32)",
32846 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32847 let hasNewValue = 1;
32848 let opNewValue = 0;
32850 let isCodeGenOnly = 1;
32851 let DecoderNamespace = "EXT_mmvec";
32853 def V6_vmpahhsat : HInst<
32854 (outs HvxVR:$Vx32),
32855 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
32856 "$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
32857 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
32858 let Inst{7-5} = 0b100;
32859 let Inst{13-13} = 0b1;
32860 let Inst{31-21} = 0b00011001100;
32861 let hasNewValue = 1;
32862 let opNewValue = 0;
32863 let DecoderNamespace = "EXT_mmvec";
32864 let Constraints = "$Vx32 = $Vx32in";
32866 def V6_vmpauhb : HInst<
32867 (outs HvxWR:$Vdd32),
32868 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32869 "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
32870 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
32871 let Inst{7-5} = 0b101;
32872 let Inst{13-13} = 0b0;
32873 let Inst{31-21} = 0b00011001100;
32874 let hasNewValue = 1;
32875 let opNewValue = 0;
32876 let DecoderNamespace = "EXT_mmvec";
32878 def V6_vmpauhb_acc : HInst<
32879 (outs HvxWR:$Vxx32),
32880 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32881 "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
32882 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
32883 let Inst{7-5} = 0b010;
32884 let Inst{13-13} = 0b1;
32885 let Inst{31-21} = 0b00011001100;
32886 let hasNewValue = 1;
32887 let opNewValue = 0;
32888 let isAccumulator = 1;
32889 let DecoderNamespace = "EXT_mmvec";
32890 let Constraints = "$Vxx32 = $Vxx32in";
32892 def V6_vmpauhb_acc_alt : HInst<
32893 (outs HvxWR:$Vxx32),
32894 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32895 "$Vxx32 += vmpauhb($Vuu32,$Rt32)",
32896 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32897 let hasNewValue = 1;
32898 let opNewValue = 0;
32899 let isAccumulator = 1;
32901 let isCodeGenOnly = 1;
32902 let DecoderNamespace = "EXT_mmvec";
32903 let Constraints = "$Vxx32 = $Vxx32in";
32905 def V6_vmpauhb_alt : HInst<
32906 (outs HvxWR:$Vdd32),
32907 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
32908 "$Vdd32 = vmpauhb($Vuu32,$Rt32)",
32909 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32910 let hasNewValue = 1;
32911 let opNewValue = 0;
32913 let isCodeGenOnly = 1;
32914 let DecoderNamespace = "EXT_mmvec";
32916 def V6_vmpauhuhsat : HInst<
32917 (outs HvxVR:$Vx32),
32918 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
32919 "$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
32920 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
32921 let Inst{7-5} = 0b101;
32922 let Inst{13-13} = 0b1;
32923 let Inst{31-21} = 0b00011001100;
32924 let hasNewValue = 1;
32925 let opNewValue = 0;
32926 let DecoderNamespace = "EXT_mmvec";
32927 let Constraints = "$Vx32 = $Vx32in";
32929 def V6_vmpsuhuhsat : HInst<
32930 (outs HvxVR:$Vx32),
32931 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
32932 "$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
32933 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
32934 let Inst{7-5} = 0b110;
32935 let Inst{13-13} = 0b1;
32936 let Inst{31-21} = 0b00011001100;
32937 let hasNewValue = 1;
32938 let opNewValue = 0;
32939 let DecoderNamespace = "EXT_mmvec";
32940 let Constraints = "$Vx32 = $Vx32in";
32942 def V6_vmpybus : HInst<
32943 (outs HvxWR:$Vdd32),
32944 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32945 "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
32946 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
32947 let Inst{7-5} = 0b101;
32948 let Inst{13-13} = 0b0;
32949 let Inst{31-21} = 0b00011001001;
32950 let hasNewValue = 1;
32951 let opNewValue = 0;
32952 let DecoderNamespace = "EXT_mmvec";
32954 def V6_vmpybus_acc : HInst<
32955 (outs HvxWR:$Vxx32),
32956 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32957 "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
32958 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
32959 let Inst{7-5} = 0b101;
32960 let Inst{13-13} = 0b1;
32961 let Inst{31-21} = 0b00011001001;
32962 let hasNewValue = 1;
32963 let opNewValue = 0;
32964 let isAccumulator = 1;
32965 let DecoderNamespace = "EXT_mmvec";
32966 let Constraints = "$Vxx32 = $Vxx32in";
32968 def V6_vmpybus_acc_alt : HInst<
32969 (outs HvxWR:$Vxx32),
32970 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32971 "$Vxx32 += vmpybus($Vu32,$Rt32)",
32972 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32973 let hasNewValue = 1;
32974 let opNewValue = 0;
32975 let isAccumulator = 1;
32977 let isCodeGenOnly = 1;
32978 let DecoderNamespace = "EXT_mmvec";
32979 let Constraints = "$Vxx32 = $Vxx32in";
32981 def V6_vmpybus_alt : HInst<
32982 (outs HvxWR:$Vdd32),
32983 (ins HvxVR:$Vu32, IntRegs:$Rt32),
32984 "$Vdd32 = vmpybus($Vu32,$Rt32)",
32985 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32986 let hasNewValue = 1;
32987 let opNewValue = 0;
32989 let isCodeGenOnly = 1;
32990 let DecoderNamespace = "EXT_mmvec";
32992 def V6_vmpybusv : HInst<
32993 (outs HvxWR:$Vdd32),
32994 (ins HvxVR:$Vu32, HvxVR:$Vv32),
32995 "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
32996 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
32997 let Inst{7-5} = 0b110;
32998 let Inst{13-13} = 0b0;
32999 let Inst{31-21} = 0b00011100000;
33000 let hasNewValue = 1;
33001 let opNewValue = 0;
33002 let DecoderNamespace = "EXT_mmvec";
33004 def V6_vmpybusv_acc : HInst<
33005 (outs HvxWR:$Vxx32),
33006 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33007 "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
33008 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33009 let Inst{7-5} = 0b110;
33010 let Inst{13-13} = 0b1;
33011 let Inst{31-21} = 0b00011100000;
33012 let hasNewValue = 1;
33013 let opNewValue = 0;
33014 let isAccumulator = 1;
33015 let DecoderNamespace = "EXT_mmvec";
33016 let Constraints = "$Vxx32 = $Vxx32in";
33018 def V6_vmpybusv_acc_alt : HInst<
33019 (outs HvxWR:$Vxx32),
33020 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33021 "$Vxx32 += vmpybus($Vu32,$Vv32)",
33022 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33023 let hasNewValue = 1;
33024 let opNewValue = 0;
33025 let isAccumulator = 1;
33027 let isCodeGenOnly = 1;
33028 let DecoderNamespace = "EXT_mmvec";
33029 let Constraints = "$Vxx32 = $Vxx32in";
33031 def V6_vmpybusv_alt : HInst<
33032 (outs HvxWR:$Vdd32),
33033 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33034 "$Vdd32 = vmpybus($Vu32,$Vv32)",
33035 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33036 let hasNewValue = 1;
33037 let opNewValue = 0;
33039 let isCodeGenOnly = 1;
33040 let DecoderNamespace = "EXT_mmvec";
33042 def V6_vmpybv : HInst<
33043 (outs HvxWR:$Vdd32),
33044 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33045 "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
33046 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33047 let Inst{7-5} = 0b100;
33048 let Inst{13-13} = 0b0;
33049 let Inst{31-21} = 0b00011100000;
33050 let hasNewValue = 1;
33051 let opNewValue = 0;
33052 let DecoderNamespace = "EXT_mmvec";
33054 def V6_vmpybv_acc : HInst<
33055 (outs HvxWR:$Vxx32),
33056 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33057 "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
33058 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33059 let Inst{7-5} = 0b100;
33060 let Inst{13-13} = 0b1;
33061 let Inst{31-21} = 0b00011100000;
33062 let hasNewValue = 1;
33063 let opNewValue = 0;
33064 let isAccumulator = 1;
33065 let DecoderNamespace = "EXT_mmvec";
33066 let Constraints = "$Vxx32 = $Vxx32in";
33068 def V6_vmpybv_acc_alt : HInst<
33069 (outs HvxWR:$Vxx32),
33070 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33071 "$Vxx32 += vmpyb($Vu32,$Vv32)",
33072 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33073 let hasNewValue = 1;
33074 let opNewValue = 0;
33075 let isAccumulator = 1;
33077 let isCodeGenOnly = 1;
33078 let DecoderNamespace = "EXT_mmvec";
33079 let Constraints = "$Vxx32 = $Vxx32in";
33081 def V6_vmpybv_alt : HInst<
33082 (outs HvxWR:$Vdd32),
33083 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33084 "$Vdd32 = vmpyb($Vu32,$Vv32)",
33085 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33086 let hasNewValue = 1;
33087 let opNewValue = 0;
33089 let isCodeGenOnly = 1;
33090 let DecoderNamespace = "EXT_mmvec";
33092 def V6_vmpyewuh : HInst<
33093 (outs HvxVR:$Vd32),
33094 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33095 "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
33096 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33097 let Inst{7-5} = 0b101;
33098 let Inst{13-13} = 0b0;
33099 let Inst{31-21} = 0b00011111111;
33100 let hasNewValue = 1;
33101 let opNewValue = 0;
33102 let DecoderNamespace = "EXT_mmvec";
33104 def V6_vmpyewuh_64 : HInst<
33105 (outs HvxWR:$Vdd32),
33106 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33107 "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
33108 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
33109 let Inst{7-5} = 0b110;
33110 let Inst{13-13} = 0b0;
33111 let Inst{31-21} = 0b00011110101;
33112 let hasNewValue = 1;
33113 let opNewValue = 0;
33114 let DecoderNamespace = "EXT_mmvec";
33116 def V6_vmpyewuh_alt : HInst<
33117 (outs HvxVR:$Vd32),
33118 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33119 "$Vd32 = vmpyewuh($Vu32,$Vv32)",
33120 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33121 let hasNewValue = 1;
33122 let opNewValue = 0;
33124 let isCodeGenOnly = 1;
33125 let DecoderNamespace = "EXT_mmvec";
33127 def V6_vmpyh : HInst<
33128 (outs HvxWR:$Vdd32),
33129 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33130 "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
33131 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33132 let Inst{7-5} = 0b000;
33133 let Inst{13-13} = 0b0;
33134 let Inst{31-21} = 0b00011001010;
33135 let hasNewValue = 1;
33136 let opNewValue = 0;
33137 let DecoderNamespace = "EXT_mmvec";
33139 def V6_vmpyh_acc : HInst<
33140 (outs HvxWR:$Vxx32),
33141 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33142 "$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
33143 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
33144 let Inst{7-5} = 0b110;
33145 let Inst{13-13} = 0b1;
33146 let Inst{31-21} = 0b00011001101;
33147 let hasNewValue = 1;
33148 let opNewValue = 0;
33149 let isAccumulator = 1;
33150 let DecoderNamespace = "EXT_mmvec";
33151 let Constraints = "$Vxx32 = $Vxx32in";
33153 def V6_vmpyh_acc_alt : HInst<
33154 (outs HvxWR:$Vxx32),
33155 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33156 "$Vxx32 += vmpyh($Vu32,$Rt32)",
33157 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33158 let hasNewValue = 1;
33159 let opNewValue = 0;
33160 let isAccumulator = 1;
33162 let isCodeGenOnly = 1;
33163 let DecoderNamespace = "EXT_mmvec";
33164 let Constraints = "$Vxx32 = $Vxx32in";
33166 def V6_vmpyh_alt : HInst<
33167 (outs HvxWR:$Vdd32),
33168 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33169 "$Vdd32 = vmpyh($Vu32,$Rt32)",
33170 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33171 let hasNewValue = 1;
33172 let opNewValue = 0;
33174 let isCodeGenOnly = 1;
33175 let DecoderNamespace = "EXT_mmvec";
33177 def V6_vmpyhsat_acc : HInst<
33178 (outs HvxWR:$Vxx32),
33179 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33180 "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
33181 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33182 let Inst{7-5} = 0b000;
33183 let Inst{13-13} = 0b1;
33184 let Inst{31-21} = 0b00011001010;
33185 let hasNewValue = 1;
33186 let opNewValue = 0;
33187 let isAccumulator = 1;
33188 let DecoderNamespace = "EXT_mmvec";
33189 let Constraints = "$Vxx32 = $Vxx32in";
33191 def V6_vmpyhsat_acc_alt : HInst<
33192 (outs HvxWR:$Vxx32),
33193 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33194 "$Vxx32 += vmpyh($Vu32,$Rt32):sat",
33195 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33196 let hasNewValue = 1;
33197 let opNewValue = 0;
33198 let isAccumulator = 1;
33200 let isCodeGenOnly = 1;
33201 let DecoderNamespace = "EXT_mmvec";
33202 let Constraints = "$Vxx32 = $Vxx32in";
33204 def V6_vmpyhsrs : HInst<
33205 (outs HvxVR:$Vd32),
33206 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33207 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
33208 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33209 let Inst{7-5} = 0b010;
33210 let Inst{13-13} = 0b0;
33211 let Inst{31-21} = 0b00011001010;
33212 let hasNewValue = 1;
33213 let opNewValue = 0;
33214 let DecoderNamespace = "EXT_mmvec";
33216 def V6_vmpyhsrs_alt : HInst<
33217 (outs HvxVR:$Vd32),
33218 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33219 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
33220 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33221 let hasNewValue = 1;
33222 let opNewValue = 0;
33224 let isCodeGenOnly = 1;
33225 let DecoderNamespace = "EXT_mmvec";
33227 def V6_vmpyhss : HInst<
33228 (outs HvxVR:$Vd32),
33229 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33230 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
33231 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33232 let Inst{7-5} = 0b001;
33233 let Inst{13-13} = 0b0;
33234 let Inst{31-21} = 0b00011001010;
33235 let hasNewValue = 1;
33236 let opNewValue = 0;
33237 let DecoderNamespace = "EXT_mmvec";
33239 def V6_vmpyhss_alt : HInst<
33240 (outs HvxVR:$Vd32),
33241 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33242 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
33243 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33244 let hasNewValue = 1;
33245 let opNewValue = 0;
33247 let isCodeGenOnly = 1;
33248 let DecoderNamespace = "EXT_mmvec";
33250 def V6_vmpyhus : HInst<
33251 (outs HvxWR:$Vdd32),
33252 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33253 "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
33254 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33255 let Inst{7-5} = 0b010;
33256 let Inst{13-13} = 0b0;
33257 let Inst{31-21} = 0b00011100001;
33258 let hasNewValue = 1;
33259 let opNewValue = 0;
33260 let DecoderNamespace = "EXT_mmvec";
33262 def V6_vmpyhus_acc : HInst<
33263 (outs HvxWR:$Vxx32),
33264 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33265 "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
33266 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33267 let Inst{7-5} = 0b001;
33268 let Inst{13-13} = 0b1;
33269 let Inst{31-21} = 0b00011100001;
33270 let hasNewValue = 1;
33271 let opNewValue = 0;
33272 let isAccumulator = 1;
33273 let DecoderNamespace = "EXT_mmvec";
33274 let Constraints = "$Vxx32 = $Vxx32in";
33276 def V6_vmpyhus_acc_alt : HInst<
33277 (outs HvxWR:$Vxx32),
33278 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33279 "$Vxx32 += vmpyhus($Vu32,$Vv32)",
33280 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33281 let hasNewValue = 1;
33282 let opNewValue = 0;
33283 let isAccumulator = 1;
33285 let isCodeGenOnly = 1;
33286 let DecoderNamespace = "EXT_mmvec";
33287 let Constraints = "$Vxx32 = $Vxx32in";
33289 def V6_vmpyhus_alt : HInst<
33290 (outs HvxWR:$Vdd32),
33291 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33292 "$Vdd32 = vmpyhus($Vu32,$Vv32)",
33293 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33294 let hasNewValue = 1;
33295 let opNewValue = 0;
33297 let isCodeGenOnly = 1;
33298 let DecoderNamespace = "EXT_mmvec";
33300 def V6_vmpyhv : HInst<
33301 (outs HvxWR:$Vdd32),
33302 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33303 "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
33304 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33305 let Inst{7-5} = 0b111;
33306 let Inst{13-13} = 0b0;
33307 let Inst{31-21} = 0b00011100000;
33308 let hasNewValue = 1;
33309 let opNewValue = 0;
33310 let DecoderNamespace = "EXT_mmvec";
33312 def V6_vmpyhv_acc : HInst<
33313 (outs HvxWR:$Vxx32),
33314 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33315 "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
33316 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33317 let Inst{7-5} = 0b111;
33318 let Inst{13-13} = 0b1;
33319 let Inst{31-21} = 0b00011100000;
33320 let hasNewValue = 1;
33321 let opNewValue = 0;
33322 let isAccumulator = 1;
33323 let DecoderNamespace = "EXT_mmvec";
33324 let Constraints = "$Vxx32 = $Vxx32in";
33326 def V6_vmpyhv_acc_alt : HInst<
33327 (outs HvxWR:$Vxx32),
33328 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33329 "$Vxx32 += vmpyh($Vu32,$Vv32)",
33330 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33331 let hasNewValue = 1;
33332 let opNewValue = 0;
33333 let isAccumulator = 1;
33335 let isCodeGenOnly = 1;
33336 let DecoderNamespace = "EXT_mmvec";
33337 let Constraints = "$Vxx32 = $Vxx32in";
33339 def V6_vmpyhv_alt : HInst<
33340 (outs HvxWR:$Vdd32),
33341 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33342 "$Vdd32 = vmpyh($Vu32,$Vv32)",
33343 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33344 let hasNewValue = 1;
33345 let opNewValue = 0;
33347 let isCodeGenOnly = 1;
33348 let DecoderNamespace = "EXT_mmvec";
33350 def V6_vmpyhvsrs : HInst<
33351 (outs HvxVR:$Vd32),
33352 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33353 "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
33354 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33355 let Inst{7-5} = 0b001;
33356 let Inst{13-13} = 0b0;
33357 let Inst{31-21} = 0b00011100001;
33358 let hasNewValue = 1;
33359 let opNewValue = 0;
33360 let DecoderNamespace = "EXT_mmvec";
33362 def V6_vmpyhvsrs_alt : HInst<
33363 (outs HvxVR:$Vd32),
33364 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33365 "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
33366 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33367 let hasNewValue = 1;
33368 let opNewValue = 0;
33370 let isCodeGenOnly = 1;
33371 let DecoderNamespace = "EXT_mmvec";
33373 def V6_vmpyieoh : HInst<
33374 (outs HvxVR:$Vd32),
33375 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33376 "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
33377 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
33378 let Inst{7-5} = 0b000;
33379 let Inst{13-13} = 0b0;
33380 let Inst{31-21} = 0b00011111011;
33381 let hasNewValue = 1;
33382 let opNewValue = 0;
33383 let DecoderNamespace = "EXT_mmvec";
33385 def V6_vmpyiewh_acc : HInst<
33386 (outs HvxVR:$Vx32),
33387 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33388 "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
33389 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33390 let Inst{7-5} = 0b000;
33391 let Inst{13-13} = 0b1;
33392 let Inst{31-21} = 0b00011100010;
33393 let hasNewValue = 1;
33394 let opNewValue = 0;
33395 let isAccumulator = 1;
33396 let DecoderNamespace = "EXT_mmvec";
33397 let Constraints = "$Vx32 = $Vx32in";
33399 def V6_vmpyiewh_acc_alt : HInst<
33400 (outs HvxVR:$Vx32),
33401 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33402 "$Vx32 += vmpyiewh($Vu32,$Vv32)",
33403 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33404 let hasNewValue = 1;
33405 let opNewValue = 0;
33406 let isAccumulator = 1;
33408 let isCodeGenOnly = 1;
33409 let DecoderNamespace = "EXT_mmvec";
33410 let Constraints = "$Vx32 = $Vx32in";
33412 def V6_vmpyiewuh : HInst<
33413 (outs HvxVR:$Vd32),
33414 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33415 "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
33416 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33417 let Inst{7-5} = 0b000;
33418 let Inst{13-13} = 0b0;
33419 let Inst{31-21} = 0b00011111110;
33420 let hasNewValue = 1;
33421 let opNewValue = 0;
33422 let DecoderNamespace = "EXT_mmvec";
33424 def V6_vmpyiewuh_acc : HInst<
33425 (outs HvxVR:$Vx32),
33426 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33427 "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
33428 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33429 let Inst{7-5} = 0b101;
33430 let Inst{13-13} = 0b1;
33431 let Inst{31-21} = 0b00011100001;
33432 let hasNewValue = 1;
33433 let opNewValue = 0;
33434 let isAccumulator = 1;
33435 let DecoderNamespace = "EXT_mmvec";
33436 let Constraints = "$Vx32 = $Vx32in";
33438 def V6_vmpyiewuh_acc_alt : HInst<
33439 (outs HvxVR:$Vx32),
33440 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33441 "$Vx32 += vmpyiewuh($Vu32,$Vv32)",
33442 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33443 let hasNewValue = 1;
33444 let opNewValue = 0;
33445 let isAccumulator = 1;
33447 let isCodeGenOnly = 1;
33448 let DecoderNamespace = "EXT_mmvec";
33449 let Constraints = "$Vx32 = $Vx32in";
33451 def V6_vmpyiewuh_alt : HInst<
33452 (outs HvxVR:$Vd32),
33453 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33454 "$Vd32 = vmpyiewuh($Vu32,$Vv32)",
33455 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33456 let hasNewValue = 1;
33457 let opNewValue = 0;
33459 let isCodeGenOnly = 1;
33460 let DecoderNamespace = "EXT_mmvec";
33462 def V6_vmpyih : HInst<
33463 (outs HvxVR:$Vd32),
33464 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33465 "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
33466 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33467 let Inst{7-5} = 0b100;
33468 let Inst{13-13} = 0b0;
33469 let Inst{31-21} = 0b00011100001;
33470 let hasNewValue = 1;
33471 let opNewValue = 0;
33472 let DecoderNamespace = "EXT_mmvec";
33474 def V6_vmpyih_acc : HInst<
33475 (outs HvxVR:$Vx32),
33476 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33477 "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
33478 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33479 let Inst{7-5} = 0b100;
33480 let Inst{13-13} = 0b1;
33481 let Inst{31-21} = 0b00011100001;
33482 let hasNewValue = 1;
33483 let opNewValue = 0;
33484 let isAccumulator = 1;
33485 let DecoderNamespace = "EXT_mmvec";
33486 let Constraints = "$Vx32 = $Vx32in";
33488 def V6_vmpyih_acc_alt : HInst<
33489 (outs HvxVR:$Vx32),
33490 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33491 "$Vx32 += vmpyih($Vu32,$Vv32)",
33492 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33493 let hasNewValue = 1;
33494 let opNewValue = 0;
33495 let isAccumulator = 1;
33497 let isCodeGenOnly = 1;
33498 let DecoderNamespace = "EXT_mmvec";
33499 let Constraints = "$Vx32 = $Vx32in";
33501 def V6_vmpyih_alt : HInst<
33502 (outs HvxVR:$Vd32),
33503 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33504 "$Vd32 = vmpyih($Vu32,$Vv32)",
33505 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33506 let hasNewValue = 1;
33507 let opNewValue = 0;
33509 let isCodeGenOnly = 1;
33510 let DecoderNamespace = "EXT_mmvec";
33512 def V6_vmpyihb : HInst<
33513 (outs HvxVR:$Vd32),
33514 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33515 "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
33516 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33517 let Inst{7-5} = 0b000;
33518 let Inst{13-13} = 0b0;
33519 let Inst{31-21} = 0b00011001011;
33520 let hasNewValue = 1;
33521 let opNewValue = 0;
33522 let DecoderNamespace = "EXT_mmvec";
33524 def V6_vmpyihb_acc : HInst<
33525 (outs HvxVR:$Vx32),
33526 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33527 "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
33528 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33529 let Inst{7-5} = 0b001;
33530 let Inst{13-13} = 0b1;
33531 let Inst{31-21} = 0b00011001011;
33532 let hasNewValue = 1;
33533 let opNewValue = 0;
33534 let isAccumulator = 1;
33535 let DecoderNamespace = "EXT_mmvec";
33536 let Constraints = "$Vx32 = $Vx32in";
33538 def V6_vmpyihb_acc_alt : HInst<
33539 (outs HvxVR:$Vx32),
33540 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33541 "$Vx32 += vmpyihb($Vu32,$Rt32)",
33542 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33543 let hasNewValue = 1;
33544 let opNewValue = 0;
33545 let isAccumulator = 1;
33547 let isCodeGenOnly = 1;
33548 let DecoderNamespace = "EXT_mmvec";
33549 let Constraints = "$Vx32 = $Vx32in";
33551 def V6_vmpyihb_alt : HInst<
33552 (outs HvxVR:$Vd32),
33553 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33554 "$Vd32 = vmpyihb($Vu32,$Rt32)",
33555 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33556 let hasNewValue = 1;
33557 let opNewValue = 0;
33559 let isCodeGenOnly = 1;
33560 let DecoderNamespace = "EXT_mmvec";
33562 def V6_vmpyiowh : HInst<
33563 (outs HvxVR:$Vd32),
33564 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33565 "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
33566 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33567 let Inst{7-5} = 0b001;
33568 let Inst{13-13} = 0b0;
33569 let Inst{31-21} = 0b00011111110;
33570 let hasNewValue = 1;
33571 let opNewValue = 0;
33572 let DecoderNamespace = "EXT_mmvec";
33574 def V6_vmpyiowh_alt : HInst<
33575 (outs HvxVR:$Vd32),
33576 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33577 "$Vd32 = vmpyiowh($Vu32,$Vv32)",
33578 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33579 let hasNewValue = 1;
33580 let opNewValue = 0;
33582 let isCodeGenOnly = 1;
33583 let DecoderNamespace = "EXT_mmvec";
33585 def V6_vmpyiwb : HInst<
33586 (outs HvxVR:$Vd32),
33587 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33588 "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
33589 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33590 let Inst{7-5} = 0b000;
33591 let Inst{13-13} = 0b0;
33592 let Inst{31-21} = 0b00011001101;
33593 let hasNewValue = 1;
33594 let opNewValue = 0;
33595 let DecoderNamespace = "EXT_mmvec";
33597 def V6_vmpyiwb_acc : HInst<
33598 (outs HvxVR:$Vx32),
33599 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33600 "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
33601 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33602 let Inst{7-5} = 0b010;
33603 let Inst{13-13} = 0b1;
33604 let Inst{31-21} = 0b00011001010;
33605 let hasNewValue = 1;
33606 let opNewValue = 0;
33607 let isAccumulator = 1;
33608 let DecoderNamespace = "EXT_mmvec";
33609 let Constraints = "$Vx32 = $Vx32in";
33611 def V6_vmpyiwb_acc_alt : HInst<
33612 (outs HvxVR:$Vx32),
33613 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33614 "$Vx32 += vmpyiwb($Vu32,$Rt32)",
33615 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33616 let hasNewValue = 1;
33617 let opNewValue = 0;
33618 let isAccumulator = 1;
33620 let isCodeGenOnly = 1;
33621 let DecoderNamespace = "EXT_mmvec";
33622 let Constraints = "$Vx32 = $Vx32in";
33624 def V6_vmpyiwb_alt : HInst<
33625 (outs HvxVR:$Vd32),
33626 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33627 "$Vd32 = vmpyiwb($Vu32,$Rt32)",
33628 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33629 let hasNewValue = 1;
33630 let opNewValue = 0;
33632 let isCodeGenOnly = 1;
33633 let DecoderNamespace = "EXT_mmvec";
33635 def V6_vmpyiwh : HInst<
33636 (outs HvxVR:$Vd32),
33637 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33638 "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
33639 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33640 let Inst{7-5} = 0b111;
33641 let Inst{13-13} = 0b0;
33642 let Inst{31-21} = 0b00011001100;
33643 let hasNewValue = 1;
33644 let opNewValue = 0;
33645 let DecoderNamespace = "EXT_mmvec";
33647 def V6_vmpyiwh_acc : HInst<
33648 (outs HvxVR:$Vx32),
33649 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33650 "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
33651 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
33652 let Inst{7-5} = 0b011;
33653 let Inst{13-13} = 0b1;
33654 let Inst{31-21} = 0b00011001010;
33655 let hasNewValue = 1;
33656 let opNewValue = 0;
33657 let isAccumulator = 1;
33658 let DecoderNamespace = "EXT_mmvec";
33659 let Constraints = "$Vx32 = $Vx32in";
33661 def V6_vmpyiwh_acc_alt : HInst<
33662 (outs HvxVR:$Vx32),
33663 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33664 "$Vx32 += vmpyiwh($Vu32,$Rt32)",
33665 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33666 let hasNewValue = 1;
33667 let opNewValue = 0;
33668 let isAccumulator = 1;
33670 let isCodeGenOnly = 1;
33671 let DecoderNamespace = "EXT_mmvec";
33672 let Constraints = "$Vx32 = $Vx32in";
33674 def V6_vmpyiwh_alt : HInst<
33675 (outs HvxVR:$Vd32),
33676 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33677 "$Vd32 = vmpyiwh($Vu32,$Rt32)",
33678 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33679 let hasNewValue = 1;
33680 let opNewValue = 0;
33682 let isCodeGenOnly = 1;
33683 let DecoderNamespace = "EXT_mmvec";
33685 def V6_vmpyiwub : HInst<
33686 (outs HvxVR:$Vd32),
33687 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33688 "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
33689 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
33690 let Inst{7-5} = 0b110;
33691 let Inst{13-13} = 0b0;
33692 let Inst{31-21} = 0b00011001100;
33693 let hasNewValue = 1;
33694 let opNewValue = 0;
33695 let DecoderNamespace = "EXT_mmvec";
33697 def V6_vmpyiwub_acc : HInst<
33698 (outs HvxVR:$Vx32),
33699 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33700 "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
33701 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
33702 let Inst{7-5} = 0b001;
33703 let Inst{13-13} = 0b1;
33704 let Inst{31-21} = 0b00011001100;
33705 let hasNewValue = 1;
33706 let opNewValue = 0;
33707 let isAccumulator = 1;
33708 let DecoderNamespace = "EXT_mmvec";
33709 let Constraints = "$Vx32 = $Vx32in";
33711 def V6_vmpyiwub_acc_alt : HInst<
33712 (outs HvxVR:$Vx32),
33713 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33714 "$Vx32 += vmpyiwub($Vu32,$Rt32)",
33715 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33716 let hasNewValue = 1;
33717 let opNewValue = 0;
33718 let isAccumulator = 1;
33720 let isCodeGenOnly = 1;
33721 let DecoderNamespace = "EXT_mmvec";
33722 let Constraints = "$Vx32 = $Vx32in";
33724 def V6_vmpyiwub_alt : HInst<
33725 (outs HvxVR:$Vd32),
33726 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33727 "$Vd32 = vmpyiwub($Vu32,$Rt32)",
33728 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33729 let hasNewValue = 1;
33730 let opNewValue = 0;
33732 let isCodeGenOnly = 1;
33733 let DecoderNamespace = "EXT_mmvec";
33735 def V6_vmpyowh : HInst<
33736 (outs HvxVR:$Vd32),
33737 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33738 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
33739 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33740 let Inst{7-5} = 0b111;
33741 let Inst{13-13} = 0b0;
33742 let Inst{31-21} = 0b00011111111;
33743 let hasNewValue = 1;
33744 let opNewValue = 0;
33745 let DecoderNamespace = "EXT_mmvec";
33747 def V6_vmpyowh_64_acc : HInst<
33748 (outs HvxWR:$Vxx32),
33749 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33750 "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
33751 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
33752 let Inst{7-5} = 0b011;
33753 let Inst{13-13} = 0b1;
33754 let Inst{31-21} = 0b00011100001;
33755 let hasNewValue = 1;
33756 let opNewValue = 0;
33757 let isAccumulator = 1;
33758 let DecoderNamespace = "EXT_mmvec";
33759 let Constraints = "$Vxx32 = $Vxx32in";
33761 def V6_vmpyowh_alt : HInst<
33762 (outs HvxVR:$Vd32),
33763 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33764 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
33765 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33766 let hasNewValue = 1;
33767 let opNewValue = 0;
33769 let isCodeGenOnly = 1;
33770 let DecoderNamespace = "EXT_mmvec";
33772 def V6_vmpyowh_rnd : HInst<
33773 (outs HvxVR:$Vd32),
33774 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33775 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
33776 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33777 let Inst{7-5} = 0b000;
33778 let Inst{13-13} = 0b0;
33779 let Inst{31-21} = 0b00011111010;
33780 let hasNewValue = 1;
33781 let opNewValue = 0;
33782 let DecoderNamespace = "EXT_mmvec";
33784 def V6_vmpyowh_rnd_alt : HInst<
33785 (outs HvxVR:$Vd32),
33786 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33787 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
33788 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33789 let hasNewValue = 1;
33790 let opNewValue = 0;
33792 let isCodeGenOnly = 1;
33793 let DecoderNamespace = "EXT_mmvec";
33795 def V6_vmpyowh_rnd_sacc : HInst<
33796 (outs HvxVR:$Vx32),
33797 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33798 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
33799 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33800 let Inst{7-5} = 0b111;
33801 let Inst{13-13} = 0b1;
33802 let Inst{31-21} = 0b00011100001;
33803 let hasNewValue = 1;
33804 let opNewValue = 0;
33805 let isAccumulator = 1;
33806 let DecoderNamespace = "EXT_mmvec";
33807 let Constraints = "$Vx32 = $Vx32in";
33809 def V6_vmpyowh_rnd_sacc_alt : HInst<
33810 (outs HvxVR:$Vx32),
33811 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33812 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
33813 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33814 let hasNewValue = 1;
33815 let opNewValue = 0;
33816 let isAccumulator = 1;
33818 let DecoderNamespace = "EXT_mmvec";
33819 let Constraints = "$Vx32 = $Vx32in";
33821 def V6_vmpyowh_sacc : HInst<
33822 (outs HvxVR:$Vx32),
33823 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33824 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
33825 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33826 let Inst{7-5} = 0b110;
33827 let Inst{13-13} = 0b1;
33828 let Inst{31-21} = 0b00011100001;
33829 let hasNewValue = 1;
33830 let opNewValue = 0;
33831 let isAccumulator = 1;
33832 let DecoderNamespace = "EXT_mmvec";
33833 let Constraints = "$Vx32 = $Vx32in";
33835 def V6_vmpyowh_sacc_alt : HInst<
33836 (outs HvxVR:$Vx32),
33837 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33838 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
33839 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33840 let hasNewValue = 1;
33841 let opNewValue = 0;
33842 let isAccumulator = 1;
33844 let DecoderNamespace = "EXT_mmvec";
33845 let Constraints = "$Vx32 = $Vx32in";
33847 def V6_vmpyub : HInst<
33848 (outs HvxWR:$Vdd32),
33849 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33850 "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
33851 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33852 let Inst{7-5} = 0b000;
33853 let Inst{13-13} = 0b0;
33854 let Inst{31-21} = 0b00011001110;
33855 let hasNewValue = 1;
33856 let opNewValue = 0;
33857 let DecoderNamespace = "EXT_mmvec";
33859 def V6_vmpyub_acc : HInst<
33860 (outs HvxWR:$Vxx32),
33861 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33862 "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
33863 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33864 let Inst{7-5} = 0b000;
33865 let Inst{13-13} = 0b1;
33866 let Inst{31-21} = 0b00011001100;
33867 let hasNewValue = 1;
33868 let opNewValue = 0;
33869 let isAccumulator = 1;
33870 let DecoderNamespace = "EXT_mmvec";
33871 let Constraints = "$Vxx32 = $Vxx32in";
33873 def V6_vmpyub_acc_alt : HInst<
33874 (outs HvxWR:$Vxx32),
33875 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33876 "$Vxx32 += vmpyub($Vu32,$Rt32)",
33877 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33878 let hasNewValue = 1;
33879 let opNewValue = 0;
33880 let isAccumulator = 1;
33882 let isCodeGenOnly = 1;
33883 let DecoderNamespace = "EXT_mmvec";
33884 let Constraints = "$Vxx32 = $Vxx32in";
33886 def V6_vmpyub_alt : HInst<
33887 (outs HvxWR:$Vdd32),
33888 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33889 "$Vdd32 = vmpyub($Vu32,$Rt32)",
33890 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33891 let hasNewValue = 1;
33892 let opNewValue = 0;
33894 let isCodeGenOnly = 1;
33895 let DecoderNamespace = "EXT_mmvec";
33897 def V6_vmpyubv : HInst<
33898 (outs HvxWR:$Vdd32),
33899 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33900 "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
33901 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33902 let Inst{7-5} = 0b101;
33903 let Inst{13-13} = 0b0;
33904 let Inst{31-21} = 0b00011100000;
33905 let hasNewValue = 1;
33906 let opNewValue = 0;
33907 let DecoderNamespace = "EXT_mmvec";
33909 def V6_vmpyubv_acc : HInst<
33910 (outs HvxWR:$Vxx32),
33911 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33912 "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
33913 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33914 let Inst{7-5} = 0b101;
33915 let Inst{13-13} = 0b1;
33916 let Inst{31-21} = 0b00011100000;
33917 let hasNewValue = 1;
33918 let opNewValue = 0;
33919 let isAccumulator = 1;
33920 let DecoderNamespace = "EXT_mmvec";
33921 let Constraints = "$Vxx32 = $Vxx32in";
33923 def V6_vmpyubv_acc_alt : HInst<
33924 (outs HvxWR:$Vxx32),
33925 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33926 "$Vxx32 += vmpyub($Vu32,$Vv32)",
33927 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33928 let hasNewValue = 1;
33929 let opNewValue = 0;
33930 let isAccumulator = 1;
33932 let isCodeGenOnly = 1;
33933 let DecoderNamespace = "EXT_mmvec";
33934 let Constraints = "$Vxx32 = $Vxx32in";
33936 def V6_vmpyubv_alt : HInst<
33937 (outs HvxWR:$Vdd32),
33938 (ins HvxVR:$Vu32, HvxVR:$Vv32),
33939 "$Vdd32 = vmpyub($Vu32,$Vv32)",
33940 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33941 let hasNewValue = 1;
33942 let opNewValue = 0;
33944 let isCodeGenOnly = 1;
33945 let DecoderNamespace = "EXT_mmvec";
33947 def V6_vmpyuh : HInst<
33948 (outs HvxWR:$Vdd32),
33949 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33950 "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
33951 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33952 let Inst{7-5} = 0b011;
33953 let Inst{13-13} = 0b0;
33954 let Inst{31-21} = 0b00011001010;
33955 let hasNewValue = 1;
33956 let opNewValue = 0;
33957 let DecoderNamespace = "EXT_mmvec";
33959 def V6_vmpyuh_acc : HInst<
33960 (outs HvxWR:$Vxx32),
33961 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33962 "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
33963 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33964 let Inst{7-5} = 0b001;
33965 let Inst{13-13} = 0b1;
33966 let Inst{31-21} = 0b00011001010;
33967 let hasNewValue = 1;
33968 let opNewValue = 0;
33969 let isAccumulator = 1;
33970 let DecoderNamespace = "EXT_mmvec";
33971 let Constraints = "$Vxx32 = $Vxx32in";
33973 def V6_vmpyuh_acc_alt : HInst<
33974 (outs HvxWR:$Vxx32),
33975 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33976 "$Vxx32 += vmpyuh($Vu32,$Rt32)",
33977 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33978 let hasNewValue = 1;
33979 let opNewValue = 0;
33980 let isAccumulator = 1;
33982 let isCodeGenOnly = 1;
33983 let DecoderNamespace = "EXT_mmvec";
33984 let Constraints = "$Vxx32 = $Vxx32in";
33986 def V6_vmpyuh_alt : HInst<
33987 (outs HvxWR:$Vdd32),
33988 (ins HvxVR:$Vu32, IntRegs:$Rt32),
33989 "$Vdd32 = vmpyuh($Vu32,$Rt32)",
33990 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33991 let hasNewValue = 1;
33992 let opNewValue = 0;
33994 let isCodeGenOnly = 1;
33995 let DecoderNamespace = "EXT_mmvec";
33997 def V6_vmpyuhe : HInst<
33998 (outs HvxVR:$Vd32),
33999 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34000 "$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
34001 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
34002 let Inst{7-5} = 0b010;
34003 let Inst{13-13} = 0b0;
34004 let Inst{31-21} = 0b00011001011;
34005 let hasNewValue = 1;
34006 let opNewValue = 0;
34007 let DecoderNamespace = "EXT_mmvec";
34009 def V6_vmpyuhe_acc : HInst<
34010 (outs HvxVR:$Vx32),
34011 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34012 "$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
34013 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
34014 let Inst{7-5} = 0b011;
34015 let Inst{13-13} = 0b1;
34016 let Inst{31-21} = 0b00011001100;
34017 let hasNewValue = 1;
34018 let opNewValue = 0;
34019 let isAccumulator = 1;
34020 let DecoderNamespace = "EXT_mmvec";
34021 let Constraints = "$Vx32 = $Vx32in";
34023 def V6_vmpyuhv : HInst<
34024 (outs HvxWR:$Vdd32),
34025 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34026 "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
34027 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34028 let Inst{7-5} = 0b000;
34029 let Inst{13-13} = 0b0;
34030 let Inst{31-21} = 0b00011100001;
34031 let hasNewValue = 1;
34032 let opNewValue = 0;
34033 let DecoderNamespace = "EXT_mmvec";
34035 def V6_vmpyuhv_acc : HInst<
34036 (outs HvxWR:$Vxx32),
34037 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34038 "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
34039 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34040 let Inst{7-5} = 0b000;
34041 let Inst{13-13} = 0b1;
34042 let Inst{31-21} = 0b00011100001;
34043 let hasNewValue = 1;
34044 let opNewValue = 0;
34045 let isAccumulator = 1;
34046 let DecoderNamespace = "EXT_mmvec";
34047 let Constraints = "$Vxx32 = $Vxx32in";
34049 def V6_vmpyuhv_acc_alt : HInst<
34050 (outs HvxWR:$Vxx32),
34051 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34052 "$Vxx32 += vmpyuh($Vu32,$Vv32)",
34053 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34054 let hasNewValue = 1;
34055 let opNewValue = 0;
34056 let isAccumulator = 1;
34058 let isCodeGenOnly = 1;
34059 let DecoderNamespace = "EXT_mmvec";
34060 let Constraints = "$Vxx32 = $Vxx32in";
34062 def V6_vmpyuhv_alt : HInst<
34063 (outs HvxWR:$Vdd32),
34064 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34065 "$Vdd32 = vmpyuh($Vu32,$Vv32)",
34066 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34067 let hasNewValue = 1;
34068 let opNewValue = 0;
34070 let isCodeGenOnly = 1;
34071 let DecoderNamespace = "EXT_mmvec";
34073 def V6_vmux : HInst<
34074 (outs HvxVR:$Vd32),
34075 (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
34076 "$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
34077 tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
34078 let Inst{7-7} = 0b0;
34079 let Inst{13-13} = 0b1;
34080 let Inst{31-21} = 0b00011110111;
34081 let hasNewValue = 1;
34082 let opNewValue = 0;
34083 let DecoderNamespace = "EXT_mmvec";
34085 def V6_vnavgb : HInst<
34086 (outs HvxVR:$Vd32),
34087 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34088 "$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
34089 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
34090 let Inst{7-5} = 0b110;
34091 let Inst{13-13} = 0b1;
34092 let Inst{31-21} = 0b00011111000;
34093 let hasNewValue = 1;
34094 let opNewValue = 0;
34095 let DecoderNamespace = "EXT_mmvec";
34097 def V6_vnavgb_alt : HInst<
34098 (outs HvxVR:$Vd32),
34099 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34100 "$Vd32 = vnavgb($Vu32,$Vv32)",
34101 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34102 let hasNewValue = 1;
34103 let opNewValue = 0;
34105 let isCodeGenOnly = 1;
34106 let DecoderNamespace = "EXT_mmvec";
34108 def V6_vnavgh : HInst<
34109 (outs HvxVR:$Vd32),
34110 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34111 "$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
34112 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34113 let Inst{7-5} = 0b001;
34114 let Inst{13-13} = 0b0;
34115 let Inst{31-21} = 0b00011100111;
34116 let hasNewValue = 1;
34117 let opNewValue = 0;
34118 let DecoderNamespace = "EXT_mmvec";
34120 def V6_vnavgh_alt : HInst<
34121 (outs HvxVR:$Vd32),
34122 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34123 "$Vd32 = vnavgh($Vu32,$Vv32)",
34124 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34125 let hasNewValue = 1;
34126 let opNewValue = 0;
34128 let isCodeGenOnly = 1;
34129 let DecoderNamespace = "EXT_mmvec";
34131 def V6_vnavgub : HInst<
34132 (outs HvxVR:$Vd32),
34133 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34134 "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
34135 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34136 let Inst{7-5} = 0b000;
34137 let Inst{13-13} = 0b0;
34138 let Inst{31-21} = 0b00011100111;
34139 let hasNewValue = 1;
34140 let opNewValue = 0;
34141 let DecoderNamespace = "EXT_mmvec";
34143 def V6_vnavgub_alt : HInst<
34144 (outs HvxVR:$Vd32),
34145 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34146 "$Vd32 = vnavgub($Vu32,$Vv32)",
34147 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34148 let hasNewValue = 1;
34149 let opNewValue = 0;
34151 let isCodeGenOnly = 1;
34152 let DecoderNamespace = "EXT_mmvec";
34154 def V6_vnavgw : HInst<
34155 (outs HvxVR:$Vd32),
34156 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34157 "$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
34158 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34159 let Inst{7-5} = 0b010;
34160 let Inst{13-13} = 0b0;
34161 let Inst{31-21} = 0b00011100111;
34162 let hasNewValue = 1;
34163 let opNewValue = 0;
34164 let DecoderNamespace = "EXT_mmvec";
34166 def V6_vnavgw_alt : HInst<
34167 (outs HvxVR:$Vd32),
34168 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34169 "$Vd32 = vnavgw($Vu32,$Vv32)",
34170 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34171 let hasNewValue = 1;
34172 let opNewValue = 0;
34174 let isCodeGenOnly = 1;
34175 let DecoderNamespace = "EXT_mmvec";
34177 def V6_vnccombine : HInst<
34178 (outs HvxWR:$Vdd32),
34179 (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
34180 "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
34181 tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
34182 let Inst{7-7} = 0b0;
34183 let Inst{13-13} = 0b0;
34184 let Inst{31-21} = 0b00011010010;
34185 let isPredicated = 1;
34186 let isPredicatedFalse = 1;
34187 let hasNewValue = 1;
34188 let opNewValue = 0;
34189 let DecoderNamespace = "EXT_mmvec";
34191 def V6_vncmov : HInst<
34192 (outs HvxVR:$Vd32),
34193 (ins PredRegs:$Ps4, HvxVR:$Vu32),
34194 "if (!$Ps4) $Vd32 = $Vu32",
34195 tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
34196 let Inst{7-7} = 0b0;
34197 let Inst{13-13} = 0b0;
34198 let Inst{31-16} = 0b0001101000100000;
34199 let isPredicated = 1;
34200 let isPredicatedFalse = 1;
34201 let hasNewValue = 1;
34202 let opNewValue = 0;
34203 let DecoderNamespace = "EXT_mmvec";
34205 def V6_vnormamth : HInst<
34206 (outs HvxVR:$Vd32),
34208 "$Vd32.h = vnormamt($Vu32.h)",
34209 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34210 let Inst{7-5} = 0b101;
34211 let Inst{13-13} = 0b0;
34212 let Inst{31-16} = 0b0001111000000011;
34213 let hasNewValue = 1;
34214 let opNewValue = 0;
34215 let DecoderNamespace = "EXT_mmvec";
34217 def V6_vnormamth_alt : HInst<
34218 (outs HvxVR:$Vd32),
34220 "$Vd32 = vnormamth($Vu32)",
34221 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34222 let hasNewValue = 1;
34223 let opNewValue = 0;
34225 let isCodeGenOnly = 1;
34226 let DecoderNamespace = "EXT_mmvec";
34228 def V6_vnormamtw : HInst<
34229 (outs HvxVR:$Vd32),
34231 "$Vd32.w = vnormamt($Vu32.w)",
34232 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34233 let Inst{7-5} = 0b100;
34234 let Inst{13-13} = 0b0;
34235 let Inst{31-16} = 0b0001111000000011;
34236 let hasNewValue = 1;
34237 let opNewValue = 0;
34238 let DecoderNamespace = "EXT_mmvec";
34240 def V6_vnormamtw_alt : HInst<
34241 (outs HvxVR:$Vd32),
34243 "$Vd32 = vnormamtw($Vu32)",
34244 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34245 let hasNewValue = 1;
34246 let opNewValue = 0;
34248 let isCodeGenOnly = 1;
34249 let DecoderNamespace = "EXT_mmvec";
34251 def V6_vnot : HInst<
34252 (outs HvxVR:$Vd32),
34254 "$Vd32 = vnot($Vu32)",
34255 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
34256 let Inst{7-5} = 0b100;
34257 let Inst{13-13} = 0b0;
34258 let Inst{31-16} = 0b0001111000000000;
34259 let hasNewValue = 1;
34260 let opNewValue = 0;
34261 let DecoderNamespace = "EXT_mmvec";
34263 def V6_vor : HInst<
34264 (outs HvxVR:$Vd32),
34265 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34266 "$Vd32 = vor($Vu32,$Vv32)",
34267 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34268 let Inst{7-5} = 0b110;
34269 let Inst{13-13} = 0b0;
34270 let Inst{31-21} = 0b00011100001;
34271 let hasNewValue = 1;
34272 let opNewValue = 0;
34273 let DecoderNamespace = "EXT_mmvec";
34275 def V6_vpackeb : HInst<
34276 (outs HvxVR:$Vd32),
34277 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34278 "$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
34279 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34280 let Inst{7-5} = 0b010;
34281 let Inst{13-13} = 0b0;
34282 let Inst{31-21} = 0b00011111110;
34283 let hasNewValue = 1;
34284 let opNewValue = 0;
34285 let DecoderNamespace = "EXT_mmvec";
34287 def V6_vpackeb_alt : HInst<
34288 (outs HvxVR:$Vd32),
34289 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34290 "$Vd32 = vpackeb($Vu32,$Vv32)",
34291 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34292 let hasNewValue = 1;
34293 let opNewValue = 0;
34295 let isCodeGenOnly = 1;
34296 let DecoderNamespace = "EXT_mmvec";
34298 def V6_vpackeh : HInst<
34299 (outs HvxVR:$Vd32),
34300 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34301 "$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
34302 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34303 let Inst{7-5} = 0b011;
34304 let Inst{13-13} = 0b0;
34305 let Inst{31-21} = 0b00011111110;
34306 let hasNewValue = 1;
34307 let opNewValue = 0;
34308 let DecoderNamespace = "EXT_mmvec";
34310 def V6_vpackeh_alt : HInst<
34311 (outs HvxVR:$Vd32),
34312 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34313 "$Vd32 = vpackeh($Vu32,$Vv32)",
34314 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34315 let hasNewValue = 1;
34316 let opNewValue = 0;
34318 let isCodeGenOnly = 1;
34319 let DecoderNamespace = "EXT_mmvec";
34321 def V6_vpackhb_sat : HInst<
34322 (outs HvxVR:$Vd32),
34323 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34324 "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
34325 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34326 let Inst{7-5} = 0b110;
34327 let Inst{13-13} = 0b0;
34328 let Inst{31-21} = 0b00011111110;
34329 let hasNewValue = 1;
34330 let opNewValue = 0;
34331 let DecoderNamespace = "EXT_mmvec";
34333 def V6_vpackhb_sat_alt : HInst<
34334 (outs HvxVR:$Vd32),
34335 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34336 "$Vd32 = vpackhb($Vu32,$Vv32):sat",
34337 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34338 let hasNewValue = 1;
34339 let opNewValue = 0;
34341 let isCodeGenOnly = 1;
34342 let DecoderNamespace = "EXT_mmvec";
34344 def V6_vpackhub_sat : HInst<
34345 (outs HvxVR:$Vd32),
34346 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34347 "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
34348 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34349 let Inst{7-5} = 0b101;
34350 let Inst{13-13} = 0b0;
34351 let Inst{31-21} = 0b00011111110;
34352 let hasNewValue = 1;
34353 let opNewValue = 0;
34354 let DecoderNamespace = "EXT_mmvec";
34356 def V6_vpackhub_sat_alt : HInst<
34357 (outs HvxVR:$Vd32),
34358 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34359 "$Vd32 = vpackhub($Vu32,$Vv32):sat",
34360 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34361 let hasNewValue = 1;
34362 let opNewValue = 0;
34364 let isCodeGenOnly = 1;
34365 let DecoderNamespace = "EXT_mmvec";
34367 def V6_vpackob : HInst<
34368 (outs HvxVR:$Vd32),
34369 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34370 "$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
34371 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34372 let Inst{7-5} = 0b001;
34373 let Inst{13-13} = 0b0;
34374 let Inst{31-21} = 0b00011111111;
34375 let hasNewValue = 1;
34376 let opNewValue = 0;
34377 let DecoderNamespace = "EXT_mmvec";
34379 def V6_vpackob_alt : HInst<
34380 (outs HvxVR:$Vd32),
34381 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34382 "$Vd32 = vpackob($Vu32,$Vv32)",
34383 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34384 let hasNewValue = 1;
34385 let opNewValue = 0;
34387 let isCodeGenOnly = 1;
34388 let DecoderNamespace = "EXT_mmvec";
34390 def V6_vpackoh : HInst<
34391 (outs HvxVR:$Vd32),
34392 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34393 "$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
34394 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34395 let Inst{7-5} = 0b010;
34396 let Inst{13-13} = 0b0;
34397 let Inst{31-21} = 0b00011111111;
34398 let hasNewValue = 1;
34399 let opNewValue = 0;
34400 let DecoderNamespace = "EXT_mmvec";
34402 def V6_vpackoh_alt : HInst<
34403 (outs HvxVR:$Vd32),
34404 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34405 "$Vd32 = vpackoh($Vu32,$Vv32)",
34406 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34407 let hasNewValue = 1;
34408 let opNewValue = 0;
34410 let isCodeGenOnly = 1;
34411 let DecoderNamespace = "EXT_mmvec";
34413 def V6_vpackwh_sat : HInst<
34414 (outs HvxVR:$Vd32),
34415 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34416 "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
34417 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34418 let Inst{7-5} = 0b000;
34419 let Inst{13-13} = 0b0;
34420 let Inst{31-21} = 0b00011111111;
34421 let hasNewValue = 1;
34422 let opNewValue = 0;
34423 let DecoderNamespace = "EXT_mmvec";
34425 def V6_vpackwh_sat_alt : HInst<
34426 (outs HvxVR:$Vd32),
34427 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34428 "$Vd32 = vpackwh($Vu32,$Vv32):sat",
34429 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34430 let hasNewValue = 1;
34431 let opNewValue = 0;
34433 let isCodeGenOnly = 1;
34434 let DecoderNamespace = "EXT_mmvec";
34436 def V6_vpackwuh_sat : HInst<
34437 (outs HvxVR:$Vd32),
34438 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34439 "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
34440 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34441 let Inst{7-5} = 0b111;
34442 let Inst{13-13} = 0b0;
34443 let Inst{31-21} = 0b00011111110;
34444 let hasNewValue = 1;
34445 let opNewValue = 0;
34446 let DecoderNamespace = "EXT_mmvec";
34448 def V6_vpackwuh_sat_alt : HInst<
34449 (outs HvxVR:$Vd32),
34450 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34451 "$Vd32 = vpackwuh($Vu32,$Vv32):sat",
34452 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34453 let hasNewValue = 1;
34454 let opNewValue = 0;
34456 let isCodeGenOnly = 1;
34457 let DecoderNamespace = "EXT_mmvec";
34459 def V6_vpopcounth : HInst<
34460 (outs HvxVR:$Vd32),
34462 "$Vd32.h = vpopcount($Vu32.h)",
34463 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34464 let Inst{7-5} = 0b110;
34465 let Inst{13-13} = 0b0;
34466 let Inst{31-16} = 0b0001111000000010;
34467 let hasNewValue = 1;
34468 let opNewValue = 0;
34469 let DecoderNamespace = "EXT_mmvec";
34471 def V6_vpopcounth_alt : HInst<
34472 (outs HvxVR:$Vd32),
34474 "$Vd32 = vpopcounth($Vu32)",
34475 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34476 let hasNewValue = 1;
34477 let opNewValue = 0;
34479 let isCodeGenOnly = 1;
34480 let DecoderNamespace = "EXT_mmvec";
34482 def V6_vprefixqb : HInst<
34483 (outs HvxVR:$Vd32),
34485 "$Vd32.b = prefixsum($Qv4)",
34486 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34487 let Inst{13-5} = 0b100000010;
34488 let Inst{21-16} = 0b000011;
34489 let Inst{31-24} = 0b00011110;
34490 let hasNewValue = 1;
34491 let opNewValue = 0;
34492 let DecoderNamespace = "EXT_mmvec";
34494 def V6_vprefixqh : HInst<
34495 (outs HvxVR:$Vd32),
34497 "$Vd32.h = prefixsum($Qv4)",
34498 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34499 let Inst{13-5} = 0b100001010;
34500 let Inst{21-16} = 0b000011;
34501 let Inst{31-24} = 0b00011110;
34502 let hasNewValue = 1;
34503 let opNewValue = 0;
34504 let DecoderNamespace = "EXT_mmvec";
34506 def V6_vprefixqw : HInst<
34507 (outs HvxVR:$Vd32),
34509 "$Vd32.w = prefixsum($Qv4)",
34510 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34511 let Inst{13-5} = 0b100010010;
34512 let Inst{21-16} = 0b000011;
34513 let Inst{31-24} = 0b00011110;
34514 let hasNewValue = 1;
34515 let opNewValue = 0;
34516 let DecoderNamespace = "EXT_mmvec";
34518 def V6_vrdelta : HInst<
34519 (outs HvxVR:$Vd32),
34520 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34521 "$Vd32 = vrdelta($Vu32,$Vv32)",
34522 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34523 let Inst{7-5} = 0b011;
34524 let Inst{13-13} = 0b0;
34525 let Inst{31-21} = 0b00011111001;
34526 let hasNewValue = 1;
34527 let opNewValue = 0;
34528 let DecoderNamespace = "EXT_mmvec";
34530 def V6_vrmpybub_rtt : HInst<
34531 (outs HvxWR:$Vdd32),
34532 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34533 "$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
34534 tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
34535 let Inst{7-5} = 0b101;
34536 let Inst{13-13} = 0b0;
34537 let Inst{31-21} = 0b00011001110;
34538 let hasNewValue = 1;
34539 let opNewValue = 0;
34540 let DecoderNamespace = "EXT_mmvec";
34542 def V6_vrmpybub_rtt_acc : HInst<
34543 (outs HvxWR:$Vxx32),
34544 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34545 "$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
34546 tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
34547 let Inst{7-5} = 0b000;
34548 let Inst{13-13} = 0b1;
34549 let Inst{31-21} = 0b00011001101;
34550 let hasNewValue = 1;
34551 let opNewValue = 0;
34552 let isAccumulator = 1;
34553 let DecoderNamespace = "EXT_mmvec";
34554 let Constraints = "$Vxx32 = $Vxx32in";
34556 def V6_vrmpybub_rtt_acc_alt : HInst<
34557 (outs HvxWR:$Vxx32),
34558 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34559 "$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
34560 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34561 let hasNewValue = 1;
34562 let opNewValue = 0;
34563 let isAccumulator = 1;
34565 let isCodeGenOnly = 1;
34566 let DecoderNamespace = "EXT_mmvec";
34567 let Constraints = "$Vxx32 = $Vxx32in";
34569 def V6_vrmpybub_rtt_alt : HInst<
34570 (outs HvxWR:$Vdd32),
34571 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34572 "$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
34573 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34574 let hasNewValue = 1;
34575 let opNewValue = 0;
34577 let isCodeGenOnly = 1;
34578 let DecoderNamespace = "EXT_mmvec";
34580 def V6_vrmpybus : HInst<
34581 (outs HvxVR:$Vd32),
34582 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34583 "$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
34584 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34585 let Inst{7-5} = 0b100;
34586 let Inst{13-13} = 0b0;
34587 let Inst{31-21} = 0b00011001000;
34588 let hasNewValue = 1;
34589 let opNewValue = 0;
34590 let DecoderNamespace = "EXT_mmvec";
34592 def V6_vrmpybus_acc : HInst<
34593 (outs HvxVR:$Vx32),
34594 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34595 "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
34596 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34597 let Inst{7-5} = 0b101;
34598 let Inst{13-13} = 0b1;
34599 let Inst{31-21} = 0b00011001000;
34600 let hasNewValue = 1;
34601 let opNewValue = 0;
34602 let isAccumulator = 1;
34603 let DecoderNamespace = "EXT_mmvec";
34604 let Constraints = "$Vx32 = $Vx32in";
34606 def V6_vrmpybus_acc_alt : HInst<
34607 (outs HvxVR:$Vx32),
34608 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34609 "$Vx32 += vrmpybus($Vu32,$Rt32)",
34610 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34611 let hasNewValue = 1;
34612 let opNewValue = 0;
34613 let isAccumulator = 1;
34615 let isCodeGenOnly = 1;
34616 let DecoderNamespace = "EXT_mmvec";
34617 let Constraints = "$Vx32 = $Vx32in";
34619 def V6_vrmpybus_alt : HInst<
34620 (outs HvxVR:$Vd32),
34621 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34622 "$Vd32 = vrmpybus($Vu32,$Rt32)",
34623 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34624 let hasNewValue = 1;
34625 let opNewValue = 0;
34627 let isCodeGenOnly = 1;
34628 let DecoderNamespace = "EXT_mmvec";
34630 def V6_vrmpybusi : HInst<
34631 (outs HvxWR:$Vdd32),
34632 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34633 "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
34634 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
34635 let Inst{7-6} = 0b10;
34636 let Inst{13-13} = 0b0;
34637 let Inst{31-21} = 0b00011001010;
34638 let hasNewValue = 1;
34639 let opNewValue = 0;
34640 let DecoderNamespace = "EXT_mmvec";
34642 def V6_vrmpybusi_acc : HInst<
34643 (outs HvxWR:$Vxx32),
34644 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34645 "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
34646 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
34647 let Inst{7-6} = 0b10;
34648 let Inst{13-13} = 0b1;
34649 let Inst{31-21} = 0b00011001010;
34650 let hasNewValue = 1;
34651 let opNewValue = 0;
34652 let isAccumulator = 1;
34653 let DecoderNamespace = "EXT_mmvec";
34654 let Constraints = "$Vxx32 = $Vxx32in";
34656 def V6_vrmpybusi_acc_alt : HInst<
34657 (outs HvxWR:$Vxx32),
34658 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34659 "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
34660 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34661 let hasNewValue = 1;
34662 let opNewValue = 0;
34663 let isAccumulator = 1;
34665 let isCodeGenOnly = 1;
34666 let DecoderNamespace = "EXT_mmvec";
34667 let Constraints = "$Vxx32 = $Vxx32in";
34669 def V6_vrmpybusi_alt : HInst<
34670 (outs HvxWR:$Vdd32),
34671 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34672 "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
34673 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34674 let hasNewValue = 1;
34675 let opNewValue = 0;
34677 let isCodeGenOnly = 1;
34678 let DecoderNamespace = "EXT_mmvec";
34680 def V6_vrmpybusv : HInst<
34681 (outs HvxVR:$Vd32),
34682 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34683 "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
34684 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34685 let Inst{7-5} = 0b010;
34686 let Inst{13-13} = 0b0;
34687 let Inst{31-21} = 0b00011100000;
34688 let hasNewValue = 1;
34689 let opNewValue = 0;
34690 let DecoderNamespace = "EXT_mmvec";
34692 def V6_vrmpybusv_acc : HInst<
34693 (outs HvxVR:$Vx32),
34694 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34695 "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
34696 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34697 let Inst{7-5} = 0b010;
34698 let Inst{13-13} = 0b1;
34699 let Inst{31-21} = 0b00011100000;
34700 let hasNewValue = 1;
34701 let opNewValue = 0;
34702 let isAccumulator = 1;
34703 let DecoderNamespace = "EXT_mmvec";
34704 let Constraints = "$Vx32 = $Vx32in";
34706 def V6_vrmpybusv_acc_alt : HInst<
34707 (outs HvxVR:$Vx32),
34708 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34709 "$Vx32 += vrmpybus($Vu32,$Vv32)",
34710 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34711 let hasNewValue = 1;
34712 let opNewValue = 0;
34713 let isAccumulator = 1;
34715 let isCodeGenOnly = 1;
34716 let DecoderNamespace = "EXT_mmvec";
34717 let Constraints = "$Vx32 = $Vx32in";
34719 def V6_vrmpybusv_alt : HInst<
34720 (outs HvxVR:$Vd32),
34721 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34722 "$Vd32 = vrmpybus($Vu32,$Vv32)",
34723 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34724 let hasNewValue = 1;
34725 let opNewValue = 0;
34727 let isCodeGenOnly = 1;
34728 let DecoderNamespace = "EXT_mmvec";
34730 def V6_vrmpybv : HInst<
34731 (outs HvxVR:$Vd32),
34732 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34733 "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
34734 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34735 let Inst{7-5} = 0b001;
34736 let Inst{13-13} = 0b0;
34737 let Inst{31-21} = 0b00011100000;
34738 let hasNewValue = 1;
34739 let opNewValue = 0;
34740 let DecoderNamespace = "EXT_mmvec";
34742 def V6_vrmpybv_acc : HInst<
34743 (outs HvxVR:$Vx32),
34744 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34745 "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
34746 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34747 let Inst{7-5} = 0b001;
34748 let Inst{13-13} = 0b1;
34749 let Inst{31-21} = 0b00011100000;
34750 let hasNewValue = 1;
34751 let opNewValue = 0;
34752 let isAccumulator = 1;
34753 let DecoderNamespace = "EXT_mmvec";
34754 let Constraints = "$Vx32 = $Vx32in";
34756 def V6_vrmpybv_acc_alt : HInst<
34757 (outs HvxVR:$Vx32),
34758 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34759 "$Vx32 += vrmpyb($Vu32,$Vv32)",
34760 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34761 let hasNewValue = 1;
34762 let opNewValue = 0;
34763 let isAccumulator = 1;
34765 let isCodeGenOnly = 1;
34766 let DecoderNamespace = "EXT_mmvec";
34767 let Constraints = "$Vx32 = $Vx32in";
34769 def V6_vrmpybv_alt : HInst<
34770 (outs HvxVR:$Vd32),
34771 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34772 "$Vd32 = vrmpyb($Vu32,$Vv32)",
34773 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34774 let hasNewValue = 1;
34775 let opNewValue = 0;
34777 let isCodeGenOnly = 1;
34778 let DecoderNamespace = "EXT_mmvec";
34780 def V6_vrmpyub : HInst<
34781 (outs HvxVR:$Vd32),
34782 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34783 "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
34784 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34785 let Inst{7-5} = 0b011;
34786 let Inst{13-13} = 0b0;
34787 let Inst{31-21} = 0b00011001000;
34788 let hasNewValue = 1;
34789 let opNewValue = 0;
34790 let DecoderNamespace = "EXT_mmvec";
34792 def V6_vrmpyub_acc : HInst<
34793 (outs HvxVR:$Vx32),
34794 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34795 "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
34796 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34797 let Inst{7-5} = 0b100;
34798 let Inst{13-13} = 0b1;
34799 let Inst{31-21} = 0b00011001000;
34800 let hasNewValue = 1;
34801 let opNewValue = 0;
34802 let isAccumulator = 1;
34803 let DecoderNamespace = "EXT_mmvec";
34804 let Constraints = "$Vx32 = $Vx32in";
34806 def V6_vrmpyub_acc_alt : HInst<
34807 (outs HvxVR:$Vx32),
34808 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34809 "$Vx32 += vrmpyub($Vu32,$Rt32)",
34810 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34811 let hasNewValue = 1;
34812 let opNewValue = 0;
34813 let isAccumulator = 1;
34815 let isCodeGenOnly = 1;
34816 let DecoderNamespace = "EXT_mmvec";
34817 let Constraints = "$Vx32 = $Vx32in";
34819 def V6_vrmpyub_alt : HInst<
34820 (outs HvxVR:$Vd32),
34821 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34822 "$Vd32 = vrmpyub($Vu32,$Rt32)",
34823 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34824 let hasNewValue = 1;
34825 let opNewValue = 0;
34827 let isCodeGenOnly = 1;
34828 let DecoderNamespace = "EXT_mmvec";
34830 def V6_vrmpyub_rtt : HInst<
34831 (outs HvxWR:$Vdd32),
34832 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34833 "$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
34834 tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
34835 let Inst{7-5} = 0b100;
34836 let Inst{13-13} = 0b0;
34837 let Inst{31-21} = 0b00011001110;
34838 let hasNewValue = 1;
34839 let opNewValue = 0;
34840 let DecoderNamespace = "EXT_mmvec";
34842 def V6_vrmpyub_rtt_acc : HInst<
34843 (outs HvxWR:$Vxx32),
34844 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34845 "$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
34846 tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
34847 let Inst{7-5} = 0b111;
34848 let Inst{13-13} = 0b1;
34849 let Inst{31-21} = 0b00011001101;
34850 let hasNewValue = 1;
34851 let opNewValue = 0;
34852 let isAccumulator = 1;
34853 let DecoderNamespace = "EXT_mmvec";
34854 let Constraints = "$Vxx32 = $Vxx32in";
34856 def V6_vrmpyub_rtt_acc_alt : HInst<
34857 (outs HvxWR:$Vxx32),
34858 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34859 "$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
34860 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34861 let hasNewValue = 1;
34862 let opNewValue = 0;
34863 let isAccumulator = 1;
34865 let isCodeGenOnly = 1;
34866 let DecoderNamespace = "EXT_mmvec";
34867 let Constraints = "$Vxx32 = $Vxx32in";
34869 def V6_vrmpyub_rtt_alt : HInst<
34870 (outs HvxWR:$Vdd32),
34871 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34872 "$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
34873 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34874 let hasNewValue = 1;
34875 let opNewValue = 0;
34877 let isCodeGenOnly = 1;
34878 let DecoderNamespace = "EXT_mmvec";
34880 def V6_vrmpyubi : HInst<
34881 (outs HvxWR:$Vdd32),
34882 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34883 "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
34884 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
34885 let Inst{7-6} = 0b11;
34886 let Inst{13-13} = 0b0;
34887 let Inst{31-21} = 0b00011001101;
34888 let hasNewValue = 1;
34889 let opNewValue = 0;
34890 let DecoderNamespace = "EXT_mmvec";
34892 def V6_vrmpyubi_acc : HInst<
34893 (outs HvxWR:$Vxx32),
34894 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34895 "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
34896 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
34897 let Inst{7-6} = 0b11;
34898 let Inst{13-13} = 0b1;
34899 let Inst{31-21} = 0b00011001011;
34900 let hasNewValue = 1;
34901 let opNewValue = 0;
34902 let isAccumulator = 1;
34903 let DecoderNamespace = "EXT_mmvec";
34904 let Constraints = "$Vxx32 = $Vxx32in";
34906 def V6_vrmpyubi_acc_alt : HInst<
34907 (outs HvxWR:$Vxx32),
34908 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34909 "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
34910 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34911 let hasNewValue = 1;
34912 let opNewValue = 0;
34913 let isAccumulator = 1;
34915 let isCodeGenOnly = 1;
34916 let DecoderNamespace = "EXT_mmvec";
34917 let Constraints = "$Vxx32 = $Vxx32in";
34919 def V6_vrmpyubi_alt : HInst<
34920 (outs HvxWR:$Vdd32),
34921 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34922 "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
34923 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34924 let hasNewValue = 1;
34925 let opNewValue = 0;
34927 let isCodeGenOnly = 1;
34928 let DecoderNamespace = "EXT_mmvec";
34930 def V6_vrmpyubv : HInst<
34931 (outs HvxVR:$Vd32),
34932 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34933 "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
34934 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34935 let Inst{7-5} = 0b000;
34936 let Inst{13-13} = 0b0;
34937 let Inst{31-21} = 0b00011100000;
34938 let hasNewValue = 1;
34939 let opNewValue = 0;
34940 let DecoderNamespace = "EXT_mmvec";
34942 def V6_vrmpyubv_acc : HInst<
34943 (outs HvxVR:$Vx32),
34944 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34945 "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
34946 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34947 let Inst{7-5} = 0b000;
34948 let Inst{13-13} = 0b1;
34949 let Inst{31-21} = 0b00011100000;
34950 let hasNewValue = 1;
34951 let opNewValue = 0;
34952 let isAccumulator = 1;
34953 let DecoderNamespace = "EXT_mmvec";
34954 let Constraints = "$Vx32 = $Vx32in";
34956 def V6_vrmpyubv_acc_alt : HInst<
34957 (outs HvxVR:$Vx32),
34958 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34959 "$Vx32 += vrmpyub($Vu32,$Vv32)",
34960 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34961 let hasNewValue = 1;
34962 let opNewValue = 0;
34963 let isAccumulator = 1;
34965 let isCodeGenOnly = 1;
34966 let DecoderNamespace = "EXT_mmvec";
34967 let Constraints = "$Vx32 = $Vx32in";
34969 def V6_vrmpyubv_alt : HInst<
34970 (outs HvxVR:$Vd32),
34971 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34972 "$Vd32 = vrmpyub($Vu32,$Vv32)",
34973 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34974 let hasNewValue = 1;
34975 let opNewValue = 0;
34977 let isCodeGenOnly = 1;
34978 let DecoderNamespace = "EXT_mmvec";
34980 def V6_vror : HInst<
34981 (outs HvxVR:$Vd32),
34982 (ins HvxVR:$Vu32, IntRegs:$Rt32),
34983 "$Vd32 = vror($Vu32,$Rt32)",
34984 tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
34985 let Inst{7-5} = 0b001;
34986 let Inst{13-13} = 0b0;
34987 let Inst{31-21} = 0b00011001011;
34988 let hasNewValue = 1;
34989 let opNewValue = 0;
34990 let DecoderNamespace = "EXT_mmvec";
34992 def V6_vroundhb : HInst<
34993 (outs HvxVR:$Vd32),
34994 (ins HvxVR:$Vu32, HvxVR:$Vv32),
34995 "$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
34996 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34997 let Inst{7-5} = 0b110;
34998 let Inst{13-13} = 0b0;
34999 let Inst{31-21} = 0b00011111011;
35000 let hasNewValue = 1;
35001 let opNewValue = 0;
35002 let DecoderNamespace = "EXT_mmvec";
35004 def V6_vroundhb_alt : HInst<
35005 (outs HvxVR:$Vd32),
35006 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35007 "$Vd32 = vroundhb($Vu32,$Vv32):sat",
35008 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35009 let hasNewValue = 1;
35010 let opNewValue = 0;
35012 let isCodeGenOnly = 1;
35013 let DecoderNamespace = "EXT_mmvec";
35015 def V6_vroundhub : HInst<
35016 (outs HvxVR:$Vd32),
35017 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35018 "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
35019 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35020 let Inst{7-5} = 0b111;
35021 let Inst{13-13} = 0b0;
35022 let Inst{31-21} = 0b00011111011;
35023 let hasNewValue = 1;
35024 let opNewValue = 0;
35025 let DecoderNamespace = "EXT_mmvec";
35027 def V6_vroundhub_alt : HInst<
35028 (outs HvxVR:$Vd32),
35029 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35030 "$Vd32 = vroundhub($Vu32,$Vv32):sat",
35031 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35032 let hasNewValue = 1;
35033 let opNewValue = 0;
35035 let isCodeGenOnly = 1;
35036 let DecoderNamespace = "EXT_mmvec";
35038 def V6_vrounduhub : HInst<
35039 (outs HvxVR:$Vd32),
35040 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35041 "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
35042 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
35043 let Inst{7-5} = 0b011;
35044 let Inst{13-13} = 0b0;
35045 let Inst{31-21} = 0b00011111111;
35046 let hasNewValue = 1;
35047 let opNewValue = 0;
35048 let DecoderNamespace = "EXT_mmvec";
35050 def V6_vrounduhub_alt : HInst<
35051 (outs HvxVR:$Vd32),
35052 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35053 "$Vd32 = vrounduhub($Vu32,$Vv32):sat",
35054 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35055 let hasNewValue = 1;
35056 let opNewValue = 0;
35058 let isCodeGenOnly = 1;
35059 let DecoderNamespace = "EXT_mmvec";
35061 def V6_vrounduwuh : HInst<
35062 (outs HvxVR:$Vd32),
35063 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35064 "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
35065 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
35066 let Inst{7-5} = 0b100;
35067 let Inst{13-13} = 0b0;
35068 let Inst{31-21} = 0b00011111111;
35069 let hasNewValue = 1;
35070 let opNewValue = 0;
35071 let DecoderNamespace = "EXT_mmvec";
35073 def V6_vrounduwuh_alt : HInst<
35074 (outs HvxVR:$Vd32),
35075 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35076 "$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
35077 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35078 let hasNewValue = 1;
35079 let opNewValue = 0;
35081 let isCodeGenOnly = 1;
35082 let DecoderNamespace = "EXT_mmvec";
35084 def V6_vroundwh : HInst<
35085 (outs HvxVR:$Vd32),
35086 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35087 "$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
35088 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35089 let Inst{7-5} = 0b100;
35090 let Inst{13-13} = 0b0;
35091 let Inst{31-21} = 0b00011111011;
35092 let hasNewValue = 1;
35093 let opNewValue = 0;
35094 let DecoderNamespace = "EXT_mmvec";
35096 def V6_vroundwh_alt : HInst<
35097 (outs HvxVR:$Vd32),
35098 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35099 "$Vd32 = vroundwh($Vu32,$Vv32):sat",
35100 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35101 let hasNewValue = 1;
35102 let opNewValue = 0;
35104 let isCodeGenOnly = 1;
35105 let DecoderNamespace = "EXT_mmvec";
35107 def V6_vroundwuh : HInst<
35108 (outs HvxVR:$Vd32),
35109 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35110 "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
35111 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35112 let Inst{7-5} = 0b101;
35113 let Inst{13-13} = 0b0;
35114 let Inst{31-21} = 0b00011111011;
35115 let hasNewValue = 1;
35116 let opNewValue = 0;
35117 let DecoderNamespace = "EXT_mmvec";
35119 def V6_vroundwuh_alt : HInst<
35120 (outs HvxVR:$Vd32),
35121 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35122 "$Vd32 = vroundwuh($Vu32,$Vv32):sat",
35123 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35124 let hasNewValue = 1;
35125 let opNewValue = 0;
35127 let isCodeGenOnly = 1;
35128 let DecoderNamespace = "EXT_mmvec";
35130 def V6_vrsadubi : HInst<
35131 (outs HvxWR:$Vdd32),
35132 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35133 "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
35134 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
35135 let Inst{7-6} = 0b11;
35136 let Inst{13-13} = 0b0;
35137 let Inst{31-21} = 0b00011001010;
35138 let hasNewValue = 1;
35139 let opNewValue = 0;
35140 let DecoderNamespace = "EXT_mmvec";
35142 def V6_vrsadubi_acc : HInst<
35143 (outs HvxWR:$Vxx32),
35144 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35145 "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
35146 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
35147 let Inst{7-6} = 0b11;
35148 let Inst{13-13} = 0b1;
35149 let Inst{31-21} = 0b00011001010;
35150 let hasNewValue = 1;
35151 let opNewValue = 0;
35152 let isAccumulator = 1;
35153 let DecoderNamespace = "EXT_mmvec";
35154 let Constraints = "$Vxx32 = $Vxx32in";
35156 def V6_vrsadubi_acc_alt : HInst<
35157 (outs HvxWR:$Vxx32),
35158 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35159 "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
35160 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35161 let hasNewValue = 1;
35162 let opNewValue = 0;
35163 let isAccumulator = 1;
35165 let isCodeGenOnly = 1;
35166 let DecoderNamespace = "EXT_mmvec";
35167 let Constraints = "$Vxx32 = $Vxx32in";
35169 def V6_vrsadubi_alt : HInst<
35170 (outs HvxWR:$Vdd32),
35171 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35172 "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
35173 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35174 let hasNewValue = 1;
35175 let opNewValue = 0;
35177 let isCodeGenOnly = 1;
35178 let DecoderNamespace = "EXT_mmvec";
35180 def V6_vsathub : HInst<
35181 (outs HvxVR:$Vd32),
35182 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35183 "$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
35184 tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
35185 let Inst{7-5} = 0b010;
35186 let Inst{13-13} = 0b0;
35187 let Inst{31-21} = 0b00011111011;
35188 let hasNewValue = 1;
35189 let opNewValue = 0;
35190 let DecoderNamespace = "EXT_mmvec";
35192 def V6_vsathub_alt : HInst<
35193 (outs HvxVR:$Vd32),
35194 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35195 "$Vd32 = vsathub($Vu32,$Vv32)",
35196 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35197 let hasNewValue = 1;
35198 let opNewValue = 0;
35200 let isCodeGenOnly = 1;
35201 let DecoderNamespace = "EXT_mmvec";
35203 def V6_vsatuwuh : HInst<
35204 (outs HvxVR:$Vd32),
35205 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35206 "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
35207 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
35208 let Inst{7-5} = 0b110;
35209 let Inst{13-13} = 0b0;
35210 let Inst{31-21} = 0b00011111001;
35211 let hasNewValue = 1;
35212 let opNewValue = 0;
35213 let DecoderNamespace = "EXT_mmvec";
35215 def V6_vsatuwuh_alt : HInst<
35216 (outs HvxVR:$Vd32),
35217 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35218 "$Vd32 = vsatuwuh($Vu32,$Vv32)",
35219 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35220 let hasNewValue = 1;
35221 let opNewValue = 0;
35223 let isCodeGenOnly = 1;
35224 let DecoderNamespace = "EXT_mmvec";
35226 def V6_vsatwh : HInst<
35227 (outs HvxVR:$Vd32),
35228 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35229 "$Vd32.h = vsat($Vu32.w,$Vv32.w)",
35230 tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
35231 let Inst{7-5} = 0b011;
35232 let Inst{13-13} = 0b0;
35233 let Inst{31-21} = 0b00011111011;
35234 let hasNewValue = 1;
35235 let opNewValue = 0;
35236 let DecoderNamespace = "EXT_mmvec";
35238 def V6_vsatwh_alt : HInst<
35239 (outs HvxVR:$Vd32),
35240 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35241 "$Vd32 = vsatwh($Vu32,$Vv32)",
35242 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35243 let hasNewValue = 1;
35244 let opNewValue = 0;
35246 let isCodeGenOnly = 1;
35247 let DecoderNamespace = "EXT_mmvec";
35249 def V6_vsb : HInst<
35250 (outs HvxWR:$Vdd32),
35252 "$Vdd32.h = vsxt($Vu32.b)",
35253 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
35254 let Inst{7-5} = 0b011;
35255 let Inst{13-13} = 0b0;
35256 let Inst{31-16} = 0b0001111000000010;
35257 let hasNewValue = 1;
35258 let opNewValue = 0;
35259 let DecoderNamespace = "EXT_mmvec";
35261 def V6_vsb_alt : HInst<
35262 (outs HvxWR:$Vdd32),
35264 "$Vdd32 = vsxtb($Vu32)",
35265 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35266 let hasNewValue = 1;
35267 let opNewValue = 0;
35269 let isCodeGenOnly = 1;
35270 let DecoderNamespace = "EXT_mmvec";
35272 def V6_vscattermh : HInst<
35274 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35275 "vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
35276 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35277 let Inst{7-5} = 0b001;
35278 let Inst{31-21} = 0b00101111001;
35279 let accessSize = HalfWordAccess;
35281 let DecoderNamespace = "EXT_mmvec";
35283 def V6_vscattermh_add : HInst<
35285 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35286 "vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
35287 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35288 let Inst{7-5} = 0b101;
35289 let Inst{31-21} = 0b00101111001;
35290 let accessSize = HalfWordAccess;
35291 let isAccumulator = 1;
35293 let DecoderNamespace = "EXT_mmvec";
35295 def V6_vscattermh_add_alt : HInst<
35297 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35298 "vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
35299 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35300 let isAccumulator = 1;
35302 let isCodeGenOnly = 1;
35303 let DecoderNamespace = "EXT_mmvec";
35305 def V6_vscattermh_alt : HInst<
35307 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35308 "vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
35309 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35311 let isCodeGenOnly = 1;
35312 let DecoderNamespace = "EXT_mmvec";
35314 def V6_vscattermhq : HInst<
35316 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35317 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
35318 tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
35319 let Inst{7-7} = 0b1;
35320 let Inst{31-21} = 0b00101111100;
35321 let accessSize = HalfWordAccess;
35323 let DecoderNamespace = "EXT_mmvec";
35325 def V6_vscattermhq_alt : HInst<
35327 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35328 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
35329 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35331 let isCodeGenOnly = 1;
35332 let DecoderNamespace = "EXT_mmvec";
35334 def V6_vscattermhw : HInst<
35336 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35337 "vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
35338 tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
35339 let Inst{7-5} = 0b010;
35340 let Inst{31-21} = 0b00101111001;
35341 let accessSize = HalfWordAccess;
35343 let DecoderNamespace = "EXT_mmvec";
35345 def V6_vscattermhw_add : HInst<
35347 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35348 "vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
35349 tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
35350 let Inst{7-5} = 0b110;
35351 let Inst{31-21} = 0b00101111001;
35352 let accessSize = HalfWordAccess;
35353 let isAccumulator = 1;
35355 let DecoderNamespace = "EXT_mmvec";
35357 def V6_vscattermhwq : HInst<
35359 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35360 "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
35361 tc_94f43c04, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
35362 let Inst{7-7} = 0b0;
35363 let Inst{31-21} = 0b00101111101;
35364 let accessSize = HalfWordAccess;
35366 let DecoderNamespace = "EXT_mmvec";
35368 def V6_vscattermw : HInst<
35370 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35371 "vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
35372 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35373 let Inst{7-5} = 0b000;
35374 let Inst{31-21} = 0b00101111001;
35375 let accessSize = WordAccess;
35377 let DecoderNamespace = "EXT_mmvec";
35379 def V6_vscattermw_add : HInst<
35381 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35382 "vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
35383 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35384 let Inst{7-5} = 0b100;
35385 let Inst{31-21} = 0b00101111001;
35386 let accessSize = WordAccess;
35387 let isAccumulator = 1;
35389 let DecoderNamespace = "EXT_mmvec";
35391 def V6_vscattermw_add_alt : HInst<
35393 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35394 "vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
35395 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35396 let isAccumulator = 1;
35398 let isCodeGenOnly = 1;
35399 let DecoderNamespace = "EXT_mmvec";
35401 def V6_vscattermw_alt : HInst<
35403 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35404 "vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
35405 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35407 let isCodeGenOnly = 1;
35408 let DecoderNamespace = "EXT_mmvec";
35410 def V6_vscattermwh_add_alt : HInst<
35412 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35413 "vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
35414 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35415 let isAccumulator = 1;
35417 let isCodeGenOnly = 1;
35418 let DecoderNamespace = "EXT_mmvec";
35420 def V6_vscattermwh_alt : HInst<
35422 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35423 "vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
35424 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35426 let isCodeGenOnly = 1;
35427 let DecoderNamespace = "EXT_mmvec";
35429 def V6_vscattermwhq_alt : HInst<
35431 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35432 "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
35433 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35435 let isCodeGenOnly = 1;
35436 let DecoderNamespace = "EXT_mmvec";
35438 def V6_vscattermwq : HInst<
35440 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35441 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
35442 tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
35443 let Inst{7-7} = 0b0;
35444 let Inst{31-21} = 0b00101111100;
35445 let accessSize = WordAccess;
35447 let DecoderNamespace = "EXT_mmvec";
35449 def V6_vscattermwq_alt : HInst<
35451 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35452 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
35453 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35455 let isCodeGenOnly = 1;
35456 let DecoderNamespace = "EXT_mmvec";
35458 def V6_vsh : HInst<
35459 (outs HvxWR:$Vdd32),
35461 "$Vdd32.w = vsxt($Vu32.h)",
35462 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
35463 let Inst{7-5} = 0b100;
35464 let Inst{13-13} = 0b0;
35465 let Inst{31-16} = 0b0001111000000010;
35466 let hasNewValue = 1;
35467 let opNewValue = 0;
35468 let DecoderNamespace = "EXT_mmvec";
35470 def V6_vsh_alt : HInst<
35471 (outs HvxWR:$Vdd32),
35473 "$Vdd32 = vsxth($Vu32)",
35474 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35475 let hasNewValue = 1;
35476 let opNewValue = 0;
35478 let isCodeGenOnly = 1;
35479 let DecoderNamespace = "EXT_mmvec";
35481 def V6_vshufeh : HInst<
35482 (outs HvxVR:$Vd32),
35483 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35484 "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
35485 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35486 let Inst{7-5} = 0b011;
35487 let Inst{13-13} = 0b0;
35488 let Inst{31-21} = 0b00011111010;
35489 let hasNewValue = 1;
35490 let opNewValue = 0;
35491 let DecoderNamespace = "EXT_mmvec";
35493 def V6_vshufeh_alt : HInst<
35494 (outs HvxVR:$Vd32),
35495 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35496 "$Vd32 = vshuffeh($Vu32,$Vv32)",
35497 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35498 let hasNewValue = 1;
35499 let opNewValue = 0;
35501 let isCodeGenOnly = 1;
35502 let DecoderNamespace = "EXT_mmvec";
35504 def V6_vshuff : HInst<
35505 (outs HvxVR:$Vy32, HvxVR:$Vx32),
35506 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
35507 "vshuff($Vy32,$Vx32,$Rt32)",
35508 tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
35509 let Inst{7-5} = 0b001;
35510 let Inst{13-13} = 0b1;
35511 let Inst{31-21} = 0b00011001111;
35512 let hasNewValue = 1;
35513 let opNewValue = 0;
35514 let hasNewValue2 = 1;
35515 let opNewValue2 = 1;
35516 let DecoderNamespace = "EXT_mmvec";
35517 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
35519 def V6_vshuffb : HInst<
35520 (outs HvxVR:$Vd32),
35522 "$Vd32.b = vshuff($Vu32.b)",
35523 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
35524 let Inst{7-5} = 0b000;
35525 let Inst{13-13} = 0b0;
35526 let Inst{31-16} = 0b0001111000000010;
35527 let hasNewValue = 1;
35528 let opNewValue = 0;
35529 let DecoderNamespace = "EXT_mmvec";
35531 def V6_vshuffb_alt : HInst<
35532 (outs HvxVR:$Vd32),
35534 "$Vd32 = vshuffb($Vu32)",
35535 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35536 let hasNewValue = 1;
35537 let opNewValue = 0;
35539 let isCodeGenOnly = 1;
35540 let DecoderNamespace = "EXT_mmvec";
35542 def V6_vshuffeb : HInst<
35543 (outs HvxVR:$Vd32),
35544 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35545 "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
35546 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35547 let Inst{7-5} = 0b001;
35548 let Inst{13-13} = 0b0;
35549 let Inst{31-21} = 0b00011111010;
35550 let hasNewValue = 1;
35551 let opNewValue = 0;
35552 let DecoderNamespace = "EXT_mmvec";
35554 def V6_vshuffeb_alt : HInst<
35555 (outs HvxVR:$Vd32),
35556 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35557 "$Vd32 = vshuffeb($Vu32,$Vv32)",
35558 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35559 let hasNewValue = 1;
35560 let opNewValue = 0;
35562 let isCodeGenOnly = 1;
35563 let DecoderNamespace = "EXT_mmvec";
35565 def V6_vshuffh : HInst<
35566 (outs HvxVR:$Vd32),
35568 "$Vd32.h = vshuff($Vu32.h)",
35569 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
35570 let Inst{7-5} = 0b111;
35571 let Inst{13-13} = 0b0;
35572 let Inst{31-16} = 0b0001111000000001;
35573 let hasNewValue = 1;
35574 let opNewValue = 0;
35575 let DecoderNamespace = "EXT_mmvec";
35577 def V6_vshuffh_alt : HInst<
35578 (outs HvxVR:$Vd32),
35580 "$Vd32 = vshuffh($Vu32)",
35581 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35582 let hasNewValue = 1;
35583 let opNewValue = 0;
35585 let isCodeGenOnly = 1;
35586 let DecoderNamespace = "EXT_mmvec";
35588 def V6_vshuffob : HInst<
35589 (outs HvxVR:$Vd32),
35590 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35591 "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
35592 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35593 let Inst{7-5} = 0b010;
35594 let Inst{13-13} = 0b0;
35595 let Inst{31-21} = 0b00011111010;
35596 let hasNewValue = 1;
35597 let opNewValue = 0;
35598 let DecoderNamespace = "EXT_mmvec";
35600 def V6_vshuffob_alt : HInst<
35601 (outs HvxVR:$Vd32),
35602 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35603 "$Vd32 = vshuffob($Vu32,$Vv32)",
35604 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35605 let hasNewValue = 1;
35606 let opNewValue = 0;
35608 let isCodeGenOnly = 1;
35609 let DecoderNamespace = "EXT_mmvec";
35611 def V6_vshuffvdd : HInst<
35612 (outs HvxWR:$Vdd32),
35613 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
35614 "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
35615 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
35616 let Inst{7-5} = 0b011;
35617 let Inst{13-13} = 0b1;
35618 let Inst{31-24} = 0b00011011;
35619 let hasNewValue = 1;
35620 let opNewValue = 0;
35621 let DecoderNamespace = "EXT_mmvec";
35623 def V6_vshufoeb : HInst<
35624 (outs HvxWR:$Vdd32),
35625 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35626 "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
35627 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35628 let Inst{7-5} = 0b110;
35629 let Inst{13-13} = 0b0;
35630 let Inst{31-21} = 0b00011111010;
35631 let hasNewValue = 1;
35632 let opNewValue = 0;
35633 let DecoderNamespace = "EXT_mmvec";
35635 def V6_vshufoeb_alt : HInst<
35636 (outs HvxWR:$Vdd32),
35637 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35638 "$Vdd32 = vshuffoeb($Vu32,$Vv32)",
35639 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35640 let hasNewValue = 1;
35641 let opNewValue = 0;
35643 let isCodeGenOnly = 1;
35644 let DecoderNamespace = "EXT_mmvec";
35646 def V6_vshufoeh : HInst<
35647 (outs HvxWR:$Vdd32),
35648 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35649 "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
35650 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35651 let Inst{7-5} = 0b101;
35652 let Inst{13-13} = 0b0;
35653 let Inst{31-21} = 0b00011111010;
35654 let hasNewValue = 1;
35655 let opNewValue = 0;
35656 let DecoderNamespace = "EXT_mmvec";
35658 def V6_vshufoeh_alt : HInst<
35659 (outs HvxWR:$Vdd32),
35660 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35661 "$Vdd32 = vshuffoeh($Vu32,$Vv32)",
35662 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35663 let hasNewValue = 1;
35664 let opNewValue = 0;
35666 let isCodeGenOnly = 1;
35667 let DecoderNamespace = "EXT_mmvec";
35669 def V6_vshufoh : HInst<
35670 (outs HvxVR:$Vd32),
35671 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35672 "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
35673 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35674 let Inst{7-5} = 0b100;
35675 let Inst{13-13} = 0b0;
35676 let Inst{31-21} = 0b00011111010;
35677 let hasNewValue = 1;
35678 let opNewValue = 0;
35679 let DecoderNamespace = "EXT_mmvec";
35681 def V6_vshufoh_alt : HInst<
35682 (outs HvxVR:$Vd32),
35683 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35684 "$Vd32 = vshuffoh($Vu32,$Vv32)",
35685 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35686 let hasNewValue = 1;
35687 let opNewValue = 0;
35689 let isCodeGenOnly = 1;
35690 let DecoderNamespace = "EXT_mmvec";
35692 def V6_vsubb : HInst<
35693 (outs HvxVR:$Vd32),
35694 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35695 "$Vd32.b = vsub($Vu32.b,$Vv32.b)",
35696 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35697 let Inst{7-5} = 0b101;
35698 let Inst{13-13} = 0b0;
35699 let Inst{31-21} = 0b00011100010;
35700 let hasNewValue = 1;
35701 let opNewValue = 0;
35702 let DecoderNamespace = "EXT_mmvec";
35704 def V6_vsubb_alt : HInst<
35705 (outs HvxVR:$Vd32),
35706 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35707 "$Vd32 = vsubb($Vu32,$Vv32)",
35708 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35709 let hasNewValue = 1;
35710 let opNewValue = 0;
35712 let isCodeGenOnly = 1;
35713 let DecoderNamespace = "EXT_mmvec";
35715 def V6_vsubb_dv : HInst<
35716 (outs HvxWR:$Vdd32),
35717 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35718 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
35719 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35720 let Inst{7-5} = 0b011;
35721 let Inst{13-13} = 0b0;
35722 let Inst{31-21} = 0b00011100100;
35723 let hasNewValue = 1;
35724 let opNewValue = 0;
35725 let DecoderNamespace = "EXT_mmvec";
35727 def V6_vsubb_dv_alt : HInst<
35728 (outs HvxWR:$Vdd32),
35729 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35730 "$Vdd32 = vsubb($Vuu32,$Vvv32)",
35731 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35732 let hasNewValue = 1;
35733 let opNewValue = 0;
35735 let isCodeGenOnly = 1;
35736 let DecoderNamespace = "EXT_mmvec";
35738 def V6_vsubbnq : HInst<
35739 (outs HvxVR:$Vx32),
35740 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35741 "if (!$Qv4) $Vx32.b -= $Vu32.b",
35742 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
35743 let Inst{7-5} = 0b001;
35744 let Inst{13-13} = 0b1;
35745 let Inst{21-16} = 0b000010;
35746 let Inst{31-24} = 0b00011110;
35747 let hasNewValue = 1;
35748 let opNewValue = 0;
35749 let DecoderNamespace = "EXT_mmvec";
35750 let Constraints = "$Vx32 = $Vx32in";
35752 def V6_vsubbnq_alt : HInst<
35753 (outs HvxVR:$Vx32),
35754 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35755 "if (!$Qv4.b) $Vx32.b -= $Vu32.b",
35756 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35757 let hasNewValue = 1;
35758 let opNewValue = 0;
35760 let isCodeGenOnly = 1;
35761 let DecoderNamespace = "EXT_mmvec";
35762 let Constraints = "$Vx32 = $Vx32in";
35764 def V6_vsubbq : HInst<
35765 (outs HvxVR:$Vx32),
35766 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35767 "if ($Qv4) $Vx32.b -= $Vu32.b",
35768 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
35769 let Inst{7-5} = 0b110;
35770 let Inst{13-13} = 0b1;
35771 let Inst{21-16} = 0b000001;
35772 let Inst{31-24} = 0b00011110;
35773 let hasNewValue = 1;
35774 let opNewValue = 0;
35775 let DecoderNamespace = "EXT_mmvec";
35776 let Constraints = "$Vx32 = $Vx32in";
35778 def V6_vsubbq_alt : HInst<
35779 (outs HvxVR:$Vx32),
35780 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35781 "if ($Qv4.b) $Vx32.b -= $Vu32.b",
35782 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35783 let hasNewValue = 1;
35784 let opNewValue = 0;
35786 let isCodeGenOnly = 1;
35787 let DecoderNamespace = "EXT_mmvec";
35788 let Constraints = "$Vx32 = $Vx32in";
35790 def V6_vsubbsat : HInst<
35791 (outs HvxVR:$Vd32),
35792 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35793 "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
35794 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
35795 let Inst{7-5} = 0b010;
35796 let Inst{13-13} = 0b0;
35797 let Inst{31-21} = 0b00011111001;
35798 let hasNewValue = 1;
35799 let opNewValue = 0;
35800 let DecoderNamespace = "EXT_mmvec";
35802 def V6_vsubbsat_alt : HInst<
35803 (outs HvxVR:$Vd32),
35804 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35805 "$Vd32 = vsubb($Vu32,$Vv32):sat",
35806 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35807 let hasNewValue = 1;
35808 let opNewValue = 0;
35810 let isCodeGenOnly = 1;
35811 let DecoderNamespace = "EXT_mmvec";
35813 def V6_vsubbsat_dv : HInst<
35814 (outs HvxWR:$Vdd32),
35815 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35816 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
35817 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
35818 let Inst{7-5} = 0b001;
35819 let Inst{13-13} = 0b0;
35820 let Inst{31-21} = 0b00011110101;
35821 let hasNewValue = 1;
35822 let opNewValue = 0;
35823 let DecoderNamespace = "EXT_mmvec";
35825 def V6_vsubbsat_dv_alt : HInst<
35826 (outs HvxWR:$Vdd32),
35827 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35828 "$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
35829 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35830 let hasNewValue = 1;
35831 let opNewValue = 0;
35833 let isCodeGenOnly = 1;
35834 let DecoderNamespace = "EXT_mmvec";
35836 def V6_vsubcarry : HInst<
35837 (outs HvxVR:$Vd32, HvxQR:$Qx4),
35838 (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
35839 "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
35840 tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
35841 let Inst{7-7} = 0b1;
35842 let Inst{13-13} = 0b1;
35843 let Inst{31-21} = 0b00011100101;
35844 let hasNewValue = 1;
35845 let opNewValue = 0;
35846 let DecoderNamespace = "EXT_mmvec";
35847 let Constraints = "$Qx4 = $Qx4in";
35849 def V6_vsubh : HInst<
35850 (outs HvxVR:$Vd32),
35851 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35852 "$Vd32.h = vsub($Vu32.h,$Vv32.h)",
35853 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35854 let Inst{7-5} = 0b110;
35855 let Inst{13-13} = 0b0;
35856 let Inst{31-21} = 0b00011100010;
35857 let hasNewValue = 1;
35858 let opNewValue = 0;
35859 let DecoderNamespace = "EXT_mmvec";
35861 def V6_vsubh_alt : HInst<
35862 (outs HvxVR:$Vd32),
35863 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35864 "$Vd32 = vsubh($Vu32,$Vv32)",
35865 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35866 let hasNewValue = 1;
35867 let opNewValue = 0;
35869 let isCodeGenOnly = 1;
35870 let DecoderNamespace = "EXT_mmvec";
35872 def V6_vsubh_dv : HInst<
35873 (outs HvxWR:$Vdd32),
35874 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35875 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
35876 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35877 let Inst{7-5} = 0b100;
35878 let Inst{13-13} = 0b0;
35879 let Inst{31-21} = 0b00011100100;
35880 let hasNewValue = 1;
35881 let opNewValue = 0;
35882 let DecoderNamespace = "EXT_mmvec";
35884 def V6_vsubh_dv_alt : HInst<
35885 (outs HvxWR:$Vdd32),
35886 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35887 "$Vdd32 = vsubh($Vuu32,$Vvv32)",
35888 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35889 let hasNewValue = 1;
35890 let opNewValue = 0;
35892 let isCodeGenOnly = 1;
35893 let DecoderNamespace = "EXT_mmvec";
35895 def V6_vsubhnq : HInst<
35896 (outs HvxVR:$Vx32),
35897 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35898 "if (!$Qv4) $Vx32.h -= $Vu32.h",
35899 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
35900 let Inst{7-5} = 0b010;
35901 let Inst{13-13} = 0b1;
35902 let Inst{21-16} = 0b000010;
35903 let Inst{31-24} = 0b00011110;
35904 let hasNewValue = 1;
35905 let opNewValue = 0;
35906 let DecoderNamespace = "EXT_mmvec";
35907 let Constraints = "$Vx32 = $Vx32in";
35909 def V6_vsubhnq_alt : HInst<
35910 (outs HvxVR:$Vx32),
35911 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35912 "if (!$Qv4.h) $Vx32.h -= $Vu32.h",
35913 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35914 let hasNewValue = 1;
35915 let opNewValue = 0;
35917 let isCodeGenOnly = 1;
35918 let DecoderNamespace = "EXT_mmvec";
35919 let Constraints = "$Vx32 = $Vx32in";
35921 def V6_vsubhq : HInst<
35922 (outs HvxVR:$Vx32),
35923 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35924 "if ($Qv4) $Vx32.h -= $Vu32.h",
35925 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
35926 let Inst{7-5} = 0b111;
35927 let Inst{13-13} = 0b1;
35928 let Inst{21-16} = 0b000001;
35929 let Inst{31-24} = 0b00011110;
35930 let hasNewValue = 1;
35931 let opNewValue = 0;
35932 let DecoderNamespace = "EXT_mmvec";
35933 let Constraints = "$Vx32 = $Vx32in";
35935 def V6_vsubhq_alt : HInst<
35936 (outs HvxVR:$Vx32),
35937 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
35938 "if ($Qv4.h) $Vx32.h -= $Vu32.h",
35939 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35940 let hasNewValue = 1;
35941 let opNewValue = 0;
35943 let isCodeGenOnly = 1;
35944 let DecoderNamespace = "EXT_mmvec";
35945 let Constraints = "$Vx32 = $Vx32in";
35947 def V6_vsubhsat : HInst<
35948 (outs HvxVR:$Vd32),
35949 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35950 "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
35951 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35952 let Inst{7-5} = 0b010;
35953 let Inst{13-13} = 0b0;
35954 let Inst{31-21} = 0b00011100011;
35955 let hasNewValue = 1;
35956 let opNewValue = 0;
35957 let DecoderNamespace = "EXT_mmvec";
35959 def V6_vsubhsat_alt : HInst<
35960 (outs HvxVR:$Vd32),
35961 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35962 "$Vd32 = vsubh($Vu32,$Vv32):sat",
35963 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35964 let hasNewValue = 1;
35965 let opNewValue = 0;
35967 let isCodeGenOnly = 1;
35968 let DecoderNamespace = "EXT_mmvec";
35970 def V6_vsubhsat_dv : HInst<
35971 (outs HvxWR:$Vdd32),
35972 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35973 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
35974 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35975 let Inst{7-5} = 0b000;
35976 let Inst{13-13} = 0b0;
35977 let Inst{31-21} = 0b00011100101;
35978 let hasNewValue = 1;
35979 let opNewValue = 0;
35980 let DecoderNamespace = "EXT_mmvec";
35982 def V6_vsubhsat_dv_alt : HInst<
35983 (outs HvxWR:$Vdd32),
35984 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35985 "$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
35986 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35987 let hasNewValue = 1;
35988 let opNewValue = 0;
35990 let isCodeGenOnly = 1;
35991 let DecoderNamespace = "EXT_mmvec";
35993 def V6_vsubhw : HInst<
35994 (outs HvxWR:$Vdd32),
35995 (ins HvxVR:$Vu32, HvxVR:$Vv32),
35996 "$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
35997 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35998 let Inst{7-5} = 0b111;
35999 let Inst{13-13} = 0b0;
36000 let Inst{31-21} = 0b00011100101;
36001 let hasNewValue = 1;
36002 let opNewValue = 0;
36003 let DecoderNamespace = "EXT_mmvec";
36005 def V6_vsubhw_alt : HInst<
36006 (outs HvxWR:$Vdd32),
36007 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36008 "$Vdd32 = vsubh($Vu32,$Vv32)",
36009 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36010 let hasNewValue = 1;
36011 let opNewValue = 0;
36013 let isCodeGenOnly = 1;
36014 let DecoderNamespace = "EXT_mmvec";
36016 def V6_vsububh : HInst<
36017 (outs HvxWR:$Vdd32),
36018 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36019 "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
36020 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36021 let Inst{7-5} = 0b101;
36022 let Inst{13-13} = 0b0;
36023 let Inst{31-21} = 0b00011100101;
36024 let hasNewValue = 1;
36025 let opNewValue = 0;
36026 let DecoderNamespace = "EXT_mmvec";
36028 def V6_vsububh_alt : HInst<
36029 (outs HvxWR:$Vdd32),
36030 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36031 "$Vdd32 = vsubub($Vu32,$Vv32)",
36032 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36033 let hasNewValue = 1;
36034 let opNewValue = 0;
36036 let isCodeGenOnly = 1;
36037 let DecoderNamespace = "EXT_mmvec";
36039 def V6_vsububsat : HInst<
36040 (outs HvxVR:$Vd32),
36041 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36042 "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
36043 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36044 let Inst{7-5} = 0b000;
36045 let Inst{13-13} = 0b0;
36046 let Inst{31-21} = 0b00011100011;
36047 let hasNewValue = 1;
36048 let opNewValue = 0;
36049 let DecoderNamespace = "EXT_mmvec";
36051 def V6_vsububsat_alt : HInst<
36052 (outs HvxVR:$Vd32),
36053 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36054 "$Vd32 = vsubub($Vu32,$Vv32):sat",
36055 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36056 let hasNewValue = 1;
36057 let opNewValue = 0;
36059 let isCodeGenOnly = 1;
36060 let DecoderNamespace = "EXT_mmvec";
36062 def V6_vsububsat_dv : HInst<
36063 (outs HvxWR:$Vdd32),
36064 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36065 "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
36066 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36067 let Inst{7-5} = 0b110;
36068 let Inst{13-13} = 0b0;
36069 let Inst{31-21} = 0b00011100100;
36070 let hasNewValue = 1;
36071 let opNewValue = 0;
36072 let DecoderNamespace = "EXT_mmvec";
36074 def V6_vsububsat_dv_alt : HInst<
36075 (outs HvxWR:$Vdd32),
36076 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36077 "$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
36078 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36079 let hasNewValue = 1;
36080 let opNewValue = 0;
36082 let isCodeGenOnly = 1;
36083 let DecoderNamespace = "EXT_mmvec";
36085 def V6_vsubububb_sat : HInst<
36086 (outs HvxVR:$Vd32),
36087 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36088 "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
36089 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36090 let Inst{7-5} = 0b101;
36091 let Inst{13-13} = 0b0;
36092 let Inst{31-21} = 0b00011110101;
36093 let hasNewValue = 1;
36094 let opNewValue = 0;
36095 let DecoderNamespace = "EXT_mmvec";
36097 def V6_vsubuhsat : HInst<
36098 (outs HvxVR:$Vd32),
36099 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36100 "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
36101 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36102 let Inst{7-5} = 0b001;
36103 let Inst{13-13} = 0b0;
36104 let Inst{31-21} = 0b00011100011;
36105 let hasNewValue = 1;
36106 let opNewValue = 0;
36107 let DecoderNamespace = "EXT_mmvec";
36109 def V6_vsubuhsat_alt : HInst<
36110 (outs HvxVR:$Vd32),
36111 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36112 "$Vd32 = vsubuh($Vu32,$Vv32):sat",
36113 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36114 let hasNewValue = 1;
36115 let opNewValue = 0;
36117 let isCodeGenOnly = 1;
36118 let DecoderNamespace = "EXT_mmvec";
36120 def V6_vsubuhsat_dv : HInst<
36121 (outs HvxWR:$Vdd32),
36122 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36123 "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
36124 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36125 let Inst{7-5} = 0b111;
36126 let Inst{13-13} = 0b0;
36127 let Inst{31-21} = 0b00011100100;
36128 let hasNewValue = 1;
36129 let opNewValue = 0;
36130 let DecoderNamespace = "EXT_mmvec";
36132 def V6_vsubuhsat_dv_alt : HInst<
36133 (outs HvxWR:$Vdd32),
36134 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36135 "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
36136 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36137 let hasNewValue = 1;
36138 let opNewValue = 0;
36140 let isCodeGenOnly = 1;
36141 let DecoderNamespace = "EXT_mmvec";
36143 def V6_vsubuhw : HInst<
36144 (outs HvxWR:$Vdd32),
36145 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36146 "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
36147 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36148 let Inst{7-5} = 0b110;
36149 let Inst{13-13} = 0b0;
36150 let Inst{31-21} = 0b00011100101;
36151 let hasNewValue = 1;
36152 let opNewValue = 0;
36153 let DecoderNamespace = "EXT_mmvec";
36155 def V6_vsubuhw_alt : HInst<
36156 (outs HvxWR:$Vdd32),
36157 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36158 "$Vdd32 = vsubuh($Vu32,$Vv32)",
36159 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36160 let hasNewValue = 1;
36161 let opNewValue = 0;
36163 let isCodeGenOnly = 1;
36164 let DecoderNamespace = "EXT_mmvec";
36166 def V6_vsubuwsat : HInst<
36167 (outs HvxVR:$Vd32),
36168 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36169 "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
36170 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36171 let Inst{7-5} = 0b100;
36172 let Inst{13-13} = 0b0;
36173 let Inst{31-21} = 0b00011111110;
36174 let hasNewValue = 1;
36175 let opNewValue = 0;
36176 let DecoderNamespace = "EXT_mmvec";
36178 def V6_vsubuwsat_alt : HInst<
36179 (outs HvxVR:$Vd32),
36180 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36181 "$Vd32 = vsubuw($Vu32,$Vv32):sat",
36182 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36183 let hasNewValue = 1;
36184 let opNewValue = 0;
36186 let isCodeGenOnly = 1;
36187 let DecoderNamespace = "EXT_mmvec";
36189 def V6_vsubuwsat_dv : HInst<
36190 (outs HvxWR:$Vdd32),
36191 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36192 "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
36193 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
36194 let Inst{7-5} = 0b011;
36195 let Inst{13-13} = 0b0;
36196 let Inst{31-21} = 0b00011110101;
36197 let hasNewValue = 1;
36198 let opNewValue = 0;
36199 let DecoderNamespace = "EXT_mmvec";
36201 def V6_vsubuwsat_dv_alt : HInst<
36202 (outs HvxWR:$Vdd32),
36203 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36204 "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
36205 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36206 let hasNewValue = 1;
36207 let opNewValue = 0;
36209 let isCodeGenOnly = 1;
36210 let DecoderNamespace = "EXT_mmvec";
36212 def V6_vsubw : HInst<
36213 (outs HvxVR:$Vd32),
36214 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36215 "$Vd32.w = vsub($Vu32.w,$Vv32.w)",
36216 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36217 let Inst{7-5} = 0b111;
36218 let Inst{13-13} = 0b0;
36219 let Inst{31-21} = 0b00011100010;
36220 let hasNewValue = 1;
36221 let opNewValue = 0;
36222 let DecoderNamespace = "EXT_mmvec";
36224 def V6_vsubw_alt : HInst<
36225 (outs HvxVR:$Vd32),
36226 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36227 "$Vd32 = vsubw($Vu32,$Vv32)",
36228 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36229 let hasNewValue = 1;
36230 let opNewValue = 0;
36232 let isCodeGenOnly = 1;
36233 let DecoderNamespace = "EXT_mmvec";
36235 def V6_vsubw_dv : HInst<
36236 (outs HvxWR:$Vdd32),
36237 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36238 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
36239 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36240 let Inst{7-5} = 0b101;
36241 let Inst{13-13} = 0b0;
36242 let Inst{31-21} = 0b00011100100;
36243 let hasNewValue = 1;
36244 let opNewValue = 0;
36245 let DecoderNamespace = "EXT_mmvec";
36247 def V6_vsubw_dv_alt : HInst<
36248 (outs HvxWR:$Vdd32),
36249 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36250 "$Vdd32 = vsubw($Vuu32,$Vvv32)",
36251 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36252 let hasNewValue = 1;
36253 let opNewValue = 0;
36255 let isCodeGenOnly = 1;
36256 let DecoderNamespace = "EXT_mmvec";
36258 def V6_vsubwnq : HInst<
36259 (outs HvxVR:$Vx32),
36260 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36261 "if (!$Qv4) $Vx32.w -= $Vu32.w",
36262 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36263 let Inst{7-5} = 0b011;
36264 let Inst{13-13} = 0b1;
36265 let Inst{21-16} = 0b000010;
36266 let Inst{31-24} = 0b00011110;
36267 let hasNewValue = 1;
36268 let opNewValue = 0;
36269 let DecoderNamespace = "EXT_mmvec";
36270 let Constraints = "$Vx32 = $Vx32in";
36272 def V6_vsubwnq_alt : HInst<
36273 (outs HvxVR:$Vx32),
36274 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36275 "if (!$Qv4.w) $Vx32.w -= $Vu32.w",
36276 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36277 let hasNewValue = 1;
36278 let opNewValue = 0;
36280 let isCodeGenOnly = 1;
36281 let DecoderNamespace = "EXT_mmvec";
36282 let Constraints = "$Vx32 = $Vx32in";
36284 def V6_vsubwq : HInst<
36285 (outs HvxVR:$Vx32),
36286 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36287 "if ($Qv4) $Vx32.w -= $Vu32.w",
36288 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36289 let Inst{7-5} = 0b000;
36290 let Inst{13-13} = 0b1;
36291 let Inst{21-16} = 0b000010;
36292 let Inst{31-24} = 0b00011110;
36293 let hasNewValue = 1;
36294 let opNewValue = 0;
36295 let DecoderNamespace = "EXT_mmvec";
36296 let Constraints = "$Vx32 = $Vx32in";
36298 def V6_vsubwq_alt : HInst<
36299 (outs HvxVR:$Vx32),
36300 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36301 "if ($Qv4.w) $Vx32.w -= $Vu32.w",
36302 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36303 let hasNewValue = 1;
36304 let opNewValue = 0;
36306 let isCodeGenOnly = 1;
36307 let DecoderNamespace = "EXT_mmvec";
36308 let Constraints = "$Vx32 = $Vx32in";
36310 def V6_vsubwsat : HInst<
36311 (outs HvxVR:$Vd32),
36312 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36313 "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
36314 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36315 let Inst{7-5} = 0b011;
36316 let Inst{13-13} = 0b0;
36317 let Inst{31-21} = 0b00011100011;
36318 let hasNewValue = 1;
36319 let opNewValue = 0;
36320 let DecoderNamespace = "EXT_mmvec";
36322 def V6_vsubwsat_alt : HInst<
36323 (outs HvxVR:$Vd32),
36324 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36325 "$Vd32 = vsubw($Vu32,$Vv32):sat",
36326 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36327 let hasNewValue = 1;
36328 let opNewValue = 0;
36330 let isCodeGenOnly = 1;
36331 let DecoderNamespace = "EXT_mmvec";
36333 def V6_vsubwsat_dv : HInst<
36334 (outs HvxWR:$Vdd32),
36335 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36336 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
36337 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36338 let Inst{7-5} = 0b001;
36339 let Inst{13-13} = 0b0;
36340 let Inst{31-21} = 0b00011100101;
36341 let hasNewValue = 1;
36342 let opNewValue = 0;
36343 let DecoderNamespace = "EXT_mmvec";
36345 def V6_vsubwsat_dv_alt : HInst<
36346 (outs HvxWR:$Vdd32),
36347 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36348 "$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
36349 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36350 let hasNewValue = 1;
36351 let opNewValue = 0;
36353 let isCodeGenOnly = 1;
36354 let DecoderNamespace = "EXT_mmvec";
36356 def V6_vswap : HInst<
36357 (outs HvxWR:$Vdd32),
36358 (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
36359 "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
36360 tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
36361 let Inst{7-7} = 0b0;
36362 let Inst{13-13} = 0b1;
36363 let Inst{31-21} = 0b00011110101;
36364 let hasNewValue = 1;
36365 let opNewValue = 0;
36366 let DecoderNamespace = "EXT_mmvec";
36368 def V6_vtmpyb : HInst<
36369 (outs HvxWR:$Vdd32),
36370 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36371 "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
36372 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36373 let Inst{7-5} = 0b000;
36374 let Inst{13-13} = 0b0;
36375 let Inst{31-21} = 0b00011001000;
36376 let hasNewValue = 1;
36377 let opNewValue = 0;
36378 let DecoderNamespace = "EXT_mmvec";
36380 def V6_vtmpyb_acc : HInst<
36381 (outs HvxWR:$Vxx32),
36382 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36383 "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
36384 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
36385 let Inst{7-5} = 0b000;
36386 let Inst{13-13} = 0b1;
36387 let Inst{31-21} = 0b00011001000;
36388 let hasNewValue = 1;
36389 let opNewValue = 0;
36390 let isAccumulator = 1;
36391 let DecoderNamespace = "EXT_mmvec";
36392 let Constraints = "$Vxx32 = $Vxx32in";
36394 def V6_vtmpyb_acc_alt : HInst<
36395 (outs HvxWR:$Vxx32),
36396 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36397 "$Vxx32 += vtmpyb($Vuu32,$Rt32)",
36398 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36399 let hasNewValue = 1;
36400 let opNewValue = 0;
36401 let isAccumulator = 1;
36403 let isCodeGenOnly = 1;
36404 let DecoderNamespace = "EXT_mmvec";
36405 let Constraints = "$Vxx32 = $Vxx32in";
36407 def V6_vtmpyb_alt : HInst<
36408 (outs HvxWR:$Vdd32),
36409 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36410 "$Vdd32 = vtmpyb($Vuu32,$Rt32)",
36411 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36412 let hasNewValue = 1;
36413 let opNewValue = 0;
36415 let isCodeGenOnly = 1;
36416 let DecoderNamespace = "EXT_mmvec";
36418 def V6_vtmpybus : HInst<
36419 (outs HvxWR:$Vdd32),
36420 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36421 "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
36422 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36423 let Inst{7-5} = 0b001;
36424 let Inst{13-13} = 0b0;
36425 let Inst{31-21} = 0b00011001000;
36426 let hasNewValue = 1;
36427 let opNewValue = 0;
36428 let DecoderNamespace = "EXT_mmvec";
36430 def V6_vtmpybus_acc : HInst<
36431 (outs HvxWR:$Vxx32),
36432 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36433 "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
36434 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
36435 let Inst{7-5} = 0b001;
36436 let Inst{13-13} = 0b1;
36437 let Inst{31-21} = 0b00011001000;
36438 let hasNewValue = 1;
36439 let opNewValue = 0;
36440 let isAccumulator = 1;
36441 let DecoderNamespace = "EXT_mmvec";
36442 let Constraints = "$Vxx32 = $Vxx32in";
36444 def V6_vtmpybus_acc_alt : HInst<
36445 (outs HvxWR:$Vxx32),
36446 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36447 "$Vxx32 += vtmpybus($Vuu32,$Rt32)",
36448 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36449 let hasNewValue = 1;
36450 let opNewValue = 0;
36451 let isAccumulator = 1;
36453 let isCodeGenOnly = 1;
36454 let DecoderNamespace = "EXT_mmvec";
36455 let Constraints = "$Vxx32 = $Vxx32in";
36457 def V6_vtmpybus_alt : HInst<
36458 (outs HvxWR:$Vdd32),
36459 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36460 "$Vdd32 = vtmpybus($Vuu32,$Rt32)",
36461 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36462 let hasNewValue = 1;
36463 let opNewValue = 0;
36465 let isCodeGenOnly = 1;
36466 let DecoderNamespace = "EXT_mmvec";
36468 def V6_vtmpyhb : HInst<
36469 (outs HvxWR:$Vdd32),
36470 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36471 "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
36472 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36473 let Inst{7-5} = 0b100;
36474 let Inst{13-13} = 0b0;
36475 let Inst{31-21} = 0b00011001101;
36476 let hasNewValue = 1;
36477 let opNewValue = 0;
36478 let DecoderNamespace = "EXT_mmvec";
36480 def V6_vtmpyhb_acc : HInst<
36481 (outs HvxWR:$Vxx32),
36482 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36483 "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
36484 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
36485 let Inst{7-5} = 0b010;
36486 let Inst{13-13} = 0b1;
36487 let Inst{31-21} = 0b00011001000;
36488 let hasNewValue = 1;
36489 let opNewValue = 0;
36490 let isAccumulator = 1;
36491 let DecoderNamespace = "EXT_mmvec";
36492 let Constraints = "$Vxx32 = $Vxx32in";
36494 def V6_vtmpyhb_acc_alt : HInst<
36495 (outs HvxWR:$Vxx32),
36496 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36497 "$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
36498 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36499 let hasNewValue = 1;
36500 let opNewValue = 0;
36501 let isAccumulator = 1;
36503 let isCodeGenOnly = 1;
36504 let DecoderNamespace = "EXT_mmvec";
36505 let Constraints = "$Vxx32 = $Vxx32in";
36507 def V6_vtmpyhb_alt : HInst<
36508 (outs HvxWR:$Vdd32),
36509 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
36510 "$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
36511 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36512 let hasNewValue = 1;
36513 let opNewValue = 0;
36515 let isCodeGenOnly = 1;
36516 let DecoderNamespace = "EXT_mmvec";
36518 def V6_vtran2x2_map : HInst<
36519 (outs HvxVR:$Vy32, HvxVR:$Vx32),
36520 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
36521 "vtrans2x2($Vy32,$Vx32,$Rt32)",
36522 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36523 let hasNewValue = 1;
36524 let opNewValue = 0;
36525 let hasNewValue2 = 1;
36526 let opNewValue2 = 1;
36528 let isCodeGenOnly = 1;
36529 let DecoderNamespace = "EXT_mmvec";
36530 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
36532 def V6_vunpackb : HInst<
36533 (outs HvxWR:$Vdd32),
36535 "$Vdd32.h = vunpack($Vu32.b)",
36536 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
36537 let Inst{7-5} = 0b010;
36538 let Inst{13-13} = 0b0;
36539 let Inst{31-16} = 0b0001111000000001;
36540 let hasNewValue = 1;
36541 let opNewValue = 0;
36542 let DecoderNamespace = "EXT_mmvec";
36544 def V6_vunpackb_alt : HInst<
36545 (outs HvxWR:$Vdd32),
36547 "$Vdd32 = vunpackb($Vu32)",
36548 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36549 let hasNewValue = 1;
36550 let opNewValue = 0;
36552 let isCodeGenOnly = 1;
36553 let DecoderNamespace = "EXT_mmvec";
36555 def V6_vunpackh : HInst<
36556 (outs HvxWR:$Vdd32),
36558 "$Vdd32.w = vunpack($Vu32.h)",
36559 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
36560 let Inst{7-5} = 0b011;
36561 let Inst{13-13} = 0b0;
36562 let Inst{31-16} = 0b0001111000000001;
36563 let hasNewValue = 1;
36564 let opNewValue = 0;
36565 let DecoderNamespace = "EXT_mmvec";
36567 def V6_vunpackh_alt : HInst<
36568 (outs HvxWR:$Vdd32),
36570 "$Vdd32 = vunpackh($Vu32)",
36571 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36572 let hasNewValue = 1;
36573 let opNewValue = 0;
36575 let isCodeGenOnly = 1;
36576 let DecoderNamespace = "EXT_mmvec";
36578 def V6_vunpackob : HInst<
36579 (outs HvxWR:$Vxx32),
36580 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
36581 "$Vxx32.h |= vunpacko($Vu32.b)",
36582 tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
36583 let Inst{7-5} = 0b000;
36584 let Inst{13-13} = 0b1;
36585 let Inst{31-16} = 0b0001111000000000;
36586 let hasNewValue = 1;
36587 let opNewValue = 0;
36588 let isAccumulator = 1;
36589 let DecoderNamespace = "EXT_mmvec";
36590 let Constraints = "$Vxx32 = $Vxx32in";
36592 def V6_vunpackob_alt : HInst<
36593 (outs HvxWR:$Vxx32),
36594 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
36595 "$Vxx32 |= vunpackob($Vu32)",
36596 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36597 let hasNewValue = 1;
36598 let opNewValue = 0;
36599 let isAccumulator = 1;
36601 let DecoderNamespace = "EXT_mmvec";
36602 let Constraints = "$Vxx32 = $Vxx32in";
36604 def V6_vunpackoh : HInst<
36605 (outs HvxWR:$Vxx32),
36606 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
36607 "$Vxx32.w |= vunpacko($Vu32.h)",
36608 tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
36609 let Inst{7-5} = 0b001;
36610 let Inst{13-13} = 0b1;
36611 let Inst{31-16} = 0b0001111000000000;
36612 let hasNewValue = 1;
36613 let opNewValue = 0;
36614 let isAccumulator = 1;
36615 let DecoderNamespace = "EXT_mmvec";
36616 let Constraints = "$Vxx32 = $Vxx32in";
36618 def V6_vunpackoh_alt : HInst<
36619 (outs HvxWR:$Vxx32),
36620 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
36621 "$Vxx32 |= vunpackoh($Vu32)",
36622 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36623 let hasNewValue = 1;
36624 let opNewValue = 0;
36625 let isAccumulator = 1;
36627 let isCodeGenOnly = 1;
36628 let DecoderNamespace = "EXT_mmvec";
36629 let Constraints = "$Vxx32 = $Vxx32in";
36631 def V6_vunpackub : HInst<
36632 (outs HvxWR:$Vdd32),
36634 "$Vdd32.uh = vunpack($Vu32.ub)",
36635 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
36636 let Inst{7-5} = 0b000;
36637 let Inst{13-13} = 0b0;
36638 let Inst{31-16} = 0b0001111000000001;
36639 let hasNewValue = 1;
36640 let opNewValue = 0;
36641 let DecoderNamespace = "EXT_mmvec";
36643 def V6_vunpackub_alt : HInst<
36644 (outs HvxWR:$Vdd32),
36646 "$Vdd32 = vunpackub($Vu32)",
36647 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36648 let hasNewValue = 1;
36649 let opNewValue = 0;
36651 let isCodeGenOnly = 1;
36652 let DecoderNamespace = "EXT_mmvec";
36654 def V6_vunpackuh : HInst<
36655 (outs HvxWR:$Vdd32),
36657 "$Vdd32.uw = vunpack($Vu32.uh)",
36658 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
36659 let Inst{7-5} = 0b001;
36660 let Inst{13-13} = 0b0;
36661 let Inst{31-16} = 0b0001111000000001;
36662 let hasNewValue = 1;
36663 let opNewValue = 0;
36664 let DecoderNamespace = "EXT_mmvec";
36666 def V6_vunpackuh_alt : HInst<
36667 (outs HvxWR:$Vdd32),
36669 "$Vdd32 = vunpackuh($Vu32)",
36670 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36671 let hasNewValue = 1;
36672 let opNewValue = 0;
36674 let isCodeGenOnly = 1;
36675 let DecoderNamespace = "EXT_mmvec";
36677 def V6_vwhist128 : HInst<
36681 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
36682 let Inst{13-0} = 0b10010010000000;
36683 let Inst{31-16} = 0b0001111000000000;
36684 let DecoderNamespace = "EXT_mmvec";
36686 def V6_vwhist128m : HInst<
36690 tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
36691 let Inst{7-0} = 0b10000000;
36692 let Inst{13-9} = 0b10011;
36693 let Inst{31-16} = 0b0001111000000000;
36694 let DecoderNamespace = "EXT_mmvec";
36696 def V6_vwhist128q : HInst<
36700 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
36701 let Inst{13-0} = 0b10010010000000;
36702 let Inst{21-16} = 0b000010;
36703 let Inst{31-24} = 0b00011110;
36704 let DecoderNamespace = "EXT_mmvec";
36706 def V6_vwhist128qm : HInst<
36708 (ins HvxQR:$Qv4, u1_0Imm:$Ii),
36709 "vwhist128($Qv4,#$Ii)",
36710 tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
36711 let Inst{7-0} = 0b10000000;
36712 let Inst{13-9} = 0b10011;
36713 let Inst{21-16} = 0b000010;
36714 let Inst{31-24} = 0b00011110;
36715 let DecoderNamespace = "EXT_mmvec";
36717 def V6_vwhist256 : HInst<
36721 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
36722 let Inst{13-0} = 0b10001010000000;
36723 let Inst{31-16} = 0b0001111000000000;
36724 let DecoderNamespace = "EXT_mmvec";
36726 def V6_vwhist256_sat : HInst<
36730 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
36731 let Inst{13-0} = 0b10001110000000;
36732 let Inst{31-16} = 0b0001111000000000;
36733 let DecoderNamespace = "EXT_mmvec";
36735 def V6_vwhist256q : HInst<
36739 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
36740 let Inst{13-0} = 0b10001010000000;
36741 let Inst{21-16} = 0b000010;
36742 let Inst{31-24} = 0b00011110;
36743 let DecoderNamespace = "EXT_mmvec";
36745 def V6_vwhist256q_sat : HInst<
36748 "vwhist256($Qv4):sat",
36749 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
36750 let Inst{13-0} = 0b10001110000000;
36751 let Inst{21-16} = 0b000010;
36752 let Inst{31-24} = 0b00011110;
36753 let DecoderNamespace = "EXT_mmvec";
36755 def V6_vxor : HInst<
36756 (outs HvxVR:$Vd32),
36757 (ins HvxVR:$Vu32, HvxVR:$Vv32),
36758 "$Vd32 = vxor($Vu32,$Vv32)",
36759 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36760 let Inst{7-5} = 0b111;
36761 let Inst{13-13} = 0b0;
36762 let Inst{31-21} = 0b00011100001;
36763 let hasNewValue = 1;
36764 let opNewValue = 0;
36765 let DecoderNamespace = "EXT_mmvec";
36767 def V6_vzb : HInst<
36768 (outs HvxWR:$Vdd32),
36770 "$Vdd32.uh = vzxt($Vu32.ub)",
36771 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
36772 let Inst{7-5} = 0b001;
36773 let Inst{13-13} = 0b0;
36774 let Inst{31-16} = 0b0001111000000010;
36775 let hasNewValue = 1;
36776 let opNewValue = 0;
36777 let DecoderNamespace = "EXT_mmvec";
36779 def V6_vzb_alt : HInst<
36780 (outs HvxWR:$Vdd32),
36782 "$Vdd32 = vzxtb($Vu32)",
36783 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36784 let hasNewValue = 1;
36785 let opNewValue = 0;
36787 let isCodeGenOnly = 1;
36788 let DecoderNamespace = "EXT_mmvec";
36790 def V6_vzh : HInst<
36791 (outs HvxWR:$Vdd32),
36793 "$Vdd32.uw = vzxt($Vu32.uh)",
36794 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
36795 let Inst{7-5} = 0b010;
36796 let Inst{13-13} = 0b0;
36797 let Inst{31-16} = 0b0001111000000010;
36798 let hasNewValue = 1;
36799 let opNewValue = 0;
36800 let DecoderNamespace = "EXT_mmvec";
36802 def V6_vzh_alt : HInst<
36803 (outs HvxWR:$Vdd32),
36805 "$Vdd32 = vzxth($Vu32)",
36806 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36807 let hasNewValue = 1;
36808 let opNewValue = 0;
36810 let isCodeGenOnly = 1;
36811 let DecoderNamespace = "EXT_mmvec";
36813 def Y2_barrier : HInst<
36817 tc_367f7f3d, TypeST>, Enc_e3b0c4 {
36818 let Inst{13-0} = 0b00000000000000;
36819 let Inst{31-16} = 0b1010100000000000;
36821 let hasSideEffects = 1;
36823 def Y2_break : HInst<
36827 tc_4ca572d4, TypeCR>, Enc_e3b0c4 {
36828 let Inst{13-0} = 0b00000000000000;
36829 let Inst{31-16} = 0b0110110000100000;
36832 def Y2_dccleana : HInst<
36834 (ins IntRegs:$Rs32),
36836 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
36837 let Inst{13-0} = 0b00000000000000;
36838 let Inst{31-21} = 0b10100000000;
36839 let isRestrictSlot1AOK = 1;
36840 let hasSideEffects = 1;
36842 def Y2_dccleaninva : HInst<
36844 (ins IntRegs:$Rs32),
36845 "dccleaninva($Rs32)",
36846 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
36847 let Inst{13-0} = 0b00000000000000;
36848 let Inst{31-21} = 0b10100000010;
36849 let isRestrictSlot1AOK = 1;
36850 let hasSideEffects = 1;
36852 def Y2_dcfetch : HInst<
36854 (ins IntRegs:$Rs32),
36856 tc_3da80ba5, TypeMAPPING> {
36857 let hasSideEffects = 1;
36859 let isCodeGenOnly = 1;
36861 def Y2_dcfetchbo : HInst<
36863 (ins IntRegs:$Rs32, u11_3Imm:$Ii),
36864 "dcfetch($Rs32+#$Ii)",
36865 tc_4d9914c9, TypeLD>, Enc_2d829e {
36866 let Inst{13-11} = 0b000;
36867 let Inst{31-21} = 0b10010100000;
36868 let addrMode = BaseImmOffset;
36869 let isRestrictNoSlot1Store = 1;
36870 let hasSideEffects = 1;
36872 def Y2_dcinva : HInst<
36874 (ins IntRegs:$Rs32),
36876 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
36877 let Inst{13-0} = 0b00000000000000;
36878 let Inst{31-21} = 0b10100000001;
36879 let isRestrictSlot1AOK = 1;
36880 let hasSideEffects = 1;
36882 def Y2_dczeroa : HInst<
36884 (ins IntRegs:$Rs32),
36886 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
36887 let Inst{13-0} = 0b00000000000000;
36888 let Inst{31-21} = 0b10100000110;
36889 let isRestrictSlot1AOK = 1;
36891 let hasSideEffects = 1;
36893 def Y2_icinva : HInst<
36895 (ins IntRegs:$Rs32),
36897 tc_999d32db, TypeJ>, Enc_ecbcc8 {
36898 let Inst{13-0} = 0b00000000000000;
36899 let Inst{31-21} = 0b01010110110;
36902 def Y2_isync : HInst<
36906 tc_b13761ae, TypeJ>, Enc_e3b0c4 {
36907 let Inst{13-0} = 0b00000000000010;
36908 let Inst{31-16} = 0b0101011111000000;
36911 def Y2_syncht : HInst<
36915 tc_367f7f3d, TypeST>, Enc_e3b0c4 {
36916 let Inst{13-0} = 0b00000000000000;
36917 let Inst{31-16} = 0b1010100001000000;
36920 def Y4_l2fetch : HInst<
36922 (ins IntRegs:$Rs32, IntRegs:$Rt32),
36923 "l2fetch($Rs32,$Rt32)",
36924 tc_daa058fa, TypeST>, Enc_ca3887 {
36925 let Inst{7-0} = 0b00000000;
36926 let Inst{13-13} = 0b0;
36927 let Inst{31-21} = 0b10100110000;
36930 let hasSideEffects = 1;
36932 def Y4_trace : HInst<
36934 (ins IntRegs:$Rs32),
36936 tc_c82dc1ff, TypeCR>, Enc_ecbcc8 {
36937 let Inst{13-0} = 0b00000000000000;
36938 let Inst{31-21} = 0b01100010010;
36941 def Y5_l2fetch : HInst<
36943 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
36944 "l2fetch($Rs32,$Rtt32)",
36945 tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5T]> {
36946 let Inst{7-0} = 0b00000000;
36947 let Inst{13-13} = 0b0;
36948 let Inst{31-21} = 0b10100110100;
36951 let hasSideEffects = 1;
36953 def dep_A2_addsat : HInst<
36954 (outs IntRegs:$Rd32),
36955 (ins IntRegs:$Rs32, IntRegs:$Rt32),
36956 "$Rd32 = add($Rs32,$Rt32):sat:deprecated",
36957 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
36958 let Inst{7-5} = 0b000;
36959 let Inst{13-13} = 0b0;
36960 let Inst{31-21} = 0b11010101100;
36961 let hasNewValue = 1;
36962 let opNewValue = 0;
36963 let prefersSlot3 = 1;
36964 let Defs = [USR_OVF];
36966 def dep_A2_subsat : HInst<
36967 (outs IntRegs:$Rd32),
36968 (ins IntRegs:$Rt32, IntRegs:$Rs32),
36969 "$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
36970 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
36971 let Inst{7-5} = 0b100;
36972 let Inst{13-13} = 0b0;
36973 let Inst{31-21} = 0b11010101100;
36974 let hasNewValue = 1;
36975 let opNewValue = 0;
36976 let prefersSlot3 = 1;
36977 let Defs = [USR_OVF];
36979 def dep_S2_packhl : HInst<
36980 (outs DoubleRegs:$Rdd32),
36981 (ins IntRegs:$Rs32, IntRegs:$Rt32),
36982 "$Rdd32 = packhl($Rs32,$Rt32):deprecated",
36983 tc_540fdfbc, TypeALU64>, Enc_be32a5 {
36984 let Inst{7-5} = 0b000;
36985 let Inst{13-13} = 0b0;
36986 let Inst{31-21} = 0b11010100000;