1 //===--- HexagonExpandCondsets.cpp ----------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Replace mux instructions with the corresponding legal instructions.
11 // It is meant to work post-SSA, but still on virtual registers. It was
12 // originally placed between register coalescing and machine instruction
14 // In this place in the optimization sequence, live interval analysis had
15 // been performed, and the live intervals should be preserved. A large part
16 // of the code deals with preserving the liveness information.
18 // Liveness tracking aside, the main functionality of this pass is divided
19 // into two steps. The first step is to replace an instruction
20 // vreg0 = C2_mux vreg1, vreg2, vreg3
21 // with a pair of conditional transfers
22 // vreg0 = A2_tfrt vreg1, vreg2
23 // vreg0 = A2_tfrf vreg1, vreg3
24 // It is the intention that the execution of this pass could be terminated
25 // after this step, and the code generated would be functionally correct.
27 // If the uses of the source values vreg1 and vreg2 are kills, and their
28 // definitions are predicable, then in the second step, the conditional
29 // transfers will then be rewritten as predicated instructions. E.g.
30 // vreg0 = A2_or vreg1, vreg2
31 // vreg3 = A2_tfrt vreg99, vreg0<kill>
32 // will be rewritten as
33 // vreg3 = A2_port vreg99, vreg1, vreg2
35 // This replacement has two variants: "up" and "down". Consider this case:
36 // vreg0 = A2_or vreg1, vreg2
37 // ... [intervening instructions] ...
38 // vreg3 = A2_tfrt vreg99, vreg0<kill>
40 // vreg3 = A2_port vreg99, vreg1, vreg2
41 // ... [intervening instructions, vreg0->vreg3] ...
45 // ... [intervening instructions] ...
46 // vreg3 = A2_port vreg99, vreg1, vreg2
48 // Both, one or none of these variants may be valid, and checks are made
49 // to rule out inapplicable variants.
51 // As an additional optimization, before either of the two steps above is
52 // executed, the pass attempts to coalesce the target register with one of
53 // the source registers, e.g. given an instruction
54 // vreg3 = C2_mux vreg0, vreg1, vreg2
55 // vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds,
56 // the instruction would then be (for example)
57 // vreg3 = C2_mux vreg0, vreg3, vreg2
58 // and, under certain circumstances, this could result in only one predicated
60 // vreg3 = A2_tfrf vreg0, vreg2
63 // Splitting a definition of a register into two predicated transfers
64 // creates a complication in liveness tracking. Live interval computation
65 // will see both instructions as actual definitions, and will mark the
66 // first one as dead. The definition is not actually dead, and this
67 // situation will need to be fixed. For example:
68 // vreg1<def,dead> = A2_tfrt ... ; marked as dead
69 // vreg1<def> = A2_tfrf ...
71 // Since any of the individual predicated transfers may end up getting
72 // removed (in case it is an identity copy), some pre-existing def may
73 // be marked as dead after live interval recomputation:
74 // vreg1<def,dead> = ... ; marked as dead
76 // vreg1<def> = A2_tfrf ... ; if A2_tfrt is removed
77 // This case happens if vreg1 was used as a source in A2_tfrt, which means
78 // that is it actually live at the A2_tfrf, and so the now dead definition
79 // of vreg1 will need to be updated to non-dead at some point.
81 // This issue could be remedied by adding implicit uses to the predicated
82 // transfers, but this will create a problem with subsequent predication,
83 // since the transfers will no longer be possible to reorder. To avoid
84 // that, the initial splitting will not add any implicit uses. These
85 // implicit uses will be added later, after predication. The extra price,
86 // however, is that finding the locations where the implicit uses need
87 // to be added, and updating the live ranges will be more involved.
89 #define DEBUG_TYPE "expand-condsets"
91 #include "HexagonInstrInfo.h"
92 #include "llvm/ADT/DenseMap.h"
93 #include "llvm/ADT/SetVector.h"
94 #include "llvm/ADT/SmallVector.h"
95 #include "llvm/ADT/StringRef.h"
96 #include "llvm/CodeGen/LiveInterval.h"
97 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
98 #include "llvm/CodeGen/MachineBasicBlock.h"
99 #include "llvm/CodeGen/MachineDominators.h"
100 #include "llvm/CodeGen/MachineFunction.h"
101 #include "llvm/CodeGen/MachineFunctionPass.h"
102 #include "llvm/CodeGen/MachineInstr.h"
103 #include "llvm/CodeGen/MachineInstrBuilder.h"
104 #include "llvm/CodeGen/MachineOperand.h"
105 #include "llvm/CodeGen/MachineRegisterInfo.h"
106 #include "llvm/CodeGen/SlotIndexes.h"
107 #include "llvm/IR/DebugLoc.h"
108 #include "llvm/Pass.h"
109 #include "llvm/Support/CommandLine.h"
110 #include "llvm/Support/Debug.h"
111 #include "llvm/Support/ErrorHandling.h"
112 #include "llvm/Support/raw_ostream.h"
113 #include "llvm/Target/TargetRegisterInfo.h"
119 using namespace llvm;
121 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
122 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
123 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
124 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
128 void initializeHexagonExpandCondsetsPass(PassRegistry&);
129 FunctionPass *createHexagonExpandCondsets();
131 } // end namespace llvm
135 class HexagonExpandCondsets : public MachineFunctionPass {
139 HexagonExpandCondsets() :
140 MachineFunctionPass(ID), HII(nullptr), TRI(nullptr), MRI(nullptr),
141 LIS(nullptr), CoaLimitActive(false),
142 TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
143 if (OptCoaLimit.getPosition())
144 CoaLimitActive = true, CoaLimit = OptCoaLimit;
145 if (OptTfrLimit.getPosition())
146 TfrLimitActive = true, TfrLimit = OptTfrLimit;
147 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
150 StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
152 void getAnalysisUsage(AnalysisUsage &AU) const override {
153 AU.addRequired<LiveIntervals>();
154 AU.addPreserved<LiveIntervals>();
155 AU.addPreserved<SlotIndexes>();
156 AU.addRequired<MachineDominatorTree>();
157 AU.addPreserved<MachineDominatorTree>();
158 MachineFunctionPass::getAnalysisUsage(AU);
161 bool runOnMachineFunction(MachineFunction &MF) override;
164 const HexagonInstrInfo *HII;
165 const TargetRegisterInfo *TRI;
166 MachineDominatorTree *MDT;
167 MachineRegisterInfo *MRI;
170 bool CoaLimitActive, TfrLimitActive;
171 unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
174 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
175 Sub(Op.getSubReg()) {}
176 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
178 bool operator== (RegisterRef RR) const {
179 return Reg == RR.Reg && Sub == RR.Sub;
181 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
182 bool operator< (RegisterRef RR) const {
183 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
189 typedef DenseMap<unsigned,unsigned> ReferenceMap;
190 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
191 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
192 unsigned getMaskForSub(unsigned Sub);
193 bool isCondset(const MachineInstr &MI);
194 LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
196 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
197 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
199 void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
200 void updateKillFlags(unsigned Reg);
201 void updateDeadFlags(unsigned Reg);
202 void recalculateLiveInterval(unsigned Reg);
203 void removeInstr(MachineInstr &MI);
204 void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
205 bool UpdateKills, bool UpdateDeads);
207 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
208 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
209 MachineBasicBlock::iterator At, unsigned DstR,
210 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
211 bool ReadUndef, bool ImpUse);
212 bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
214 bool isPredicable(MachineInstr *MI);
215 MachineInstr *getReachingDefForPred(RegisterRef RD,
216 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
217 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
218 bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
219 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
220 MachineBasicBlock::iterator Where,
221 const MachineOperand &PredOp, bool Cond,
222 std::set<unsigned> &UpdRegs);
223 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
224 bool Cond, MachineBasicBlock::iterator First,
225 MachineBasicBlock::iterator Last);
226 bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
227 bool predicateInBlock(MachineBasicBlock &B,
228 std::set<unsigned> &UpdRegs);
230 bool isIntReg(RegisterRef RR, unsigned &BW);
231 bool isIntraBlocks(LiveInterval &LI);
232 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
233 bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
234 std::set<unsigned> &UpdRegs);
237 } // end anonymous namespace
239 char HexagonExpandCondsets::ID = 0;
243 char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID;
245 } // end namespace llvm
247 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
248 "Hexagon Expand Condsets", false, false)
249 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
250 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
251 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
252 INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets",
253 "Hexagon Expand Condsets", false, false)
255 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
257 case Hexagon::isub_lo:
258 case Hexagon::vsub_lo:
260 case Hexagon::isub_hi:
261 case Hexagon::vsub_hi:
263 case Hexagon::NoSubRegister:
266 llvm_unreachable("Invalid subregister");
269 bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
270 unsigned Opc = MI.getOpcode();
272 case Hexagon::C2_mux:
273 case Hexagon::C2_muxii:
274 case Hexagon::C2_muxir:
275 case Hexagon::C2_muxri:
276 case Hexagon::PS_pselect:
283 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
284 assert(TargetRegisterInfo::isVirtualRegister(Reg));
285 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
286 : MRI->getMaxLaneMaskForVReg(Reg);
289 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
291 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
292 ReferenceMap::iterator F = Map.find(RR.Reg);
294 Map.insert(std::make_pair(RR.Reg, Mask));
299 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
301 ReferenceMap::iterator F = Map.find(RR.Reg);
304 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
305 if (Mask & F->second)
310 void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
311 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
312 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
313 MachineInstr *MI = LIS->getInstructionFromIndex(K);
314 for (auto &Op : MI->operands()) {
315 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
317 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
318 if ((SLM & LM) == SLM) {
319 // Only set the kill flag on the first encountered use of Reg in this
327 LiveInterval &LI = LIS->getInterval(Reg);
328 for (auto I = LI.begin(), E = LI.end(); I != E; ++I) {
329 if (!I->end.isRegister())
331 // Do not mark the end of the segment as <kill>, if the next segment
332 // starts with a predicated instruction.
333 auto NextI = std::next(I);
334 if (NextI != E && NextI->start.isRegister()) {
335 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
336 if (HII->isPredicated(*DefI))
339 bool WholeReg = true;
340 if (LI.hasSubRanges()) {
341 auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool {
342 LiveRange::iterator F = S.find(I->end);
343 return F != S.end() && I->end == F->end;
345 // Check if all subranges end at I->end. If so, make sure to kill
346 // the whole register.
347 for (LiveInterval::SubRange &S : LI.subranges()) {
349 KillAt(I->end, S.LaneMask);
355 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
359 void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
361 assert(TargetRegisterInfo::isVirtualRegister(Reg));
365 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool {
366 if (!Op.isReg() || !Op.isDef())
368 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
369 if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
371 LaneBitmask SLM = getLaneMask(DR, DSR);
372 return (SLM & LM).any();
375 // The splitting step will create pairs of predicated definitions without
376 // any implicit uses (since implicit uses would interfere with predication).
377 // This can cause the reaching defs to become dead after live range
378 // recomputation, even though they are not really dead.
379 // We need to identify predicated defs that need implicit uses, and
380 // dead defs that are not really dead, and correct both problems.
382 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
383 MachineBasicBlock *Dest) -> bool {
384 for (MachineBasicBlock *D : Defs)
385 if (D != Dest && MDT->dominates(D, Dest))
388 MachineBasicBlock *Entry = &Dest->getParent()->front();
389 SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end());
390 for (unsigned i = 0; i < Work.size(); ++i) {
391 MachineBasicBlock *B = Work[i];
396 for (auto *P : B->predecessors())
402 // First, try to extend live range within individual basic blocks. This
403 // will leave us only with dead defs that do not reach any predicated
404 // defs in the same block.
405 SetVector<MachineBasicBlock*> Defs;
406 SmallVector<SlotIndex,4> PredDefs;
407 for (auto &Seg : Range) {
408 if (!Seg.start.isRegister())
410 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
411 Defs.insert(DefI->getParent());
412 if (HII->isPredicated(*DefI))
413 PredDefs.push_back(Seg.start);
416 SmallVector<SlotIndex,8> Undefs;
417 LiveInterval &LI = LIS->getInterval(Reg);
418 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes());
420 for (auto &SI : PredDefs) {
421 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
422 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
423 if (P.first != nullptr || P.second)
427 // Calculate reachability for those predicated defs that were not handled
428 // by the in-block extension.
429 SmallVector<SlotIndex,4> ExtTo;
430 for (auto &SI : PredDefs) {
433 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
434 if (BB->pred_empty())
436 // If the defs from this range reach SI via all predecessors, it is live.
437 // It can happen that SI is reached by the defs through some paths, but
438 // not all. In the IR coming into this optimization, SI would not be
439 // considered live, since the defs would then not jointly dominate SI.
440 // That means that SI is an overwriting def, and no implicit use is
441 // needed at this point. Do not add SI to the extension points, since
442 // extendToIndices will abort if there is no joint dominance.
443 // If the abort was avoided by adding extra undefs added to Undefs,
444 // extendToIndices could actually indicate that SI is live, contrary
445 // to the original IR.
446 if (Dominate(Defs, BB))
451 LIS->extendToIndices(Range, ExtTo, Undefs);
453 // Remove <dead> flags from all defs that are not dead after live range
454 // extension, and collect all def operands. They will be used to generate
455 // the necessary implicit uses.
456 std::set<RegisterRef> DefRegs;
457 for (auto &Seg : Range) {
458 if (!Seg.start.isRegister())
460 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
461 for (auto &Op : DefI->operands()) {
462 if (Seg.start.isDead() || !IsRegDef(Op))
469 // Finally, add implicit uses to each predicated def that is reached
471 for (auto &Seg : Range) {
472 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
474 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
475 if (!HII->isPredicated(*DefI))
477 // Construct the set of all necessary implicit uses, based on the def
478 // operands in the instruction.
479 std::set<RegisterRef> ImpUses;
480 for (auto &Op : DefI->operands())
481 if (Op.isReg() && Op.isDef() && DefRegs.count(Op))
485 MachineFunction &MF = *DefI->getParent()->getParent();
486 for (RegisterRef R : ImpUses)
487 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
491 void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
492 LiveInterval &LI = LIS->getInterval(Reg);
493 if (LI.hasSubRanges()) {
494 for (LiveInterval::SubRange &S : LI.subranges()) {
495 updateDeadsInRange(Reg, S.LaneMask, S);
496 LIS->shrinkToUses(S, Reg);
499 LIS->constructMainRangeFromSubranges(LI);
501 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
505 void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
506 LIS->removeInterval(Reg);
507 LIS->createAndComputeVirtRegInterval(Reg);
510 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
511 LIS->RemoveMachineInstrFromMaps(MI);
512 MI.eraseFromParent();
515 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
516 bool Recalc, bool UpdateKills, bool UpdateDeads) {
517 UpdateKills |= UpdateDeads;
518 for (auto R : RegSet) {
520 recalculateLiveInterval(R);
522 MRI->clearKillFlags(R);
525 // Fixing <dead> flags may extend live ranges, so reset <kill> flags
529 LIS->getInterval(R).verify();
533 /// Get the opcode for a conditional transfer of the value in SO (source
534 /// operand). The condition (true/false) is given in Cond.
535 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
537 using namespace Hexagon;
542 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
543 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
544 assert(VC->begin() != VC->end() && "Empty register class");
545 PhysR = *VC->begin();
547 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
550 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
551 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
552 switch (RC->getSize()) {
554 return IfTrue ? A2_tfrt : A2_tfrf;
556 return IfTrue ? A2_tfrpt : A2_tfrpf;
558 llvm_unreachable("Invalid register operand");
560 if (SO.isImm() || SO.isFPImm())
561 return IfTrue ? C2_cmoveit : C2_cmoveif;
562 llvm_unreachable("Unexpected source operand");
565 /// Generate a conditional transfer, copying the value SrcOp to the
566 /// destination register DstR:DstSR, and using the predicate register from
567 /// PredOp. The Cond argument specifies whether the predicate is to be
568 /// if(PredOp), or if(!PredOp).
569 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
570 MachineBasicBlock::iterator At,
571 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
572 bool PredSense, bool ReadUndef, bool ImpUse) {
573 MachineInstr *MI = SrcOp.getParent();
574 MachineBasicBlock &B = *At->getParent();
575 const DebugLoc &DL = MI->getDebugLoc();
577 // Don't avoid identity copies here (i.e. if the source and the destination
578 // are the same registers). It is actually better to generate them here,
579 // since this would cause the copy to potentially be predicated in the next
580 // step. The predication will remove such a copy if it is unable to
583 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
584 unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0);
585 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
586 MachineInstrBuilder MIB;
589 unsigned SrcState = getRegState(SrcOp);
590 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
591 SrcState &= ~RegState::Kill;
592 MIB = BuildMI(B, At, DL, HII->get(Opc))
593 .addReg(DstR, DstState, DstSR)
594 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
595 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
597 MIB = BuildMI(B, At, DL, HII->get(Opc))
598 .addReg(DstR, DstState, DstSR)
599 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
603 DEBUG(dbgs() << "created an initial copy: " << *MIB);
607 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
608 /// performs all necessary changes to complete the replacement.
609 bool HexagonExpandCondsets::split(MachineInstr &MI,
610 std::set<unsigned> &UpdRegs) {
611 if (TfrLimitActive) {
612 if (TfrCounter >= TfrLimit)
616 DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
618 MachineOperand &MD = MI.getOperand(0); // Definition
619 MachineOperand &MP = MI.getOperand(1); // Predicate register
621 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
622 bool ReadUndef = MD.isUndef();
623 MachineBasicBlock::iterator At = MI;
625 // If this is a mux of the same register, just replace it with COPY.
626 // Ideally, this would happen earlier, so that register coalescing would
628 MachineOperand &ST = MI.getOperand(2);
629 MachineOperand &SF = MI.getOperand(3);
630 if (ST.isReg() && SF.isReg()) {
632 if (RT == RegisterRef(SF)) {
633 MI.setDesc(HII->get(TargetOpcode::COPY));
634 unsigned S = getRegState(ST);
635 while (MI.getNumOperands() > 1)
636 MI.RemoveOperand(MI.getNumOperands()-1);
637 MachineFunction &MF = *MI.getParent()->getParent();
638 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
643 // First, create the two invididual conditional transfers, and add each
644 // of them to the live intervals information. Do that first and then remove
645 // the old instruction from live intervals.
647 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
649 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
650 LIS->InsertMachineInstrInMaps(*TfrT);
651 LIS->InsertMachineInstrInMaps(*TfrF);
653 // Will need to recalculate live intervals for all registers in MI.
654 for (auto &Op : MI.operands())
656 UpdRegs.insert(Op.getReg());
662 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
663 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
665 if (MI->hasUnmodeledSideEffects() || MI->mayStore())
667 // Reject instructions with multiple defs (e.g. post-increment loads).
669 for (auto &Op : MI->operands()) {
670 if (!Op.isReg() || !Op.isDef())
676 for (auto &Mo : MI->memoperands())
677 if (Mo->isVolatile())
682 /// Find the reaching definition for a predicated use of RD. The RD is used
683 /// under the conditions given by PredR and Cond, and this function will ignore
684 /// definitions that set RD under the opposite conditions.
685 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
686 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
687 MachineBasicBlock &B = *UseIt->getParent();
688 MachineBasicBlock::iterator I = UseIt, S = B.begin();
692 bool PredValid = true;
695 MachineInstr *MI = &*I;
696 // Check if this instruction can be ignored, i.e. if it is predicated
697 // on the complementary condition.
698 if (PredValid && HII->isPredicated(*MI)) {
699 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
703 // Check the defs. If the PredR is defined, invalidate it. If RD is
704 // defined, return the instruction or 0, depending on the circumstances.
705 for (auto &Op : MI->operands()) {
706 if (!Op.isReg() || !Op.isDef())
709 if (RR.Reg == PredR) {
713 if (RR.Reg != RD.Reg)
715 // If the "Reg" part agrees, there is still the subregister to check.
716 // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
717 // not vreg1 (w/o subregisters).
718 if (RR.Sub == RD.Sub)
720 if (RR.Sub == 0 || RD.Sub == 0)
722 // We have different subregisters, so we can continue looking.
729 /// Check if the instruction MI can be safely moved over a set of instructions
730 /// whose side-effects (in terms of register defs and uses) are expressed in
731 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
732 /// that depend on the same predicate register to allow moving instructions
733 /// over instructions predicated on the opposite condition.
734 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
735 ReferenceMap &Uses) {
736 // In order to be able to safely move MI over instructions that define
737 // "Defs" and use "Uses", no def operand from MI can be defined or used
738 // and no use operand can be defined.
739 for (auto &Op : MI.operands()) {
743 // For physical register we would need to check register aliases, etc.
744 // and we don't want to bother with that. It would be of little value
745 // before the actual register rewriting (from virtual to physical).
746 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
748 // No redefs for any operand.
749 if (isRefInMap(RR, Defs, Exec_Then))
751 // For defs, there cannot be uses.
752 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
758 /// Check if the instruction accessing memory (TheI) can be moved to the
760 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
762 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
763 if (!IsLoad && !IsStore)
765 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
767 if (TheI.hasUnmodeledSideEffects())
770 MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
771 MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
772 bool Ordered = TheI.hasOrderedMemoryRef();
774 // Search for aliased memory reference in (StartI, EndI).
775 for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
776 MachineInstr *MI = &*I;
777 if (MI->hasUnmodeledSideEffects())
779 bool L = MI->mayLoad(), S = MI->mayStore();
782 if (Ordered && MI->hasOrderedMemoryRef())
785 bool Conflict = (L && IsStore) || S;
792 /// Generate a predicated version of MI (where the condition is given via
793 /// PredR and Cond) at the point indicated by Where.
794 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
796 MachineBasicBlock::iterator Where,
797 const MachineOperand &PredOp, bool Cond,
798 std::set<unsigned> &UpdRegs) {
799 // The problem with updating live intervals is that we can move one def
800 // past another def. In particular, this can happen when moving an A2_tfrt
801 // over an A2_tfrf defining the same register. From the point of view of
802 // live intervals, these two instructions are two separate definitions,
803 // and each one starts another live segment. LiveIntervals's "handleMove"
804 // does not allow such moves, so we need to handle it ourselves. To avoid
805 // invalidating liveness data while we are using it, the move will be
806 // implemented in 4 steps: (1) add a clone of the instruction MI at the
807 // target location, (2) update liveness, (3) delete the old instruction,
808 // and (4) update liveness again.
810 MachineBasicBlock &B = *MI.getParent();
811 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
812 unsigned Opc = MI.getOpcode();
813 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
814 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
815 unsigned Ox = 0, NP = MI.getNumOperands();
816 // Skip all defs from MI first.
818 MachineOperand &MO = MI.getOperand(Ox);
819 if (!MO.isReg() || !MO.isDef())
823 // Add the new def, then the predicate register, then the rest of the
825 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
826 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
829 MachineOperand &MO = MI.getOperand(Ox);
830 if (!MO.isReg() || !MO.isImplicit())
835 MachineFunction &MF = *B.getParent();
836 MachineInstr::mmo_iterator I = MI.memoperands_begin();
837 unsigned NR = std::distance(I, MI.memoperands_end());
838 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
839 for (unsigned i = 0; i < NR; ++i)
841 MB.setMemRefs(MemRefs, MemRefs+NR);
843 MachineInstr *NewI = MB;
844 NewI->clearKillInfo();
845 LIS->InsertMachineInstrInMaps(*NewI);
847 for (auto &Op : NewI->operands())
849 UpdRegs.insert(Op.getReg());
852 /// In the range [First, Last], rename all references to the "old" register RO
853 /// to the "new" register RN, but only in instructions predicated on the given
855 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
856 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
857 MachineBasicBlock::iterator Last) {
858 MachineBasicBlock::iterator End = std::next(Last);
859 for (MachineBasicBlock::iterator I = First; I != End; ++I) {
860 MachineInstr *MI = &*I;
861 // Do not touch instructions that are not predicated, or are predicated
862 // on the opposite condition.
863 if (!HII->isPredicated(*MI))
865 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
868 for (auto &Op : MI->operands()) {
869 if (!Op.isReg() || RO != RegisterRef(Op))
872 Op.setSubReg(RN.Sub);
873 // In practice, this isn't supposed to see any defs.
874 assert(!Op.isDef() && "Not expecting a def");
879 /// For a given conditional copy, predicate the definition of the source of
880 /// the copy under the given condition (using the same predicate register as
882 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
883 std::set<unsigned> &UpdRegs) {
884 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
885 unsigned Opc = TfrI.getOpcode();
887 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
888 DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
891 MachineOperand &MD = TfrI.getOperand(0);
892 MachineOperand &MP = TfrI.getOperand(1);
893 MachineOperand &MS = TfrI.getOperand(2);
894 // The source operand should be a <kill>. This is not strictly necessary,
895 // but it makes things a lot simpler. Otherwise, we would need to rename
896 // some registers, which would complicate the transformation considerably.
899 // Avoid predicating instructions that define a subregister if subregister
900 // liveness tracking is not enabled.
901 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
905 unsigned PredR = MP.getReg();
906 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
907 if (!DefI || !isPredicable(DefI))
910 DEBUG(dbgs() << "Source def: " << *DefI);
912 // Collect the information about registers defined and used between the
913 // DefI and the TfrI.
914 // Map: reg -> bitmask of subregs
915 ReferenceMap Uses, Defs;
916 MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
918 // Check if the predicate register is valid between DefI and TfrI.
919 // If it is, we can then ignore instructions predicated on the negated
920 // conditions when collecting def and use information.
921 bool PredValid = true;
922 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
923 if (!I->modifiesRegister(PredR, nullptr))
929 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
930 MachineInstr *MI = &*I;
931 // If this instruction is predicated on the same register, it could
932 // potentially be ignored.
933 // By default assume that the instruction executes on the same condition
934 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
935 unsigned Exec = Exec_Then | Exec_Else;
936 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
937 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
939 for (auto &Op : MI->operands()) {
942 // We don't want to deal with physical registers. The reason is that
943 // they can be aliased with other physical registers. Aliased virtual
944 // registers must share the same register number, and can only differ
945 // in the subregisters, which we are keeping track of. Physical
946 // registers ters no longer have subregisters---their super- and
947 // subregisters are other physical registers, and we are not checking
950 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
953 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
954 if (Op.isDef() && Op.isUndef()) {
955 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
956 // If this is a <def,read-undef>, then it invalidates the non-written
957 // part of the register. For the purpose of checking the validity of
958 // the move, assume that it modifies the whole register.
961 addRefToMap(RR, Map, Exec);
970 // If the register-in-the-middle (RT) is used or redefined between
971 // DefI and TfrI, we may not be able proceed with this transformation.
972 // We can ignore a def that will not execute together with TfrI, and a
973 // use that will. If there is such a use (that does execute together with
974 // TfrI), we will not be able to move DefI down. If there is a use that
975 // executed if TfrI's condition is false, then RT must be available
976 // unconditionally (cannot be predicated).
977 // Essentially, we need to be able to rename RT to RD in this segment.
978 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
981 // If the predicate register is defined between DefI and TfrI, the only
982 // potential thing to do would be to move the DefI down to TfrI, and then
983 // predicate. The reaching def (DefI) must be movable down to the location
985 // If the target register of the TfrI (RD) is not used or defined between
986 // DefI and TfrI, consider moving TfrI up to DefI.
987 bool CanUp = canMoveOver(TfrI, Defs, Uses);
988 bool CanDown = canMoveOver(*DefI, Defs, Uses);
989 // The TfrI does not access memory, but DefI could. Check if it's safe
990 // to move DefI down to TfrI.
991 if (DefI->mayLoad() || DefI->mayStore())
992 if (!canMoveMemTo(*DefI, TfrI, true))
995 DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
996 << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
997 MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
999 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
1001 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
1006 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
1007 UpdRegs.insert(RT.Reg);
1015 /// Predicate all cases of conditional copies in the specified block.
1016 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
1017 std::set<unsigned> &UpdRegs) {
1018 bool Changed = false;
1019 MachineBasicBlock::iterator I, E, NextI;
1020 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
1021 NextI = std::next(I);
1022 unsigned Opc = I->getOpcode();
1023 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1024 bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
1026 // If we didn't predicate I, we may need to remove it in case it is
1027 // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1.
1028 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1029 for (auto &Op : I->operands())
1031 UpdRegs.insert(Op.getReg());
1041 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1042 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1044 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1045 if (RC == &Hexagon::IntRegsRegClass) {
1049 if (RC == &Hexagon::DoubleRegsRegClass) {
1050 BW = (RR.Sub != 0) ? 32 : 64;
1056 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
1057 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
1058 LiveRange::Segment &LR = *I;
1059 // Range must start at a register...
1060 if (!LR.start.isRegister())
1062 // ...and end in a register or in a dead slot.
1063 if (!LR.end.isRegister() && !LR.end.isDead())
1069 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1070 if (CoaLimitActive) {
1071 if (CoaCounter >= CoaLimit)
1076 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2)
1078 if (MRI->isLiveIn(R1.Reg))
1080 if (MRI->isLiveIn(R2.Reg))
1083 LiveInterval &L1 = LIS->getInterval(R1.Reg);
1084 LiveInterval &L2 = LIS->getInterval(R2.Reg);
1087 if (L1.hasSubRanges() || L2.hasSubRanges())
1089 bool Overlap = L1.overlaps(L2);
1091 DEBUG(dbgs() << "compatible registers: ("
1092 << (Overlap ? "overlap" : "disjoint") << ")\n "
1093 << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1094 << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
1095 if (R1.Sub || R2.Sub)
1100 // Coalescing could have a negative impact on scheduling, so try to limit
1101 // to some reasonable extent. Only consider coalescing segments, when one
1102 // of them does not cross basic block boundaries.
1103 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1106 MRI->replaceRegWith(R2.Reg, R1.Reg);
1108 // Move all live segments from L2 to L1.
1109 typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
1111 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
1112 VNInfo *NewVN, *OldVN = I->valno;
1113 ValueInfoMap::iterator F = VM.find(OldVN);
1114 if (F == VM.end()) {
1115 NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
1116 VM.insert(std::make_pair(OldVN, NewVN));
1120 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
1122 while (L2.begin() != L2.end())
1123 L2.removeSegment(*L2.begin());
1124 LIS->removeInterval(R2.Reg);
1126 updateKillFlags(R1.Reg);
1127 DEBUG(dbgs() << "coalesced: " << L1 << "\n");
1133 /// Attempt to coalesce one of the source registers to a MUX instruction with
1134 /// the destination register. This could lead to having only one predicated
1135 /// instruction in the end instead of two.
1136 bool HexagonExpandCondsets::coalesceSegments(
1137 const SmallVectorImpl<MachineInstr*> &Condsets,
1138 std::set<unsigned> &UpdRegs) {
1139 SmallVector<MachineInstr*,16> TwoRegs;
1140 for (MachineInstr *MI : Condsets) {
1141 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1142 if (!S1.isReg() && !S2.isReg())
1144 TwoRegs.push_back(MI);
1147 bool Changed = false;
1148 for (MachineInstr *CI : TwoRegs) {
1149 RegisterRef RD = CI->getOperand(0);
1150 RegisterRef RP = CI->getOperand(1);
1151 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1153 // Consider this case:
1154 // vreg1 = instr1 ...
1155 // vreg2 = instr2 ...
1156 // vreg0 = C2_mux ..., vreg1, vreg2
1157 // If vreg0 was coalesced with vreg1, we could end up with the following
1159 // vreg0 = instr1 ...
1160 // vreg2 = instr2 ...
1161 // vreg0 = A2_tfrf ..., vreg2
1162 // which will later become:
1163 // vreg0 = instr1 ...
1164 // vreg0 = instr2_cNotPt ...
1165 // i.e. there will be an unconditional definition (instr1) of vreg0
1166 // followed by a conditional one. The output dependency was there before
1167 // and it unavoidable, but if instr1 is predicable, we will no longer be
1168 // able to predicate it here.
1169 // To avoid this scenario, don't coalesce the destination register with
1170 // a source register that is defined by a predicable instruction.
1172 RegisterRef RS = S1;
1173 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1174 if (!RDef || !HII->isPredicable(*RDef)) {
1175 Done = coalesceRegisters(RD, RegisterRef(S1));
1177 UpdRegs.insert(RD.Reg);
1178 UpdRegs.insert(S1.getReg());
1182 if (!Done && S2.isReg()) {
1183 RegisterRef RS = S2;
1184 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
1185 if (!RDef || !HII->isPredicable(*RDef)) {
1186 Done = coalesceRegisters(RD, RegisterRef(S2));
1188 UpdRegs.insert(RD.Reg);
1189 UpdRegs.insert(S2.getReg());
1198 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
1199 if (skipFunction(*MF.getFunction()))
1202 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
1203 TRI = MF.getSubtarget().getRegisterInfo();
1204 MDT = &getAnalysis<MachineDominatorTree>();
1205 LIS = &getAnalysis<LiveIntervals>();
1206 MRI = &MF.getRegInfo();
1208 DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
1209 MF.getFunction()->getParent()));
1211 bool Changed = false;
1212 std::set<unsigned> CoalUpd, PredUpd;
1214 SmallVector<MachineInstr*,16> Condsets;
1218 Condsets.push_back(&I);
1220 // Try to coalesce the target of a mux with one of its sources.
1221 // This could eliminate a register copy in some circumstances.
1222 Changed |= coalesceSegments(Condsets, CoalUpd);
1224 // Update kill flags on all source operands. This is done here because
1225 // at this moment (when expand-condsets runs), there are no kill flags
1226 // in the IR (they have been removed by live range analysis).
1227 // Updating them right before we split is the easiest, because splitting
1228 // adds definitions which would interfere with updating kills afterwards.
1229 std::set<unsigned> KillUpd;
1230 for (MachineInstr *MI : Condsets)
1231 for (MachineOperand &Op : MI->operands())
1232 if (Op.isReg() && Op.isUse())
1233 if (!CoalUpd.count(Op.getReg()))
1234 KillUpd.insert(Op.getReg());
1235 updateLiveness(KillUpd, false, true, false);
1236 DEBUG(LIS->print(dbgs() << "After coalescing\n",
1237 MF.getFunction()->getParent()));
1239 // First, simply split all muxes into a pair of conditional transfers
1240 // and update the live intervals to reflect the new arrangement. The
1241 // goal is to update the kill flags, since predication will rely on
1243 for (MachineInstr *MI : Condsets)
1244 Changed |= split(*MI, PredUpd);
1245 Condsets.clear(); // The contents of Condsets are invalid here anyway.
1247 // Do not update live ranges after splitting. Recalculation of live
1248 // intervals removes kill flags, which were preserved by splitting on
1249 // the source operands of condsets. These kill flags are needed by
1250 // predication, and after splitting they are difficult to recalculate
1251 // (because of predicated defs), so make sure they are left untouched.
1252 // Predication does not use live intervals.
1253 DEBUG(LIS->print(dbgs() << "After splitting\n",
1254 MF.getFunction()->getParent()));
1256 // Traverse all blocks and collapse predicable instructions feeding
1257 // conditional transfers into predicated instructions.
1258 // Walk over all the instructions again, so we may catch pre-existing
1259 // cases that were not created in the previous step.
1261 Changed |= predicateInBlock(B, PredUpd);
1262 DEBUG(LIS->print(dbgs() << "After predicating\n",
1263 MF.getFunction()->getParent()));
1265 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1266 updateLiveness(PredUpd, true, true, true);
1270 LIS->print(dbgs() << "After expand-condsets\n",
1271 MF.getFunction()->getParent());
1277 //===----------------------------------------------------------------------===//
1278 // Public Constructor Functions
1279 //===----------------------------------------------------------------------===//
1281 FunctionPass *llvm::createHexagonExpandCondsets() {
1282 return new HexagonExpandCondsets();