1 //===- HexagonExpandCondsets.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Replace mux instructions with the corresponding legal instructions.
11 // It is meant to work post-SSA, but still on virtual registers. It was
12 // originally placed between register coalescing and machine instruction
14 // In this place in the optimization sequence, live interval analysis had
15 // been performed, and the live intervals should be preserved. A large part
16 // of the code deals with preserving the liveness information.
18 // Liveness tracking aside, the main functionality of this pass is divided
19 // into two steps. The first step is to replace an instruction
20 // %0 = C2_mux %1, %2, %3
21 // with a pair of conditional transfers
22 // %0 = A2_tfrt %1, %2
23 // %0 = A2_tfrf %1, %3
24 // It is the intention that the execution of this pass could be terminated
25 // after this step, and the code generated would be functionally correct.
27 // If the uses of the source values %1 and %2 are kills, and their
28 // definitions are predicable, then in the second step, the conditional
29 // transfers will then be rewritten as predicated instructions. E.g.
31 // %3 = A2_tfrt %99, killed %0
32 // will be rewritten as
33 // %3 = A2_port %99, %1, %2
35 // This replacement has two variants: "up" and "down". Consider this case:
37 // ... [intervening instructions] ...
38 // %3 = A2_tfrt %99, killed %0
40 // %3 = A2_port %99, %1, %2
41 // ... [intervening instructions, %0->vreg3] ...
45 // ... [intervening instructions] ...
46 // %3 = A2_port %99, %1, %2
48 // Both, one or none of these variants may be valid, and checks are made
49 // to rule out inapplicable variants.
51 // As an additional optimization, before either of the two steps above is
52 // executed, the pass attempts to coalesce the target register with one of
53 // the source registers, e.g. given an instruction
54 // %3 = C2_mux %0, %1, %2
55 // %3 will be coalesced with either %1 or %2. If this succeeds,
56 // the instruction would then be (for example)
57 // %3 = C2_mux %0, %3, %2
58 // and, under certain circumstances, this could result in only one predicated
60 // %3 = A2_tfrf %0, %2
63 // Splitting a definition of a register into two predicated transfers
64 // creates a complication in liveness tracking. Live interval computation
65 // will see both instructions as actual definitions, and will mark the
66 // first one as dead. The definition is not actually dead, and this
67 // situation will need to be fixed. For example:
68 // dead %1 = A2_tfrt ... ; marked as dead
71 // Since any of the individual predicated transfers may end up getting
72 // removed (in case it is an identity copy), some pre-existing def may
73 // be marked as dead after live interval recomputation:
74 // dead %1 = ... ; marked as dead
76 // %1 = A2_tfrf ... ; if A2_tfrt is removed
77 // This case happens if %1 was used as a source in A2_tfrt, which means
78 // that is it actually live at the A2_tfrf, and so the now dead definition
79 // of %1 will need to be updated to non-dead at some point.
81 // This issue could be remedied by adding implicit uses to the predicated
82 // transfers, but this will create a problem with subsequent predication,
83 // since the transfers will no longer be possible to reorder. To avoid
84 // that, the initial splitting will not add any implicit uses. These
85 // implicit uses will be added later, after predication. The extra price,
86 // however, is that finding the locations where the implicit uses need
87 // to be added, and updating the live ranges will be more involved.
89 #include "HexagonInstrInfo.h"
90 #include "HexagonRegisterInfo.h"
91 #include "llvm/ADT/DenseMap.h"
92 #include "llvm/ADT/SetVector.h"
93 #include "llvm/ADT/SmallVector.h"
94 #include "llvm/ADT/StringRef.h"
95 #include "llvm/CodeGen/LiveInterval.h"
96 #include "llvm/CodeGen/LiveIntervals.h"
97 #include "llvm/CodeGen/MachineBasicBlock.h"
98 #include "llvm/CodeGen/MachineDominators.h"
99 #include "llvm/CodeGen/MachineFunction.h"
100 #include "llvm/CodeGen/MachineFunctionPass.h"
101 #include "llvm/CodeGen/MachineInstr.h"
102 #include "llvm/CodeGen/MachineInstrBuilder.h"
103 #include "llvm/CodeGen/MachineOperand.h"
104 #include "llvm/CodeGen/MachineRegisterInfo.h"
105 #include "llvm/CodeGen/SlotIndexes.h"
106 #include "llvm/CodeGen/TargetRegisterInfo.h"
107 #include "llvm/CodeGen/TargetSubtargetInfo.h"
108 #include "llvm/IR/DebugLoc.h"
109 #include "llvm/IR/Function.h"
110 #include "llvm/MC/LaneBitmask.h"
111 #include "llvm/Pass.h"
112 #include "llvm/Support/CommandLine.h"
113 #include "llvm/Support/Debug.h"
114 #include "llvm/Support/ErrorHandling.h"
115 #include "llvm/Support/raw_ostream.h"
121 #define DEBUG_TYPE "expand-condsets"
123 using namespace llvm;
125 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
126 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
127 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
128 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
132 void initializeHexagonExpandCondsetsPass(PassRegistry&);
133 FunctionPass *createHexagonExpandCondsets();
135 } // end namespace llvm
139 class HexagonExpandCondsets : public MachineFunctionPass {
143 HexagonExpandCondsets() : MachineFunctionPass(ID) {
144 if (OptCoaLimit.getPosition())
145 CoaLimitActive = true, CoaLimit = OptCoaLimit;
146 if (OptTfrLimit.getPosition())
147 TfrLimitActive = true, TfrLimit = OptTfrLimit;
148 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
151 StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
153 void getAnalysisUsage(AnalysisUsage &AU) const override {
154 AU.addRequired<LiveIntervals>();
155 AU.addPreserved<LiveIntervals>();
156 AU.addPreserved<SlotIndexes>();
157 AU.addRequired<MachineDominatorTree>();
158 AU.addPreserved<MachineDominatorTree>();
159 MachineFunctionPass::getAnalysisUsage(AU);
162 bool runOnMachineFunction(MachineFunction &MF) override;
165 const HexagonInstrInfo *HII = nullptr;
166 const TargetRegisterInfo *TRI = nullptr;
167 MachineDominatorTree *MDT;
168 MachineRegisterInfo *MRI = nullptr;
169 LiveIntervals *LIS = nullptr;
170 bool CoaLimitActive = false;
171 bool TfrLimitActive = false;
174 unsigned CoaCounter = 0;
175 unsigned TfrCounter = 0;
178 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
179 Sub(Op.getSubReg()) {}
180 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
182 bool operator== (RegisterRef RR) const {
183 return Reg == RR.Reg && Sub == RR.Sub;
185 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
186 bool operator< (RegisterRef RR) const {
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
193 using ReferenceMap = DenseMap<unsigned, unsigned>;
194 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
195 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
197 unsigned getMaskForSub(unsigned Sub);
198 bool isCondset(const MachineInstr &MI);
199 LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
202 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
204 void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
205 void updateKillFlags(unsigned Reg);
206 void updateDeadFlags(unsigned Reg);
207 void recalculateLiveInterval(unsigned Reg);
208 void removeInstr(MachineInstr &MI);
209 void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
210 bool UpdateKills, bool UpdateDeads);
212 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
214 MachineBasicBlock::iterator At, unsigned DstR,
215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
216 bool ReadUndef, bool ImpUse);
217 bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
219 bool isPredicable(MachineInstr *MI);
220 MachineInstr *getReachingDefForPred(RegisterRef RD,
221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
222 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
223 bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
224 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
225 MachineBasicBlock::iterator Where,
226 const MachineOperand &PredOp, bool Cond,
227 std::set<unsigned> &UpdRegs);
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
229 bool Cond, MachineBasicBlock::iterator First,
230 MachineBasicBlock::iterator Last);
231 bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
232 bool predicateInBlock(MachineBasicBlock &B,
233 std::set<unsigned> &UpdRegs);
235 bool isIntReg(RegisterRef RR, unsigned &BW);
236 bool isIntraBlocks(LiveInterval &LI);
237 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
238 bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
239 std::set<unsigned> &UpdRegs);
242 } // end anonymous namespace
244 char HexagonExpandCondsets::ID = 0;
248 char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID;
250 } // end namespace llvm
252 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
253 "Hexagon Expand Condsets", false, false)
254 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
255 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
256 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
257 INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets",
258 "Hexagon Expand Condsets", false, false)
260 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
262 case Hexagon::isub_lo:
263 case Hexagon::vsub_lo:
265 case Hexagon::isub_hi:
266 case Hexagon::vsub_hi:
268 case Hexagon::NoSubRegister:
271 llvm_unreachable("Invalid subregister");
274 bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
275 unsigned Opc = MI.getOpcode();
277 case Hexagon::C2_mux:
278 case Hexagon::C2_muxii:
279 case Hexagon::C2_muxir:
280 case Hexagon::C2_muxri:
281 case Hexagon::PS_pselect:
288 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
289 assert(TargetRegisterInfo::isVirtualRegister(Reg));
290 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
291 : MRI->getMaxLaneMaskForVReg(Reg);
294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
296 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
297 ReferenceMap::iterator F = Map.find(RR.Reg);
299 Map.insert(std::make_pair(RR.Reg, Mask));
304 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
306 ReferenceMap::iterator F = Map.find(RR.Reg);
309 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
310 if (Mask & F->second)
315 void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
316 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
317 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
318 MachineInstr *MI = LIS->getInstructionFromIndex(K);
319 for (auto &Op : MI->operands()) {
320 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
322 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
323 if ((SLM & LM) == SLM) {
324 // Only set the kill flag on the first encountered use of Reg in this
332 LiveInterval &LI = LIS->getInterval(Reg);
333 for (auto I = LI.begin(), E = LI.end(); I != E; ++I) {
334 if (!I->end.isRegister())
336 // Do not mark the end of the segment as <kill>, if the next segment
337 // starts with a predicated instruction.
338 auto NextI = std::next(I);
339 if (NextI != E && NextI->start.isRegister()) {
340 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
341 if (HII->isPredicated(*DefI))
344 bool WholeReg = true;
345 if (LI.hasSubRanges()) {
346 auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool {
347 LiveRange::iterator F = S.find(I->end);
348 return F != S.end() && I->end == F->end;
350 // Check if all subranges end at I->end. If so, make sure to kill
351 // the whole register.
352 for (LiveInterval::SubRange &S : LI.subranges()) {
354 KillAt(I->end, S.LaneMask);
360 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
364 void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
366 assert(TargetRegisterInfo::isVirtualRegister(Reg));
370 // Return two booleans: { def-modifes-reg, def-covers-reg }.
371 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
372 if (!Op.isReg() || !Op.isDef())
373 return { false, false };
374 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
375 if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
376 return { false, false };
377 LaneBitmask SLM = getLaneMask(DR, DSR);
378 LaneBitmask A = SLM & LM;
379 return { A.any(), A == SLM };
382 // The splitting step will create pairs of predicated definitions without
383 // any implicit uses (since implicit uses would interfere with predication).
384 // This can cause the reaching defs to become dead after live range
385 // recomputation, even though they are not really dead.
386 // We need to identify predicated defs that need implicit uses, and
387 // dead defs that are not really dead, and correct both problems.
389 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
390 MachineBasicBlock *Dest) -> bool {
391 for (MachineBasicBlock *D : Defs)
392 if (D != Dest && MDT->dominates(D, Dest))
395 MachineBasicBlock *Entry = &Dest->getParent()->front();
396 SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end());
397 for (unsigned i = 0; i < Work.size(); ++i) {
398 MachineBasicBlock *B = Work[i];
403 for (auto *P : B->predecessors())
409 // First, try to extend live range within individual basic blocks. This
410 // will leave us only with dead defs that do not reach any predicated
411 // defs in the same block.
412 SetVector<MachineBasicBlock*> Defs;
413 SmallVector<SlotIndex,4> PredDefs;
414 for (auto &Seg : Range) {
415 if (!Seg.start.isRegister())
417 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
418 Defs.insert(DefI->getParent());
419 if (HII->isPredicated(*DefI))
420 PredDefs.push_back(Seg.start);
423 SmallVector<SlotIndex,8> Undefs;
424 LiveInterval &LI = LIS->getInterval(Reg);
425 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes());
427 for (auto &SI : PredDefs) {
428 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
429 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
430 if (P.first != nullptr || P.second)
434 // Calculate reachability for those predicated defs that were not handled
435 // by the in-block extension.
436 SmallVector<SlotIndex,4> ExtTo;
437 for (auto &SI : PredDefs) {
440 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
441 if (BB->pred_empty())
443 // If the defs from this range reach SI via all predecessors, it is live.
444 // It can happen that SI is reached by the defs through some paths, but
445 // not all. In the IR coming into this optimization, SI would not be
446 // considered live, since the defs would then not jointly dominate SI.
447 // That means that SI is an overwriting def, and no implicit use is
448 // needed at this point. Do not add SI to the extension points, since
449 // extendToIndices will abort if there is no joint dominance.
450 // If the abort was avoided by adding extra undefs added to Undefs,
451 // extendToIndices could actually indicate that SI is live, contrary
452 // to the original IR.
453 if (Dominate(Defs, BB))
458 LIS->extendToIndices(Range, ExtTo, Undefs);
460 // Remove <dead> flags from all defs that are not dead after live range
461 // extension, and collect all def operands. They will be used to generate
462 // the necessary implicit uses.
463 // At the same time, add <dead> flag to all defs that are actually dead.
464 // This can happen, for example, when a mux with identical inputs is
465 // replaced with a COPY: the use of the predicate register disappears and
466 // the dead can become dead.
467 std::set<RegisterRef> DefRegs;
468 for (auto &Seg : Range) {
469 if (!Seg.start.isRegister())
471 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
472 for (auto &Op : DefI->operands()) {
473 auto P = IsRegDef(Op);
474 if (P.second && Seg.end.isDead()) {
476 } else if (P.first) {
483 // Now, add implicit uses to each predicated def that is reached
485 for (auto &Seg : Range) {
486 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
488 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
489 if (!HII->isPredicated(*DefI))
491 // Construct the set of all necessary implicit uses, based on the def
492 // operands in the instruction. We need to tie the implicit uses to
493 // the corresponding defs.
494 std::map<RegisterRef,unsigned> ImpUses;
495 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
496 MachineOperand &Op = DefI->getOperand(i);
497 if (!Op.isReg() || !DefRegs.count(Op))
500 ImpUses.insert({Op, i});
502 // This function can be called for the same register with different
503 // lane masks. If the def in this instruction was for the whole
504 // register, we can get here more than once. Avoid adding multiple
505 // implicit uses (or adding an implicit use when an explicit one is
512 MachineFunction &MF = *DefI->getParent()->getParent();
513 for (std::pair<RegisterRef, unsigned> P : ImpUses) {
514 RegisterRef R = P.first;
515 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
516 DefI->tieOperands(P.second, DefI->getNumOperands()-1);
521 void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
522 LiveInterval &LI = LIS->getInterval(Reg);
523 if (LI.hasSubRanges()) {
524 for (LiveInterval::SubRange &S : LI.subranges()) {
525 updateDeadsInRange(Reg, S.LaneMask, S);
526 LIS->shrinkToUses(S, Reg);
529 LIS->constructMainRangeFromSubranges(LI);
531 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
535 void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
536 LIS->removeInterval(Reg);
537 LIS->createAndComputeVirtRegInterval(Reg);
540 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
541 LIS->RemoveMachineInstrFromMaps(MI);
542 MI.eraseFromParent();
545 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
546 bool Recalc, bool UpdateKills, bool UpdateDeads) {
547 UpdateKills |= UpdateDeads;
548 for (auto R : RegSet) {
550 recalculateLiveInterval(R);
552 MRI->clearKillFlags(R);
555 // Fixing <dead> flags may extend live ranges, so reset <kill> flags
559 LIS->getInterval(R).verify();
563 /// Get the opcode for a conditional transfer of the value in SO (source
564 /// operand). The condition (true/false) is given in Cond.
565 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
567 using namespace Hexagon;
572 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
573 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
574 assert(VC->begin() != VC->end() && "Empty register class");
575 PhysR = *VC->begin();
577 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
580 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
581 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
582 switch (TRI->getRegSizeInBits(*RC)) {
584 return IfTrue ? A2_tfrt : A2_tfrf;
586 return IfTrue ? A2_tfrpt : A2_tfrpf;
588 llvm_unreachable("Invalid register operand");
590 switch (SO.getType()) {
591 case MachineOperand::MO_Immediate:
592 case MachineOperand::MO_FPImmediate:
593 case MachineOperand::MO_ConstantPoolIndex:
594 case MachineOperand::MO_TargetIndex:
595 case MachineOperand::MO_JumpTableIndex:
596 case MachineOperand::MO_ExternalSymbol:
597 case MachineOperand::MO_GlobalAddress:
598 case MachineOperand::MO_BlockAddress:
599 return IfTrue ? C2_cmoveit : C2_cmoveif;
603 llvm_unreachable("Unexpected source operand");
606 /// Generate a conditional transfer, copying the value SrcOp to the
607 /// destination register DstR:DstSR, and using the predicate register from
608 /// PredOp. The Cond argument specifies whether the predicate is to be
609 /// if(PredOp), or if(!PredOp).
610 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
611 MachineBasicBlock::iterator At,
612 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
613 bool PredSense, bool ReadUndef, bool ImpUse) {
614 MachineInstr *MI = SrcOp.getParent();
615 MachineBasicBlock &B = *At->getParent();
616 const DebugLoc &DL = MI->getDebugLoc();
618 // Don't avoid identity copies here (i.e. if the source and the destination
619 // are the same registers). It is actually better to generate them here,
620 // since this would cause the copy to potentially be predicated in the next
621 // step. The predication will remove such a copy if it is unable to
624 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
625 unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0);
626 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
627 MachineInstrBuilder MIB;
630 unsigned SrcState = getRegState(SrcOp);
631 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
632 SrcState &= ~RegState::Kill;
633 MIB = BuildMI(B, At, DL, HII->get(Opc))
634 .addReg(DstR, DstState, DstSR)
635 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
636 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
638 MIB = BuildMI(B, At, DL, HII->get(Opc))
639 .addReg(DstR, DstState, DstSR)
640 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
644 DEBUG(dbgs() << "created an initial copy: " << *MIB);
648 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
649 /// performs all necessary changes to complete the replacement.
650 bool HexagonExpandCondsets::split(MachineInstr &MI,
651 std::set<unsigned> &UpdRegs) {
652 if (TfrLimitActive) {
653 if (TfrCounter >= TfrLimit)
657 DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": "
659 MachineOperand &MD = MI.getOperand(0); // Definition
660 MachineOperand &MP = MI.getOperand(1); // Predicate register
662 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
663 bool ReadUndef = MD.isUndef();
664 MachineBasicBlock::iterator At = MI;
666 auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
667 for (auto &Op : MI.operands())
669 UpdRegs.insert(Op.getReg());
672 // If this is a mux of the same register, just replace it with COPY.
673 // Ideally, this would happen earlier, so that register coalescing would
675 MachineOperand &ST = MI.getOperand(2);
676 MachineOperand &SF = MI.getOperand(3);
677 if (ST.isReg() && SF.isReg()) {
679 if (RT == RegisterRef(SF)) {
680 // Copy regs to update first.
682 MI.setDesc(HII->get(TargetOpcode::COPY));
683 unsigned S = getRegState(ST);
684 while (MI.getNumOperands() > 1)
685 MI.RemoveOperand(MI.getNumOperands()-1);
686 MachineFunction &MF = *MI.getParent()->getParent();
687 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
692 // First, create the two invididual conditional transfers, and add each
693 // of them to the live intervals information. Do that first and then remove
694 // the old instruction from live intervals.
696 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
698 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
699 LIS->InsertMachineInstrInMaps(*TfrT);
700 LIS->InsertMachineInstrInMaps(*TfrF);
702 // Will need to recalculate live intervals for all registers in MI.
709 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
710 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
712 if (MI->hasUnmodeledSideEffects() || MI->mayStore())
714 // Reject instructions with multiple defs (e.g. post-increment loads).
716 for (auto &Op : MI->operands()) {
717 if (!Op.isReg() || !Op.isDef())
723 for (auto &Mo : MI->memoperands())
724 if (Mo->isVolatile())
729 /// Find the reaching definition for a predicated use of RD. The RD is used
730 /// under the conditions given by PredR and Cond, and this function will ignore
731 /// definitions that set RD under the opposite conditions.
732 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
733 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
734 MachineBasicBlock &B = *UseIt->getParent();
735 MachineBasicBlock::iterator I = UseIt, S = B.begin();
739 bool PredValid = true;
742 MachineInstr *MI = &*I;
743 // Check if this instruction can be ignored, i.e. if it is predicated
744 // on the complementary condition.
745 if (PredValid && HII->isPredicated(*MI)) {
746 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
750 // Check the defs. If the PredR is defined, invalidate it. If RD is
751 // defined, return the instruction or 0, depending on the circumstances.
752 for (auto &Op : MI->operands()) {
753 if (!Op.isReg() || !Op.isDef())
756 if (RR.Reg == PredR) {
760 if (RR.Reg != RD.Reg)
762 // If the "Reg" part agrees, there is still the subregister to check.
763 // If we are looking for %1:loreg, we can skip %1:hireg, but
764 // not %1 (w/o subregisters).
765 if (RR.Sub == RD.Sub)
767 if (RR.Sub == 0 || RD.Sub == 0)
769 // We have different subregisters, so we can continue looking.
776 /// Check if the instruction MI can be safely moved over a set of instructions
777 /// whose side-effects (in terms of register defs and uses) are expressed in
778 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
779 /// that depend on the same predicate register to allow moving instructions
780 /// over instructions predicated on the opposite condition.
781 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
782 ReferenceMap &Uses) {
783 // In order to be able to safely move MI over instructions that define
784 // "Defs" and use "Uses", no def operand from MI can be defined or used
785 // and no use operand can be defined.
786 for (auto &Op : MI.operands()) {
790 // For physical register we would need to check register aliases, etc.
791 // and we don't want to bother with that. It would be of little value
792 // before the actual register rewriting (from virtual to physical).
793 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
795 // No redefs for any operand.
796 if (isRefInMap(RR, Defs, Exec_Then))
798 // For defs, there cannot be uses.
799 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
805 /// Check if the instruction accessing memory (TheI) can be moved to the
807 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
809 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
810 if (!IsLoad && !IsStore)
812 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
814 if (TheI.hasUnmodeledSideEffects())
817 MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
818 MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
819 bool Ordered = TheI.hasOrderedMemoryRef();
821 // Search for aliased memory reference in (StartI, EndI).
822 for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
823 MachineInstr *MI = &*I;
824 if (MI->hasUnmodeledSideEffects())
826 bool L = MI->mayLoad(), S = MI->mayStore();
829 if (Ordered && MI->hasOrderedMemoryRef())
832 bool Conflict = (L && IsStore) || S;
839 /// Generate a predicated version of MI (where the condition is given via
840 /// PredR and Cond) at the point indicated by Where.
841 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
843 MachineBasicBlock::iterator Where,
844 const MachineOperand &PredOp, bool Cond,
845 std::set<unsigned> &UpdRegs) {
846 // The problem with updating live intervals is that we can move one def
847 // past another def. In particular, this can happen when moving an A2_tfrt
848 // over an A2_tfrf defining the same register. From the point of view of
849 // live intervals, these two instructions are two separate definitions,
850 // and each one starts another live segment. LiveIntervals's "handleMove"
851 // does not allow such moves, so we need to handle it ourselves. To avoid
852 // invalidating liveness data while we are using it, the move will be
853 // implemented in 4 steps: (1) add a clone of the instruction MI at the
854 // target location, (2) update liveness, (3) delete the old instruction,
855 // and (4) update liveness again.
857 MachineBasicBlock &B = *MI.getParent();
858 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
859 unsigned Opc = MI.getOpcode();
860 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
861 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
862 unsigned Ox = 0, NP = MI.getNumOperands();
863 // Skip all defs from MI first.
865 MachineOperand &MO = MI.getOperand(Ox);
866 if (!MO.isReg() || !MO.isDef())
870 // Add the new def, then the predicate register, then the rest of the
872 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
873 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
876 MachineOperand &MO = MI.getOperand(Ox);
877 if (!MO.isReg() || !MO.isImplicit())
882 MachineFunction &MF = *B.getParent();
883 MachineInstr::mmo_iterator I = MI.memoperands_begin();
884 unsigned NR = std::distance(I, MI.memoperands_end());
885 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
886 for (unsigned i = 0; i < NR; ++i)
888 MB.setMemRefs(MemRefs, MemRefs+NR);
890 MachineInstr *NewI = MB;
891 NewI->clearKillInfo();
892 LIS->InsertMachineInstrInMaps(*NewI);
894 for (auto &Op : NewI->operands())
896 UpdRegs.insert(Op.getReg());
899 /// In the range [First, Last], rename all references to the "old" register RO
900 /// to the "new" register RN, but only in instructions predicated on the given
902 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
903 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
904 MachineBasicBlock::iterator Last) {
905 MachineBasicBlock::iterator End = std::next(Last);
906 for (MachineBasicBlock::iterator I = First; I != End; ++I) {
907 MachineInstr *MI = &*I;
908 // Do not touch instructions that are not predicated, or are predicated
909 // on the opposite condition.
910 if (!HII->isPredicated(*MI))
912 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
915 for (auto &Op : MI->operands()) {
916 if (!Op.isReg() || RO != RegisterRef(Op))
919 Op.setSubReg(RN.Sub);
920 // In practice, this isn't supposed to see any defs.
921 assert(!Op.isDef() && "Not expecting a def");
926 /// For a given conditional copy, predicate the definition of the source of
927 /// the copy under the given condition (using the same predicate register as
929 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
930 std::set<unsigned> &UpdRegs) {
931 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
932 unsigned Opc = TfrI.getOpcode();
934 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
935 DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
938 MachineOperand &MD = TfrI.getOperand(0);
939 MachineOperand &MP = TfrI.getOperand(1);
940 MachineOperand &MS = TfrI.getOperand(2);
941 // The source operand should be a <kill>. This is not strictly necessary,
942 // but it makes things a lot simpler. Otherwise, we would need to rename
943 // some registers, which would complicate the transformation considerably.
946 // Avoid predicating instructions that define a subregister if subregister
947 // liveness tracking is not enabled.
948 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
952 unsigned PredR = MP.getReg();
953 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
954 if (!DefI || !isPredicable(DefI))
957 DEBUG(dbgs() << "Source def: " << *DefI);
959 // Collect the information about registers defined and used between the
960 // DefI and the TfrI.
961 // Map: reg -> bitmask of subregs
962 ReferenceMap Uses, Defs;
963 MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
965 // Check if the predicate register is valid between DefI and TfrI.
966 // If it is, we can then ignore instructions predicated on the negated
967 // conditions when collecting def and use information.
968 bool PredValid = true;
969 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
970 if (!I->modifiesRegister(PredR, nullptr))
976 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
977 MachineInstr *MI = &*I;
978 // If this instruction is predicated on the same register, it could
979 // potentially be ignored.
980 // By default assume that the instruction executes on the same condition
981 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
982 unsigned Exec = Exec_Then | Exec_Else;
983 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
984 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
986 for (auto &Op : MI->operands()) {
989 // We don't want to deal with physical registers. The reason is that
990 // they can be aliased with other physical registers. Aliased virtual
991 // registers must share the same register number, and can only differ
992 // in the subregisters, which we are keeping track of. Physical
993 // registers ters no longer have subregisters---their super- and
994 // subregisters are other physical registers, and we are not checking
997 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1000 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
1001 if (Op.isDef() && Op.isUndef()) {
1002 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
1003 // If this is a <def,read-undef>, then it invalidates the non-written
1004 // part of the register. For the purpose of checking the validity of
1005 // the move, assume that it modifies the whole register.
1008 addRefToMap(RR, Map, Exec);
1015 // RD = TfrI ..., RT
1017 // If the register-in-the-middle (RT) is used or redefined between
1018 // DefI and TfrI, we may not be able proceed with this transformation.
1019 // We can ignore a def that will not execute together with TfrI, and a
1020 // use that will. If there is such a use (that does execute together with
1021 // TfrI), we will not be able to move DefI down. If there is a use that
1022 // executed if TfrI's condition is false, then RT must be available
1023 // unconditionally (cannot be predicated).
1024 // Essentially, we need to be able to rename RT to RD in this segment.
1025 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
1027 RegisterRef RD = MD;
1028 // If the predicate register is defined between DefI and TfrI, the only
1029 // potential thing to do would be to move the DefI down to TfrI, and then
1030 // predicate. The reaching def (DefI) must be movable down to the location
1032 // If the target register of the TfrI (RD) is not used or defined between
1033 // DefI and TfrI, consider moving TfrI up to DefI.
1034 bool CanUp = canMoveOver(TfrI, Defs, Uses);
1035 bool CanDown = canMoveOver(*DefI, Defs, Uses);
1036 // The TfrI does not access memory, but DefI could. Check if it's safe
1037 // to move DefI down to TfrI.
1038 if (DefI->mayLoad() || DefI->mayStore())
1039 if (!canMoveMemTo(*DefI, TfrI, true))
1042 DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
1043 << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
1044 MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
1046 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
1048 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
1053 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
1054 UpdRegs.insert(RT.Reg);
1062 /// Predicate all cases of conditional copies in the specified block.
1063 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
1064 std::set<unsigned> &UpdRegs) {
1065 bool Changed = false;
1066 MachineBasicBlock::iterator I, E, NextI;
1067 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
1068 NextI = std::next(I);
1069 unsigned Opc = I->getOpcode();
1070 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1071 bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
1073 // If we didn't predicate I, we may need to remove it in case it is
1074 // an "identity" copy, e.g. %1 = A2_tfrt %2, %1.
1075 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1076 for (auto &Op : I->operands())
1078 UpdRegs.insert(Op.getReg());
1088 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1089 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1091 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1092 if (RC == &Hexagon::IntRegsRegClass) {
1096 if (RC == &Hexagon::DoubleRegsRegClass) {
1097 BW = (RR.Sub != 0) ? 32 : 64;
1103 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
1104 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
1105 LiveRange::Segment &LR = *I;
1106 // Range must start at a register...
1107 if (!LR.start.isRegister())
1109 // ...and end in a register or in a dead slot.
1110 if (!LR.end.isRegister() && !LR.end.isDead())
1116 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1117 if (CoaLimitActive) {
1118 if (CoaCounter >= CoaLimit)
1123 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2)
1125 if (MRI->isLiveIn(R1.Reg))
1127 if (MRI->isLiveIn(R2.Reg))
1130 LiveInterval &L1 = LIS->getInterval(R1.Reg);
1131 LiveInterval &L2 = LIS->getInterval(R2.Reg);
1134 if (L1.hasSubRanges() || L2.hasSubRanges())
1136 bool Overlap = L1.overlaps(L2);
1138 DEBUG(dbgs() << "compatible registers: ("
1139 << (Overlap ? "overlap" : "disjoint") << ")\n "
1140 << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1141 << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
1142 if (R1.Sub || R2.Sub)
1147 // Coalescing could have a negative impact on scheduling, so try to limit
1148 // to some reasonable extent. Only consider coalescing segments, when one
1149 // of them does not cross basic block boundaries.
1150 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1153 MRI->replaceRegWith(R2.Reg, R1.Reg);
1155 // Move all live segments from L2 to L1.
1156 using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
1158 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
1159 VNInfo *NewVN, *OldVN = I->valno;
1160 ValueInfoMap::iterator F = VM.find(OldVN);
1161 if (F == VM.end()) {
1162 NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
1163 VM.insert(std::make_pair(OldVN, NewVN));
1167 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
1169 while (L2.begin() != L2.end())
1170 L2.removeSegment(*L2.begin());
1171 LIS->removeInterval(R2.Reg);
1173 updateKillFlags(R1.Reg);
1174 DEBUG(dbgs() << "coalesced: " << L1 << "\n");
1180 /// Attempt to coalesce one of the source registers to a MUX instruction with
1181 /// the destination register. This could lead to having only one predicated
1182 /// instruction in the end instead of two.
1183 bool HexagonExpandCondsets::coalesceSegments(
1184 const SmallVectorImpl<MachineInstr*> &Condsets,
1185 std::set<unsigned> &UpdRegs) {
1186 SmallVector<MachineInstr*,16> TwoRegs;
1187 for (MachineInstr *MI : Condsets) {
1188 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1189 if (!S1.isReg() && !S2.isReg())
1191 TwoRegs.push_back(MI);
1194 bool Changed = false;
1195 for (MachineInstr *CI : TwoRegs) {
1196 RegisterRef RD = CI->getOperand(0);
1197 RegisterRef RP = CI->getOperand(1);
1198 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1200 // Consider this case:
1203 // %0 = C2_mux ..., %1, %2
1204 // If %0 was coalesced with %1, we could end up with the following
1208 // %0 = A2_tfrf ..., %2
1209 // which will later become:
1211 // %0 = instr2_cNotPt ...
1212 // i.e. there will be an unconditional definition (instr1) of %0
1213 // followed by a conditional one. The output dependency was there before
1214 // and it unavoidable, but if instr1 is predicable, we will no longer be
1215 // able to predicate it here.
1216 // To avoid this scenario, don't coalesce the destination register with
1217 // a source register that is defined by a predicable instruction.
1219 RegisterRef RS = S1;
1220 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1221 if (!RDef || !HII->isPredicable(*RDef)) {
1222 Done = coalesceRegisters(RD, RegisterRef(S1));
1224 UpdRegs.insert(RD.Reg);
1225 UpdRegs.insert(S1.getReg());
1229 if (!Done && S2.isReg()) {
1230 RegisterRef RS = S2;
1231 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
1232 if (!RDef || !HII->isPredicable(*RDef)) {
1233 Done = coalesceRegisters(RD, RegisterRef(S2));
1235 UpdRegs.insert(RD.Reg);
1236 UpdRegs.insert(S2.getReg());
1245 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
1246 if (skipFunction(MF.getFunction()))
1249 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
1250 TRI = MF.getSubtarget().getRegisterInfo();
1251 MDT = &getAnalysis<MachineDominatorTree>();
1252 LIS = &getAnalysis<LiveIntervals>();
1253 MRI = &MF.getRegInfo();
1255 DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
1256 MF.getFunction().getParent()));
1258 bool Changed = false;
1259 std::set<unsigned> CoalUpd, PredUpd;
1261 SmallVector<MachineInstr*,16> Condsets;
1265 Condsets.push_back(&I);
1267 // Try to coalesce the target of a mux with one of its sources.
1268 // This could eliminate a register copy in some circumstances.
1269 Changed |= coalesceSegments(Condsets, CoalUpd);
1271 // Update kill flags on all source operands. This is done here because
1272 // at this moment (when expand-condsets runs), there are no kill flags
1273 // in the IR (they have been removed by live range analysis).
1274 // Updating them right before we split is the easiest, because splitting
1275 // adds definitions which would interfere with updating kills afterwards.
1276 std::set<unsigned> KillUpd;
1277 for (MachineInstr *MI : Condsets)
1278 for (MachineOperand &Op : MI->operands())
1279 if (Op.isReg() && Op.isUse())
1280 if (!CoalUpd.count(Op.getReg()))
1281 KillUpd.insert(Op.getReg());
1282 updateLiveness(KillUpd, false, true, false);
1283 DEBUG(LIS->print(dbgs() << "After coalescing\n",
1284 MF.getFunction().getParent()));
1286 // First, simply split all muxes into a pair of conditional transfers
1287 // and update the live intervals to reflect the new arrangement. The
1288 // goal is to update the kill flags, since predication will rely on
1290 for (MachineInstr *MI : Condsets)
1291 Changed |= split(*MI, PredUpd);
1292 Condsets.clear(); // The contents of Condsets are invalid here anyway.
1294 // Do not update live ranges after splitting. Recalculation of live
1295 // intervals removes kill flags, which were preserved by splitting on
1296 // the source operands of condsets. These kill flags are needed by
1297 // predication, and after splitting they are difficult to recalculate
1298 // (because of predicated defs), so make sure they are left untouched.
1299 // Predication does not use live intervals.
1300 DEBUG(LIS->print(dbgs() << "After splitting\n",
1301 MF.getFunction().getParent()));
1303 // Traverse all blocks and collapse predicable instructions feeding
1304 // conditional transfers into predicated instructions.
1305 // Walk over all the instructions again, so we may catch pre-existing
1306 // cases that were not created in the previous step.
1308 Changed |= predicateInBlock(B, PredUpd);
1309 DEBUG(LIS->print(dbgs() << "After predicating\n",
1310 MF.getFunction().getParent()));
1312 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1313 updateLiveness(PredUpd, true, true, true);
1317 LIS->print(dbgs() << "After expand-condsets\n",
1318 MF.getFunction().getParent());
1324 //===----------------------------------------------------------------------===//
1325 // Public Constructor Functions
1326 //===----------------------------------------------------------------------===//
1328 FunctionPass *llvm::createHexagonExpandCondsets() {
1329 return new HexagonExpandCondsets();