1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "HexagonFrameLowering.h"
12 #include "HexagonBlockRanges.h"
13 #include "HexagonInstrInfo.h"
14 #include "HexagonMachineFunctionInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "HexagonTargetMachine.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/None.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/PostOrderIterator.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/LivePhysRegs.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineDominators.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineOperand.h"
38 #include "llvm/CodeGen/MachinePostDominators.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/RegisterScavenging.h"
41 #include "llvm/CodeGen/TargetRegisterInfo.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
66 #define DEBUG_TYPE "hexagon-pei"
68 // Hexagon stack frame layout as defined by the ABI:
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
83 // Low address High address
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
116 // Illustration of the AP:
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
148 // A - required alignment
150 using namespace llvm;
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156 cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160 cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
161 cl::init(6), cl::ZeroOrMore);
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164 cl::Hidden, cl::desc("Specify Os spill func threshold"),
165 cl::init(1), cl::ZeroOrMore);
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168 cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169 cl::init(false), cl::ZeroOrMore);
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
172 cl::init(true), cl::Hidden, cl::ZeroOrMore,
173 cl::desc("Enable stack frame shrink wrapping"));
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
176 cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, cl::ZeroOrMore,
177 cl::desc("Max count of stack frame shrink-wraps"));
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180 cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181 cl::init(false), cl::ZeroOrMore);
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184 cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187 cl::init(true), cl::desc("Optimize spill slots"));
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
191 cl::init(std::numeric_limits<unsigned>::max()));
192 static unsigned SpillOptCount = 0;
197 void initializeHexagonCallFrameInformationPass(PassRegistry&);
198 FunctionPass *createHexagonCallFrameInformation();
200 } // end namespace llvm
204 class HexagonCallFrameInformation : public MachineFunctionPass {
208 HexagonCallFrameInformation() : MachineFunctionPass(ID) {
209 PassRegistry &PR = *PassRegistry::getPassRegistry();
210 initializeHexagonCallFrameInformationPass(PR);
213 bool runOnMachineFunction(MachineFunction &MF) override;
215 MachineFunctionProperties getRequiredProperties() const override {
216 return MachineFunctionProperties().set(
217 MachineFunctionProperties::Property::NoVRegs);
221 char HexagonCallFrameInformation::ID = 0;
223 } // end anonymous namespace
225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227 bool NeedCFI = MF.getMMI().hasDebugInfo() ||
228 MF.getFunction().needsUnwindTableEntry();
232 HFI.insertCFIInstructions(MF);
236 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
237 "Hexagon call frame information", false, false)
239 FunctionPass *llvm::createHexagonCallFrameInformation() {
240 return new HexagonCallFrameInformation();
243 /// Map a register pair Reg to the subregister that has the greater "number",
244 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
245 static unsigned getMax32BitSubRegister(unsigned Reg,
246 const TargetRegisterInfo &TRI,
248 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
252 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
254 if (*SubRegs > RegNo)
257 if (!RegNo || *SubRegs < RegNo)
264 /// Returns the callee saved register with the largest id in the vector.
265 static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
266 const TargetRegisterInfo &TRI) {
267 static_assert(Hexagon::R1 > 0,
268 "Assume physical registers are encoded as positive integers");
272 unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
273 for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
274 unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
281 /// Checks if the basic block contains any instruction that needs a stack
282 /// frame to be already in place.
283 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
284 const HexagonRegisterInfo &HRI) {
285 for (auto &I : MBB) {
286 const MachineInstr *MI = &I;
289 unsigned Opc = MI->getOpcode();
291 case Hexagon::PS_alloca:
292 case Hexagon::PS_aligna:
297 // Check individual operands.
298 for (const MachineOperand &MO : MI->operands()) {
299 // While the presence of a frame index does not prove that a stack
300 // frame will be required, all frame indexes should be within alloc-
301 // frame/deallocframe. Otherwise, the code that translates a frame
302 // index into an offset would have to be aware of the placement of
303 // the frame creation/destruction instructions.
307 unsigned R = MO.getReg();
308 // Virtual registers will need scavenging, which then may require
310 if (TargetRegisterInfo::isVirtualRegister(R))
312 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
317 if (MO.isRegMask()) {
318 // A regmask would normally have all callee-saved registers marked
319 // as preserved, so this check would not be needed, but in case of
320 // ever having other regmasks (for other calling conventions),
321 // make sure they would be processed correctly.
322 const uint32_t *BM = MO.getRegMask();
323 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
325 // If this regmask does not preserve a CSR, a frame will be needed.
326 if (!(BM[R/32] & (1u << (R%32))))
335 /// Returns true if MBB has a machine instructions that indicates a tail call
337 static bool hasTailCall(const MachineBasicBlock &MBB) {
338 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
341 unsigned RetOpc = I->getOpcode();
342 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
345 /// Returns true if MBB contains an instruction that returns.
346 static bool hasReturn(const MachineBasicBlock &MBB) {
347 for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
353 /// Returns the "return" instruction from this block, or nullptr if there
355 static MachineInstr *getReturn(MachineBasicBlock &MBB) {
362 static bool isRestoreCall(unsigned Opc) {
364 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
365 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
366 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
367 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
368 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
369 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
370 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
371 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
377 static inline bool isOptNone(const MachineFunction &MF) {
378 return MF.getFunction().hasFnAttribute(Attribute::OptimizeNone) ||
379 MF.getTarget().getOptLevel() == CodeGenOpt::None;
382 static inline bool isOptSize(const MachineFunction &MF) {
383 const Function &F = MF.getFunction();
384 return F.optForSize() && !F.optForMinSize();
387 static inline bool isMinSize(const MachineFunction &MF) {
388 return MF.getFunction().optForMinSize();
391 /// Implements shrink-wrapping of the stack frame. By default, stack frame
392 /// is created in the function entry block, and is cleaned up in every block
393 /// that returns. This function finds alternate blocks: one for the frame
394 /// setup (prolog) and one for the cleanup (epilog).
395 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
396 MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
397 static unsigned ShrinkCounter = 0;
399 if (ShrinkLimit.getPosition()) {
400 if (ShrinkCounter >= ShrinkLimit)
405 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
407 MachineDominatorTree MDT;
408 MDT.runOnMachineFunction(MF);
409 MachinePostDominatorTree MPT;
410 MPT.runOnMachineFunction(MF);
412 using UnsignedMap = DenseMap<unsigned, unsigned>;
413 using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
418 for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
419 RPO[(*I)->getNumber()] = RPON++;
421 // Don't process functions that have loops, at least for now. Placement
422 // of prolog and epilog must take loop structure into account. For simpli-
423 // city don't do it right now.
425 unsigned BN = RPO[I.getNumber()];
426 for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
427 // If found a back-edge, return.
428 if (RPO[(*SI)->getNumber()] <= BN)
433 // Collect the set of blocks that need a stack frame to execute. Scan
434 // each block for uses/defs of callee-saved registers, calls, etc.
435 SmallVector<MachineBasicBlock*,16> SFBlocks;
436 BitVector CSR(Hexagon::NUM_TARGET_REGS);
437 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
438 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
442 if (needsStackFrame(I, CSR, HRI))
443 SFBlocks.push_back(&I);
446 dbgs() << "Blocks needing SF: {";
447 for (auto &B : SFBlocks)
448 dbgs() << " " << printMBBReference(*B);
452 if (SFBlocks.empty())
455 // Pick a common dominator and a common post-dominator.
456 MachineBasicBlock *DomB = SFBlocks[0];
457 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
458 DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
462 MachineBasicBlock *PDomB = SFBlocks[0];
463 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
464 PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
469 dbgs() << "Computed dom block: ";
471 dbgs() << printMBBReference(*DomB);
474 dbgs() << ", computed pdom block: ";
476 dbgs() << printMBBReference(*PDomB);
484 // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
485 if (!MDT.dominates(DomB, PDomB)) {
486 LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
489 if (!MPT.dominates(PDomB, DomB)) {
490 LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
494 // Finally, everything seems right.
499 /// Perform most of the PEI work here:
500 /// - saving/restoring of the callee-saved registers,
501 /// - stack frame creation and destruction.
502 /// Normally, this work is distributed among various functions, but doing it
503 /// in one place allows shrink-wrapping of the stack frame.
504 void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
505 MachineBasicBlock &MBB) const {
506 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
508 MachineFrameInfo &MFI = MF.getFrameInfo();
509 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
511 MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
512 if (EnableShrinkWrapping)
513 findShrunkPrologEpilog(MF, PrologB, EpilogB);
515 bool PrologueStubs = false;
516 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
517 insertPrologueInBlock(*PrologB, PrologueStubs);
518 updateEntryPaths(MF, *PrologB);
521 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
522 insertEpilogueInBlock(*EpilogB);
525 if (B.isReturnBlock())
526 insertCSRRestoresInBlock(B, CSI, HRI);
529 if (B.isReturnBlock())
530 insertEpilogueInBlock(B);
535 MachineInstr *RetI = getReturn(B);
536 if (!RetI || isRestoreCall(RetI->getOpcode()))
539 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
544 // If there is an epilog block, it may not have a return instruction.
545 // In such case, we need to add the callee-saved registers as live-ins
546 // in all blocks on all paths from the epilog to any return block.
547 unsigned MaxBN = MF.getNumBlockIDs();
548 BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
549 updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
553 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
554 bool PrologueStubs) const {
555 MachineFunction &MF = *MBB.getParent();
556 MachineFrameInfo &MFI = MF.getFrameInfo();
557 auto &HST = MF.getSubtarget<HexagonSubtarget>();
558 auto &HII = *HST.getInstrInfo();
559 auto &HRI = *HST.getRegisterInfo();
561 unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
563 // Calculate the total stack frame size.
564 // Get the number of bytes to allocate from the FrameInfo.
565 unsigned FrameSize = MFI.getStackSize();
566 // Round up the max call frame size to the max alignment on the stack.
567 unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
568 MFI.setMaxCallFrameSize(MaxCFA);
570 FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
571 MFI.setStackSize(FrameSize);
573 bool AlignStack = (MaxAlign > getStackAlignment());
575 // Get the number of bytes to allocate from the FrameInfo.
576 unsigned NumBytes = MFI.getStackSize();
577 unsigned SP = HRI.getStackRegister();
578 unsigned MaxCF = MFI.getMaxCallFrameSize();
579 MachineBasicBlock::iterator InsertPt = MBB.begin();
581 SmallVector<MachineInstr *, 4> AdjustRegs;
584 if (MI.getOpcode() == Hexagon::PS_alloca)
585 AdjustRegs.push_back(&MI);
587 for (auto MI : AdjustRegs) {
588 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
589 expandAlloca(MI, HII, SP, MaxCF);
590 MI->eraseFromParent();
593 DebugLoc dl = MBB.findDebugLoc(InsertPt);
596 insertAllocframe(MBB, InsertPt, NumBytes);
598 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
600 .addImm(-int64_t(MaxAlign));
602 // If the stack-checking is enabled, and we spilled the callee-saved
603 // registers inline (i.e. did not use a spill function), then call
604 // the stack checker directly.
605 if (EnableStackOVFSanitizer && !PrologueStubs)
606 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
607 .addExternalSymbol("__runtime_stack_check");
608 } else if (NumBytes > 0) {
609 assert(alignTo(NumBytes, 8) == NumBytes);
610 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
612 .addImm(-int(NumBytes));
616 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
617 MachineFunction &MF = *MBB.getParent();
618 auto &HST = MF.getSubtarget<HexagonSubtarget>();
619 auto &HII = *HST.getInstrInfo();
620 auto &HRI = *HST.getRegisterInfo();
621 unsigned SP = HRI.getStackRegister();
623 MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();
624 DebugLoc dl = MBB.findDebugLoc(InsertPt);
627 MachineFrameInfo &MFI = MF.getFrameInfo();
628 if (unsigned NumBytes = MFI.getStackSize()) {
629 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
636 MachineInstr *RetI = getReturn(MBB);
637 unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
640 if (RetOpc == Hexagon::EH_RETURN_JMPR) {
641 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
642 .addDef(Hexagon::D15)
643 .addReg(Hexagon::R30);
644 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
646 .addReg(Hexagon::R28);
650 // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
651 // frame instruction if we encounter it.
652 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
653 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
654 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
655 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
656 MachineBasicBlock::iterator It = RetI;
658 // Delete all instructions after the RESTORE (except labels).
659 while (It != MBB.end()) {
668 // It is possible that the restoring code is a call to a library function.
669 // All of the restore* functions include "deallocframe", so we need to make
670 // sure that we don't add an extra one.
671 bool NeedsDeallocframe = true;
672 if (!MBB.empty() && InsertPt != MBB.begin()) {
673 MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
674 unsigned COpc = PrevIt->getOpcode();
675 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
676 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
677 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
678 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
679 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
680 NeedsDeallocframe = false;
683 if (!NeedsDeallocframe)
685 // If the returning instruction is PS_jmpret, replace it with dealloc_return,
686 // otherwise just add deallocframe. The function could be returning via a
688 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
689 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
690 .addDef(Hexagon::D15)
691 .addReg(Hexagon::R30);
694 unsigned NewOpc = Hexagon::L4_return;
695 MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
696 .addDef(Hexagon::D15)
697 .addReg(Hexagon::R30);
698 // Transfer the function live-out registers.
699 NewI->copyImplicitOps(MF, *RetI);
703 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
704 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
705 MachineFunction &MF = *MBB.getParent();
706 auto &HST = MF.getSubtarget<HexagonSubtarget>();
707 auto &HII = *HST.getInstrInfo();
708 auto &HRI = *HST.getRegisterInfo();
710 // Check for overflow.
711 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
712 const unsigned int ALLOCFRAME_MAX = 16384;
714 // Create a dummy memory operand to avoid allocframe from being treated as
715 // a volatile memory reference.
716 auto *MMO = MF.getMachineMemOperand(MachinePointerInfo::getStack(MF, 0),
717 MachineMemOperand::MOStore, 4, 4);
719 DebugLoc dl = MBB.findDebugLoc(InsertPt);
720 unsigned SP = HRI.getStackRegister();
722 if (NumBytes >= ALLOCFRAME_MAX) {
723 // Emit allocframe(#0).
724 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
730 // Subtract the size from the stack pointer.
731 unsigned SP = HRI.getStackRegister();
732 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
734 .addImm(-int(NumBytes));
736 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
744 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
745 MachineBasicBlock &SaveB) const {
746 SetVector<unsigned> Worklist;
748 MachineBasicBlock &EntryB = MF.front();
749 Worklist.insert(EntryB.getNumber());
751 unsigned SaveN = SaveB.getNumber();
752 auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
754 for (unsigned i = 0; i < Worklist.size(); ++i) {
755 unsigned BN = Worklist[i];
756 MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);
758 if (!MBB.isLiveIn(R.getReg()))
759 MBB.addLiveIn(R.getReg());
761 for (auto &SB : MBB.successors())
762 Worklist.insert(SB->getNumber());
766 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
767 MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
768 BitVector &Path) const {
769 assert(MBB.getNumber() >= 0);
770 unsigned BN = MBB.getNumber();
771 if (Path[BN] || DoneF[BN])
776 auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
779 bool ReachedExit = false;
780 for (auto &SB : MBB.successors())
781 ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
783 if (!MBB.empty() && MBB.back().isReturn()) {
784 // Add implicit uses of all callee-saved registers to the reached
785 // return instructions. This is to prevent the anti-dependency breaker
786 // from renaming these registers.
787 MachineInstr &RetI = MBB.back();
788 if (!isRestoreCall(RetI.getOpcode()))
790 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
794 // We don't want to add unnecessary live-ins to the restore block: since
795 // the callee-saved registers are being defined in it, the entry of the
796 // restore block cannot be on the path from the definitions to any exit.
797 if (ReachedExit && &MBB != &RestoreB) {
799 if (!MBB.isLiveIn(R.getReg()))
800 MBB.addLiveIn(R.getReg());
810 static Optional<MachineBasicBlock::iterator>
811 findCFILocation(MachineBasicBlock &B) {
812 // The CFI instructions need to be inserted right after allocframe.
813 // An exception to this is a situation where allocframe is bundled
814 // with a call: then the CFI instructions need to be inserted before
815 // the packet with the allocframe+call (in case the call throws an
817 auto End = B.instr_end();
819 for (MachineInstr &I : B) {
820 MachineBasicBlock::iterator It = I.getIterator();
822 if (I.getOpcode() == Hexagon::S2_allocframe)
823 return std::next(It);
827 bool HasCall = false, HasAllocFrame = false;
828 auto T = It.getInstrIterator();
829 while (++T != End && T->isBundled()) {
830 if (T->getOpcode() == Hexagon::S2_allocframe)
831 HasAllocFrame = true;
832 else if (T->isCall())
836 return HasCall ? It : std::next(It);
841 void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {
843 auto At = findCFILocation(B);
845 insertCFIInstructionsAt(B, At.getValue());
849 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
850 MachineBasicBlock::iterator At) const {
851 MachineFunction &MF = *MBB.getParent();
852 MachineFrameInfo &MFI = MF.getFrameInfo();
853 MachineModuleInfo &MMI = MF.getMMI();
854 auto &HST = MF.getSubtarget<HexagonSubtarget>();
855 auto &HII = *HST.getInstrInfo();
856 auto &HRI = *HST.getRegisterInfo();
858 // If CFI instructions have debug information attached, something goes
859 // wrong with the final assembly generation: the prolog_end is placed
860 // in a wrong location.
862 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
864 MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
865 bool HasFP = hasFP(MF);
868 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
869 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
871 // Define CFA via an offset from the value of FP.
874 // --+----+----+---------------------
875 // | FP | LR | increasing addresses -->
876 // --+----+----+---------------------
877 // | +-- Old SP (before allocframe)
878 // +-- New FP (after allocframe)
880 // MCCFIInstruction::createDefCfa subtracts the offset from the register.
881 // MCCFIInstruction::createOffset takes the offset without sign change.
882 auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8);
883 BuildMI(MBB, At, DL, CFID)
884 .addCFIIndex(MF.addFrameInst(DefCfa));
885 // R31 (return addr) = CFA - 4
886 auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
887 BuildMI(MBB, At, DL, CFID)
888 .addCFIIndex(MF.addFrameInst(OffR31));
889 // R30 (frame ptr) = CFA - 8
890 auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
891 BuildMI(MBB, At, DL, CFID)
892 .addCFIIndex(MF.addFrameInst(OffR30));
895 static unsigned int RegsToMove[] = {
896 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
897 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
898 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
899 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
900 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
901 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
905 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
907 for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
908 unsigned Reg = RegsToMove[i];
909 auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
910 return C.getReg() == Reg;
912 auto F = find_if(CSI, IfR);
918 // If the function has a frame pointer (i.e. has an allocframe),
919 // then the CFA has been defined in terms of FP. Any offsets in
920 // the following CFI instructions have to be defined relative
921 // to FP, which points to the bottom of the stack frame.
922 // The function getFrameIndexReference can still choose to use SP
923 // for the offset calculation, so we cannot simply call it here.
924 // Instead, get the offset (relative to the FP) directly.
925 Offset = MFI.getObjectOffset(F->getFrameIdx());
928 Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg);
930 // Subtract 8 to make room for R30 and R31, which are added above.
933 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
934 unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
935 auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
937 BuildMI(MBB, At, DL, CFID)
938 .addCFIIndex(MF.addFrameInst(OffReg));
940 // Split the double regs into subregs, and generate appropriate
942 // The only reason, we are split double regs is, llvm-mc does not
943 // understand paired registers for cfi_offset.
944 // Eg .cfi_offset r1:0, -64
946 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
947 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
948 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
949 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
950 auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
952 BuildMI(MBB, At, DL, CFID)
953 .addCFIIndex(MF.addFrameInst(OffHi));
954 auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
956 BuildMI(MBB, At, DL, CFID)
957 .addCFIIndex(MF.addFrameInst(OffLo));
962 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
963 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
966 auto &MFI = MF.getFrameInfo();
967 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
968 bool HasExtraAlign = HRI.needsStackRealignment(MF);
969 bool HasAlloca = MFI.hasVarSizedObjects();
971 // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
972 // that this shouldn't be required, but doing so now because gcc does and
973 // gdb can't break at the start of the function without it. Will remove if
974 // this turns out to be a gdb bug.
976 if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
979 // By default we want to use SP (since it's always there). FP requires
980 // some setup (i.e. ALLOCFRAME).
981 // Both, alloca and stack alignment modify the stack pointer by an
982 // undetermined value, so we need to save it at the entry to the function
983 // (i.e. use allocframe).
984 if (HasAlloca || HasExtraAlign)
987 if (MFI.getStackSize() > 0) {
988 // If FP-elimination is disabled, we have to use FP at this point.
989 const TargetMachine &TM = MF.getTarget();
990 if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
992 if (EnableStackOVFSanitizer)
996 const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
997 if (MFI.hasCalls() || HMFI.hasClobberLR())
1009 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
1010 bool Stkchk = false) {
1011 const char * V4SpillToMemoryFunctions[] = {
1012 "__save_r16_through_r17",
1013 "__save_r16_through_r19",
1014 "__save_r16_through_r21",
1015 "__save_r16_through_r23",
1016 "__save_r16_through_r25",
1017 "__save_r16_through_r27" };
1019 const char * V4SpillToMemoryStkchkFunctions[] = {
1020 "__save_r16_through_r17_stkchk",
1021 "__save_r16_through_r19_stkchk",
1022 "__save_r16_through_r21_stkchk",
1023 "__save_r16_through_r23_stkchk",
1024 "__save_r16_through_r25_stkchk",
1025 "__save_r16_through_r27_stkchk" };
1027 const char * V4SpillFromMemoryFunctions[] = {
1028 "__restore_r16_through_r17_and_deallocframe",
1029 "__restore_r16_through_r19_and_deallocframe",
1030 "__restore_r16_through_r21_and_deallocframe",
1031 "__restore_r16_through_r23_and_deallocframe",
1032 "__restore_r16_through_r25_and_deallocframe",
1033 "__restore_r16_through_r27_and_deallocframe" };
1035 const char * V4SpillFromMemoryTailcallFunctions[] = {
1036 "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1037 "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1038 "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1039 "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1040 "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1041 "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1044 const char **SpillFunc = nullptr;
1048 SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1049 : V4SpillToMemoryFunctions;
1052 SpillFunc = V4SpillFromMemoryFunctions;
1054 case SK_FromMemTailcall:
1055 SpillFunc = V4SpillFromMemoryTailcallFunctions;
1058 assert(SpillFunc && "Unknown spill kind");
1060 // Spill all callee-saved registers up to the highest register used.
1063 return SpillFunc[0];
1065 return SpillFunc[1];
1067 return SpillFunc[2];
1069 return SpillFunc[3];
1071 return SpillFunc[4];
1073 return SpillFunc[5];
1075 llvm_unreachable("Unhandled maximum callee save register");
1080 int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
1081 int FI, unsigned &FrameReg) const {
1082 auto &MFI = MF.getFrameInfo();
1083 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1085 int Offset = MFI.getObjectOffset(FI);
1086 bool HasAlloca = MFI.hasVarSizedObjects();
1087 bool HasExtraAlign = HRI.needsStackRealignment(MF);
1088 bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1090 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1091 unsigned FrameSize = MFI.getStackSize();
1092 unsigned SP = HRI.getStackRegister();
1093 unsigned FP = HRI.getFrameRegister();
1094 unsigned AP = HMFI.getStackAlignBasePhysReg();
1095 // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1096 // is true. HasExtraAlign may be set because of vector spills, without
1097 // aligned locals or aligned outgoing function arguments. Since vector
1098 // spills will ultimately be "unaligned", it is safe to use FP as the
1100 // In fact, in such a scenario the stack is actually not required to be
1101 // aligned, although it may end up being aligned anyway, since this
1102 // particular case is not easily detectable. The alignment will be
1103 // unnecessary, but not incorrect.
1104 // Unfortunately there is no quick way to verify that the above is
1105 // indeed the case (and that it's not a result of an error), so just
1106 // assume that missing AP will be replaced by FP.
1107 // (A better fix would be to rematerialize AP from FP and always align
1112 bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1113 // Use FP at -O0, except when there are objects with extra alignment.
1114 // That additional alignment requirement may cause a pad to be inserted,
1115 // which will make it impossible to use FP to access objects located
1117 if (NoOpt && !HasExtraAlign)
1119 if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1120 // Fixed and preallocated objects will be located before any padding
1121 // so FP must be used to access them.
1122 UseFP |= (HasAlloca || HasExtraAlign);
1132 // If FP was picked, then there had better be FP.
1133 bool HasFP = hasFP(MF);
1134 assert((HasFP || !UseFP) && "This function must have frame pointer");
1136 // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1137 // FP/LR. If the base register is used to access an object across these
1138 // 8 bytes, then the offset will need to be adjusted by 8.
1140 // After allocframe:
1141 // HexagonISelLowering adds 8 to ---+
1142 // the offsets of all stack-based |
1145 // getObjectOffset < 0 0 8 getObjectOffset >= 8
1146 // ------------------------+-----+------------------------> increasing
1147 // <local objects> |FP/LR| <input arguments> addresses
1148 // -----------------+------+-----+------------------------>
1150 // SP/AP point --+ +-- FP points here (**)
1152 // this side of FP/LR
1154 // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1155 // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1157 // The lowering assumes that FP/LR is present, and so the offsets of
1158 // the formal arguments start at 8. If FP/LR is not there we need to
1159 // reduce the offset by 8.
1160 if (Offset > 0 && !HasFP)
1170 // Calculate the actual offset in the instruction. If there is no FP
1171 // (in other words, no allocframe), then SP will not be adjusted (i.e.
1172 // there will be no SP -= FrameSize), so the frame size should not be
1173 // added to the calculated offset.
1174 int RealOffset = Offset;
1175 if (!UseFP && !UseAP)
1176 RealOffset = FrameSize+Offset;
1180 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1181 const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1182 bool &PrologueStubs) const {
1186 MachineBasicBlock::iterator MI = MBB.begin();
1187 PrologueStubs = false;
1188 MachineFunction &MF = *MBB.getParent();
1189 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1190 auto &HII = *HST.getInstrInfo();
1192 if (useSpillFunction(MF, CSI)) {
1193 PrologueStubs = true;
1194 unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1195 bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1196 const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1198 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1199 bool IsPIC = HTM.isPositionIndependent();
1200 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1202 // Call spill function.
1203 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1205 if (StkOvrFlowEnabled) {
1207 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1208 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1210 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1211 : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1214 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1215 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1217 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1218 : Hexagon::SAVE_REGISTERS_CALL_V4;
1221 MachineInstr *SaveRegsCall =
1222 BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1223 .addExternalSymbol(SpillFun);
1225 // Add callee-saved registers as use.
1226 addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1227 // Add live in registers.
1228 for (unsigned I = 0; I < CSI.size(); ++I)
1229 MBB.addLiveIn(CSI[I].getReg());
1233 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1234 unsigned Reg = CSI[i].getReg();
1235 // Add live in registers. We treat eh_return callee saved register r0 - r3
1236 // specially. They are not really callee saved registers as they are not
1237 // supposed to be killed.
1238 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1239 int FI = CSI[i].getFrameIdx();
1240 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1241 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1248 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1249 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1253 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1254 MachineFunction &MF = *MBB.getParent();
1255 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1256 auto &HII = *HST.getInstrInfo();
1258 if (useRestoreFunction(MF, CSI)) {
1259 bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1260 unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1261 SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;
1262 const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1263 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1264 bool IsPIC = HTM.isPositionIndependent();
1265 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1267 // Call spill function.
1268 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1269 : MBB.getLastNonDebugInstr()->getDebugLoc();
1270 MachineInstr *DeallocCall = nullptr;
1275 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1276 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1278 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1279 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1280 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1281 .addExternalSymbol(RestoreFn);
1283 // The block has a return.
1284 MachineBasicBlock::iterator It = MBB.getFirstTerminator();
1285 assert(It->isReturn() && std::next(It) == MBB.end());
1288 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1289 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1291 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1292 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1293 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1294 .addExternalSymbol(RestoreFn);
1295 // Transfer the function live-out registers.
1296 DeallocCall->copyImplicitOps(MF, *It);
1298 addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1302 for (unsigned i = 0; i < CSI.size(); ++i) {
1303 unsigned Reg = CSI[i].getReg();
1304 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1305 int FI = CSI[i].getFrameIdx();
1306 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1312 MachineBasicBlock::iterator HexagonFrameLowering::eliminateCallFramePseudoInstr(
1313 MachineFunction &MF, MachineBasicBlock &MBB,
1314 MachineBasicBlock::iterator I) const {
1315 MachineInstr &MI = *I;
1316 unsigned Opc = MI.getOpcode();
1317 (void)Opc; // Silence compiler warning.
1318 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1319 "Cannot handle this call frame pseudo instruction");
1320 return MBB.erase(I);
1323 void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
1324 MachineFunction &MF, RegScavenger *RS) const {
1325 // If this function has uses aligned stack and also has variable sized stack
1326 // objects, then we need to map all spill slots to fixed positions, so that
1327 // they can be accessed through FP. Otherwise they would have to be accessed
1328 // via AP, which may not be available at the particular place in the program.
1329 MachineFrameInfo &MFI = MF.getFrameInfo();
1330 bool HasAlloca = MFI.hasVarSizedObjects();
1331 bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
1333 if (!HasAlloca || !NeedsAlign)
1336 unsigned LFS = MFI.getLocalFrameSize();
1337 for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1338 if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1340 unsigned S = MFI.getObjectSize(i);
1341 // Reduce the alignment to at most 8. This will require unaligned vector
1342 // stores if they happen here.
1343 unsigned A = std::max(MFI.getObjectAlignment(i), 8U);
1344 MFI.setObjectAlignment(i, 8);
1345 LFS = alignTo(LFS+S, A);
1346 MFI.mapLocalFrameObject(i, -LFS);
1349 MFI.setLocalFrameSize(LFS);
1350 unsigned A = MFI.getLocalFrameMaxAlign();
1351 assert(A <= 8 && "Unexpected local frame alignment");
1353 MFI.setLocalFrameMaxAlign(8);
1354 MFI.setUseLocalStackAllocationBlock(true);
1356 // Set the physical aligned-stack base address register.
1358 if (const MachineInstr *AI = getAlignaInstr(MF))
1359 AP = AI->getOperand(0).getReg();
1360 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1361 HMFI.setStackAlignBasePhysReg(AP);
1364 /// Returns true if there are no caller-saved registers available in class RC.
1365 static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
1366 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1367 MachineRegisterInfo &MRI = MF.getRegInfo();
1369 auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1370 for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1371 if (MRI.isPhysRegUsed(*AI))
1376 // Check for an unused caller-saved register. Callee-saved registers
1377 // have become pristine by now.
1378 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1382 // All caller-saved registers are used.
1387 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1389 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1391 dbgs() << ' ' << printReg(R, &TRI);
1397 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
1398 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1399 LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1400 MachineFrameInfo &MFI = MF.getFrameInfo();
1401 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1403 // Generate a set of unique, callee-saved registers (SRegs), where each
1404 // register in the set is maximal in terms of sub-/super-register relation,
1405 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1407 // (1) For each callee-saved register, add that register and all of its
1408 // sub-registers to SRegs.
1409 LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1410 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1411 unsigned R = CSI[i].getReg();
1412 LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1413 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1416 LLVM_DEBUG(dbgs() << " }\n");
1417 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1420 // (2) For each reserved register, remove that register and all of its
1421 // sub- and super-registers from SRegs.
1422 BitVector Reserved = TRI->getReservedRegs(MF);
1423 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1425 for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1428 LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1430 LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1433 // (3) Collect all registers that have at least one sub-register in SRegs,
1434 // and also have no sub-registers that are reserved. These will be the can-
1435 // didates for saving as a whole instead of their individual sub-registers.
1436 // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1437 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1438 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1440 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1443 for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1445 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1452 LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1455 // (4) Include all super-registers found in (3) into SRegs.
1457 LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1460 // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1461 // remove R from SRegs.
1462 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1464 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1471 LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1474 // Now, for each register that has a fixed stack slot, create the stack
1478 using SpillSlot = TargetFrameLowering::SpillSlot;
1481 int MinOffset = 0; // CS offsets are negative.
1482 const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1483 for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1486 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1487 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1488 MinOffset = std::min(MinOffset, S->Offset);
1489 CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1490 SRegs[S->Reg] = false;
1493 // There can be some registers that don't have fixed slots. For example,
1494 // we need to store R0-R3 in functions with exception handling. For each
1495 // such register, create a non-fixed stack object.
1496 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1498 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1499 unsigned Size = TRI->getSpillSize(*RC);
1500 int Off = MinOffset - Size;
1501 unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment());
1502 assert(isPowerOf2_32(Align));
1504 int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1505 MinOffset = std::min(MinOffset, Off);
1506 CSI.push_back(CalleeSavedInfo(R, FI));
1511 dbgs() << "CS information: {";
1512 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1513 int FI = CSI[i].getFrameIdx();
1514 int Off = MFI.getObjectOffset(FI);
1515 dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1524 // Verify that all registers were handled.
1525 bool MissedReg = false;
1526 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1528 dbgs() << printReg(R, TRI) << ' ';
1532 llvm_unreachable("...there are unhandled callee-saved registers!");
1538 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1539 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1540 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1541 MachineInstr *MI = &*It;
1542 DebugLoc DL = MI->getDebugLoc();
1543 unsigned DstR = MI->getOperand(0).getReg();
1544 unsigned SrcR = MI->getOperand(1).getReg();
1545 if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1546 !Hexagon::ModRegsRegClass.contains(SrcR))
1549 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1550 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1551 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1552 .addReg(TmpR, RegState::Kill);
1554 NewRegs.push_back(TmpR);
1559 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1560 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1561 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1562 MachineInstr *MI = &*It;
1563 if (!MI->getOperand(0).isFI())
1566 DebugLoc DL = MI->getDebugLoc();
1567 unsigned Opc = MI->getOpcode();
1568 unsigned SrcR = MI->getOperand(2).getReg();
1569 bool IsKill = MI->getOperand(2).isKill();
1570 int FI = MI->getOperand(0).getIndex();
1572 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1573 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1574 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1575 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1576 : Hexagon::A2_tfrcrr;
1577 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1578 .addReg(SrcR, getKillRegState(IsKill));
1580 // S2_storeri_io FI, 0, TmpR
1581 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1584 .addReg(TmpR, RegState::Kill)
1585 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1587 NewRegs.push_back(TmpR);
1592 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1593 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1594 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1595 MachineInstr *MI = &*It;
1596 if (!MI->getOperand(1).isFI())
1599 DebugLoc DL = MI->getDebugLoc();
1600 unsigned Opc = MI->getOpcode();
1601 unsigned DstR = MI->getOperand(0).getReg();
1602 int FI = MI->getOperand(1).getIndex();
1604 // TmpR = L2_loadri_io FI, 0
1605 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1606 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1609 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1611 // DstR = C2_tfrrp TmpR if DstR is a predicate register
1612 // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1613 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1614 : Hexagon::A2_tfrrcr;
1615 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1616 .addReg(TmpR, RegState::Kill);
1618 NewRegs.push_back(TmpR);
1623 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1624 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1625 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1626 MachineInstr *MI = &*It;
1627 if (!MI->getOperand(0).isFI())
1630 DebugLoc DL = MI->getDebugLoc();
1631 unsigned SrcR = MI->getOperand(2).getReg();
1632 bool IsKill = MI->getOperand(2).isKill();
1633 int FI = MI->getOperand(0).getIndex();
1634 auto *RC = &Hexagon::HvxVRRegClass;
1636 // Insert transfer to general vector register.
1637 // TmpR0 = A2_tfrsi 0x01010101
1638 // TmpR1 = V6_vandqrt Qx, TmpR0
1639 // store FI, 0, TmpR1
1640 unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1641 unsigned TmpR1 = MRI.createVirtualRegister(RC);
1643 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1644 .addImm(0x01010101);
1646 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1647 .addReg(SrcR, getKillRegState(IsKill))
1648 .addReg(TmpR0, RegState::Kill);
1650 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1651 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1652 expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1654 NewRegs.push_back(TmpR0);
1655 NewRegs.push_back(TmpR1);
1660 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1661 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1662 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1663 MachineInstr *MI = &*It;
1664 if (!MI->getOperand(1).isFI())
1667 DebugLoc DL = MI->getDebugLoc();
1668 unsigned DstR = MI->getOperand(0).getReg();
1669 int FI = MI->getOperand(1).getIndex();
1670 auto *RC = &Hexagon::HvxVRRegClass;
1672 // TmpR0 = A2_tfrsi 0x01010101
1673 // TmpR1 = load FI, 0
1674 // DstR = V6_vandvrt TmpR1, TmpR0
1675 unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1676 unsigned TmpR1 = MRI.createVirtualRegister(RC);
1678 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1679 .addImm(0x01010101);
1680 MachineFunction &MF = *B.getParent();
1681 auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1682 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1683 expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1685 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1686 .addReg(TmpR1, RegState::Kill)
1687 .addReg(TmpR0, RegState::Kill);
1689 NewRegs.push_back(TmpR0);
1690 NewRegs.push_back(TmpR1);
1695 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1696 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1697 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1698 MachineFunction &MF = *B.getParent();
1699 auto &MFI = MF.getFrameInfo();
1700 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1701 MachineInstr *MI = &*It;
1702 if (!MI->getOperand(0).isFI())
1705 // It is possible that the double vector being stored is only partially
1706 // defined. From the point of view of the liveness tracking, it is ok to
1707 // store it as a whole, but if we break it up we may end up storing a
1708 // register that is entirely undefined.
1709 LivePhysRegs LPR(HRI);
1711 SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers;
1712 for (auto R = B.begin(); R != It; ++R) {
1714 LPR.stepForward(*R, Clobbers);
1717 DebugLoc DL = MI->getDebugLoc();
1718 unsigned SrcR = MI->getOperand(2).getReg();
1719 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1720 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1721 bool IsKill = MI->getOperand(2).isKill();
1722 int FI = MI->getOperand(0).getIndex();
1724 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1725 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1726 unsigned HasAlign = MFI.getObjectAlignment(FI);
1730 if (LPR.contains(SrcLo)) {
1731 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1732 : Hexagon::V6_vS32Ub_ai;
1733 BuildMI(B, It, DL, HII.get(StoreOpc))
1736 .addReg(SrcLo, getKillRegState(IsKill))
1737 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1741 if (LPR.contains(SrcHi)) {
1742 StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai
1743 : Hexagon::V6_vS32Ub_ai;
1744 BuildMI(B, It, DL, HII.get(StoreOpc))
1747 .addReg(SrcHi, getKillRegState(IsKill))
1748 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1755 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1756 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1757 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1758 MachineFunction &MF = *B.getParent();
1759 auto &MFI = MF.getFrameInfo();
1760 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1761 MachineInstr *MI = &*It;
1762 if (!MI->getOperand(1).isFI())
1765 DebugLoc DL = MI->getDebugLoc();
1766 unsigned DstR = MI->getOperand(0).getReg();
1767 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1768 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1769 int FI = MI->getOperand(1).getIndex();
1771 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1772 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1773 unsigned HasAlign = MFI.getObjectAlignment(FI);
1777 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1778 : Hexagon::V6_vL32Ub_ai;
1779 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1782 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1785 LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai
1786 : Hexagon::V6_vL32Ub_ai;
1787 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1790 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1796 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1797 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1798 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1799 MachineFunction &MF = *B.getParent();
1800 auto &MFI = MF.getFrameInfo();
1801 MachineInstr *MI = &*It;
1802 if (!MI->getOperand(0).isFI())
1805 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1806 DebugLoc DL = MI->getDebugLoc();
1807 unsigned SrcR = MI->getOperand(2).getReg();
1808 bool IsKill = MI->getOperand(2).isKill();
1809 int FI = MI->getOperand(0).getIndex();
1811 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1812 unsigned HasAlign = MFI.getObjectAlignment(FI);
1813 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1814 : Hexagon::V6_vS32Ub_ai;
1815 BuildMI(B, It, DL, HII.get(StoreOpc))
1818 .addReg(SrcR, getKillRegState(IsKill))
1819 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1825 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
1826 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1827 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1828 MachineFunction &MF = *B.getParent();
1829 auto &MFI = MF.getFrameInfo();
1830 MachineInstr *MI = &*It;
1831 if (!MI->getOperand(1).isFI())
1834 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1835 DebugLoc DL = MI->getDebugLoc();
1836 unsigned DstR = MI->getOperand(0).getReg();
1837 int FI = MI->getOperand(1).getIndex();
1839 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1840 unsigned HasAlign = MFI.getObjectAlignment(FI);
1841 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1842 : Hexagon::V6_vL32Ub_ai;
1843 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
1846 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1852 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
1853 SmallVectorImpl<unsigned> &NewRegs) const {
1854 auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1855 MachineRegisterInfo &MRI = MF.getRegInfo();
1856 bool Changed = false;
1858 for (auto &B : MF) {
1859 // Traverse the basic block.
1860 MachineBasicBlock::iterator NextI;
1861 for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
1862 MachineInstr *MI = &*I;
1863 NextI = std::next(I);
1864 unsigned Opc = MI->getOpcode();
1867 case TargetOpcode::COPY:
1868 Changed |= expandCopy(B, I, MRI, HII, NewRegs);
1870 case Hexagon::STriw_pred:
1871 case Hexagon::STriw_ctr:
1872 Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
1874 case Hexagon::LDriw_pred:
1875 case Hexagon::LDriw_ctr:
1876 Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
1878 case Hexagon::PS_vstorerq_ai:
1879 Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
1881 case Hexagon::PS_vloadrq_ai:
1882 Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
1884 case Hexagon::PS_vloadrw_ai:
1885 case Hexagon::PS_vloadrwu_ai:
1886 Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
1888 case Hexagon::PS_vstorerw_ai:
1889 case Hexagon::PS_vstorerwu_ai:
1890 Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
1899 void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
1900 BitVector &SavedRegs,
1901 RegScavenger *RS) const {
1902 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1904 SavedRegs.resize(HRI.getNumRegs());
1906 // If we have a function containing __builtin_eh_return we want to spill and
1907 // restore all callee saved registers. Pretend that they are used.
1908 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
1909 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
1912 // Replace predicate register pseudo spill code.
1913 SmallVector<unsigned,8> NewRegs;
1914 expandSpillMacros(MF, NewRegs);
1915 if (OptimizeSpillSlots && !isOptNone(MF))
1916 optimizeSpillSlots(MF, NewRegs);
1918 // We need to reserve a spill slot if scavenging could potentially require
1919 // spilling a scavenged register.
1920 if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
1921 MachineFrameInfo &MFI = MF.getFrameInfo();
1922 MachineRegisterInfo &MRI = MF.getRegInfo();
1923 SetVector<const TargetRegisterClass*> SpillRCs;
1924 // Reserve an int register in any case, because it could be used to hold
1925 // the stack offset in case it does not fit into a spill instruction.
1926 SpillRCs.insert(&Hexagon::IntRegsRegClass);
1928 for (unsigned VR : NewRegs)
1929 SpillRCs.insert(MRI.getRegClass(VR));
1931 for (auto *RC : SpillRCs) {
1932 if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
1934 unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1935 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);
1936 for (unsigned i = 0; i < Num; i++) {
1937 int NewFI = MFI.CreateSpillStackObject(S, A);
1938 RS->addScavengingFrameIndex(NewFI);
1943 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1946 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
1947 HexagonBlockRanges::IndexRange &FIR,
1948 HexagonBlockRanges::InstrIndexMap &IndexMap,
1949 HexagonBlockRanges::RegToRangeMap &DeadMap,
1950 const TargetRegisterClass *RC) const {
1951 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1952 auto &MRI = MF.getRegInfo();
1954 auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
1955 auto F = DeadMap.find({Reg,0});
1956 if (F == DeadMap.end())
1958 for (auto &DR : F->second)
1959 if (DR.contains(FIR))
1964 for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
1966 for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
1978 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
1979 SmallVectorImpl<unsigned> &VRegs) const {
1980 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1981 auto &HII = *HST.getInstrInfo();
1982 auto &HRI = *HST.getRegisterInfo();
1983 auto &MRI = MF.getRegInfo();
1984 HexagonBlockRanges HBR(MF);
1986 using BlockIndexMap =
1987 std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
1988 using BlockRangeMap =
1989 std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
1990 using IndexType = HexagonBlockRanges::IndexType;
1995 const TargetRegisterClass *RC = nullptr;
1997 SlotInfo() = default;
2000 BlockIndexMap BlockIndexes;
2001 SmallSet<int,4> BadFIs;
2002 std::map<int,SlotInfo> FIRangeMap;
2004 // Accumulate register classes: get a common class for a pre-existing
2005 // class HaveRC and a new class NewRC. Return nullptr if a common class
2006 // cannot be found, otherwise return the resulting class. If HaveRC is
2007 // nullptr, assume that it is still unset.
2009 [](const TargetRegisterClass *HaveRC,
2010 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2011 if (HaveRC == nullptr || HaveRC == NewRC)
2013 // Different classes, both non-null. Pick the more general one.
2014 if (HaveRC->hasSubClassEq(NewRC))
2016 if (NewRC->hasSubClassEq(HaveRC))
2021 // Scan all blocks in the function. Check all occurrences of frame indexes,
2022 // and collect relevant information.
2023 for (auto &B : MF) {
2024 std::map<int,IndexType> LastStore, LastLoad;
2025 // Emplace appears not to be supported in gcc 4.7.2-4.
2026 //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2027 auto P = BlockIndexes.insert(
2028 std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2029 auto &IndexMap = P.first->second;
2030 LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2031 << IndexMap << '\n');
2033 for (auto &In : B) {
2035 bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2036 bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2037 if (Load && Store) {
2038 // If it's both a load and a store, then we won't handle it.
2043 // Check for register classes of the register used as the source for
2044 // the store, and the register used as the destination for the load.
2045 // Also, only accept base+imm_offset addressing modes. Other addressing
2046 // modes can have side-effects (post-increments, etc.). For stack
2047 // slots they are very unlikely, so there is not much loss due to
2048 // this restriction.
2049 if (Load || Store) {
2050 int TFI = Load ? LFI : SFI;
2051 unsigned AM = HII.getAddrMode(In);
2052 SlotInfo &SI = FIRangeMap[TFI];
2053 bool Bad = (AM != HexagonII::BaseImmOffset);
2055 // If the addressing mode is ok, check the register class.
2056 unsigned OpNum = Load ? 0 : 2;
2057 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2058 RC = getCommonRC(SI.RC, RC);
2066 unsigned S = HII.getMemAccessSize(In);
2067 if (SI.Size != 0 && SI.Size != S)
2073 for (auto *Mo : In.memoperands()) {
2074 if (!Mo->isVolatile())
2084 // Locate uses of frame indices.
2085 for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2086 const MachineOperand &Op = In.getOperand(i);
2089 int FI = Op.getIndex();
2090 // Make sure that the following operand is an immediate and that
2091 // it is 0. This is the offset in the stack object.
2092 if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2093 In.getOperand(i+1).getImm() != 0)
2095 if (BadFIs.count(FI))
2098 IndexType Index = IndexMap.getIndex(&In);
2100 if (LastStore[FI] == IndexType::None)
2101 LastStore[FI] = IndexType::Entry;
2102 LastLoad[FI] = Index;
2104 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2105 if (LastStore[FI] != IndexType::None)
2106 RL.add(LastStore[FI], LastLoad[FI], false, false);
2107 else if (LastLoad[FI] != IndexType::None)
2108 RL.add(IndexType::Entry, LastLoad[FI], false, false);
2109 LastLoad[FI] = IndexType::None;
2110 LastStore[FI] = Index;
2117 for (auto &I : LastLoad) {
2118 IndexType LL = I.second;
2119 if (LL == IndexType::None)
2121 auto &RL = FIRangeMap[I.first].Map[&B];
2122 IndexType &LS = LastStore[I.first];
2123 if (LS != IndexType::None)
2124 RL.add(LS, LL, false, false);
2126 RL.add(IndexType::Entry, LL, false, false);
2127 LS = IndexType::None;
2129 for (auto &I : LastStore) {
2130 IndexType LS = I.second;
2131 if (LS == IndexType::None)
2133 auto &RL = FIRangeMap[I.first].Map[&B];
2134 RL.add(LS, IndexType::None, false, false);
2139 for (auto &P : FIRangeMap) {
2140 dbgs() << "fi#" << P.first;
2141 if (BadFIs.count(P.first))
2144 if (P.second.RC != nullptr)
2145 dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2147 dbgs() << "<null>\n";
2148 for (auto &R : P.second.Map)
2149 dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2154 // When a slot is loaded from in a block without being stored to in the
2155 // same block, it is live-on-entry to this block. To avoid CFG analysis,
2156 // consider this slot to be live-on-exit from all blocks.
2157 SmallSet<int,4> LoxFIs;
2159 std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2161 for (auto &P : FIRangeMap) {
2162 // P = pair(FI, map: BB->RangeList)
2163 if (BadFIs.count(P.first))
2165 for (auto &B : MF) {
2166 auto F = P.second.Map.find(&B);
2167 // F = pair(BB, RangeList)
2168 if (F == P.second.Map.end() || F->second.empty())
2170 HexagonBlockRanges::IndexRange &IR = F->second.front();
2171 if (IR.start() == IndexType::Entry)
2172 LoxFIs.insert(P.first);
2173 BlockFIMap[&B].push_back(P.first);
2178 dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2179 for (auto &P : BlockFIMap) {
2180 auto &FIs = P.second;
2183 dbgs() << " " << printMBBReference(*P.first) << ": {";
2184 for (auto I : FIs) {
2185 dbgs() << " fi#" << I;
2186 if (LoxFIs.count(I))
2194 bool HasOptLimit = SpillOptMax.getPosition();
2197 // eliminate loads, when all loads eliminated, eliminate all stores.
2198 for (auto &B : MF) {
2199 auto F = BlockIndexes.find(&B);
2200 assert(F != BlockIndexes.end());
2201 HexagonBlockRanges::InstrIndexMap &IM = F->second;
2202 HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2203 HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2204 LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2205 << HexagonBlockRanges::PrintRangeMap(DM, HRI));
2207 for (auto FI : BlockFIMap[&B]) {
2208 if (BadFIs.count(FI))
2210 LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2211 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2212 for (auto &Range : RL) {
2213 LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2214 if (!IndexType::isInstr(Range.start()) ||
2215 !IndexType::isInstr(Range.end()))
2217 MachineInstr &SI = *IM.getInstr(Range.start());
2218 MachineInstr &EI = *IM.getInstr(Range.end());
2219 assert(SI.mayStore() && "Unexpected start instruction");
2220 assert(EI.mayLoad() && "Unexpected end instruction");
2221 MachineOperand &SrcOp = SI.getOperand(2);
2223 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2224 SrcOp.getSubReg() };
2225 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2226 // The this-> is needed to unconfuse MSVC.
2227 unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2228 LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2234 if (SpillOptCount >= SpillOptMax)
2240 // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2241 MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2242 MachineInstr *CopyIn = nullptr;
2243 if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2244 const DebugLoc &DL = SI.getDebugLoc();
2245 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2250 // Check if this is a last store and the FI is live-on-exit.
2251 if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2252 // Update store's source register.
2253 if (unsigned SR = SrcOp.getSubReg())
2254 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2256 SrcOp.setReg(FoundR);
2258 // We are keeping this register live.
2259 SrcOp.setIsKill(false);
2262 IM.replaceInstr(&SI, CopyIn);
2265 auto EndIt = std::next(EI.getIterator());
2266 for (auto It = StartIt; It != EndIt; It = NextIt) {
2267 MachineInstr &MI = *It;
2268 NextIt = std::next(It);
2270 if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2272 unsigned DstR = MI.getOperand(0).getReg();
2273 assert(MI.getOperand(0).getSubReg() == 0);
2274 MachineInstr *CopyOut = nullptr;
2275 if (DstR != FoundR) {
2276 DebugLoc DL = MI.getDebugLoc();
2277 unsigned MemSize = HII.getMemAccessSize(MI);
2278 assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2279 unsigned CopyOpc = TargetOpcode::COPY;
2280 if (HII.isSignExtendingLoad(MI))
2281 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2282 else if (HII.isZeroExtendingLoad(MI))
2283 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2284 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2285 .addReg(FoundR, getKillRegState(&MI == &EI));
2287 IM.replaceInstr(&MI, CopyOut);
2291 // Update the dead map.
2292 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2293 for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2294 DM[RR].subtract(Range);
2295 } // for Range in range list
2300 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2301 const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2302 MachineBasicBlock &MB = *AI->getParent();
2303 DebugLoc DL = AI->getDebugLoc();
2304 unsigned A = AI->getOperand(2).getImm();
2307 // Rd = alloca Rs, #A
2309 // If Rs and Rd are different registers, use this sequence:
2310 // Rd = sub(r29, Rs)
2311 // r29 = sub(r29, Rs)
2312 // Rd = and(Rd, #-A) ; if necessary
2313 // r29 = and(r29, #-A) ; if necessary
2314 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2316 // Rd = sub(r29, Rs)
2317 // Rd = and(Rd, #-A) ; if necessary
2319 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2321 MachineOperand &RdOp = AI->getOperand(0);
2322 MachineOperand &RsOp = AI->getOperand(1);
2323 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2325 // Rd = sub(r29, Rs)
2326 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2330 // r29 = sub(r29, Rs)
2331 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2336 // Rd = and(Rd, #-A)
2337 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2339 .addImm(-int64_t(A));
2341 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2343 .addImm(-int64_t(A));
2347 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2351 // Rd = add(Rd, #CF)
2352 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2358 bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
2359 const MachineFrameInfo &MFI = MF.getFrameInfo();
2360 if (!MFI.hasVarSizedObjects())
2362 unsigned MaxA = MFI.getMaxAlignment();
2363 if (MaxA <= getStackAlignment())
2368 const MachineInstr *HexagonFrameLowering::getAlignaInstr(
2369 const MachineFunction &MF) const {
2372 if (I.getOpcode() == Hexagon::PS_aligna)
2377 /// Adds all callee-saved registers as implicit uses or defs to the
2379 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2380 const CSIVect &CSI, bool IsDef, bool IsKill) const {
2381 // Add the callee-saved registers as implicit uses.
2383 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2386 /// Determine whether the callee-saved register saves and restores should
2387 /// be generated via inline code. If this function returns "true", inline
2388 /// code will be generated. If this function returns "false", additional
2389 /// checks are performed, which may still lead to the inline code.
2390 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2391 const CSIVect &CSI) const {
2392 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
2396 if (!isOptSize(MF) && !isMinSize(MF))
2397 if (MF.getTarget().getOptLevel() > CodeGenOpt::Default)
2400 // Check if CSI only has double registers, and if the registers form
2401 // a contiguous block starting from D8.
2402 BitVector Regs(Hexagon::NUM_TARGET_REGS);
2403 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2404 unsigned R = CSI[i].getReg();
2405 if (!Hexagon::DoubleRegsRegClass.contains(R))
2409 int F = Regs.find_first();
2410 if (F != Hexagon::D8)
2413 int N = Regs.find_next(F);
2414 if (N >= 0 && N != F+1)
2422 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2423 const CSIVect &CSI) const {
2424 if (shouldInlineCSR(MF, CSI))
2426 unsigned NumCSI = CSI.size();
2430 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2431 : SpillFuncThreshold;
2432 return Threshold < NumCSI;
2435 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2436 const CSIVect &CSI) const {
2437 if (shouldInlineCSR(MF, CSI))
2439 // The restore functions do a bit more than just restoring registers.
2440 // The non-returning versions will go back directly to the caller's
2441 // caller, others will clean up the stack frame in preparation for
2442 // a tail call. Using them can still save code size even if only one
2443 // register is getting restores. Make the decision based on -Oz:
2444 // using -Os will use inline restore for a single register.
2447 unsigned NumCSI = CSI.size();
2451 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2452 : SpillFuncThreshold;
2453 return Threshold < NumCSI;
2456 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2457 unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2458 auto &HST = MF.getSubtarget<HexagonSubtarget>();
2459 // A fairly simplistic guess as to whether a potential load/store to a
2460 // stack location could require an extra register.
2461 if (HST.useHVXOps() && StackSize > 256)
2464 // Check if the function has store-immediate instructions that access
2465 // the stack. Since the offset field is not extendable, if the stack
2466 // size exceeds the offset limit (6 bits, shifted), the stores will
2467 // require a new base register.
2468 bool HasImmStack = false;
2469 unsigned MinLS = ~0u; // Log_2 of the memory access size.
2471 for (const MachineBasicBlock &B : MF) {
2472 for (const MachineInstr &MI : B) {
2474 switch (MI.getOpcode()) {
2475 case Hexagon::S4_storeirit_io:
2476 case Hexagon::S4_storeirif_io:
2477 case Hexagon::S4_storeiri_io:
2480 case Hexagon::S4_storeirht_io:
2481 case Hexagon::S4_storeirhf_io:
2482 case Hexagon::S4_storeirh_io:
2485 case Hexagon::S4_storeirbt_io:
2486 case Hexagon::S4_storeirbf_io:
2487 case Hexagon::S4_storeirb_io:
2488 if (MI.getOperand(0).isFI())
2490 MinLS = std::min(MinLS, LS);
2497 return !isUInt<6>(StackSize >> MinLS);