1 //===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #define DEBUG_TYPE "hexagon-pei"
13 #include "HexagonBlockRanges.h"
14 #include "HexagonFrameLowering.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "MCTargetDesc/HexagonBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/None.h"
24 #include "llvm/ADT/Optional.h"
25 #include "llvm/ADT/PostOrderIterator.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/CodeGen/LivePhysRegs.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineDominators.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineModuleInfo.h"
39 #include "llvm/CodeGen/MachineOperand.h"
40 #include "llvm/CodeGen/MachinePostDominators.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/RegisterScavenging.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
66 // Hexagon stack frame layout as defined by the ABI:
72 // SP during function's FP during function's |
73 // +-- runtime (top of stack) runtime (bottom) --+ |
75 // --++---------------------+------------------+-----------------++-+-------
76 // | parameter area for | variable-size | fixed-size |LR| arg
77 // | called functions | local objects | local objects |FP|
78 // --+----------------------+------------------+-----------------+--+-------
79 // <- size known -> <- size unknown -> <- size known ->
81 // Low address High address
86 // - In any circumstances, the outgoing function arguments are always accessi-
87 // ble using the SP, and the incoming arguments are accessible using the FP.
88 // - If the local objects are not aligned, they can always be accessed using
90 // - If there are no variable-sized objects, the local objects can always be
91 // accessed using the SP, regardless whether they are aligned or not. (The
92 // alignment padding will be at the bottom of the stack (highest address),
93 // and so the offset with respect to the SP will be known at the compile-
96 // The only complication occurs if there are both, local aligned objects, and
97 // dynamically allocated (variable-sized) objects. The alignment pad will be
98 // placed between the FP and the local objects, thus preventing the use of the
99 // FP to access the local objects. At the same time, the variable-sized objects
100 // will be between the SP and the local objects, thus introducing an unknown
101 // distance from the SP to the locals.
103 // To avoid this problem, a new register is created that holds the aligned
104 // address of the bottom of the stack, referred in the sources as AP (aligned
105 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
106 // that aligns AP to the required boundary (a maximum of the alignments of
107 // all stack objects, fixed- and variable-sized). All local objects[1] will
108 // then use AP as the base pointer.
109 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
110 // their name from being allocated at fixed locations on the stack, relative
111 // to the FP. In the presence of dynamic allocation and local alignment, such
112 // objects can only be accessed through the FP.
114 // Illustration of the AP:
117 // ---------------+---------------------+-----+-----------------------++-+--
118 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
119 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
120 // ---------------+---------------------+-----+-----------------+-----+--+--
121 // |<-- Multiple of the -->|
122 // stack alignment +-- AP
124 // The AP is set up at the beginning of the function. Since it is not a dedi-
125 // cated (reserved) register, it needs to be kept live throughout the function
126 // to be available as the base register for local object accesses.
127 // Normally, an address of a stack objects is obtained by a pseudo-instruction
128 // PS_fi. To access local objects with the AP register present, a different
129 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
130 // argument compared to PS_fi: the first input register is the AP register.
131 // This keeps the register live between its definition and its uses.
133 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // A - required stack alignment
137 // The alignment value must be the maximum of all alignments required by
140 // The dynamic allocation uses a pseudo-instruction PS_alloca:
141 // Rd = PS_alloca Rs, A
143 // Rd - address of the allocated space
144 // Rs - minimum size (the actual allocated can be larger to accommodate
146 // A - required alignment
148 using namespace llvm;
150 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
151 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
153 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
154 cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
157 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
158 cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
159 cl::init(6), cl::ZeroOrMore);
161 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
162 cl::Hidden, cl::desc("Specify Os spill func threshold"),
163 cl::init(1), cl::ZeroOrMore);
165 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
166 cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
167 cl::init(false), cl::ZeroOrMore);
169 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
170 cl::init(true), cl::Hidden, cl::ZeroOrMore,
171 cl::desc("Enable stack frame shrink wrapping"));
173 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
174 cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, cl::ZeroOrMore,
175 cl::desc("Max count of stack frame shrink-wraps"));
177 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
178 cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
179 cl::init(false), cl::ZeroOrMore);
181 static cl::opt<bool> UseAllocframe("use-allocframe", cl::init(true),
182 cl::Hidden, cl::desc("Use allocframe more conservatively"));
184 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
185 cl::init(true), cl::desc("Optimize spill slots"));
188 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
189 cl::init(std::numeric_limits<unsigned>::max()));
190 static unsigned SpillOptCount = 0;
195 void initializeHexagonCallFrameInformationPass(PassRegistry&);
196 FunctionPass *createHexagonCallFrameInformation();
198 } // end namespace llvm
202 class HexagonCallFrameInformation : public MachineFunctionPass {
206 HexagonCallFrameInformation() : MachineFunctionPass(ID) {
207 PassRegistry &PR = *PassRegistry::getPassRegistry();
208 initializeHexagonCallFrameInformationPass(PR);
211 bool runOnMachineFunction(MachineFunction &MF) override;
213 MachineFunctionProperties getRequiredProperties() const override {
214 return MachineFunctionProperties().set(
215 MachineFunctionProperties::Property::NoVRegs);
219 char HexagonCallFrameInformation::ID = 0;
221 } // end anonymous namespace
223 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
224 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
225 bool NeedCFI = MF.getMMI().hasDebugInfo() ||
226 MF.getFunction()->needsUnwindTableEntry();
230 HFI.insertCFIInstructions(MF);
234 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
235 "Hexagon call frame information", false, false)
237 FunctionPass *llvm::createHexagonCallFrameInformation() {
238 return new HexagonCallFrameInformation();
241 /// Map a register pair Reg to the subregister that has the greater "number",
242 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
243 static unsigned getMax32BitSubRegister(unsigned Reg,
244 const TargetRegisterInfo &TRI,
246 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
250 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
252 if (*SubRegs > RegNo)
255 if (!RegNo || *SubRegs < RegNo)
262 /// Returns the callee saved register with the largest id in the vector.
263 static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
264 const TargetRegisterInfo &TRI) {
265 static_assert(Hexagon::R1 > 0,
266 "Assume physical registers are encoded as positive integers");
270 unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
271 for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
272 unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
279 /// Checks if the basic block contains any instruction that needs a stack
280 /// frame to be already in place.
281 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
282 const HexagonRegisterInfo &HRI) {
283 for (auto &I : MBB) {
284 const MachineInstr *MI = &I;
287 unsigned Opc = MI->getOpcode();
289 case Hexagon::PS_alloca:
290 case Hexagon::PS_aligna:
295 // Check individual operands.
296 for (const MachineOperand &MO : MI->operands()) {
297 // While the presence of a frame index does not prove that a stack
298 // frame will be required, all frame indexes should be within alloc-
299 // frame/deallocframe. Otherwise, the code that translates a frame
300 // index into an offset would have to be aware of the placement of
301 // the frame creation/destruction instructions.
306 unsigned R = MO.getReg();
307 // Virtual registers will need scavenging, which then may require
309 if (TargetRegisterInfo::isVirtualRegister(R))
311 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
319 /// Returns true if MBB has a machine instructions that indicates a tail call
321 static bool hasTailCall(const MachineBasicBlock &MBB) {
322 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
323 unsigned RetOpc = I->getOpcode();
324 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
327 /// Returns true if MBB contains an instruction that returns.
328 static bool hasReturn(const MachineBasicBlock &MBB) {
329 for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
335 /// Returns the "return" instruction from this block, or nullptr if there
337 static MachineInstr *getReturn(MachineBasicBlock &MBB) {
344 static bool isRestoreCall(unsigned Opc) {
346 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
347 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
348 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
349 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
350 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
351 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
352 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
353 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
359 static inline bool isOptNone(const MachineFunction &MF) {
360 return MF.getFunction()->hasFnAttribute(Attribute::OptimizeNone) ||
361 MF.getTarget().getOptLevel() == CodeGenOpt::None;
364 static inline bool isOptSize(const MachineFunction &MF) {
365 const Function &F = *MF.getFunction();
366 return F.optForSize() && !F.optForMinSize();
369 static inline bool isMinSize(const MachineFunction &MF) {
370 return MF.getFunction()->optForMinSize();
373 /// Implements shrink-wrapping of the stack frame. By default, stack frame
374 /// is created in the function entry block, and is cleaned up in every block
375 /// that returns. This function finds alternate blocks: one for the frame
376 /// setup (prolog) and one for the cleanup (epilog).
377 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
378 MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
379 static unsigned ShrinkCounter = 0;
381 if (ShrinkLimit.getPosition()) {
382 if (ShrinkCounter >= ShrinkLimit)
387 auto &HST = MF.getSubtarget<HexagonSubtarget>();
388 auto &HRI = *HST.getRegisterInfo();
390 MachineDominatorTree MDT;
391 MDT.runOnMachineFunction(MF);
392 MachinePostDominatorTree MPT;
393 MPT.runOnMachineFunction(MF);
395 typedef DenseMap<unsigned,unsigned> UnsignedMap;
397 typedef ReversePostOrderTraversal<const MachineFunction*> RPOTType;
400 for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
401 RPO[(*I)->getNumber()] = RPON++;
403 // Don't process functions that have loops, at least for now. Placement
404 // of prolog and epilog must take loop structure into account. For simpli-
405 // city don't do it right now.
407 unsigned BN = RPO[I.getNumber()];
408 for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
409 // If found a back-edge, return.
410 if (RPO[(*SI)->getNumber()] <= BN)
415 // Collect the set of blocks that need a stack frame to execute. Scan
416 // each block for uses/defs of callee-saved registers, calls, etc.
417 SmallVector<MachineBasicBlock*,16> SFBlocks;
418 BitVector CSR(Hexagon::NUM_TARGET_REGS);
419 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
420 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
424 if (needsStackFrame(I, CSR, HRI))
425 SFBlocks.push_back(&I);
428 dbgs() << "Blocks needing SF: {";
429 for (auto &B : SFBlocks)
430 dbgs() << " BB#" << B->getNumber();
434 if (SFBlocks.empty())
437 // Pick a common dominator and a common post-dominator.
438 MachineBasicBlock *DomB = SFBlocks[0];
439 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
440 DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
444 MachineBasicBlock *PDomB = SFBlocks[0];
445 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
446 PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
451 dbgs() << "Computed dom block: BB#";
452 if (DomB) dbgs() << DomB->getNumber();
453 else dbgs() << "<null>";
454 dbgs() << ", computed pdom block: BB#";
455 if (PDomB) dbgs() << PDomB->getNumber();
456 else dbgs() << "<null>";
462 // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
463 if (!MDT.dominates(DomB, PDomB)) {
464 DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
467 if (!MPT.dominates(PDomB, DomB)) {
468 DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
472 // Finally, everything seems right.
477 /// Perform most of the PEI work here:
478 /// - saving/restoring of the callee-saved registers,
479 /// - stack frame creation and destruction.
480 /// Normally, this work is distributed among various functions, but doing it
481 /// in one place allows shrink-wrapping of the stack frame.
482 void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
483 MachineBasicBlock &MBB) const {
484 auto &HST = MF.getSubtarget<HexagonSubtarget>();
485 auto &HRI = *HST.getRegisterInfo();
487 MachineFrameInfo &MFI = MF.getFrameInfo();
488 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
490 MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
491 if (EnableShrinkWrapping)
492 findShrunkPrologEpilog(MF, PrologB, EpilogB);
494 bool PrologueStubs = false;
495 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
496 insertPrologueInBlock(*PrologB, PrologueStubs);
497 updateEntryPaths(MF, *PrologB);
500 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
501 insertEpilogueInBlock(*EpilogB);
504 if (B.isReturnBlock())
505 insertCSRRestoresInBlock(B, CSI, HRI);
508 if (B.isReturnBlock())
509 insertEpilogueInBlock(B);
514 MachineInstr *RetI = getReturn(B);
515 if (!RetI || isRestoreCall(RetI->getOpcode()))
518 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
523 // If there is an epilog block, it may not have a return instruction.
524 // In such case, we need to add the callee-saved registers as live-ins
525 // in all blocks on all paths from the epilog to any return block.
526 unsigned MaxBN = MF.getNumBlockIDs();
527 BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
528 updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
532 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
533 bool PrologueStubs) const {
534 MachineFunction &MF = *MBB.getParent();
535 MachineFrameInfo &MFI = MF.getFrameInfo();
536 auto &HST = MF.getSubtarget<HexagonSubtarget>();
537 auto &HII = *HST.getInstrInfo();
538 auto &HRI = *HST.getRegisterInfo();
541 unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
543 // Calculate the total stack frame size.
544 // Get the number of bytes to allocate from the FrameInfo.
545 unsigned FrameSize = MFI.getStackSize();
546 // Round up the max call frame size to the max alignment on the stack.
547 unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
548 MFI.setMaxCallFrameSize(MaxCFA);
550 FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
551 MFI.setStackSize(FrameSize);
553 bool AlignStack = (MaxAlign > getStackAlignment());
555 // Get the number of bytes to allocate from the FrameInfo.
556 unsigned NumBytes = MFI.getStackSize();
557 unsigned SP = HRI.getStackRegister();
558 unsigned MaxCF = MFI.getMaxCallFrameSize();
559 MachineBasicBlock::iterator InsertPt = MBB.begin();
561 SmallVector<MachineInstr *, 4> AdjustRegs;
564 if (MI.getOpcode() == Hexagon::PS_alloca)
565 AdjustRegs.push_back(&MI);
567 for (auto MI : AdjustRegs) {
568 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
569 expandAlloca(MI, HII, SP, MaxCF);
570 MI->eraseFromParent();
576 // Check for overflow.
577 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
578 const unsigned int ALLOCFRAME_MAX = 16384;
580 // Create a dummy memory operand to avoid allocframe from being treated as
581 // a volatile memory reference.
582 MachineMemOperand *MMO =
583 MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore,
586 if (NumBytes >= ALLOCFRAME_MAX) {
587 // Emit allocframe(#0).
588 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
592 // Subtract offset from frame pointer.
593 // We use a caller-saved non-parameter register for that.
594 unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
595 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::CONST32),
596 CallerSavedReg).addImm(NumBytes);
597 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_sub), SP)
599 .addReg(CallerSavedReg);
601 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
607 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
609 .addImm(-int64_t(MaxAlign));
612 // If the stack-checking is enabled, and we spilled the callee-saved
613 // registers inline (i.e. did not use a spill function), then call
614 // the stack checker directly.
615 if (EnableStackOVFSanitizer && !PrologueStubs)
616 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
617 .addExternalSymbol("__runtime_stack_check");
620 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
621 MachineFunction &MF = *MBB.getParent();
625 auto &HST = MF.getSubtarget<HexagonSubtarget>();
626 auto &HII = *HST.getInstrInfo();
627 auto &HRI = *HST.getRegisterInfo();
628 unsigned SP = HRI.getStackRegister();
630 MachineInstr *RetI = getReturn(MBB);
631 unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
633 MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();
635 if (InsertPt != MBB.end())
636 DL = InsertPt->getDebugLoc();
637 else if (!MBB.empty())
638 DL = std::prev(MBB.end())->getDebugLoc();
641 if (RetOpc == Hexagon::EH_RETURN_JMPR) {
642 BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
643 BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::A2_add), SP)
645 .addReg(Hexagon::R28);
649 // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
650 // frame instruction if we encounter it.
651 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
652 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
653 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
654 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
655 MachineBasicBlock::iterator It = RetI;
657 // Delete all instructions after the RESTORE (except labels).
658 while (It != MBB.end()) {
667 // It is possible that the restoring code is a call to a library function.
668 // All of the restore* functions include "deallocframe", so we need to make
669 // sure that we don't add an extra one.
670 bool NeedsDeallocframe = true;
671 if (!MBB.empty() && InsertPt != MBB.begin()) {
672 MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
673 unsigned COpc = PrevIt->getOpcode();
674 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
675 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
676 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
677 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
678 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
679 NeedsDeallocframe = false;
682 if (!NeedsDeallocframe)
684 // If the returning instruction is PS_jmpret, replace it with dealloc_return,
685 // otherwise just add deallocframe. The function could be returning via a
687 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
688 BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
691 unsigned NewOpc = Hexagon::L4_return;
692 MachineInstr *NewI = BuildMI(MBB, RetI, DL, HII.get(NewOpc));
693 // Transfer the function live-out registers.
694 NewI->copyImplicitOps(MF, *RetI);
698 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
699 MachineBasicBlock &SaveB) const {
700 SetVector<unsigned> Worklist;
702 MachineBasicBlock &EntryB = MF.front();
703 Worklist.insert(EntryB.getNumber());
705 unsigned SaveN = SaveB.getNumber();
706 auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
708 for (unsigned i = 0; i < Worklist.size(); ++i) {
709 unsigned BN = Worklist[i];
710 MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);
712 if (!MBB.isLiveIn(R.getReg()))
713 MBB.addLiveIn(R.getReg());
715 for (auto &SB : MBB.successors())
716 Worklist.insert(SB->getNumber());
720 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
721 MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
722 BitVector &Path) const {
723 assert(MBB.getNumber() >= 0);
724 unsigned BN = MBB.getNumber();
725 if (Path[BN] || DoneF[BN])
730 auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
733 bool ReachedExit = false;
734 for (auto &SB : MBB.successors())
735 ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
737 if (!MBB.empty() && MBB.back().isReturn()) {
738 // Add implicit uses of all callee-saved registers to the reached
739 // return instructions. This is to prevent the anti-dependency breaker
740 // from renaming these registers.
741 MachineInstr &RetI = MBB.back();
742 if (!isRestoreCall(RetI.getOpcode()))
744 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
748 // We don't want to add unnecessary live-ins to the restore block: since
749 // the callee-saved registers are being defined in it, the entry of the
750 // restore block cannot be on the path from the definitions to any exit.
751 if (ReachedExit && &MBB != &RestoreB) {
753 if (!MBB.isLiveIn(R.getReg()))
754 MBB.addLiveIn(R.getReg());
764 static Optional<MachineBasicBlock::iterator>
765 findCFILocation(MachineBasicBlock &B) {
766 // The CFI instructions need to be inserted right after allocframe.
767 // An exception to this is a situation where allocframe is bundled
768 // with a call: then the CFI instructions need to be inserted before
769 // the packet with the allocframe+call (in case the call throws an
771 auto End = B.instr_end();
773 for (MachineInstr &I : B) {
774 MachineBasicBlock::iterator It = I.getIterator();
776 if (I.getOpcode() == Hexagon::S2_allocframe)
777 return std::next(It);
781 bool HasCall = false, HasAllocFrame = false;
782 auto T = It.getInstrIterator();
783 while (++T != End && T->isBundled()) {
784 if (T->getOpcode() == Hexagon::S2_allocframe)
785 HasAllocFrame = true;
786 else if (T->isCall())
790 return HasCall ? It : std::next(It);
795 void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {
797 auto At = findCFILocation(B);
799 insertCFIInstructionsAt(B, At.getValue());
803 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
804 MachineBasicBlock::iterator At) const {
805 MachineFunction &MF = *MBB.getParent();
806 MachineFrameInfo &MFI = MF.getFrameInfo();
807 MachineModuleInfo &MMI = MF.getMMI();
808 auto &HST = MF.getSubtarget<HexagonSubtarget>();
809 auto &HII = *HST.getInstrInfo();
810 auto &HRI = *HST.getRegisterInfo();
812 // If CFI instructions have debug information attached, something goes
813 // wrong with the final assembly generation: the prolog_end is placed
814 // in a wrong location.
816 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
818 MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
819 bool HasFP = hasFP(MF);
822 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
823 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
825 // Define CFA via an offset from the value of FP.
828 // --+----+----+---------------------
829 // | FP | LR | increasing addresses -->
830 // --+----+----+---------------------
831 // | +-- Old SP (before allocframe)
832 // +-- New FP (after allocframe)
834 // MCCFIInstruction::createDefCfa subtracts the offset from the register.
835 // MCCFIInstruction::createOffset takes the offset without sign change.
836 auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8);
837 BuildMI(MBB, At, DL, CFID)
838 .addCFIIndex(MF.addFrameInst(DefCfa));
839 // R31 (return addr) = CFA - 4
840 auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
841 BuildMI(MBB, At, DL, CFID)
842 .addCFIIndex(MF.addFrameInst(OffR31));
843 // R30 (frame ptr) = CFA - 8
844 auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
845 BuildMI(MBB, At, DL, CFID)
846 .addCFIIndex(MF.addFrameInst(OffR30));
849 static unsigned int RegsToMove[] = {
850 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
851 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
852 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
853 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
854 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
855 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
859 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
861 for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
862 unsigned Reg = RegsToMove[i];
863 auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
864 return C.getReg() == Reg;
866 auto F = find_if(CSI, IfR);
872 // If the function has a frame pointer (i.e. has an allocframe),
873 // then the CFA has been defined in terms of FP. Any offsets in
874 // the following CFI instructions have to be defined relative
875 // to FP, which points to the bottom of the stack frame.
876 // The function getFrameIndexReference can still choose to use SP
877 // for the offset calculation, so we cannot simply call it here.
878 // Instead, get the offset (relative to the FP) directly.
879 Offset = MFI.getObjectOffset(F->getFrameIdx());
882 Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg);
884 // Subtract 8 to make room for R30 and R31, which are added above.
887 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
888 unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
889 auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
891 BuildMI(MBB, At, DL, CFID)
892 .addCFIIndex(MF.addFrameInst(OffReg));
894 // Split the double regs into subregs, and generate appropriate
896 // The only reason, we are split double regs is, llvm-mc does not
897 // understand paired registers for cfi_offset.
898 // Eg .cfi_offset r1:0, -64
900 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
901 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
902 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
903 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
904 auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
906 BuildMI(MBB, At, DL, CFID)
907 .addCFIIndex(MF.addFrameInst(OffHi));
908 auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
910 BuildMI(MBB, At, DL, CFID)
911 .addCFIIndex(MF.addFrameInst(OffLo));
916 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
917 auto &MFI = MF.getFrameInfo();
918 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
920 bool HasFixed = MFI.getNumFixedObjects();
921 bool HasPrealloc = const_cast<MachineFrameInfo&>(MFI)
922 .getLocalFrameObjectCount();
923 bool HasExtraAlign = HRI.needsStackRealignment(MF);
924 bool HasAlloca = MFI.hasVarSizedObjects();
926 // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
927 // that this shouldn't be required, but doing so now because gcc does and
928 // gdb can't break at the start of the function without it. Will remove if
929 // this turns out to be a gdb bug.
931 if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
934 // By default we want to use SP (since it's always there). FP requires
935 // some setup (i.e. ALLOCFRAME).
936 // Fixed and preallocated objects need FP if the distance from them to
937 // the SP is unknown (as is with alloca or aligna).
938 if ((HasFixed || HasPrealloc) && (HasAlloca || HasExtraAlign))
941 if (MFI.getStackSize() > 0) {
942 if (EnableStackOVFSanitizer || UseAllocframe)
946 if (MFI.hasCalls() ||
947 MF.getInfo<HexagonMachineFunctionInfo>()->hasClobberLR())
959 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
960 bool Stkchk = false) {
961 const char * V4SpillToMemoryFunctions[] = {
962 "__save_r16_through_r17",
963 "__save_r16_through_r19",
964 "__save_r16_through_r21",
965 "__save_r16_through_r23",
966 "__save_r16_through_r25",
967 "__save_r16_through_r27" };
969 const char * V4SpillToMemoryStkchkFunctions[] = {
970 "__save_r16_through_r17_stkchk",
971 "__save_r16_through_r19_stkchk",
972 "__save_r16_through_r21_stkchk",
973 "__save_r16_through_r23_stkchk",
974 "__save_r16_through_r25_stkchk",
975 "__save_r16_through_r27_stkchk" };
977 const char * V4SpillFromMemoryFunctions[] = {
978 "__restore_r16_through_r17_and_deallocframe",
979 "__restore_r16_through_r19_and_deallocframe",
980 "__restore_r16_through_r21_and_deallocframe",
981 "__restore_r16_through_r23_and_deallocframe",
982 "__restore_r16_through_r25_and_deallocframe",
983 "__restore_r16_through_r27_and_deallocframe" };
985 const char * V4SpillFromMemoryTailcallFunctions[] = {
986 "__restore_r16_through_r17_and_deallocframe_before_tailcall",
987 "__restore_r16_through_r19_and_deallocframe_before_tailcall",
988 "__restore_r16_through_r21_and_deallocframe_before_tailcall",
989 "__restore_r16_through_r23_and_deallocframe_before_tailcall",
990 "__restore_r16_through_r25_and_deallocframe_before_tailcall",
991 "__restore_r16_through_r27_and_deallocframe_before_tailcall"
994 const char **SpillFunc = nullptr;
998 SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
999 : V4SpillToMemoryFunctions;
1002 SpillFunc = V4SpillFromMemoryFunctions;
1004 case SK_FromMemTailcall:
1005 SpillFunc = V4SpillFromMemoryTailcallFunctions;
1008 assert(SpillFunc && "Unknown spill kind");
1010 // Spill all callee-saved registers up to the highest register used.
1013 return SpillFunc[0];
1015 return SpillFunc[1];
1017 return SpillFunc[2];
1019 return SpillFunc[3];
1021 return SpillFunc[4];
1023 return SpillFunc[5];
1025 llvm_unreachable("Unhandled maximum callee save register");
1030 int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
1031 int FI, unsigned &FrameReg) const {
1032 auto &MFI = MF.getFrameInfo();
1033 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1035 int Offset = MFI.getObjectOffset(FI);
1036 bool HasAlloca = MFI.hasVarSizedObjects();
1037 bool HasExtraAlign = HRI.needsStackRealignment(MF);
1038 bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1040 unsigned SP = HRI.getStackRegister(), FP = HRI.getFrameRegister();
1041 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1042 unsigned AP = HMFI.getStackAlignBasePhysReg();
1043 unsigned FrameSize = MFI.getStackSize();
1045 bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1046 // Use FP at -O0, except when there are objects with extra alignment.
1047 // That additional alignment requirement may cause a pad to be inserted,
1048 // which will make it impossible to use FP to access objects located
1050 if (NoOpt && !HasExtraAlign)
1052 if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1053 // Fixed and preallocated objects will be located before any padding
1054 // so FP must be used to access them.
1055 UseFP |= (HasAlloca || HasExtraAlign);
1065 // If FP was picked, then there had better be FP.
1066 bool HasFP = hasFP(MF);
1067 assert((HasFP || !UseFP) && "This function must have frame pointer");
1069 // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1070 // FP/LR. If the base register is used to access an object across these
1071 // 8 bytes, then the offset will need to be adjusted by 8.
1073 // After allocframe:
1074 // HexagonISelLowering adds 8 to ---+
1075 // the offsets of all stack-based |
1078 // getObjectOffset < 0 0 8 getObjectOffset >= 8
1079 // ------------------------+-----+------------------------> increasing
1080 // <local objects> |FP/LR| <input arguments> addresses
1081 // -----------------+------+-----+------------------------>
1083 // SP/AP point --+ +-- FP points here (**)
1085 // this side of FP/LR
1087 // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1088 // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1090 // The lowering assumes that FP/LR is present, and so the offsets of
1091 // the formal arguments start at 8. If FP/LR is not there we need to
1092 // reduce the offset by 8.
1093 if (Offset > 0 && !HasFP)
1103 // Calculate the actual offset in the instruction. If there is no FP
1104 // (in other words, no allocframe), then SP will not be adjusted (i.e.
1105 // there will be no SP -= FrameSize), so the frame size should not be
1106 // added to the calculated offset.
1107 int RealOffset = Offset;
1108 if (!UseFP && !UseAP && HasFP)
1109 RealOffset = FrameSize+Offset;
1113 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1114 const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1115 bool &PrologueStubs) const {
1119 MachineBasicBlock::iterator MI = MBB.begin();
1120 PrologueStubs = false;
1121 MachineFunction &MF = *MBB.getParent();
1122 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1123 auto &HII = *HST.getInstrInfo();
1125 if (useSpillFunction(MF, CSI)) {
1126 PrologueStubs = true;
1127 unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1128 bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1129 const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1131 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1132 bool IsPIC = HTM.isPositionIndependent();
1133 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1135 // Call spill function.
1136 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1138 if (StkOvrFlowEnabled) {
1140 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1141 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1143 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1144 : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1147 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1148 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1150 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1151 : Hexagon::SAVE_REGISTERS_CALL_V4;
1154 MachineInstr *SaveRegsCall =
1155 BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1156 .addExternalSymbol(SpillFun);
1158 // Add callee-saved registers as use.
1159 addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1160 // Add live in registers.
1161 for (unsigned I = 0; I < CSI.size(); ++I)
1162 MBB.addLiveIn(CSI[I].getReg());
1166 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1167 unsigned Reg = CSI[i].getReg();
1168 // Add live in registers. We treat eh_return callee saved register r0 - r3
1169 // specially. They are not really callee saved registers as they are not
1170 // supposed to be killed.
1171 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1172 int FI = CSI[i].getFrameIdx();
1173 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1174 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1181 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1182 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1186 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1187 MachineFunction &MF = *MBB.getParent();
1188 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1189 auto &HII = *HST.getInstrInfo();
1191 if (useRestoreFunction(MF, CSI)) {
1192 bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1193 unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1194 SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;
1195 const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1196 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1197 bool IsPIC = HTM.isPositionIndependent();
1198 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1200 // Call spill function.
1201 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1202 : MBB.getLastNonDebugInstr()->getDebugLoc();
1203 MachineInstr *DeallocCall = nullptr;
1208 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1209 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1211 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1212 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1213 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1214 .addExternalSymbol(RestoreFn);
1216 // The block has a return.
1217 MachineBasicBlock::iterator It = MBB.getFirstTerminator();
1218 assert(It->isReturn() && std::next(It) == MBB.end());
1221 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1222 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1224 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1225 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1226 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1227 .addExternalSymbol(RestoreFn);
1228 // Transfer the function live-out registers.
1229 DeallocCall->copyImplicitOps(MF, *It);
1231 addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1235 for (unsigned i = 0; i < CSI.size(); ++i) {
1236 unsigned Reg = CSI[i].getReg();
1237 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1238 int FI = CSI[i].getFrameIdx();
1239 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1245 MachineBasicBlock::iterator HexagonFrameLowering::eliminateCallFramePseudoInstr(
1246 MachineFunction &MF, MachineBasicBlock &MBB,
1247 MachineBasicBlock::iterator I) const {
1248 MachineInstr &MI = *I;
1249 unsigned Opc = MI.getOpcode();
1250 (void)Opc; // Silence compiler warning.
1251 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1252 "Cannot handle this call frame pseudo instruction");
1253 return MBB.erase(I);
1256 void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
1257 MachineFunction &MF, RegScavenger *RS) const {
1258 // If this function has uses aligned stack and also has variable sized stack
1259 // objects, then we need to map all spill slots to fixed positions, so that
1260 // they can be accessed through FP. Otherwise they would have to be accessed
1261 // via AP, which may not be available at the particular place in the program.
1262 MachineFrameInfo &MFI = MF.getFrameInfo();
1263 bool HasAlloca = MFI.hasVarSizedObjects();
1264 bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
1266 if (!HasAlloca || !NeedsAlign)
1269 unsigned LFS = MFI.getLocalFrameSize();
1270 for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1271 if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1273 unsigned S = MFI.getObjectSize(i);
1274 // Reduce the alignment to at most 8. This will require unaligned vector
1275 // stores if they happen here.
1276 unsigned A = std::max(MFI.getObjectAlignment(i), 8U);
1277 MFI.setObjectAlignment(i, 8);
1278 LFS = alignTo(LFS+S, A);
1279 MFI.mapLocalFrameObject(i, -LFS);
1282 MFI.setLocalFrameSize(LFS);
1283 unsigned A = MFI.getLocalFrameMaxAlign();
1284 assert(A <= 8 && "Unexpected local frame alignment");
1286 MFI.setLocalFrameMaxAlign(8);
1287 MFI.setUseLocalStackAllocationBlock(true);
1289 // Set the physical aligned-stack base address register.
1291 if (const MachineInstr *AI = getAlignaInstr(MF))
1292 AP = AI->getOperand(0).getReg();
1293 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1294 HMFI.setStackAlignBasePhysReg(AP);
1297 /// Returns true if there are no caller-saved registers available in class RC.
1298 static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
1299 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1300 MachineRegisterInfo &MRI = MF.getRegInfo();
1302 auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1303 for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1304 if (MRI.isPhysRegUsed(*AI))
1309 // Check for an unused caller-saved register. Callee-saved registers
1310 // have become pristine by now.
1311 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1315 // All caller-saved registers are used.
1320 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1322 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1324 dbgs() << ' ' << PrintReg(R, &TRI);
1330 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
1331 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1332 DEBUG(dbgs() << __func__ << " on "
1333 << MF.getFunction()->getName() << '\n');
1334 MachineFrameInfo &MFI = MF.getFrameInfo();
1335 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1337 // Generate a set of unique, callee-saved registers (SRegs), where each
1338 // register in the set is maximal in terms of sub-/super-register relation,
1339 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1341 // (1) For each callee-saved register, add that register and all of its
1342 // sub-registers to SRegs.
1343 DEBUG(dbgs() << "Initial CS registers: {");
1344 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1345 unsigned R = CSI[i].getReg();
1346 DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
1347 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1350 DEBUG(dbgs() << " }\n");
1351 DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1353 // (2) For each reserved register, remove that register and all of its
1354 // sub- and super-registers from SRegs.
1355 BitVector Reserved = TRI->getReservedRegs(MF);
1356 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1358 for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1361 DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); dbgs() << "\n");
1362 DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1364 // (3) Collect all registers that have at least one sub-register in SRegs,
1365 // and also have no sub-registers that are reserved. These will be the can-
1366 // didates for saving as a whole instead of their individual sub-registers.
1367 // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1368 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1369 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1371 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1374 for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1376 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1383 DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); dbgs() << "\n");
1385 // (4) Include all super-registers found in (3) into SRegs.
1387 DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1389 // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1390 // remove R from SRegs.
1391 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1393 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1400 DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1402 // Now, for each register that has a fixed stack slot, create the stack
1406 typedef TargetFrameLowering::SpillSlot SpillSlot;
1408 int MinOffset = 0; // CS offsets are negative.
1409 const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1410 for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1413 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1414 int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), S->Offset);
1415 MinOffset = std::min(MinOffset, S->Offset);
1416 CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1417 SRegs[S->Reg] = false;
1420 // There can be some registers that don't have fixed slots. For example,
1421 // we need to store R0-R3 in functions with exception handling. For each
1422 // such register, create a non-fixed stack object.
1423 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1425 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1426 int Off = MinOffset - RC->getSize();
1427 unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
1428 assert(isPowerOf2_32(Align));
1430 int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), Off);
1431 MinOffset = std::min(MinOffset, Off);
1432 CSI.push_back(CalleeSavedInfo(R, FI));
1437 dbgs() << "CS information: {";
1438 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1439 int FI = CSI[i].getFrameIdx();
1440 int Off = MFI.getObjectOffset(FI);
1441 dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1450 // Verify that all registers were handled.
1451 bool MissedReg = false;
1452 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1454 dbgs() << PrintReg(R, TRI) << ' ';
1458 llvm_unreachable("...there are unhandled callee-saved registers!");
1464 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1465 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1466 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1467 MachineInstr *MI = &*It;
1468 DebugLoc DL = MI->getDebugLoc();
1469 unsigned DstR = MI->getOperand(0).getReg();
1470 unsigned SrcR = MI->getOperand(1).getReg();
1471 if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1472 !Hexagon::ModRegsRegClass.contains(SrcR))
1475 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1476 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR)
1477 .addOperand(MI->getOperand(1));
1478 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1479 .addReg(TmpR, RegState::Kill);
1481 NewRegs.push_back(TmpR);
1486 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1487 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1488 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1489 MachineInstr *MI = &*It;
1490 if (!MI->getOperand(0).isFI())
1493 DebugLoc DL = MI->getDebugLoc();
1494 unsigned Opc = MI->getOpcode();
1495 unsigned SrcR = MI->getOperand(2).getReg();
1496 bool IsKill = MI->getOperand(2).isKill();
1497 int FI = MI->getOperand(0).getIndex();
1499 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1500 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1501 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1502 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1503 : Hexagon::A2_tfrcrr;
1504 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1505 .addReg(SrcR, getKillRegState(IsKill));
1507 // S2_storeri_io FI, 0, TmpR
1508 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1511 .addReg(TmpR, RegState::Kill)
1512 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1514 NewRegs.push_back(TmpR);
1519 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1520 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1521 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1522 MachineInstr *MI = &*It;
1523 if (!MI->getOperand(1).isFI())
1526 DebugLoc DL = MI->getDebugLoc();
1527 unsigned Opc = MI->getOpcode();
1528 unsigned DstR = MI->getOperand(0).getReg();
1529 int FI = MI->getOperand(1).getIndex();
1531 // TmpR = L2_loadri_io FI, 0
1532 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1533 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1536 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1538 // DstR = C2_tfrrp TmpR if DstR is a predicate register
1539 // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1540 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1541 : Hexagon::A2_tfrrcr;
1542 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1543 .addReg(TmpR, RegState::Kill);
1545 NewRegs.push_back(TmpR);
1550 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1551 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1552 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1553 auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>();
1554 MachineInstr *MI = &*It;
1555 if (!MI->getOperand(0).isFI())
1558 DebugLoc DL = MI->getDebugLoc();
1559 unsigned SrcR = MI->getOperand(2).getReg();
1560 bool IsKill = MI->getOperand(2).isKill();
1561 int FI = MI->getOperand(0).getIndex();
1563 bool Is128B = HST.useHVXDblOps();
1564 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1565 : &Hexagon::VectorRegs128BRegClass;
1567 // Insert transfer to general vector register.
1568 // TmpR0 = A2_tfrsi 0x01010101
1569 // TmpR1 = V6_vandqrt Qx, TmpR0
1570 // store FI, 0, TmpR1
1571 unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1572 unsigned TmpR1 = MRI.createVirtualRegister(RC);
1574 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1575 .addImm(0x01010101);
1577 unsigned VandOpc = !Is128B ? Hexagon::V6_vandqrt : Hexagon::V6_vandqrt_128B;
1578 BuildMI(B, It, DL, HII.get(VandOpc), TmpR1)
1579 .addReg(SrcR, getKillRegState(IsKill))
1580 .addReg(TmpR0, RegState::Kill);
1582 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1583 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1584 expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1586 NewRegs.push_back(TmpR0);
1587 NewRegs.push_back(TmpR1);
1592 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1593 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1594 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1595 auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>();
1596 MachineInstr *MI = &*It;
1597 if (!MI->getOperand(1).isFI())
1600 DebugLoc DL = MI->getDebugLoc();
1601 unsigned DstR = MI->getOperand(0).getReg();
1602 int FI = MI->getOperand(1).getIndex();
1604 bool Is128B = HST.useHVXDblOps();
1605 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1606 : &Hexagon::VectorRegs128BRegClass;
1608 // TmpR0 = A2_tfrsi 0x01010101
1609 // TmpR1 = load FI, 0
1610 // DstR = V6_vandvrt TmpR1, TmpR0
1611 unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1612 unsigned TmpR1 = MRI.createVirtualRegister(RC);
1614 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1615 .addImm(0x01010101);
1616 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1617 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1618 expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1620 unsigned VandOpc = !Is128B ? Hexagon::V6_vandvrt : Hexagon::V6_vandvrt_128B;
1621 BuildMI(B, It, DL, HII.get(VandOpc), DstR)
1622 .addReg(TmpR1, RegState::Kill)
1623 .addReg(TmpR0, RegState::Kill);
1625 NewRegs.push_back(TmpR0);
1626 NewRegs.push_back(TmpR1);
1631 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1632 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1633 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1634 MachineFunction &MF = *B.getParent();
1635 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1636 auto &MFI = MF.getFrameInfo();
1637 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1638 MachineInstr *MI = &*It;
1639 if (!MI->getOperand(0).isFI())
1642 // It is possible that the double vector being stored is only partially
1643 // defined. From the point of view of the liveness tracking, it is ok to
1644 // store it as a whole, but if we break it up we may end up storing a
1645 // register that is entirely undefined.
1646 LivePhysRegs LPR(&HRI);
1648 SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers;
1649 for (auto R = B.begin(); R != It; ++R)
1650 LPR.stepForward(*R, Clobbers);
1652 DebugLoc DL = MI->getDebugLoc();
1653 unsigned SrcR = MI->getOperand(2).getReg();
1654 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1655 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1656 bool IsKill = MI->getOperand(2).isKill();
1657 int FI = MI->getOperand(0).getIndex();
1659 bool Is128B = HST.useHVXDblOps();
1660 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1661 : &Hexagon::VectorRegs128BRegClass;
1662 unsigned Size = RC->getSize();
1663 unsigned NeedAlign = RC->getAlignment();
1664 unsigned HasAlign = MFI.getObjectAlignment(FI);
1668 if (LPR.contains(SrcLo)) {
1669 if (NeedAlign <= HasAlign)
1670 StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
1672 StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
1674 BuildMI(B, It, DL, HII.get(StoreOpc))
1677 .addReg(SrcLo, getKillRegState(IsKill))
1678 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1682 if (LPR.contains(SrcHi)) {
1683 if (NeedAlign <= MinAlign(HasAlign, Size))
1684 StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
1686 StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
1688 BuildMI(B, It, DL, HII.get(StoreOpc))
1691 .addReg(SrcHi, getKillRegState(IsKill))
1692 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1699 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1700 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1701 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1702 MachineFunction &MF = *B.getParent();
1703 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1704 auto &MFI = MF.getFrameInfo();
1705 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1706 MachineInstr *MI = &*It;
1707 if (!MI->getOperand(1).isFI())
1710 DebugLoc DL = MI->getDebugLoc();
1711 unsigned DstR = MI->getOperand(0).getReg();
1712 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1713 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1714 int FI = MI->getOperand(1).getIndex();
1716 bool Is128B = HST.useHVXDblOps();
1717 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1718 : &Hexagon::VectorRegs128BRegClass;
1719 unsigned Size = RC->getSize();
1720 unsigned NeedAlign = RC->getAlignment();
1721 unsigned HasAlign = MFI.getObjectAlignment(FI);
1725 if (NeedAlign <= HasAlign)
1726 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;
1728 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
1730 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1733 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1736 if (NeedAlign <= MinAlign(HasAlign, Size))
1737 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;
1739 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
1741 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1744 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1750 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1751 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1752 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1753 MachineFunction &MF = *B.getParent();
1754 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1755 auto &MFI = MF.getFrameInfo();
1756 MachineInstr *MI = &*It;
1757 if (!MI->getOperand(0).isFI())
1760 DebugLoc DL = MI->getDebugLoc();
1761 unsigned SrcR = MI->getOperand(2).getReg();
1762 bool IsKill = MI->getOperand(2).isKill();
1763 int FI = MI->getOperand(0).getIndex();
1765 bool Is128B = HST.useHVXDblOps();
1766 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1767 : &Hexagon::VectorRegs128BRegClass;
1769 unsigned NeedAlign = RC->getAlignment();
1770 unsigned HasAlign = MFI.getObjectAlignment(FI);
1773 if (NeedAlign <= HasAlign)
1774 StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
1776 StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
1778 BuildMI(B, It, DL, HII.get(StoreOpc))
1781 .addReg(SrcR, getKillRegState(IsKill))
1782 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1788 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
1789 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1790 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1791 MachineFunction &MF = *B.getParent();
1792 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1793 auto &MFI = MF.getFrameInfo();
1794 MachineInstr *MI = &*It;
1795 if (!MI->getOperand(1).isFI())
1798 DebugLoc DL = MI->getDebugLoc();
1799 unsigned DstR = MI->getOperand(0).getReg();
1800 int FI = MI->getOperand(1).getIndex();
1802 bool Is128B = HST.useHVXDblOps();
1803 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1804 : &Hexagon::VectorRegs128BRegClass;
1806 unsigned NeedAlign = RC->getAlignment();
1807 unsigned HasAlign = MFI.getObjectAlignment(FI);
1810 if (NeedAlign <= HasAlign)
1811 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;
1813 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
1815 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
1818 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1824 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
1825 SmallVectorImpl<unsigned> &NewRegs) const {
1826 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1827 auto &HII = *HST.getInstrInfo();
1828 MachineRegisterInfo &MRI = MF.getRegInfo();
1829 bool Changed = false;
1831 for (auto &B : MF) {
1832 // Traverse the basic block.
1833 MachineBasicBlock::iterator NextI;
1834 for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
1835 MachineInstr *MI = &*I;
1836 NextI = std::next(I);
1837 unsigned Opc = MI->getOpcode();
1840 case TargetOpcode::COPY:
1841 Changed |= expandCopy(B, I, MRI, HII, NewRegs);
1843 case Hexagon::STriw_pred:
1844 case Hexagon::STriw_mod:
1845 Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
1847 case Hexagon::LDriw_pred:
1848 case Hexagon::LDriw_mod:
1849 Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
1851 case Hexagon::PS_vstorerq_ai:
1852 case Hexagon::PS_vstorerq_ai_128B:
1853 Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
1855 case Hexagon::PS_vloadrq_ai:
1856 case Hexagon::PS_vloadrq_ai_128B:
1857 Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
1859 case Hexagon::PS_vloadrw_ai:
1860 case Hexagon::PS_vloadrwu_ai:
1861 case Hexagon::PS_vloadrw_ai_128B:
1862 case Hexagon::PS_vloadrwu_ai_128B:
1863 Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
1865 case Hexagon::PS_vstorerw_ai:
1866 case Hexagon::PS_vstorerwu_ai:
1867 case Hexagon::PS_vstorerw_ai_128B:
1868 case Hexagon::PS_vstorerwu_ai_128B:
1869 Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
1878 void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
1879 BitVector &SavedRegs,
1880 RegScavenger *RS) const {
1881 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1882 auto &HRI = *HST.getRegisterInfo();
1884 SavedRegs.resize(HRI.getNumRegs());
1886 // If we have a function containing __builtin_eh_return we want to spill and
1887 // restore all callee saved registers. Pretend that they are used.
1888 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
1889 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
1892 // Replace predicate register pseudo spill code.
1893 SmallVector<unsigned,8> NewRegs;
1894 expandSpillMacros(MF, NewRegs);
1895 if (OptimizeSpillSlots && !isOptNone(MF))
1896 optimizeSpillSlots(MF, NewRegs);
1898 // We need to reserve a a spill slot if scavenging could potentially require
1899 // spilling a scavenged register.
1900 if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
1901 MachineFrameInfo &MFI = MF.getFrameInfo();
1902 MachineRegisterInfo &MRI = MF.getRegInfo();
1903 SetVector<const TargetRegisterClass*> SpillRCs;
1904 // Reserve an int register in any case, because it could be used to hold
1905 // the stack offset in case it does not fit into a spill instruction.
1906 SpillRCs.insert(&Hexagon::IntRegsRegClass);
1908 for (unsigned VR : NewRegs)
1909 SpillRCs.insert(MRI.getRegClass(VR));
1911 for (auto *RC : SpillRCs) {
1912 if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
1914 unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1915 unsigned S = RC->getSize(), A = RC->getAlignment();
1916 for (unsigned i = 0; i < Num; i++) {
1917 int NewFI = MFI.CreateSpillStackObject(S, A);
1918 RS->addScavengingFrameIndex(NewFI);
1923 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1926 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
1927 HexagonBlockRanges::IndexRange &FIR,
1928 HexagonBlockRanges::InstrIndexMap &IndexMap,
1929 HexagonBlockRanges::RegToRangeMap &DeadMap,
1930 const TargetRegisterClass *RC) const {
1931 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1932 auto &MRI = MF.getRegInfo();
1934 auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
1935 auto F = DeadMap.find({Reg,0});
1936 if (F == DeadMap.end())
1938 for (auto &DR : F->second)
1939 if (DR.contains(FIR))
1944 for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
1946 for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
1958 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
1959 SmallVectorImpl<unsigned> &VRegs) const {
1960 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1961 auto &HII = *HST.getInstrInfo();
1962 auto &HRI = *HST.getRegisterInfo();
1963 auto &MRI = MF.getRegInfo();
1964 HexagonBlockRanges HBR(MF);
1966 typedef std::map<MachineBasicBlock*,HexagonBlockRanges::InstrIndexMap>
1968 typedef std::map<MachineBasicBlock*,HexagonBlockRanges::RangeList>
1970 typedef HexagonBlockRanges::IndexType IndexType;
1975 const TargetRegisterClass *RC = nullptr;
1977 SlotInfo() = default;
1980 BlockIndexMap BlockIndexes;
1981 SmallSet<int,4> BadFIs;
1982 std::map<int,SlotInfo> FIRangeMap;
1984 // Accumulate register classes: get a common class for a pre-existing
1985 // class HaveRC and a new class NewRC. Return nullptr if a common class
1986 // cannot be found, otherwise return the resulting class. If HaveRC is
1987 // nullptr, assume that it is still unset.
1988 auto getCommonRC = [&HRI] (const TargetRegisterClass *HaveRC,
1989 const TargetRegisterClass *NewRC)
1990 -> const TargetRegisterClass* {
1991 if (HaveRC == nullptr || HaveRC == NewRC)
1993 // Different classes, both non-null. Pick the more general one.
1994 if (HaveRC->hasSubClassEq(NewRC))
1996 if (NewRC->hasSubClassEq(HaveRC))
2001 // Scan all blocks in the function. Check all occurrences of frame indexes,
2002 // and collect relevant information.
2003 for (auto &B : MF) {
2004 std::map<int,IndexType> LastStore, LastLoad;
2005 // Emplace appears not to be supported in gcc 4.7.2-4.
2006 //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2007 auto P = BlockIndexes.insert(
2008 std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2009 auto &IndexMap = P.first->second;
2010 DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n"
2011 << IndexMap << '\n');
2013 for (auto &In : B) {
2015 bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2016 bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2017 if (Load && Store) {
2018 // If it's both a load and a store, then we won't handle it.
2023 // Check for register classes of the register used as the source for
2024 // the store, and the register used as the destination for the load.
2025 // Also, only accept base+imm_offset addressing modes. Other addressing
2026 // modes can have side-effects (post-increments, etc.). For stack
2027 // slots they are very unlikely, so there is not much loss due to
2028 // this restriction.
2029 if (Load || Store) {
2030 int TFI = Load ? LFI : SFI;
2031 unsigned AM = HII.getAddrMode(In);
2032 SlotInfo &SI = FIRangeMap[TFI];
2033 bool Bad = (AM != HexagonII::BaseImmOffset);
2035 // If the addressing mode is ok, check the register class.
2036 unsigned OpNum = Load ? 0 : 2;
2037 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2038 RC = getCommonRC(SI.RC, RC);
2046 unsigned S = (1U << (HII.getMemAccessSize(In) - 1));
2047 if (SI.Size != 0 && SI.Size != S)
2053 for (auto *Mo : In.memoperands()) {
2054 if (!Mo->isVolatile())
2064 // Locate uses of frame indices.
2065 for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2066 const MachineOperand &Op = In.getOperand(i);
2069 int FI = Op.getIndex();
2070 // Make sure that the following operand is an immediate and that
2071 // it is 0. This is the offset in the stack object.
2072 if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2073 In.getOperand(i+1).getImm() != 0)
2075 if (BadFIs.count(FI))
2078 IndexType Index = IndexMap.getIndex(&In);
2080 if (LastStore[FI] == IndexType::None)
2081 LastStore[FI] = IndexType::Entry;
2082 LastLoad[FI] = Index;
2084 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2085 if (LastStore[FI] != IndexType::None)
2086 RL.add(LastStore[FI], LastLoad[FI], false, false);
2087 else if (LastLoad[FI] != IndexType::None)
2088 RL.add(IndexType::Entry, LastLoad[FI], false, false);
2089 LastLoad[FI] = IndexType::None;
2090 LastStore[FI] = Index;
2097 for (auto &I : LastLoad) {
2098 IndexType LL = I.second;
2099 if (LL == IndexType::None)
2101 auto &RL = FIRangeMap[I.first].Map[&B];
2102 IndexType &LS = LastStore[I.first];
2103 if (LS != IndexType::None)
2104 RL.add(LS, LL, false, false);
2106 RL.add(IndexType::Entry, LL, false, false);
2107 LS = IndexType::None;
2109 for (auto &I : LastStore) {
2110 IndexType LS = I.second;
2111 if (LS == IndexType::None)
2113 auto &RL = FIRangeMap[I.first].Map[&B];
2114 RL.add(LS, IndexType::None, false, false);
2119 for (auto &P : FIRangeMap) {
2120 dbgs() << "fi#" << P.first;
2121 if (BadFIs.count(P.first))
2124 if (P.second.RC != nullptr)
2125 dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2127 dbgs() << "<null>\n";
2128 for (auto &R : P.second.Map)
2129 dbgs() << " BB#" << R.first->getNumber() << " { " << R.second << "}\n";
2133 // When a slot is loaded from in a block without being stored to in the
2134 // same block, it is live-on-entry to this block. To avoid CFG analysis,
2135 // consider this slot to be live-on-exit from all blocks.
2136 SmallSet<int,4> LoxFIs;
2138 std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2140 for (auto &P : FIRangeMap) {
2141 // P = pair(FI, map: BB->RangeList)
2142 if (BadFIs.count(P.first))
2144 for (auto &B : MF) {
2145 auto F = P.second.Map.find(&B);
2146 // F = pair(BB, RangeList)
2147 if (F == P.second.Map.end() || F->second.empty())
2149 HexagonBlockRanges::IndexRange &IR = F->second.front();
2150 if (IR.start() == IndexType::Entry)
2151 LoxFIs.insert(P.first);
2152 BlockFIMap[&B].push_back(P.first);
2157 dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2158 for (auto &P : BlockFIMap) {
2159 auto &FIs = P.second;
2162 dbgs() << " BB#" << P.first->getNumber() << ": {";
2163 for (auto I : FIs) {
2164 dbgs() << " fi#" << I;
2165 if (LoxFIs.count(I))
2173 bool HasOptLimit = SpillOptMax.getPosition();
2176 // eliminate loads, when all loads eliminated, eliminate all stores.
2177 for (auto &B : MF) {
2178 auto F = BlockIndexes.find(&B);
2179 assert(F != BlockIndexes.end());
2180 HexagonBlockRanges::InstrIndexMap &IM = F->second;
2181 HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2182 HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2183 DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n"
2184 << HexagonBlockRanges::PrintRangeMap(DM, HRI));
2186 for (auto FI : BlockFIMap[&B]) {
2187 if (BadFIs.count(FI))
2189 DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2190 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2191 for (auto &Range : RL) {
2192 DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2193 if (!IndexType::isInstr(Range.start()) ||
2194 !IndexType::isInstr(Range.end()))
2196 MachineInstr &SI = *IM.getInstr(Range.start());
2197 MachineInstr &EI = *IM.getInstr(Range.end());
2198 assert(SI.mayStore() && "Unexpected start instruction");
2199 assert(EI.mayLoad() && "Unexpected end instruction");
2200 MachineOperand &SrcOp = SI.getOperand(2);
2202 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2203 SrcOp.getSubReg() };
2204 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2205 // The this-> is needed to unconfuse MSVC.
2206 unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2207 DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
2212 if (SpillOptCount >= SpillOptMax)
2218 // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2219 MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2220 MachineInstr *CopyIn = nullptr;
2221 if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2222 const DebugLoc &DL = SI.getDebugLoc();
2223 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2228 // Check if this is a last store and the FI is live-on-exit.
2229 if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2230 // Update store's source register.
2231 if (unsigned SR = SrcOp.getSubReg())
2232 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2234 SrcOp.setReg(FoundR);
2236 // We are keeping this register live.
2237 SrcOp.setIsKill(false);
2240 IM.replaceInstr(&SI, CopyIn);
2243 auto EndIt = std::next(EI.getIterator());
2244 for (auto It = StartIt; It != EndIt; It = NextIt) {
2245 MachineInstr &MI = *It;
2246 NextIt = std::next(It);
2248 if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2250 unsigned DstR = MI.getOperand(0).getReg();
2251 assert(MI.getOperand(0).getSubReg() == 0);
2252 MachineInstr *CopyOut = nullptr;
2253 if (DstR != FoundR) {
2254 DebugLoc DL = MI.getDebugLoc();
2255 unsigned MemSize = (1U << (HII.getMemAccessSize(MI) - 1));
2256 assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2257 unsigned CopyOpc = TargetOpcode::COPY;
2258 if (HII.isSignExtendingLoad(MI))
2259 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2260 else if (HII.isZeroExtendingLoad(MI))
2261 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2262 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2263 .addReg(FoundR, getKillRegState(&MI == &EI));
2265 IM.replaceInstr(&MI, CopyOut);
2269 // Update the dead map.
2270 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2271 for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2272 DM[RR].subtract(Range);
2273 } // for Range in range list
2278 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2279 const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2280 MachineBasicBlock &MB = *AI->getParent();
2281 DebugLoc DL = AI->getDebugLoc();
2282 unsigned A = AI->getOperand(2).getImm();
2285 // Rd = alloca Rs, #A
2287 // If Rs and Rd are different registers, use this sequence:
2288 // Rd = sub(r29, Rs)
2289 // r29 = sub(r29, Rs)
2290 // Rd = and(Rd, #-A) ; if necessary
2291 // r29 = and(r29, #-A) ; if necessary
2292 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2294 // Rd = sub(r29, Rs)
2295 // Rd = and(Rd, #-A) ; if necessary
2297 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2299 MachineOperand &RdOp = AI->getOperand(0);
2300 MachineOperand &RsOp = AI->getOperand(1);
2301 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2303 // Rd = sub(r29, Rs)
2304 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2308 // r29 = sub(r29, Rs)
2309 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2314 // Rd = and(Rd, #-A)
2315 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2317 .addImm(-int64_t(A));
2319 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2321 .addImm(-int64_t(A));
2325 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2329 // Rd = add(Rd, #CF)
2330 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2336 bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
2337 const MachineFrameInfo &MFI = MF.getFrameInfo();
2338 if (!MFI.hasVarSizedObjects())
2340 unsigned MaxA = MFI.getMaxAlignment();
2341 if (MaxA <= getStackAlignment())
2346 const MachineInstr *HexagonFrameLowering::getAlignaInstr(
2347 const MachineFunction &MF) const {
2350 if (I.getOpcode() == Hexagon::PS_aligna)
2355 /// Adds all callee-saved registers as implicit uses or defs to the
2357 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2358 const CSIVect &CSI, bool IsDef, bool IsKill) const {
2359 // Add the callee-saved registers as implicit uses.
2361 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2364 /// Determine whether the callee-saved register saves and restores should
2365 /// be generated via inline code. If this function returns "true", inline
2366 /// code will be generated. If this function returns "false", additional
2367 /// checks are performed, which may still lead to the inline code.
2368 bool HexagonFrameLowering::shouldInlineCSR(MachineFunction &MF,
2369 const CSIVect &CSI) const {
2370 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
2372 if (!isOptSize(MF) && !isMinSize(MF))
2373 if (MF.getTarget().getOptLevel() > CodeGenOpt::Default)
2376 // Check if CSI only has double registers, and if the registers form
2377 // a contiguous block starting from D8.
2378 BitVector Regs(Hexagon::NUM_TARGET_REGS);
2379 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2380 unsigned R = CSI[i].getReg();
2381 if (!Hexagon::DoubleRegsRegClass.contains(R))
2385 int F = Regs.find_first();
2386 if (F != Hexagon::D8)
2389 int N = Regs.find_next(F);
2390 if (N >= 0 && N != F+1)
2398 bool HexagonFrameLowering::useSpillFunction(MachineFunction &MF,
2399 const CSIVect &CSI) const {
2400 if (shouldInlineCSR(MF, CSI))
2402 unsigned NumCSI = CSI.size();
2406 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2407 : SpillFuncThreshold;
2408 return Threshold < NumCSI;
2411 bool HexagonFrameLowering::useRestoreFunction(MachineFunction &MF,
2412 const CSIVect &CSI) const {
2413 if (shouldInlineCSR(MF, CSI))
2415 // The restore functions do a bit more than just restoring registers.
2416 // The non-returning versions will go back directly to the caller's
2417 // caller, others will clean up the stack frame in preparation for
2418 // a tail call. Using them can still save code size even if only one
2419 // register is getting restores. Make the decision based on -Oz:
2420 // using -Os will use inline restore for a single register.
2423 unsigned NumCSI = CSI.size();
2427 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2428 : SpillFuncThreshold;
2429 return Threshold < NumCSI;
2432 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2433 unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2434 auto &HST = MF.getSubtarget<HexagonSubtarget>();
2435 // A fairly simplistic guess as to whether a potential load/store to a
2436 // stack location could require an extra register. It does not account
2437 // for store-immediate instructions.
2438 if (HST.useHVXOps())
2439 return StackSize > 256;