1 //=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
14 #include "HexagonBlockRanges.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/Target/TargetFrameLowering.h"
23 class HexagonInstrInfo;
24 class HexagonRegisterInfo;
26 class HexagonFrameLowering : public TargetFrameLowering {
28 explicit HexagonFrameLowering()
29 : TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
31 // All of the prolog/epilog functionality, including saving and restoring
32 // callee-saved registers is handled in emitPrologue. This is to have the
33 // logic for shrink-wrapping in one place.
34 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
36 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
39 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
41 const TargetRegisterInfo *TRI) const override {
45 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
47 const TargetRegisterInfo *TRI) const override {
51 MachineBasicBlock::iterator
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator I) const override;
54 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
55 RegScavenger *RS = nullptr) const override;
56 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
57 RegScavenger *RS) const override;
59 bool targetHandlesStackFrameRounding() const override {
63 int getFrameIndexReference(const MachineFunction &MF, int FI,
64 unsigned &FrameReg) const override;
65 bool hasFP(const MachineFunction &MF) const override;
67 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
69 static const SpillSlot Offsets[] = {
70 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
71 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
72 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
73 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
74 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
75 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
77 NumEntries = array_lengthof(Offsets);
81 bool assignCalleeSavedSpillSlots(MachineFunction &MF,
82 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
85 bool needsAligna(const MachineFunction &MF) const;
86 const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
88 void insertCFIInstructions(MachineFunction &MF) const;
91 typedef std::vector<CalleeSavedInfo> CSIVect;
93 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
94 unsigned SP, unsigned CF) const;
95 void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
96 void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
97 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
98 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
99 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
100 const HexagonRegisterInfo &HRI) const;
101 void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
102 bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
103 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
104 void insertCFIInstructionsAt(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator At) const;
107 void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
109 bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
110 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
111 SmallVectorImpl<unsigned> &NewRegs) const;
112 bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
113 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
114 SmallVectorImpl<unsigned> &NewRegs) const;
115 bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
116 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
117 SmallVectorImpl<unsigned> &NewRegs) const;
118 bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
119 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
120 SmallVectorImpl<unsigned> &NewRegs) const;
121 bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
122 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
123 SmallVectorImpl<unsigned> &NewRegs) const;
124 bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
125 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
126 SmallVectorImpl<unsigned> &NewRegs) const;
127 bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
128 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
129 SmallVectorImpl<unsigned> &NewRegs) const;
130 bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
131 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
132 SmallVectorImpl<unsigned> &NewRegs) const;
133 bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
134 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
135 SmallVectorImpl<unsigned> &NewRegs) const;
136 bool expandSpillMacros(MachineFunction &MF,
137 SmallVectorImpl<unsigned> &NewRegs) const;
139 unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
140 HexagonBlockRanges::InstrIndexMap &IndexMap,
141 HexagonBlockRanges::RegToRangeMap &DeadMap,
142 const TargetRegisterClass *RC) const;
143 void optimizeSpillSlots(MachineFunction &MF,
144 SmallVectorImpl<unsigned> &VRegs) const;
146 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
147 MachineBasicBlock *&EpilogB) const;
149 void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
150 bool IsDef, bool IsKill) const;
151 bool shouldInlineCSR(MachineFunction &MF, const CSIVect &CSI) const;
152 bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
153 bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
154 bool mayOverflowFrameOffset(MachineFunction &MF) const;
157 } // end namespace llvm
159 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H