contrib/llvm/lib/Target/Hexagon/HexagonIICHVX.td

   1 //===--- HexagonIICHVX.td -------------------------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 //
  11 // Though all these itinerary classes exist for V60 onwards, they are being
  12 // listed here as 'HVXV62Itin' because itinerary class description prior to V62
  13 // doesn't include operand cycle info. In future, I plan to merge them
  14 // together and call it 'HVXItin'.
  15 //
  16 class HVXV62Itin {
  17   list<InstrItinData> HVXV62Itin_list = [
  18     InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
  19                                    [InstrStage<1, [SLOT0, SLOT1]>],
  20                                    [3, 1, 1, 1]>,
  21     InstrItinData<COPROC_VX_vtc_long_SLOT23,
  22                                    [InstrStage<1, [SLOT2, SLOT3]>],
  23                                    [3, 1, 1, 1]>,
  24     InstrItinData<COPROC_VX_vtc_SLOT23,
  25                                    [InstrStage<1, [SLOT2, SLOT3]>],
  26                                    [3, 1, 1, 1]>,
  27     InstrItinData<CVI_VA,          [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  28                                     InstrStage<1, [CVI_XLANE,CVI_SHIFT,
  29                                                    CVI_MPY0, CVI_MPY1]>],
  30                                    [1, 1, 1, 1]>,
  31     InstrItinData<CVI_VA_DV,       [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  32                                     InstrStage<1, [CVI_XLSHF, CVI_MPY01]>],
  33                                     [1, 1, 1, 1]>,
  34     InstrItinData<CVI_VX_LONG,     [InstrStage<1, [SLOT2, SLOT3], 0>,
  35                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
  36                                    [1, 1, 1, 1]>,
  37     InstrItinData<CVI_VX_LATE,     [InstrStage<1, [SLOT2, SLOT3], 0>,
  38                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
  39                                    [1, 1, 1, 1]>,
  40     InstrItinData<CVI_VX,          [InstrStage<1, [SLOT2, SLOT3], 0>,
  41                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
  42                                    [1, 1, 1, 1]>,
  43     InstrItinData<CVI_VX_DV_LONG,  [InstrStage<1, [SLOT2, SLOT3], 0>,
  44                                     InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
  45     InstrItinData<CVI_VX_DV,       [InstrStage<1, [SLOT2, SLOT3], 0>,
  46                                     InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
  47     InstrItinData<CVI_VX_DV_SLOT2, [InstrStage<1, [SLOT2], 0>,
  48                                     InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
  49     InstrItinData<CVI_VX_DV_SLOT2_LONG_EARLY,
  50                                    [InstrStage<1, [SLOT2], 0>,
  51                                     InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
  52     InstrItinData<CVI_VP,          [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  53                                     InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
  54     InstrItinData<CVI_VP_LONG,     [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  55                                     InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
  56     InstrItinData<CVI_VP_VS_EARLY, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  57                                     InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
  58     InstrItinData<CVI_VP_VS_LONG,  [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  59                                     InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
  60     InstrItinData<CVI_VP_VS,       [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  61                                     InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
  62     InstrItinData<CVI_VP_VS_LONG_EARLY,
  63                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  64                                     InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
  65     InstrItinData<CVI_VP_DV,       [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  66                                     InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
  67     InstrItinData<CVI_VS,          [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  68                                     InstrStage<1, [CVI_SHIFT]>], [1, 1, 1, 1]>,
  69     InstrItinData<CVI_VINLANESAT,  [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
  70                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
  71                                                    CVI_MPY0, CVI_MPY1]>],
  72                                    [1, 1, 1, 1]>,
  73     InstrItinData<CVI_VM_LD,       [InstrStage<1, [SLOT0, SLOT1], 0>,
  74                                     InstrStage<1, [CVI_LD], 0>,
  75                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
  76                                                    CVI_MPY0, CVI_MPY1]>],
  77                                    [1, 1, 1, 1]>,
  78     InstrItinData<CVI_VM_TMP_LD,   [InstrStage<1,[SLOT0, SLOT1], 0>,
  79                                     InstrStage<1, [CVI_LD]>],[1, 1, 1, 1, 10]>,
  80     InstrItinData<CVI_VM_CUR_LD,   [InstrStage<1,[SLOT0, SLOT1], 0>,
  81                                     InstrStage<1, [CVI_LD], 0>,
  82                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
  83                                                    CVI_MPY0, CVI_MPY1]>],
  84                                    [1, 1, 1, 1]>,
  85     InstrItinData<CVI_VM_VP_LDU,   [InstrStage<1,[SLOT0], 0>,
  86                                     InstrStage<1, [SLOT1], 0>,
  87                                     InstrStage<1, [CVI_LD], 0>,
  88                                     InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
  89     InstrItinData<CVI_VM_ST,       [InstrStage<1, [SLOT0], 0>,
  90                                     InstrStage<1, [CVI_ST], 0>,
  91                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
  92                                                    CVI_MPY0, CVI_MPY1]>],
  93                                    [1, 1, 1, 1]>,
  94     InstrItinData<CVI_VM_NEW_ST,   [InstrStage<1,[SLOT0], 0>,
  95                                     InstrStage<1, [CVI_ST]>], [1, 1, 1, 1]>,
  96     InstrItinData<CVI_VM_STU,      [InstrStage<1, [SLOT0], 0>,
  97                                     InstrStage<1, [SLOT1], 0>,
  98                                     InstrStage<1, [CVI_ST], 0>,
  99                                     InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
 100     InstrItinData<CVI_HIST,        [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 101                                     InstrStage<1, [CVI_ALL]>], [1, 1, 1, 1]>];
 102 }