1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
21 #include "HexagonTargetObjectFile.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Type.h"
44 #include "llvm/IR/Value.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CodeGen.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetCallingConv.h"
54 #include "llvm/Target/TargetMachine.h"
64 #define DEBUG_TYPE "hexagon-lowering"
66 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67 cl::init(true), cl::Hidden,
68 cl::desc("Control jump table emission on Hexagon target"));
70 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
71 cl::Hidden, cl::ZeroOrMore, cl::init(false),
72 cl::desc("Enable Hexagon SDNode scheduling"));
74 static cl::opt<bool> EnableFastMath("ffast-math",
75 cl::Hidden, cl::ZeroOrMore, cl::init(false),
76 cl::desc("Enable Fast Math processing"));
78 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
79 cl::Hidden, cl::ZeroOrMore, cl::init(5),
80 cl::desc("Set minimum jump tables"));
82 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
83 cl::Hidden, cl::ZeroOrMore, cl::init(6),
84 cl::desc("Max #stores to inline memcpy"));
86 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
87 cl::Hidden, cl::ZeroOrMore, cl::init(4),
88 cl::desc("Max #stores to inline memcpy"));
90 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
91 cl::Hidden, cl::ZeroOrMore, cl::init(6),
92 cl::desc("Max #stores to inline memmove"));
94 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
95 cl::Hidden, cl::ZeroOrMore, cl::init(4),
96 cl::desc("Max #stores to inline memmove"));
98 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
99 cl::Hidden, cl::ZeroOrMore, cl::init(8),
100 cl::desc("Max #stores to inline memset"));
102 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
103 cl::Hidden, cl::ZeroOrMore, cl::init(4),
104 cl::desc("Max #stores to inline memset"));
109 class HexagonCCState : public CCState {
110 unsigned NumNamedVarArgParams;
113 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
114 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
115 int NumNamedVarArgParams)
116 : CCState(CC, isVarArg, MF, locs, C),
117 NumNamedVarArgParams(NumNamedVarArgParams) {}
119 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
122 enum StridedLoadKind {
128 } // end anonymous namespace
130 // Implement calling convention for Hexagon.
132 static bool isHvxVectorType(MVT ty);
135 CC_Hexagon(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
140 CC_Hexagon32(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
145 CC_Hexagon64(unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State);
150 CC_HexagonVector(unsigned ValNo, MVT ValVT,
151 MVT LocVT, CCValAssign::LocInfo LocInfo,
152 ISD::ArgFlagsTy ArgFlags, CCState &State);
155 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
160 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161 MVT LocVT, CCValAssign::LocInfo LocInfo,
162 ISD::ArgFlagsTy ArgFlags, CCState &State);
165 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166 MVT LocVT, CCValAssign::LocInfo LocInfo,
167 ISD::ArgFlagsTy ArgFlags, CCState &State);
170 RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171 MVT LocVT, CCValAssign::LocInfo LocInfo,
172 ISD::ArgFlagsTy ArgFlags, CCState &State);
175 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State) {
178 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
180 if (ValNo < HState.getNumNamedVarArgParams()) {
181 // Deal with named arguments.
182 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
185 // Deal with un-named arguments.
187 if (ArgFlags.isByVal()) {
188 // If pass-by-value, the size allocated on stack is decided
189 // by ArgFlags.getByValSize(), not by the size of LocVT.
190 Offset = State.AllocateStack(ArgFlags.getByValSize(),
191 ArgFlags.getByValAlign());
192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
195 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
198 if (ArgFlags.isSExt())
199 LocInfo = CCValAssign::SExt;
200 else if (ArgFlags.isZExt())
201 LocInfo = CCValAssign::ZExt;
203 LocInfo = CCValAssign::AExt;
205 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206 Offset = State.AllocateStack(4, 4);
207 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
210 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211 Offset = State.AllocateStack(8, 8);
212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
215 if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216 LocVT == MVT::v16i8) {
217 Offset = State.AllocateStack(16, 16);
218 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
221 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222 LocVT == MVT::v32i8) {
223 Offset = State.AllocateStack(32, 32);
224 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
227 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229 Offset = State.AllocateStack(64, 64);
230 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
233 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235 Offset = State.AllocateStack(128, 128);
236 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
239 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240 LocVT == MVT::v256i8) {
241 Offset = State.AllocateStack(256, 256);
242 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
246 llvm_unreachable(nullptr);
249 static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251 if (ArgFlags.isByVal()) {
253 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254 ArgFlags.getByValAlign());
255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
259 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
262 if (ArgFlags.isSExt())
263 LocInfo = CCValAssign::SExt;
264 else if (ArgFlags.isZExt())
265 LocInfo = CCValAssign::ZExt;
267 LocInfo = CCValAssign::AExt;
268 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
270 LocInfo = CCValAssign::BCvt;
271 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
273 LocInfo = CCValAssign::BCvt;
276 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
277 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
281 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
282 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
286 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
287 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
288 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
292 if (isHvxVectorType(LocVT)) {
293 if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
297 return true; // CC didn't match.
301 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
302 MVT LocVT, CCValAssign::LocInfo LocInfo,
303 ISD::ArgFlagsTy ArgFlags, CCState &State) {
304 static const MCPhysReg RegList[] = {
305 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
308 if (unsigned Reg = State.AllocateReg(RegList)) {
309 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
313 unsigned Offset = State.AllocateStack(4, 4);
314 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
318 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
319 MVT LocVT, CCValAssign::LocInfo LocInfo,
320 ISD::ArgFlagsTy ArgFlags, CCState &State) {
321 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
322 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
326 static const MCPhysReg RegList1[] = {
327 Hexagon::D1, Hexagon::D2
329 static const MCPhysReg RegList2[] = {
330 Hexagon::R1, Hexagon::R3
332 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
333 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
337 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
338 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
342 static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
343 MVT LocVT, CCValAssign::LocInfo LocInfo,
344 ISD::ArgFlagsTy ArgFlags, CCState &State) {
345 static const MCPhysReg VecLstS[] = {
346 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
347 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
348 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
351 static const MCPhysReg VecLstD[] = {
352 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
353 Hexagon::W5, Hexagon::W6, Hexagon::W7
355 auto &MF = State.getMachineFunction();
356 auto &HST = MF.getSubtarget<HexagonSubtarget>();
357 bool UseHVX = HST.useHVXOps();
358 bool UseHVXDbl = HST.useHVXDblOps();
360 if ((UseHVX && !UseHVXDbl) &&
361 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
362 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
363 if (unsigned Reg = State.AllocateReg(VecLstS)) {
364 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
367 unsigned Offset = State.AllocateStack(64, 64);
368 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
371 if ((UseHVX && !UseHVXDbl) &&
372 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
373 LocVT == MVT::v128i8)) {
374 if (unsigned Reg = State.AllocateReg(VecLstD)) {
375 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
378 unsigned Offset = State.AllocateStack(128, 128);
379 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
383 if ((UseHVX && UseHVXDbl) &&
384 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
385 LocVT == MVT::v256i8)) {
386 if (unsigned Reg = State.AllocateReg(VecLstD)) {
387 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
390 unsigned Offset = State.AllocateStack(256, 256);
391 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
394 if ((UseHVX && UseHVXDbl) &&
395 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
396 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
397 if (unsigned Reg = State.AllocateReg(VecLstS)) {
398 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
401 unsigned Offset = State.AllocateStack(128, 128);
402 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
408 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
409 MVT LocVT, CCValAssign::LocInfo LocInfo,
410 ISD::ArgFlagsTy ArgFlags, CCState &State) {
411 auto &MF = State.getMachineFunction();
412 auto &HST = MF.getSubtarget<HexagonSubtarget>();
413 bool UseHVX = HST.useHVXOps();
414 bool UseHVXDbl = HST.useHVXDblOps();
416 if (LocVT == MVT::i1) {
417 // Return values of type MVT::i1 still need to be assigned to R0, but
418 // the value type needs to remain i1. LowerCallResult will deal with it,
419 // but it needs to recognize i1 as the value type.
421 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
424 if (ArgFlags.isSExt())
425 LocInfo = CCValAssign::SExt;
426 else if (ArgFlags.isZExt())
427 LocInfo = CCValAssign::ZExt;
429 LocInfo = CCValAssign::AExt;
430 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
432 LocInfo = CCValAssign::BCvt;
433 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
435 LocInfo = CCValAssign::BCvt;
436 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
437 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
438 LocVT == MVT::v512i1) {
441 LocInfo = CCValAssign::Full;
442 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
443 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
444 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
447 LocInfo = CCValAssign::Full;
448 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
449 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
452 LocInfo = CCValAssign::Full;
454 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
455 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
459 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
460 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
463 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
464 if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
467 return true; // CC didn't match.
470 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
471 MVT LocVT, CCValAssign::LocInfo LocInfo,
472 ISD::ArgFlagsTy ArgFlags, CCState &State) {
473 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
474 // Note that use of registers beyond R1 is not ABI compliant. However there
475 // are (experimental) IR passes which generate internal functions that
476 // return structs using these additional registers.
477 static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
478 Hexagon::R2, Hexagon::R3,
479 Hexagon::R4, Hexagon::R5 };
480 if (unsigned Reg = State.AllocateReg(RegList)) {
481 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
486 unsigned Offset = State.AllocateStack(4, 4);
487 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
491 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
492 MVT LocVT, CCValAssign::LocInfo LocInfo,
493 ISD::ArgFlagsTy ArgFlags, CCState &State) {
494 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
495 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
496 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501 unsigned Offset = State.AllocateStack(8, 8);
502 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
506 static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
507 MVT LocVT, CCValAssign::LocInfo LocInfo,
508 ISD::ArgFlagsTy ArgFlags, CCState &State) {
509 auto &MF = State.getMachineFunction();
510 auto &HST = MF.getSubtarget<HexagonSubtarget>();
511 bool UseHVX = HST.useHVXOps();
512 bool UseHVXDbl = HST.useHVXDblOps();
514 unsigned OffSiz = 64;
515 if (LocVT == MVT::v16i32) {
516 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
517 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
520 } else if (LocVT == MVT::v32i32) {
521 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
522 if (unsigned Reg = State.AllocateReg(Req)) {
523 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
527 } else if (LocVT == MVT::v64i32) {
528 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
529 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
535 unsigned Offset = State.AllocateStack(OffSiz, OffSiz);
536 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
540 void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
541 if (VT != PromotedLdStVT) {
542 setOperationAction(ISD::LOAD, VT, Promote);
543 AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
545 setOperationAction(ISD::STORE, VT, Promote);
546 AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
551 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
556 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
557 /// by "Src" to address "Dst" of size "Size". Alignment information is
558 /// specified by the specific parameter attribute. The copy will be passed as
559 /// a byval function parameter. Sometimes what we are copying is the end of a
560 /// larger object, the part that does not fit in registers.
561 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
562 SDValue Chain, ISD::ArgFlagsTy Flags,
563 SelectionDAG &DAG, const SDLoc &dl) {
564 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
565 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
566 /*isVolatile=*/false, /*AlwaysInline=*/false,
567 /*isTailCall=*/false,
568 MachinePointerInfo(), MachinePointerInfo());
571 static bool isHvxVectorType(MVT Ty) {
572 switch (Ty.SimpleTy) {
593 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
594 // passed by value, the function prototype is modified to return void and
595 // the value is stored in memory pointed by a pointer passed by caller.
597 HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
599 const SmallVectorImpl<ISD::OutputArg> &Outs,
600 const SmallVectorImpl<SDValue> &OutVals,
601 const SDLoc &dl, SelectionDAG &DAG) const {
602 // CCValAssign - represent the assignment of the return value to locations.
603 SmallVector<CCValAssign, 16> RVLocs;
605 // CCState - Info about the registers and stack slot.
606 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
609 // Analyze return values of ISD::RET
610 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
613 SmallVector<SDValue, 4> RetOps(1, Chain);
615 // Copy the result values into the output registers.
616 for (unsigned i = 0; i != RVLocs.size(); ++i) {
617 CCValAssign &VA = RVLocs[i];
619 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
621 // Guarantee that all emitted copies are stuck together with flags.
622 Flag = Chain.getValue(1);
623 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
626 RetOps[0] = Chain; // Update chain.
628 // Add the flag if we have it.
630 RetOps.push_back(Flag);
632 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
635 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
636 // If either no tail call or told not to tail call at all, don't.
638 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
639 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
645 /// LowerCallResult - Lower the result values of an ISD::CALL into the
646 /// appropriate copies out of appropriate physical registers. This assumes that
647 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
648 /// being lowered. Returns a SDNode with the same number of values as the
650 SDValue HexagonTargetLowering::LowerCallResult(
651 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
652 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
653 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
654 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
655 // Assign locations to each value returned by this call.
656 SmallVector<CCValAssign, 16> RVLocs;
658 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
661 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
663 // Copy all of the result registers out of their specified physreg.
664 for (unsigned i = 0; i != RVLocs.size(); ++i) {
666 if (RVLocs[i].getValVT() == MVT::i1) {
667 // Return values of type MVT::i1 require special handling. The reason
668 // is that MVT::i1 is associated with the PredRegs register class, but
669 // values of that type are still returned in R0. Generate an explicit
670 // copy into a predicate register from R0, and treat the value of the
671 // predicate register as the call result.
672 auto &MRI = DAG.getMachineFunction().getRegInfo();
673 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
675 // FR0 = (Value, Chain, Glue)
676 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
677 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
678 FR0.getValue(0), FR0.getValue(2));
679 // TPR = (Chain, Glue)
680 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1,
683 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
684 RVLocs[i].getValVT(), InFlag);
686 InVals.push_back(RetVal.getValue(0));
687 Chain = RetVal.getValue(1);
688 InFlag = RetVal.getValue(2);
694 /// LowerCall - Functions arguments are copied from virtual regs to
695 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
697 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
698 SmallVectorImpl<SDValue> &InVals) const {
699 SelectionDAG &DAG = CLI.DAG;
701 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
702 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
703 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
704 SDValue Chain = CLI.Chain;
705 SDValue Callee = CLI.Callee;
706 bool &IsTailCall = CLI.IsTailCall;
707 CallingConv::ID CallConv = CLI.CallConv;
708 bool IsVarArg = CLI.IsVarArg;
709 bool DoesNotReturn = CLI.DoesNotReturn;
711 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
712 MachineFunction &MF = DAG.getMachineFunction();
713 auto PtrVT = getPointerTy(MF.getDataLayout());
715 // Check for varargs.
716 unsigned NumNamedVarArgParams = -1U;
717 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
718 const GlobalValue *GV = GAN->getGlobal();
719 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
720 if (const Function* F = dyn_cast<Function>(GV)) {
721 // If a function has zero args and is a vararg function, that's
722 // disallowed so it must be an undeclared function. Do not assume
723 // varargs if the callee is undefined.
724 if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
725 NumNamedVarArgParams = F->getFunctionType()->getNumParams();
729 // Analyze operands of the call, assigning locations to each operand.
730 SmallVector<CCValAssign, 16> ArgLocs;
731 HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
732 *DAG.getContext(), NumNamedVarArgParams);
735 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
737 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
739 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
740 if (Attr.getValueAsString() == "true")
744 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
745 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
746 IsVarArg, IsStructRet,
748 Outs, OutVals, Ins, DAG);
749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
750 CCValAssign &VA = ArgLocs[i];
756 DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
757 : "Argument must be passed on stack. "
758 "Not eligible for Tail Call\n"));
760 // Get a count of how many bytes are to be pushed on the stack.
761 unsigned NumBytes = CCInfo.getNextStackOffset();
762 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
763 SmallVector<SDValue, 8> MemOpChains;
765 auto &HRI = *Subtarget.getRegisterInfo();
767 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
769 bool NeedsArgAlign = false;
770 unsigned LargestAlignSeen = 0;
771 // Walk the register/memloc assignments, inserting copies/loads.
772 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
773 CCValAssign &VA = ArgLocs[i];
774 SDValue Arg = OutVals[i];
775 ISD::ArgFlagsTy Flags = Outs[i].Flags;
776 // Record if we need > 8 byte alignment on an argument.
777 bool ArgAlign = isHvxVectorType(VA.getValVT());
778 NeedsArgAlign |= ArgAlign;
780 // Promote the value if needed.
781 switch (VA.getLocInfo()) {
783 // Loc info must be one of Full, SExt, ZExt, or AExt.
784 llvm_unreachable("Unknown loc info!");
785 case CCValAssign::BCvt:
786 case CCValAssign::Full:
788 case CCValAssign::SExt:
789 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
791 case CCValAssign::ZExt:
792 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
794 case CCValAssign::AExt:
795 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
800 unsigned LocMemOffset = VA.getLocMemOffset();
801 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
802 StackPtr.getValueType());
803 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
805 LargestAlignSeen = std::max(LargestAlignSeen,
806 VA.getLocVT().getStoreSizeInBits() >> 3);
807 if (Flags.isByVal()) {
808 // The argument is a struct passed by value. According to LLVM, "Arg"
810 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
813 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
814 DAG.getMachineFunction(), LocMemOffset);
815 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
816 MemOpChains.push_back(S);
821 // Arguments that can be passed on register must be kept at RegsToPass
824 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
827 if (NeedsArgAlign && Subtarget.hasV60TOps()) {
828 DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
829 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
830 // V6 vectors passed by value have 64 or 128 byte alignment depending
831 // on whether we are 64 byte vector mode or 128 byte.
832 bool UseHVXDbl = Subtarget.useHVXDblOps();
833 assert(Subtarget.useHVXOps());
834 const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
835 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
836 MFI.ensureMaxAlignment(LargestAlignSeen);
838 // Transform all store nodes into one single node because all store
839 // nodes are independent of each other.
840 if (!MemOpChains.empty())
841 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
844 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
845 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
848 // Build a sequence of copy-to-reg nodes chained together with token
849 // chain and flag operands which copy the outgoing args into registers.
850 // The Glue is necessary since all emitted instructions must be
854 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
855 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
856 RegsToPass[i].second, Glue);
857 Glue = Chain.getValue(1);
860 // For tail calls lower the arguments to the 'real' stack slot.
862 // Force all the incoming stack arguments to be loaded from the stack
863 // before any new outgoing arguments are stored to the stack, because the
864 // outgoing stack slots may alias the incoming argument stack slots, and
865 // the alias isn't otherwise explicit. This is slightly more conservative
866 // than necessary, because it means that each store effectively depends
867 // on every argument instead of just those arguments it would clobber.
869 // Do not flag preceding copytoreg stuff together with the following stuff.
871 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
872 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
873 RegsToPass[i].second, Glue);
874 Glue = Chain.getValue(1);
879 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
880 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
882 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
883 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
884 // node so that legalize doesn't hack it.
885 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
886 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
887 } else if (ExternalSymbolSDNode *S =
888 dyn_cast<ExternalSymbolSDNode>(Callee)) {
889 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
892 // Returns a chain & a flag for retval copy to use.
893 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
894 SmallVector<SDValue, 8> Ops;
895 Ops.push_back(Chain);
896 Ops.push_back(Callee);
898 // Add argument registers to the end of the list so that they are
899 // known live into the call.
900 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
901 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
902 RegsToPass[i].second.getValueType()));
909 MF.getFrameInfo().setHasTailCall();
910 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
913 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
914 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
915 Glue = Chain.getValue(1);
917 // Create the CALLSEQ_END node.
918 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
919 DAG.getIntPtrConstant(0, dl, true), Glue, dl);
920 Glue = Chain.getValue(1);
922 // Handle result values, copying them out of physregs into vregs that we
924 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
925 InVals, OutVals, Callee);
928 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
929 SDValue &Base, SDValue &Offset,
930 bool &IsInc, SelectionDAG &DAG) {
931 if (Ptr->getOpcode() != ISD::ADD)
934 auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
935 bool UseHVX = HST.useHVXOps();
936 bool UseHVXDbl = HST.useHVXDblOps();
938 bool ValidHVXDblType =
939 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
940 VT == MVT::v64i16 || VT == MVT::v128i8);
942 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
943 VT == MVT::v32i16 || VT == MVT::v64i8);
945 if (ValidHVXDblType || ValidHVXType ||
946 VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
947 IsInc = (Ptr->getOpcode() == ISD::ADD);
948 Base = Ptr->getOperand(0);
949 Offset = Ptr->getOperand(1);
950 // Ensure that Offset is a constant.
951 return isa<ConstantSDNode>(Offset);
957 /// getPostIndexedAddressParts - returns true by value, base pointer and
958 /// offset pointer and addressing mode by reference if this node can be
959 /// combined with a load / store to form a post-indexed load / store.
960 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
963 ISD::MemIndexedMode &AM,
964 SelectionDAG &DAG) const
969 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
970 VT = LD->getMemoryVT();
971 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
972 VT = ST->getMemoryVT();
973 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
980 bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
982 auto &HII = *Subtarget.getInstrInfo();
983 int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
984 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
985 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
994 HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
995 SDNode *Node = Op.getNode();
996 MachineFunction &MF = DAG.getMachineFunction();
997 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
998 switch (Node->getOpcode()) {
999 case ISD::INLINEASM: {
1000 unsigned NumOps = Node->getNumOperands();
1001 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1002 --NumOps; // Ignore the flag operand.
1004 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1005 if (FuncInfo.hasClobberLR())
1008 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1009 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1010 ++i; // Skip the ID value.
1012 switch (InlineAsm::getKind(Flags)) {
1013 default: llvm_unreachable("Bad flags!");
1014 case InlineAsm::Kind_RegDef:
1015 case InlineAsm::Kind_RegUse:
1016 case InlineAsm::Kind_Imm:
1017 case InlineAsm::Kind_Clobber:
1018 case InlineAsm::Kind_Mem: {
1019 for (; NumVals; --NumVals, ++i) {}
1022 case InlineAsm::Kind_RegDefEarlyClobber: {
1023 for (; NumVals; --NumVals, ++i) {
1025 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1027 // Check it to be lr
1028 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
1029 if (Reg == QRI->getRARegister()) {
1030 FuncInfo.setHasClobberLR(true);
1039 } // Node->getOpcode
1043 // Need to transform ISD::PREFETCH into something that doesn't inherit
1044 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1046 SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
1047 SelectionDAG &DAG) const {
1048 SDValue Chain = Op.getOperand(0);
1049 SDValue Addr = Op.getOperand(1);
1050 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1051 // if the "reg" is fed by an "add".
1053 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1054 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1057 SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1058 SelectionDAG &DAG) const {
1059 SDValue Chain = Op.getOperand(0);
1060 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1061 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1062 if (IntNo == Intrinsic::hexagon_prefetch) {
1063 SDValue Addr = Op.getOperand(2);
1065 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1066 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1072 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1073 SelectionDAG &DAG) const {
1074 SDValue Chain = Op.getOperand(0);
1075 SDValue Size = Op.getOperand(1);
1076 SDValue Align = Op.getOperand(2);
1079 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1080 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
1082 unsigned A = AlignConst->getSExtValue();
1083 auto &HFI = *Subtarget.getFrameLowering();
1084 // "Zero" means natural stack alignment.
1086 A = HFI.getStackAlignment();
1089 dbgs () << __func__ << " Align: " << A << " Size: ";
1090 Size.getNode()->dump(&DAG);
1094 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1095 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1096 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1098 DAG.ReplaceAllUsesOfValueWith(Op, AA);
1102 SDValue HexagonTargetLowering::LowerFormalArguments(
1103 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1104 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1105 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1106 MachineFunction &MF = DAG.getMachineFunction();
1107 MachineFrameInfo &MFI = MF.getFrameInfo();
1108 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1109 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1111 // Assign locations to all of the incoming arguments.
1112 SmallVector<CCValAssign, 16> ArgLocs;
1113 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1116 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1118 // For LLVM, in the case when returning a struct by value (>8byte),
1119 // the first argument is a pointer that points to the location on caller's
1120 // stack where the return value will be stored. For Hexagon, the location on
1121 // caller's stack is passed only when the struct size is smaller than (and
1122 // equal to) 8 bytes. If not, no address will be passed into callee and
1123 // callee return the result direclty through R0/R1.
1125 SmallVector<SDValue, 8> MemOps;
1126 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
1128 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1129 CCValAssign &VA = ArgLocs[i];
1130 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1132 unsigned StackLocation;
1135 if ( (VA.isRegLoc() && !Flags.isByVal())
1136 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1137 // Arguments passed in registers
1138 // 1. int, long long, ptr args that get allocated in register.
1139 // 2. Large struct that gets an register to put its address in.
1140 EVT RegVT = VA.getLocVT();
1141 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1142 RegVT == MVT::i32 || RegVT == MVT::f32) {
1144 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1145 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1146 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1147 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1149 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1150 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1151 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1154 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1155 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1157 RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1158 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1159 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1160 } else if (UseHVX && UseHVXDbl &&
1161 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1162 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1164 RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1165 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1166 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1169 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1170 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1172 RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1173 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1174 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1175 } else if (UseHVX && UseHVXDbl &&
1176 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1177 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1179 RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1180 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1181 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1182 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1183 assert(0 && "need to support VecPred regs");
1185 RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1186 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1187 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1191 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1192 assert (0 && "ByValSize must be bigger than 8 bytes");
1195 assert(VA.isMemLoc());
1197 if (Flags.isByVal()) {
1198 // If it's a byval parameter, then we need to compute the
1199 // "real" size, not the size of the pointer.
1200 ObjSize = Flags.getByValSize();
1202 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1205 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
1206 // Create the frame index object for this incoming parameter...
1207 FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1209 // Create the SelectionDAG nodes cordl, responding to a load
1210 // from this parameter.
1211 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1213 if (Flags.isByVal()) {
1214 // If it's a pass-by-value aggregate, then do not dereference the stack
1215 // location. Instead, we should generate a reference to the stack
1217 InVals.push_back(FIN);
1220 DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo()));
1225 if (!MemOps.empty())
1226 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1229 // This will point to the next argument passed via stack.
1230 int FrameIndex = MFI.CreateFixedObject(Hexagon_PointerSize,
1232 CCInfo.getNextStackOffset(),
1234 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1241 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1242 // VASTART stores the address of the VarArgsFrameIndex slot into the
1243 // memory location argument.
1244 MachineFunction &MF = DAG.getMachineFunction();
1245 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
1246 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1247 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1248 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1249 MachinePointerInfo(SV));
1252 // Creates a SPLAT instruction for a constant value VAL.
1253 static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT,
1255 if (VT.getSimpleVT() == MVT::v4i8)
1256 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
1258 if (VT.getSimpleVT() == MVT::v4i16)
1259 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
1264 static bool isSExtFree(SDValue N) {
1265 // A sign-extend of a truncate of a sign-extend is free.
1266 if (N.getOpcode() == ISD::TRUNCATE &&
1267 N.getOperand(0).getOpcode() == ISD::AssertSext)
1269 // We have sign-extended loads.
1270 if (N.getOpcode() == ISD::LOAD)
1275 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
1277 SDValue InpVal = Op.getOperand(0);
1278 if (isa<ConstantSDNode>(InpVal)) {
1279 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1280 return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
1282 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1283 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1286 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1289 SDValue LHS = Op.getOperand(0);
1290 SDValue RHS = Op.getOperand(1);
1291 SDValue Cmp = Op.getOperand(2);
1292 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1294 EVT VT = Op.getValueType();
1295 EVT LHSVT = LHS.getValueType();
1296 EVT RHSVT = RHS.getValueType();
1298 if (LHSVT == MVT::v2i16) {
1299 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1300 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1302 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1303 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1304 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1308 // Treat all other vector types as legal.
1312 // Equals and not equals should use sign-extend, not zero-extend, since
1313 // we can represent small negative values in the compare instructions.
1314 // The LLVM default is to use zero-extend arbitrarily in these cases.
1315 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1316 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1317 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1319 if (C && C->getAPIntValue().isNegative()) {
1320 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1321 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1322 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1323 LHS, RHS, Op.getOperand(2));
1325 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1326 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1327 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1328 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1329 LHS, RHS, Op.getOperand(2));
1336 HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1337 SDValue PredOp = Op.getOperand(0);
1338 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1339 EVT OpVT = Op1.getValueType();
1342 if (OpVT == MVT::v2i16) {
1343 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1344 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1345 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1346 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1353 // Handle only specific vector loads.
1354 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1355 EVT VT = Op.getValueType();
1357 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1358 SDValue Chain = LoadNode->getChain();
1359 SDValue Ptr = Op.getOperand(1);
1360 SDValue LoweredLoad;
1362 SDValue Base = LoadNode->getBasePtr();
1363 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1364 unsigned Alignment = LoadNode->getAlignment();
1367 if(Ext == ISD::NON_EXTLOAD)
1368 Ext = ISD::ZEXTLOAD;
1370 if (VT == MVT::v4i16) {
1371 if (Alignment == 2) {
1374 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1375 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1376 LoadNode->getMemOperand()->getFlags());
1378 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1379 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1380 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1381 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1382 LoadNode->getMemOperand()->getFlags());
1383 // SHL 16, then OR base and base+2.
1384 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1385 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1386 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1388 Increment = DAG.getConstant(4, DL, MVT::i32);
1389 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1390 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1391 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1392 LoadNode->getMemOperand()->getFlags());
1394 Increment = DAG.getConstant(6, DL, MVT::i32);
1395 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1396 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1397 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1398 LoadNode->getMemOperand()->getFlags());
1399 // SHL 16, then OR base+4 and base+6.
1400 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1401 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1402 // Combine to i64. This could be optimised out later if we can
1403 // affect reg allocation of this code.
1404 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1405 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1406 Loads[0].getValue(1), Loads[1].getValue(1),
1407 Loads[2].getValue(1), Loads[3].getValue(1));
1409 // Perform default type expansion.
1410 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1411 LoadNode->getAlignment(),
1412 LoadNode->getMemOperand()->getFlags());
1413 LoadChain = Result.getValue(1);
1416 llvm_unreachable("Custom lowering unsupported load");
1418 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1419 // Since we pretend to lower a load, we need the original chain
1420 // info attached to the result.
1421 SDValue Ops[] = { Result, LoadChain };
1423 return DAG.getMergeValues(Ops, DL);
1427 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1428 EVT ValTy = Op.getValueType();
1429 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1430 unsigned Align = CPN->getAlignment();
1431 bool IsPositionIndependent = isPositionIndependent();
1432 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1434 unsigned Offset = 0;
1436 if (CPN->isMachineConstantPoolEntry())
1437 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1440 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1443 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1444 "Inconsistent target flag encountered");
1446 if (IsPositionIndependent)
1447 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1448 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1452 HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1453 EVT VT = Op.getValueType();
1454 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1455 if (isPositionIndependent()) {
1456 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1457 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1460 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1461 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1465 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1466 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1467 MachineFunction &MF = DAG.getMachineFunction();
1468 MachineFrameInfo &MFI = MF.getFrameInfo();
1469 MFI.setReturnAddressIsTaken(true);
1471 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1474 EVT VT = Op.getValueType();
1476 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1478 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1479 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1480 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1481 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1482 MachinePointerInfo());
1485 // Return LR, which contains the return address. Mark it an implicit live-in.
1486 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1487 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1491 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1492 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1493 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1494 MFI.setFrameAddressIsTaken(true);
1496 EVT VT = Op.getValueType();
1498 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1499 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1500 HRI.getFrameRegister(), VT);
1502 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1503 MachinePointerInfo());
1508 HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1510 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1514 HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1516 auto *GAN = cast<GlobalAddressSDNode>(Op);
1517 auto PtrVT = getPointerTy(DAG.getDataLayout());
1518 auto *GV = GAN->getGlobal();
1519 int64_t Offset = GAN->getOffset();
1521 auto &HLOF = *HTM.getObjFileLowering();
1522 Reloc::Model RM = HTM.getRelocationModel();
1524 if (RM == Reloc::Static) {
1525 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1526 const GlobalObject *GO = GV->getBaseObject();
1527 if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1528 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1529 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1532 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1534 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1535 HexagonII::MO_PCREL);
1536 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1540 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1541 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1542 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1543 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1546 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1548 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1549 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1551 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1553 Reloc::Model RM = HTM.getRelocationModel();
1554 if (RM == Reloc::Static) {
1555 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1556 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1559 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1560 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1564 HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1566 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1567 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME, PtrVT,
1568 HexagonII::MO_PCREL);
1569 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1573 HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
1574 GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg,
1575 unsigned char OperandFlags) const {
1576 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1577 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1579 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1580 GA->getValueType(0),
1583 // Create Operands for the call.The Operands should have the following:
1585 // 2. Callee which in this case is the Global address value.
1586 // 3. Registers live into the call.In this case its R0, as we
1587 // have just one argument to be passed.
1588 // 4. InFlag if there is any.
1589 // Note: The order is important.
1592 SDValue Ops[] = { Chain, TGA,
1593 DAG.getRegister(Hexagon::R0, PtrVT), *InFlag };
1594 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1596 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT)};
1597 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1600 // Inform MFI that function has calls.
1601 MFI.setAdjustsStack(true);
1603 SDValue Flag = Chain.getValue(1);
1604 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
1608 // Lower using the intial executable model for TLS addresses
1611 HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
1612 SelectionDAG &DAG) const {
1614 int64_t Offset = GA->getOffset();
1615 auto PtrVT = getPointerTy(DAG.getDataLayout());
1617 // Get the thread pointer.
1618 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1620 bool IsPositionIndependent = isPositionIndependent();
1622 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1624 // First generate the TLS symbol address
1625 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1628 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1630 if (IsPositionIndependent) {
1631 // Generate the GOT pointer in case of position independent code
1632 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1634 // Add the TLS Symbol address to GOT pointer.This gives
1635 // GOT relative relocation for the symbol.
1636 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1639 // Load the offset value for TLS symbol.This offset is relative to
1641 SDValue LoadOffset =
1642 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1644 // Address of the thread local variable is the add of thread
1645 // pointer and the offset of the variable.
1646 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1650 // Lower using the local executable model for TLS addresses
1653 HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
1654 SelectionDAG &DAG) const {
1656 int64_t Offset = GA->getOffset();
1657 auto PtrVT = getPointerTy(DAG.getDataLayout());
1659 // Get the thread pointer.
1660 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1661 // Generate the TLS symbol address
1662 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1663 HexagonII::MO_TPREL);
1664 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1666 // Address of the thread local variable is the add of thread
1667 // pointer and the offset of the variable.
1668 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1672 // Lower using the general dynamic model for TLS addresses
1675 HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1676 SelectionDAG &DAG) const {
1678 int64_t Offset = GA->getOffset();
1679 auto PtrVT = getPointerTy(DAG.getDataLayout());
1681 // First generate the TLS symbol address
1682 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1683 HexagonII::MO_GDGOT);
1685 // Then, generate the GOT pointer
1686 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1688 // Add the TLS symbol and the GOT pointer
1689 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1690 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1692 // Copy over the argument to R0
1694 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1695 InFlag = Chain.getValue(1);
1697 return GetDynamicTLSAddr(DAG, Chain, GA, &InFlag, PtrVT,
1698 Hexagon::R0, HexagonII::MO_GDPLT);
1702 // Lower TLS addresses.
1704 // For now for dynamic models, we only support the general dynamic model.
1707 HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1708 SelectionDAG &DAG) const {
1709 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1711 switch (HTM.getTLSModel(GA->getGlobal())) {
1712 case TLSModel::GeneralDynamic:
1713 case TLSModel::LocalDynamic:
1714 return LowerToTLSGeneralDynamicModel(GA, DAG);
1715 case TLSModel::InitialExec:
1716 return LowerToTLSInitialExecModel(GA, DAG);
1717 case TLSModel::LocalExec:
1718 return LowerToTLSLocalExecModel(GA, DAG);
1720 llvm_unreachable("Bogus TLS model");
1723 //===----------------------------------------------------------------------===//
1724 // TargetLowering Implementation
1725 //===----------------------------------------------------------------------===//
1727 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1728 const HexagonSubtarget &ST)
1729 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1731 bool IsV4 = !Subtarget.hasV5TOps();
1732 auto &HRI = *Subtarget.getRegisterInfo();
1733 bool UseHVX = Subtarget.useHVXOps();
1734 bool UseHVXSgl = Subtarget.useHVXSglOps();
1735 bool UseHVXDbl = Subtarget.useHVXDblOps();
1737 setPrefLoopAlignment(4);
1738 setPrefFunctionAlignment(4);
1739 setMinFunctionAlignment(2);
1740 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1742 setMaxAtomicSizeInBitsSupported(64);
1743 setMinCmpXchgSizeInBits(32);
1745 if (EnableHexSDNodeSched)
1746 setSchedulingPreference(Sched::VLIW);
1748 setSchedulingPreference(Sched::Source);
1750 // Limits for inline expansion of memcpy/memmove
1751 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1752 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1753 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1754 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1755 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1756 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1759 // Set up register classes.
1762 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1763 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1764 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1765 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1766 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1767 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1768 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1769 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1770 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1771 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1772 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1774 if (Subtarget.hasV5TOps()) {
1775 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1776 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1779 if (Subtarget.hasV60TOps()) {
1780 if (Subtarget.useHVXSglOps()) {
1781 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1782 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1783 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1784 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1785 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1786 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1787 addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1788 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1789 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1790 } else if (Subtarget.useHVXDblOps()) {
1791 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1792 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1793 addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1794 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1795 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1796 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1797 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1798 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1799 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1804 // Handling of scalar operations.
1806 // All operations default to "legal", except:
1807 // - indexed loads and stores (pre-/post-incremented),
1808 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1809 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1810 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1811 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1812 // which default to "expand" for at least one type.
1815 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1816 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1818 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1819 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1820 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1821 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1822 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1823 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1824 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1825 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1826 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1827 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1828 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1830 // Custom legalize GlobalAddress nodes into CONST32.
1831 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1832 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1833 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1835 // Hexagon needs to optimize cases with negative constants.
1836 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1837 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1839 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1840 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1841 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1842 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1844 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1845 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1846 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1849 setMinimumJumpTableEntries(MinimumJumpTables);
1851 setMinimumJumpTableEntries(std::numeric_limits<int>::max());
1852 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1854 // Hexagon has instructions for add/sub with carry. The problem with
1855 // modeling these instructions is that they produce 2 results: Rdd and Px.
1856 // To model the update of Px, we will have to use Defs[p0..p3] which will
1857 // cause any predicate live range to spill. So, we pretend we dont't have
1858 // these instructions.
1859 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1860 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1861 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1862 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1863 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1864 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1865 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1866 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1867 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1868 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1869 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1870 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1871 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1872 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1873 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1874 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1876 // Only add and sub that detect overflow are the saturating ones.
1877 for (MVT VT : MVT::integer_valuetypes()) {
1878 setOperationAction(ISD::UADDO, VT, Expand);
1879 setOperationAction(ISD::SADDO, VT, Expand);
1880 setOperationAction(ISD::USUBO, VT, Expand);
1881 setOperationAction(ISD::SSUBO, VT, Expand);
1884 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1885 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1886 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1887 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1889 // In V5, popcount can count # of 1s in i64 but returns i32.
1890 // On V4 it will be expanded (set later).
1891 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1892 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1893 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1894 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1896 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1897 // operation. There is a pattern that will match i64 mul and transform it
1898 // to a series of instructions.
1899 setOperationAction(ISD::MUL, MVT::i64, Expand);
1901 for (unsigned IntExpOp :
1902 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1903 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1904 ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1905 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1906 setOperationAction(IntExpOp, MVT::i32, Expand);
1907 setOperationAction(IntExpOp, MVT::i64, Expand);
1910 for (unsigned FPExpOp :
1911 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1912 ISD::FPOW, ISD::FCOPYSIGN}) {
1913 setOperationAction(FPExpOp, MVT::f32, Expand);
1914 setOperationAction(FPExpOp, MVT::f64, Expand);
1917 // No extending loads from i32.
1918 for (MVT VT : MVT::integer_valuetypes()) {
1919 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1920 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1921 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1923 // Turn FP truncstore into trunc + store.
1924 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1925 // Turn FP extload into load/fpextend.
1926 for (MVT VT : MVT::fp_valuetypes())
1927 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1929 // Expand BR_CC and SELECT_CC for all integer and fp types.
1930 for (MVT VT : MVT::integer_valuetypes()) {
1931 setOperationAction(ISD::BR_CC, VT, Expand);
1932 setOperationAction(ISD::SELECT_CC, VT, Expand);
1934 for (MVT VT : MVT::fp_valuetypes()) {
1935 setOperationAction(ISD::BR_CC, VT, Expand);
1936 setOperationAction(ISD::SELECT_CC, VT, Expand);
1938 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1941 // Handling of vector operations.
1944 // Custom lower v4i16 load only. Let v4i16 store to be
1945 // promoted for now.
1946 promoteLdStType(MVT::v4i8, MVT::i32);
1947 promoteLdStType(MVT::v2i16, MVT::i32);
1948 promoteLdStType(MVT::v8i8, MVT::i64);
1949 promoteLdStType(MVT::v2i32, MVT::i64);
1951 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1952 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1953 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1954 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1956 // Set the action for vector operations to "expand", then override it with
1957 // either "custom" or "legal" for specific cases.
1958 static const unsigned VectExpOps[] = {
1959 // Integer arithmetic:
1960 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1961 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1962 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1963 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1965 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1966 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
1967 // Floating point arithmetic/math functions:
1968 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1969 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1970 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1971 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1972 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1973 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1975 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
1977 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1978 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1979 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1980 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1983 for (MVT VT : MVT::vector_valuetypes()) {
1984 for (unsigned VectExpOp : VectExpOps)
1985 setOperationAction(VectExpOp, VT, Expand);
1987 // Expand all extending loads and truncating stores:
1988 for (MVT TargetVT : MVT::vector_valuetypes()) {
1991 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1992 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1993 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1994 setTruncStoreAction(VT, TargetVT, Expand);
1997 // Normalize all inputs to SELECT to be vectors of i32.
1998 if (VT.getVectorElementType() != MVT::i32) {
1999 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
2000 setOperationAction(ISD::SELECT, VT, Promote);
2001 AddPromotedToType(ISD::SELECT, VT, VT32);
2003 setOperationAction(ISD::SRA, VT, Custom);
2004 setOperationAction(ISD::SHL, VT, Custom);
2005 setOperationAction(ISD::SRL, VT, Custom);
2008 // Types natively supported:
2009 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
2010 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
2011 MVT::v2i32, MVT::v1i64}) {
2012 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
2013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
2014 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2015 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
2016 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2017 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
2019 setOperationAction(ISD::ADD, NativeVT, Legal);
2020 setOperationAction(ISD::SUB, NativeVT, Legal);
2021 setOperationAction(ISD::MUL, NativeVT, Legal);
2022 setOperationAction(ISD::AND, NativeVT, Legal);
2023 setOperationAction(ISD::OR, NativeVT, Legal);
2024 setOperationAction(ISD::XOR, NativeVT, Legal);
2027 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2028 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
2029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
2030 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
2034 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
2035 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
2036 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
2037 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
2038 // We try to generate the vpack{e/o} instructions. If we fail
2039 // we fall back upon ExpandOp.
2040 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
2041 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
2042 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
2043 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
2044 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
2045 } else if (UseHVXDbl) {
2046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
2047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
2048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
2049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
2050 // We try to generate the vpack{e/o} instructions. If we fail
2051 // we fall back upon ExpandOp.
2052 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
2053 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
2054 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
2055 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v128i8, Custom);
2056 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i16, Custom);
2057 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
2059 llvm_unreachable("Unrecognized HVX mode");
2062 // Subtarget-specific operation actions.
2064 if (Subtarget.hasV5TOps()) {
2065 setOperationAction(ISD::FMA, MVT::f64, Expand);
2066 setOperationAction(ISD::FADD, MVT::f64, Expand);
2067 setOperationAction(ISD::FSUB, MVT::f64, Expand);
2068 setOperationAction(ISD::FMUL, MVT::f64, Expand);
2070 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
2071 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
2073 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
2074 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
2075 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
2076 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
2077 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
2078 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
2079 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
2080 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
2081 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
2082 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
2083 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
2084 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
2086 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
2087 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
2088 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
2089 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
2090 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
2091 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
2092 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
2093 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
2094 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
2096 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
2097 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
2098 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
2099 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
2101 // Expand these operations for both f32 and f64:
2102 for (unsigned FPExpOpV4 :
2103 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
2104 setOperationAction(FPExpOpV4, MVT::f32, Expand);
2105 setOperationAction(FPExpOpV4, MVT::f64, Expand);
2108 for (ISD::CondCode FPExpCCV4 :
2109 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
2110 ISD::SETUO, ISD::SETO}) {
2111 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2112 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2116 // Handling of indexed loads/stores: default is "expand".
2118 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2119 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2120 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2124 for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
2125 MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
2126 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2127 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2129 } else if (UseHVXDbl) {
2130 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
2131 MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
2132 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2133 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2137 computeRegisterProperties(&HRI);
2140 // Library calls for unsupported operations
2142 bool FastMath = EnableFastMath;
2144 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2145 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2146 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2147 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2148 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2149 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2150 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2151 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2153 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2154 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2155 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2156 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2157 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2158 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2161 // Handle single-precision floating point operations on V4.
2163 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2164 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2165 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2166 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2167 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2168 // Double-precision compares.
2169 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2170 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2172 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2173 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2174 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2175 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2176 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2177 // Double-precision compares.
2178 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2179 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2183 // This is the only fast library function for sqrtd.
2185 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2187 // Prefix is: nothing for "slow-math",
2188 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2189 // (actually, keep fast-math and fast-math2 separate for now)
2191 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2192 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2193 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2194 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2195 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2196 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2198 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2199 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2200 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2201 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2202 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2205 if (Subtarget.hasV5TOps()) {
2207 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2209 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2212 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2213 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2214 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2215 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2216 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2217 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2218 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2219 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2220 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2221 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2222 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2223 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2224 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2225 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2227 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2228 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2229 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2230 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2231 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2232 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2233 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2234 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2235 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2236 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2237 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2238 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2239 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2240 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2241 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2244 // These cause problems when the shift amount is non-constant.
2245 setLibcallName(RTLIB::SHL_I128, nullptr);
2246 setLibcallName(RTLIB::SRL_I128, nullptr);
2247 setLibcallName(RTLIB::SRA_I128, nullptr);
2250 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2251 switch ((HexagonISD::NodeType)Opcode) {
2252 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2253 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2254 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2255 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2256 case HexagonISD::CALL: return "HexagonISD::CALL";
2257 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2258 case HexagonISD::CALLR: return "HexagonISD::CALLR";
2259 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2260 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2261 case HexagonISD::CONST32: return "HexagonISD::CONST32";
2262 case HexagonISD::CP: return "HexagonISD::CP";
2263 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2264 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2265 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2266 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2267 case HexagonISD::INSERT: return "HexagonISD::INSERT";
2268 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2269 case HexagonISD::JT: return "HexagonISD::JT";
2270 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2271 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
2272 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2273 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
2274 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
2275 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
2276 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
2277 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2278 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
2279 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
2280 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
2281 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
2282 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
2283 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
2284 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
2285 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
2286 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
2287 case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2288 case HexagonISD::VPACK: return "HexagonISD::VPACK";
2289 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
2290 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
2291 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
2292 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
2293 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
2294 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
2295 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
2296 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
2297 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
2298 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
2299 case HexagonISD::OP_END: break;
2304 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
2305 EVT MTy1 = EVT::getEVT(Ty1);
2306 EVT MTy2 = EVT::getEVT(Ty2);
2307 if (!MTy1.isSimple() || !MTy2.isSimple())
2309 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2312 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
2313 if (!VT1.isSimple() || !VT2.isSimple())
2315 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2318 bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
2319 return isOperationLegalOrCustom(ISD::FMA, VT);
2322 // Should we expand the build vector with shuffles?
2323 bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
2324 unsigned DefinedValues) const {
2325 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2326 EVT EltVT = VT.getVectorElementType();
2327 int EltBits = EltVT.getSizeInBits();
2328 if ((EltBits != 8) && (EltBits != 16))
2331 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2334 static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
2335 int even_start = -2;
2337 size_t mask_len = Mask.size();
2338 for (auto idx : Mask) {
2339 if ((idx - even_start) == 2)
2344 if (even_start == (int)(mask_len * 2) - 2)
2345 return StridedLoadKind::Even;
2346 for (auto idx : Mask) {
2347 if ((idx - odd_start) == 2)
2352 if (odd_start == (int)(mask_len * 2) - 1)
2353 return StridedLoadKind::Odd;
2355 return StridedLoadKind::NoPattern;
2358 bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
2360 if (Subtarget.useHVXOps())
2361 return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2365 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2366 // to select data from, V3 is the permutation.
2368 HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
2370 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2371 SDValue V1 = Op.getOperand(0);
2372 SDValue V2 = Op.getOperand(1);
2374 EVT VT = Op.getValueType();
2375 bool UseHVX = Subtarget.useHVXOps();
2380 if (SVN->isSplat()) {
2381 int Lane = SVN->getSplatIndex();
2382 if (Lane == -1) Lane = 0;
2384 // Test if V1 is a SCALAR_TO_VECTOR.
2385 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2386 return createSplat(DAG, dl, VT, V1.getOperand(0));
2388 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2389 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2391 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2392 !isa<ConstantSDNode>(V1.getOperand(0))) {
2393 bool IsScalarToVector = true;
2394 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2395 if (!V1.getOperand(i).isUndef()) {
2396 IsScalarToVector = false;
2400 if (IsScalarToVector)
2401 return createSplat(DAG, dl, VT, V1.getOperand(0));
2403 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
2407 ArrayRef<int> Mask = SVN->getMask();
2408 size_t MaskLen = Mask.size();
2409 int ElemSizeInBits = VT.getScalarSizeInBits();
2410 if ((Subtarget.useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
2411 (Subtarget.useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
2412 // Return 1 for odd and 2 of even
2413 StridedLoadKind Pattern = isStridedLoad(Mask);
2415 if (Pattern == StridedLoadKind::NoPattern)
2418 SDValue Vec0 = Op.getOperand(0);
2419 SDValue Vec1 = Op.getOperand(1);
2420 SDValue StridePattern = DAG.getConstant(Pattern, dl, MVT::i32);
2421 SDValue Ops[] = { Vec1, Vec0, StridePattern };
2422 return DAG.getNode(HexagonISD::VPACK, dl, VT, Ops);
2424 // We used to assert in the "else" part here, but that is bad for Halide
2425 // Halide creates intermediate double registers by interleaving two
2426 // concatenated vector registers. The interleaving requires vector_shuffle
2427 // nodes and we shouldn't barf on a double register result of a
2428 // vector_shuffle because it is most likely an intermediate result.
2430 // FIXME: We need to support more general vector shuffles. See
2431 // below the comment from the ARM backend that deals in the general
2432 // case with the vector shuffles. For now, let expand handle these.
2435 // If the shuffle is not directly supported and it has 4 elements, use
2436 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2439 // If BUILD_VECTOR has same base element repeated several times,
2441 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
2442 unsigned NElts = BVN->getNumOperands();
2443 SDValue V0 = BVN->getOperand(0);
2445 for (unsigned i = 1, e = NElts; i != e; ++i) {
2446 if (BVN->getOperand(i) != V0)
2452 // Lower a vector shift. Try to convert
2453 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2454 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2456 HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
2457 BuildVectorSDNode *BVN = nullptr;
2458 SDValue V1 = Op.getOperand(0);
2459 SDValue V2 = Op.getOperand(1);
2462 EVT VT = Op.getValueType();
2464 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2465 isCommonSplatElement(BVN))
2467 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2468 isCommonSplatElement(BVN))
2473 SDValue CommonSplat = BVN->getOperand(0);
2476 if (VT.getSimpleVT() == MVT::v4i16) {
2477 switch (Op.getOpcode()) {
2479 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
2482 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
2485 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
2490 } else if (VT.getSimpleVT() == MVT::v2i32) {
2491 switch (Op.getOpcode()) {
2493 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
2496 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
2499 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
2508 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2512 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2513 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2515 EVT VT = Op.getValueType();
2517 unsigned Size = VT.getSizeInBits();
2519 // Only handle vectors of 64 bits or shorter.
2523 APInt APSplatBits, APSplatUndef;
2524 unsigned SplatBitSize;
2526 unsigned NElts = BVN->getNumOperands();
2528 // Try to generate a SPLAT instruction.
2529 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2530 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2531 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2532 unsigned SplatBits = APSplatBits.getZExtValue();
2533 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2534 (32 - SplatBitSize));
2535 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
2538 // Try to generate COMBINE to build v2i32 vectors.
2539 if (VT.getSimpleVT() == MVT::v2i32) {
2540 SDValue V0 = BVN->getOperand(0);
2541 SDValue V1 = BVN->getOperand(1);
2544 V0 = DAG.getConstant(0, dl, MVT::i32);
2546 V1 = DAG.getConstant(0, dl, MVT::i32);
2548 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2549 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2550 // If the element isn't a constant, it is in a register:
2551 // generate a COMBINE Register Register instruction.
2553 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2555 // If one of the operands is an 8 bit integer constant, generate
2556 // a COMBINE Immediate Immediate instruction.
2557 if (isInt<8>(C0->getSExtValue()) ||
2558 isInt<8>(C1->getSExtValue()))
2559 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2562 // Try to generate a S2_packhl to build v2i16 vectors.
2563 if (VT.getSimpleVT() == MVT::v2i16) {
2564 for (unsigned i = 0, e = NElts; i != e; ++i) {
2565 if (BVN->getOperand(i).isUndef())
2567 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2568 // If the element isn't a constant, it is in a register:
2569 // generate a S2_packhl instruction.
2571 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2572 BVN->getOperand(1), BVN->getOperand(0));
2574 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2580 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2581 // and insert_vector_elt for all the other cases.
2583 unsigned EltSize = Size / NElts;
2585 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2586 bool HasNonConstantElements = false;
2588 for (unsigned i = 0, e = NElts; i != e; ++i) {
2589 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2590 // combine, const64, etc. are Big Endian.
2591 unsigned OpIdx = NElts - i - 1;
2592 SDValue Operand = BVN->getOperand(OpIdx);
2593 if (Operand.isUndef())
2597 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2598 Val = Cst->getSExtValue();
2600 HasNonConstantElements = true;
2603 Res = (Res << EltSize) | Val;
2610 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2612 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2614 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2615 // ConstVal, the constant part of the vector.
2616 if (HasNonConstantElements) {
2617 EVT EltVT = VT.getVectorElementType();
2618 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2619 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2620 DAG.getConstant(32, dl, MVT::i64));
2622 for (unsigned i = 0, e = NElts; i != e; ++i) {
2623 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2625 unsigned OpIdx = NElts - i - 1;
2626 SDValue Operand = BVN->getOperand(OpIdx);
2627 if (isa<ConstantSDNode>(Operand))
2628 // This operand is already in ConstVal.
2631 if (VT.getSizeInBits() == 64 &&
2632 Operand.getValueSizeInBits() == 32) {
2633 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2634 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2637 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2638 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2639 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2640 const SDValue Ops[] = {ConstVal, Operand, Combined};
2642 if (VT.getSizeInBits() == 32)
2643 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2645 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2649 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2653 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2654 SelectionDAG &DAG) const {
2656 bool UseHVX = Subtarget.useHVXOps();
2657 EVT VT = Op.getValueType();
2658 unsigned NElts = Op.getNumOperands();
2659 SDValue Vec0 = Op.getOperand(0);
2660 EVT VecVT = Vec0.getValueType();
2661 unsigned Width = VecVT.getSizeInBits();
2664 MVT ST = VecVT.getSimpleVT();
2665 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2666 // into a single v8i8.
2667 if (ST == MVT::v2i16 || ST == MVT::v4i8)
2668 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2671 assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||
2672 (Width == 128*8 && Subtarget.useHVXDblOps()));
2673 SDValue Vec1 = Op.getOperand(1);
2674 MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
2675 MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
2676 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2677 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2678 SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2679 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2683 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2686 SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2687 SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2688 SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2689 // Create the "width" part of the argument to insert_rp/insertp_rp.
2690 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2693 for (unsigned i = 0, e = NElts; i != e; ++i) {
2694 unsigned N = NElts-i-1;
2695 SDValue OpN = Op.getOperand(N);
2697 if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2698 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2699 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2701 SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2702 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2703 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2704 if (VT.getSizeInBits() == 32)
2705 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2706 else if (VT.getSizeInBits() == 64)
2707 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2712 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2716 HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
2717 SelectionDAG &DAG) const {
2718 EVT VT = Op.getOperand(0).getValueType();
2720 bool UseHVX = Subtarget.useHVXOps();
2721 bool UseHVXSgl = Subtarget.useHVXSglOps();
2724 if (!VT.isVector() || !UseHVX)
2727 EVT ResVT = Op.getValueType();
2728 unsigned ResSize = ResVT.getSizeInBits();
2729 unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
2730 unsigned OpSize = VT.getSizeInBits();
2732 // We deal only with cases where the result is the vector size
2733 // and the vector operand is a double register.
2734 if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2735 !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2738 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2741 unsigned Val = Cst->getZExtValue();
2743 // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2745 SDValue Vec = Op.getOperand(0);
2746 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2749 if (ResVT.getVectorNumElements() == Val) {
2750 SDValue Vec = Op.getOperand(0);
2751 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2758 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2759 SelectionDAG &DAG) const {
2760 // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2761 // be able to simplify it to an EXTRACT_SUBREG.
2762 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2763 isHvxVectorType(Op.getValueType().getSimpleVT()))
2764 return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2766 EVT VT = Op.getValueType();
2767 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2769 SDValue Idx = Op.getOperand(1);
2770 SDValue Vec = Op.getOperand(0);
2771 EVT VecVT = Vec.getValueType();
2772 EVT EltVT = VecVT.getVectorElementType();
2773 int EltSize = EltVT.getSizeInBits();
2774 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2775 EltSize : VTN * EltSize, dl, MVT::i64);
2777 // Constant element number.
2778 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2779 uint64_t X = CI->getZExtValue();
2780 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2781 const SDValue Ops[] = {Vec, Width, Offset};
2783 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2784 assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2787 MVT SVT = VecVT.getSimpleVT();
2788 uint64_t W = CW->getZExtValue();
2791 // Translate this node into EXTRACT_SUBREG.
2792 unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
2795 Subreg = Hexagon::isub_lo;
2796 else if (SVT == MVT::v2i32 && X == 1)
2797 Subreg = Hexagon::isub_hi;
2798 else if (SVT == MVT::v4i16 && X == 2)
2799 Subreg = Hexagon::isub_hi;
2800 else if (SVT == MVT::v8i8 && X == 4)
2801 Subreg = Hexagon::isub_hi;
2803 llvm_unreachable("Bad offset");
2804 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2806 } else if (SVT.getSizeInBits() == 32) {
2807 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2808 } else if (SVT.getSizeInBits() == 64) {
2809 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2810 if (VT.getSizeInBits() == 32)
2811 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2815 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2818 // Variable element number.
2819 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2820 DAG.getConstant(EltSize, dl, MVT::i32));
2821 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2822 DAG.getConstant(32, dl, MVT::i64));
2823 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2825 const SDValue Ops[] = {Vec, Combined};
2828 if (VecVT.getSizeInBits() == 32) {
2829 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2831 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2832 if (VT.getSizeInBits() == 32)
2833 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2835 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2839 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2840 SelectionDAG &DAG) const {
2841 EVT VT = Op.getValueType();
2842 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2844 SDValue Vec = Op.getOperand(0);
2845 SDValue Val = Op.getOperand(1);
2846 SDValue Idx = Op.getOperand(2);
2847 EVT VecVT = Vec.getValueType();
2848 EVT EltVT = VecVT.getVectorElementType();
2849 int EltSize = EltVT.getSizeInBits();
2850 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2851 EltSize : VTN * EltSize, dl, MVT::i64);
2853 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2854 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2855 const SDValue Ops[] = {Vec, Val, Width, Offset};
2858 if (VT.getSizeInBits() == 32)
2859 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2860 else if (VT.getSizeInBits() == 64)
2861 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2865 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2868 // Variable element number.
2869 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2870 DAG.getConstant(EltSize, dl, MVT::i32));
2871 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2872 DAG.getConstant(32, dl, MVT::i64));
2873 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2875 if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2876 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2877 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2880 const SDValue Ops[] = {Vec, Val, Combined};
2883 if (VT.getSizeInBits() == 32)
2884 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2885 else if (VT.getSizeInBits() == 64)
2886 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2890 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2894 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2895 // Assuming the caller does not have either a signext or zeroext modifier, and
2896 // only one value is accepted, any reasonable truncation is allowed.
2897 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2900 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2901 // fragile at the moment: any support for multiple value returns would be
2902 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2903 return Ty1->getPrimitiveSizeInBits() <= 32;
2907 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2908 SDValue Chain = Op.getOperand(0);
2909 SDValue Offset = Op.getOperand(1);
2910 SDValue Handler = Op.getOperand(2);
2912 auto PtrVT = getPointerTy(DAG.getDataLayout());
2914 // Mark function as containing a call to EH_RETURN.
2915 HexagonMachineFunctionInfo *FuncInfo =
2916 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2917 FuncInfo->setHasEHReturn();
2919 unsigned OffsetReg = Hexagon::R28;
2922 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2923 DAG.getIntPtrConstant(4, dl));
2924 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2925 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2927 // Not needed we already use it as explict input to EH_RETURN.
2928 // MF.getRegInfo().addLiveOut(OffsetReg);
2930 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2934 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2935 unsigned Opc = Op.getOpcode();
2939 Op.getNode()->dumpr(&DAG);
2940 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2941 errs() << "Check for a non-legal type in this operation\n";
2943 llvm_unreachable("Should not custom lower this!");
2944 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2945 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2946 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2947 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2948 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2949 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2950 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2953 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2954 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2955 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2956 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2957 // Frame & Return address. Currently unimplemented.
2958 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2959 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2960 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2961 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2962 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2963 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2964 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2965 case ISD::VASTART: return LowerVASTART(Op, DAG);
2966 // Custom lower some vector loads.
2967 case ISD::LOAD: return LowerLOAD(Op, DAG);
2968 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2969 case ISD::SETCC: return LowerSETCC(Op, DAG);
2970 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2971 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2972 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2973 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2974 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2975 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2979 /// Returns relocation base for the given PIC jumptable.
2981 HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2982 SelectionDAG &DAG) const {
2983 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2984 EVT VT = Table.getValueType();
2985 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
2986 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2989 //===----------------------------------------------------------------------===//
2990 // Inline Assembly Support
2991 //===----------------------------------------------------------------------===//
2993 TargetLowering::ConstraintType
2994 HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
2995 if (Constraint.size() == 1) {
2996 switch (Constraint[0]) {
2999 if (Subtarget.useHVXOps())
3004 return TargetLowering::getConstraintType(Constraint);
3007 std::pair<unsigned, const TargetRegisterClass*>
3008 HexagonTargetLowering::getRegForInlineAsmConstraint(
3009 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3010 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
3012 if (Constraint.size() == 1) {
3013 switch (Constraint[0]) {
3015 switch (VT.SimpleTy) {
3017 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3023 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
3026 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
3029 switch (VT.SimpleTy) {
3031 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3038 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
3041 switch (VT.SimpleTy) {
3043 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3048 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
3053 if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
3054 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
3055 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
3060 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
3064 llvm_unreachable("Unknown asm register class");
3068 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3071 /// isFPImmLegal - Returns true if the target can instruction select the
3072 /// specified FP immediate natively. If false, the legalizer will
3073 /// materialize the FP immediate as a load from a constant pool.
3074 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3075 return Subtarget.hasV5TOps();
3078 /// isLegalAddressingMode - Return true if the addressing mode represented by
3079 /// AM is legal for this target, for a load/store of the specified type.
3080 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3081 const AddrMode &AM, Type *Ty,
3082 unsigned AS) const {
3083 if (Ty->isSized()) {
3084 // When LSR detects uses of the same base address to access different
3085 // types (e.g. unions), it will assume a conservative type for these
3087 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3088 // The type Ty passed here would then be "void". Skip the alignment
3089 // checks, but do not return false right away, since that confuses
3090 // LSR into crashing.
3091 unsigned A = DL.getABITypeAlignment(Ty);
3092 // The base offset must be a multiple of the alignment.
3093 if ((AM.BaseOffs % A) != 0)
3095 // The shifted offset must fit in 11 bits.
3096 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3100 // No global is ever allowed as a base.
3104 int Scale = AM.Scale;
3108 case 0: // No scale reg, "r+i", "r", or just "i".
3110 default: // No scaled addressing mode.
3116 /// Return true if folding a constant offset with the given GlobalAddress is
3117 /// legal. It is frequently not legal in PIC relocation models.
3118 bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
3120 return HTM.getRelocationModel() == Reloc::Static;
3123 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3124 /// icmp immediate, that is the target has icmp instructions which can compare
3125 /// a register against the immediate without having to materialize the
3126 /// immediate into a register.
3127 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3128 return Imm >= -512 && Imm <= 511;
3131 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3132 /// for tail call optimization. Targets which want to do tail call
3133 /// optimization should implement this function.
3134 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
3136 CallingConv::ID CalleeCC,
3138 bool isCalleeStructRet,
3139 bool isCallerStructRet,
3140 const SmallVectorImpl<ISD::OutputArg> &Outs,
3141 const SmallVectorImpl<SDValue> &OutVals,
3142 const SmallVectorImpl<ISD::InputArg> &Ins,
3143 SelectionDAG& DAG) const {
3144 const Function *CallerF = DAG.getMachineFunction().getFunction();
3145 CallingConv::ID CallerCC = CallerF->getCallingConv();
3146 bool CCMatch = CallerCC == CalleeCC;
3148 // ***************************************************************************
3149 // Look for obvious safe cases to perform tail call optimization that do not
3150 // require ABI changes.
3151 // ***************************************************************************
3153 // If this is a tail call via a function pointer, then don't do it!
3154 if (!isa<GlobalAddressSDNode>(Callee) &&
3155 !isa<ExternalSymbolSDNode>(Callee)) {
3159 // Do not optimize if the calling conventions do not match and the conventions
3160 // used are not C or Fast.
3162 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3163 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3164 // If R & E, then ok.
3169 // Do not tail call optimize vararg calls.
3173 // Also avoid tail call optimization if either caller or callee uses struct
3174 // return semantics.
3175 if (isCalleeStructRet || isCallerStructRet)
3178 // In addition to the cases above, we also disable Tail Call Optimization if
3179 // the calling convention code that at least one outgoing argument needs to
3180 // go on the stack. We cannot check that here because at this point that
3181 // information is not available.
3185 /// Returns the target specific optimal type for load and store operations as
3186 /// a result of memset, memcpy, and memmove lowering.
3188 /// If DstAlign is zero that means it's safe to destination alignment can
3189 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3190 /// a need to check it against alignment requirement, probably because the
3191 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3192 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3193 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3194 /// does not need to be loaded. It returns EVT::Other if the type should be
3195 /// determined using generic target-independent logic.
3196 EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
3197 unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3198 bool MemcpyStrSrc, MachineFunction &MF) const {
3200 auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3201 return (GivenA % MinA) == 0;
3204 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3206 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3208 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3214 bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
3215 unsigned AS, unsigned Align, bool *Fast) const {
3219 switch (VT.getSimpleVT().SimpleTy) {
3239 std::pair<const TargetRegisterClass*, uint8_t>
3240 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3242 const TargetRegisterClass *RRC = nullptr;
3245 switch (VT.SimpleTy) {
3247 return TargetLowering::findRepresentativeClass(TRI, VT);
3252 RRC = &Hexagon::VectorRegsRegClass;
3258 if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3259 Subtarget.useHVXDblOps())
3260 RRC = &Hexagon::VectorRegs128BRegClass;
3262 RRC = &Hexagon::VecDblRegsRegClass;
3268 RRC = &Hexagon::VecDblRegs128BRegClass;
3271 return std::make_pair(RRC, Cost);
3274 Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
3275 AtomicOrdering Ord) const {
3276 BasicBlock *BB = Builder.GetInsertBlock();
3277 Module *M = BB->getParent()->getParent();
3278 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3279 unsigned SZ = Ty->getPrimitiveSizeInBits();
3280 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3281 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3282 : Intrinsic::hexagon_L4_loadd_locked;
3283 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3284 return Builder.CreateCall(Fn, Addr, "larx");
3287 /// Perform a store-conditional operation to Addr. Return the status of the
3288 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3289 Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
3290 Value *Val, Value *Addr, AtomicOrdering Ord) const {
3291 BasicBlock *BB = Builder.GetInsertBlock();
3292 Module *M = BB->getParent()->getParent();
3293 Type *Ty = Val->getType();
3294 unsigned SZ = Ty->getPrimitiveSizeInBits();
3295 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3296 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3297 : Intrinsic::hexagon_S4_stored_locked;
3298 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3299 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3300 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3301 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3305 TargetLowering::AtomicExpansionKind
3306 HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
3307 // Do not expand loads and stores that don't exceed 64 bits.
3308 return LI->getType()->getPrimitiveSizeInBits() > 64
3309 ? AtomicExpansionKind::LLOnly
3310 : AtomicExpansionKind::None;
3313 bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
3314 // Do not expand loads and stores that don't exceed 64 bits.
3315 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3318 bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
3319 AtomicCmpXchgInst *AI) const {
3320 const DataLayout &DL = AI->getModule()->getDataLayout();
3321 unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3322 return Size >= 4 && Size <= 8;