1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
40 CMPICC, // Compare two GPR operands, set icc.
41 CMPFCC, // Compare two FP operands, set fcc.
42 BRICC, // Branch to dest on icc condition
43 BRFCC, // Branch to dest on fcc condition
44 SELECT_ICC, // Select between two values using the current ICC flags.
45 SELECT_FCC, // Select between two values using the current FCC flags.
47 Hi, Lo, // Hi/Lo operations, typically on a global address.
49 FTOI, // FP to Int within a FP register.
50 ITOF, // Int to FP within a FP register.
52 CALL, // A call instruction.
53 RET_FLAG, // Return with a flag operand.
55 BARRIER, // Memory barrier
77 class HexagonTargetLowering : public TargetLowering {
78 int VarArgsFrameOffset; // Frame offset to start of varargs area.
80 bool CanReturnSmallStruct(const Function* CalleeFn,
81 unsigned& RetSize) const;
84 const TargetMachine &TM;
85 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
87 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
88 /// for tail call optimization. Targets which want to do tail call
89 /// optimization should implement this function.
91 IsEligibleForTailCallOptimization(SDValue Callee,
92 CallingConv::ID CalleeCC,
94 bool isCalleeStructRet,
95 bool isCallerStructRet,
97 SmallVectorImpl<ISD::OutputArg> &Outs,
98 const SmallVectorImpl<SDValue> &OutVals,
99 const SmallVectorImpl<ISD::InputArg> &Ins,
100 SelectionDAG& DAG) const;
102 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
103 bool isTruncateFree(EVT VT1, EVT VT2) const override;
105 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
109 const char *getTargetNodeName(unsigned Opcode) const override;
110 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerFormalArguments(SDValue Chain,
116 CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::InputArg> &Ins,
118 SDLoc dl, SelectionDAG &DAG,
119 SmallVectorImpl<SDValue> &InVals) const override;
120 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
124 SmallVectorImpl<SDValue> &InVals) const override;
126 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
127 CallingConv::ID CallConv, bool isVarArg,
128 const SmallVectorImpl<ISD::InputArg> &Ins,
129 SDLoc dl, SelectionDAG &DAG,
130 SmallVectorImpl<SDValue> &InVals,
131 const SmallVectorImpl<SDValue> &OutVals,
132 SDValue Callee) const;
134 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
136 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerReturn(SDValue Chain,
139 CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals,
142 SDLoc dl, SelectionDAG &DAG) const override;
145 EmitInstrWithCustomInserter(MachineInstr *MI,
146 MachineBasicBlock *BB) const override;
148 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
150 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
154 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
157 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
158 SDValue &Base, SDValue &Offset,
159 ISD::MemIndexedMode &AM,
160 SelectionDAG &DAG) const override;
162 std::pair<unsigned, const TargetRegisterClass*>
163 getRegForInlineAsmConstraint(const std::string &Constraint,
164 MVT VT) const override;
167 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
168 /// isLegalAddressingMode - Return true if the addressing mode represented
169 /// by AM is legal for this target, for a load/store of the specified type.
170 /// The type may be VoidTy, in which case only return true if the addressing
171 /// mode is legal for a load/store of any legal type.
172 /// TODO: Handle pre/postinc as well.
173 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
174 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
176 /// isLegalICmpImmediate - Return true if the specified immediate is legal
177 /// icmp immediate, that is the target has icmp instructions which can
178 /// compare a register against the immediate without having to materialize
179 /// the immediate into a register.
180 bool isLegalICmpImmediate(int64_t Imm) const override;
182 } // end namespace llvm
184 #endif // Hexagon_ISELLOWERING_H