1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/ISDOpcodes.h"
21 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/InlineAsm.h"
26 #include "llvm/Target/TargetLowering.h"
32 namespace HexagonISD {
34 enum NodeType : unsigned {
35 OP_BEGIN = ISD::BUILTIN_OP_END,
38 CONST32_GP, // For marking data present in GP.
41 AT_GOT, // Index in GOT.
42 AT_PCREL, // Offset relative to PC.
44 CALL, // Function call.
45 CALLnr, // Function call that does not return.
48 RET_FLAG, // Return with a flag operand.
49 BARRIER, // Memory barrier.
93 } // end namespace HexagonISD
95 class HexagonSubtarget;
97 class HexagonTargetLowering : public TargetLowering {
98 int VarArgsFrameOffset; // Frame offset to start of varargs area.
99 const HexagonTargetMachine &HTM;
100 const HexagonSubtarget &Subtarget;
102 bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
104 void promoteLdStType(MVT VT, MVT PromotedLdStVT);
107 explicit HexagonTargetLowering(const TargetMachine &TM,
108 const HexagonSubtarget &ST);
110 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
111 /// for tail call optimization. Targets which want to do tail call
112 /// optimization should implement this function.
113 bool IsEligibleForTailCallOptimization(SDValue Callee,
114 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
115 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
116 const SmallVectorImpl<SDValue> &OutVals,
117 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
119 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
120 bool isTruncateFree(EVT VT1, EVT VT2) const override;
122 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
124 /// Return true if an FMA operation is faster than a pair of mul and add
125 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
126 /// method returns true (and FMAs are legal), otherwise fmuladd is
127 /// expanded to mul + add.
128 bool isFMAFasterThanFMulAndFAdd(EVT) const override;
130 // Should we expand the build vector with shuffles?
131 bool shouldExpandBuildVectorWithShuffles(EVT VT,
132 unsigned DefinedValues) const override;
134 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
138 const char *getTargetNodeName(unsigned Opcode) const override;
139 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
152 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
153 const SmallVectorImpl<ISD::InputArg> &Ins,
154 const SDLoc &dl, SelectionDAG &DAG,
155 SmallVectorImpl<SDValue> &InVals) const override;
156 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
160 SelectionDAG &DAG) const;
161 SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
162 SelectionDAG &DAG) const;
163 SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
164 SelectionDAG &DAG) const;
165 SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
166 GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT,
167 unsigned ReturnReg, unsigned char OperandFlags) const;
168 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
171 SmallVectorImpl<SDValue> &InVals) const override;
172 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
173 CallingConv::ID CallConv, bool isVarArg,
174 const SmallVectorImpl<ISD::InputArg> &Ins,
175 const SDLoc &dl, SelectionDAG &DAG,
176 SmallVectorImpl<SDValue> &InVals,
177 const SmallVectorImpl<SDValue> &OutVals,
178 SDValue Callee) const;
180 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
181 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
182 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
183 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
184 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
185 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
186 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
189 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 const SmallVectorImpl<SDValue> &OutVals,
191 const SDLoc &dl, SelectionDAG &DAG) const override;
193 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
195 /// If a physical register, this returns the register that receives the
196 /// exception address on entry to an EH pad.
198 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
202 /// If a physical register, this returns the register that receives the
203 /// exception typeid on entry to a landing pad.
205 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
209 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
210 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
211 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
213 EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
214 EVT VT) const override {
218 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
221 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
222 SDValue &Base, SDValue &Offset,
223 ISD::MemIndexedMode &AM,
224 SelectionDAG &DAG) const override;
226 ConstraintType getConstraintType(StringRef Constraint) const override;
228 std::pair<unsigned, const TargetRegisterClass *>
229 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
230 StringRef Constraint, MVT VT) const override;
233 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
234 if (ConstraintCode == "o")
235 return InlineAsm::Constraint_o;
236 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
240 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
241 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
242 /// isLegalAddressingMode - Return true if the addressing mode represented
243 /// by AM is legal for this target, for a load/store of the specified type.
244 /// The type may be VoidTy, in which case only return true if the addressing
245 /// mode is legal for a load/store of any legal type.
246 /// TODO: Handle pre/postinc as well.
247 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
248 Type *Ty, unsigned AS) const override;
249 /// Return true if folding a constant offset with the given GlobalAddress
250 /// is legal. It is frequently not legal in PIC relocation models.
251 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
253 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
255 /// isLegalICmpImmediate - Return true if the specified immediate is legal
256 /// icmp immediate, that is the target has icmp instructions which can
257 /// compare a register against the immediate without having to materialize
258 /// the immediate into a register.
259 bool isLegalICmpImmediate(int64_t Imm) const override;
261 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
262 unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
263 MachineFunction &MF) const override;
265 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
266 unsigned Align, bool *Fast) const override;
268 /// Returns relocation base for the given PIC jumptable.
269 SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
272 // Handling of atomic RMW instructions.
273 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
274 AtomicOrdering Ord) const override;
275 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
276 Value *Addr, AtomicOrdering Ord) const override;
277 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
278 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
279 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
282 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
283 return AtomicExpansionKind::LLSC;
287 std::pair<const TargetRegisterClass*, uint8_t>
288 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
292 } // end namespace llvm
294 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H