1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Addressing modes for load/store instructions
11 class AddrModeType<bits<3> value> {
12 bits<3> Value = value;
15 def NoAddrMode : AddrModeType<0>; // No addressing mode
16 def Absolute : AddrModeType<1>; // Absolute addressing mode
17 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
18 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
19 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
20 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
21 def PostInc : AddrModeType<6>; // Post increment addressing mode
23 class MemAccessSize<bits<4> value> {
24 bits<4> Value = value;
27 // These numbers must match the MemAccessSize enumeration values in
29 def NoMemAccess : MemAccessSize<0>;
30 def ByteAccess : MemAccessSize<1>;
31 def HalfWordAccess : MemAccessSize<2>;
32 def WordAccess : MemAccessSize<3>;
33 def DoubleWordAccess : MemAccessSize<4>;
34 def HVXVectorAccess : MemAccessSize<5>;
37 //===----------------------------------------------------------------------===//
38 // Instruction Class Declaration +
39 //===----------------------------------------------------------------------===//
42 field bits<32> Inst = ?; // Default to an invalid insn.
43 bits<4> IClass = 0; // ICLASS
46 let Inst{31-28} = IClass;
49 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
50 string cstr, InstrItinClass itin, IType type>
52 let Namespace = "Hexagon";
54 dag OutOperandList = outs;
55 dag InOperandList = ins;
56 let AsmString = asmstr;
57 let Pattern = pattern;
58 let Constraints = cstr;
62 // SoftFail is a field the disassembler can use to provide a way for
63 // instructions to not match without killing the whole decode process. It is
64 // mainly used for ARM, but Tablegen expects this field to exist or it fails
65 // to build the decode table.
66 field bits<32> SoftFail = 0;
68 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
70 // Instruction type according to the ISA.
72 let TSFlags{5-0} = Type.Value;
74 // Solo instructions, i.e., those that cannot be in a packet with others.
76 let TSFlags{6} = isSolo;
77 // Packed only with A or X-type instructions.
79 let TSFlags{7} = isSoloAX;
80 // Restricts slot 1 to ALU-only instructions.
81 bits<1> isRestrictSlot1AOK = 0;
82 let TSFlags{8} = isRestrictSlot1AOK;
84 // Predicated instructions.
85 bits<1> isPredicated = 0;
86 let TSFlags{9} = isPredicated;
87 bits<1> isPredicatedFalse = 0;
88 let TSFlags{10} = isPredicatedFalse;
89 bits<1> isPredicatedNew = 0;
90 let TSFlags{11} = isPredicatedNew;
91 bits<1> isPredicateLate = 0;
92 let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
94 // New-value insn helper fields.
95 bits<1> isNewValue = 0;
96 let TSFlags{13} = isNewValue; // New-value consumer insn.
97 bits<1> hasNewValue = 0;
98 let TSFlags{14} = hasNewValue; // New-value producer insn.
99 bits<3> opNewValue = 0;
100 let TSFlags{17-15} = opNewValue; // New-value produced operand.
101 bits<1> isNVStorable = 0;
102 let TSFlags{18} = isNVStorable; // Store that can become new-value store.
103 bits<1> isNVStore = 0;
104 let TSFlags{19} = isNVStore; // New-value store insn.
105 bits<1> isCVLoadable = 0;
106 let TSFlags{20} = isCVLoadable; // Load that can become cur-value load.
107 bits<1> isCVLoad = 0;
108 let TSFlags{21} = isCVLoad; // Cur-value load insn.
110 // Immediate extender helper fields.
111 bits<1> isExtendable = 0;
112 let TSFlags{22} = isExtendable; // Insn may be extended.
113 bits<1> isExtended = 0;
114 let TSFlags{23} = isExtended; // Insn must be extended.
115 bits<3> opExtendable = 0;
116 let TSFlags{26-24} = opExtendable; // Which operand may be extended.
117 bits<1> isExtentSigned = 0;
118 let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
119 bits<5> opExtentBits = 0;
120 let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending.
121 bits<2> opExtentAlign = 0;
122 let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
125 let TSFlags{35} = cofMax1;
127 let TSFlags{36} = cofRelax1;
129 let TSFlags{37} = cofRelax2;
131 bit isRestrictNoSlot1Store = 0;
132 let TSFlags{38} = isRestrictNoSlot1Store;
134 // Addressing mode for load/store instructions.
135 AddrModeType addrMode = NoAddrMode;
136 let TSFlags{43-41} = addrMode.Value;
138 // Memory access size for mem access instructions (load/store)
139 MemAccessSize accessSize = NoMemAccess;
140 let TSFlags{47-44} = accessSize.Value;
143 let TSFlags {48} = isTaken; // Branch prediction.
146 let TSFlags {49} = isFP; // Floating-point.
148 bits<1> isSomeOK = 0;
149 let TSFlags {50} = isSomeOK; // Relax some grouping constraints.
151 bits<1> hasNewValue2 = 0;
152 let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
153 bits<3> opNewValue2 = 0;
154 let TSFlags{54-52} = opNewValue2; // Second New-value produced operand.
156 bits<1> isAccumulator = 0;
157 let TSFlags{55} = isAccumulator;
159 bits<1> prefersSlot3 = 0;
160 let TSFlags{56} = prefersSlot3; // Complex XU
162 bits<1> hasTmpDst = 0;
163 let TSFlags{59} = hasTmpDst; // v65 : 'fake" register VTMP is set
166 let TSFlags{61} = CVINew;
168 // Fields used for relation models.
169 bit isNonTemporal = 0;
170 string isNT = ""; // set to "true" for non-temporal vector stores.
171 string BaseOpcode = "";
172 string CextOpcode = "";
173 string PredSense = "";
174 string PNewValue = "";
175 string NValueST = ""; // Set to "true" for new-value stores.
176 string InputType = ""; // Input is "imm" or "reg" type.
177 string isFloat = "false"; // Set to "true" for the floating-point load/store.
178 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
180 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
182 let PNewValue = !if(isPredicatedNew, "new", "");
183 let NValueST = !if(isNVStore, "true", "false");
184 let isNT = !if(isNonTemporal, "true", "false");
186 let hasSideEffects = 0;
187 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
190 class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
191 InstHexagon<outs, ins, asmstr, [], "", itin, type>;
193 //===----------------------------------------------------------------------===//
194 // Instruction Classes Definitions +
195 //===----------------------------------------------------------------------===//
197 // LD Instruction Class in V2/V3/V4.
198 // Definition of the instruction class NOT CHANGED.
200 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
201 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
202 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
204 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
205 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
206 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
208 // ST Instruction Class in V2/V3 can take SLOT0 only.
209 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
210 // Definition of the instruction class CHANGED from V2/V3 to V4.
212 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
214 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
216 let isCodeGenOnly = 1, isPseudo = 1 in
217 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
218 string cstr = "", InstrItinClass itin = tc_ENDLOOP>
219 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
222 let isCodeGenOnly = 1, isPseudo = 1 in
223 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
225 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
228 let isCodeGenOnly = 1, isPseudo = 1 in
229 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
231 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
234 //===----------------------------------------------------------------------===//
235 // Instruction Classes Definitions -
236 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
239 // V4 Instruction Format Definitions +
240 //===----------------------------------------------------------------------===//
242 include "HexagonInstrFormatsV4.td"
244 //===----------------------------------------------------------------------===//
245 // V60+ Instruction Format Definitions +
246 //===----------------------------------------------------------------------===//
248 include "HexagonInstrFormatsV60.td"
249 include "HexagonInstrFormatsV65.td"