1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Addressing modes for load/store instructions
11 class AddrModeType<bits<3> value> {
12 bits<3> Value = value;
15 def NoAddrMode : AddrModeType<0>; // No addressing mode
16 def Absolute : AddrModeType<1>; // Absolute addressing mode
17 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
18 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
19 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
20 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
21 def PostInc : AddrModeType<6>; // Post increment addressing mode
23 class MemAccessSize<bits<4> value> {
24 bits<4> Value = value;
27 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
28 def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction.
29 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
30 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
31 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
32 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
33 def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
34 def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
37 //===----------------------------------------------------------------------===//
38 // Instruction Class Declaration +
39 //===----------------------------------------------------------------------===//
42 field bits<32> Inst = ?; // Default to an invalid insn.
43 bits<4> IClass = 0; // ICLASS
46 let Inst{31-28} = IClass;
49 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
50 string cstr, InstrItinClass itin, IType type>
52 let Namespace = "Hexagon";
54 dag OutOperandList = outs;
55 dag InOperandList = ins;
56 let AsmString = asmstr;
57 let Pattern = pattern;
58 let Constraints = cstr;
62 // SoftFail is a field the disassembler can use to provide a way for
63 // instructions to not match without killing the whole decode process. It is
64 // mainly used for ARM, but Tablegen expects this field to exist or it fails
65 // to build the decode table.
66 field bits<32> SoftFail = 0;
68 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
70 // Instruction type according to the ISA.
72 let TSFlags{5-0} = Type.Value;
74 // Solo instructions, i.e., those that cannot be in a packet with others.
76 let TSFlags{6} = isSolo;
77 // Packed only with A or X-type instructions.
79 let TSFlags{7} = isSoloAX;
80 // Only A-type instruction in first slot or nothing.
81 bits<1> isSoloAin1 = 0;
82 let TSFlags{8} = isSoloAin1;
84 // Predicated instructions.
85 bits<1> isPredicated = 0;
86 let TSFlags{9} = isPredicated;
87 bits<1> isPredicatedFalse = 0;
88 let TSFlags{10} = isPredicatedFalse;
89 bits<1> isPredicatedNew = 0;
90 let TSFlags{11} = isPredicatedNew;
91 bits<1> isPredicateLate = 0;
92 let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
94 // New-value insn helper fields.
95 bits<1> isNewValue = 0;
96 let TSFlags{13} = isNewValue; // New-value consumer insn.
97 bits<1> hasNewValue = 0;
98 let TSFlags{14} = hasNewValue; // New-value producer insn.
99 bits<3> opNewValue = 0;
100 let TSFlags{17-15} = opNewValue; // New-value produced operand.
101 bits<1> isNVStorable = 0;
102 let TSFlags{18} = isNVStorable; // Store that can become new-value store.
103 bits<1> isNVStore = 0;
104 let TSFlags{19} = isNVStore; // New-value store insn.
105 bits<1> isCVLoadable = 0;
106 let TSFlags{20} = isCVLoadable; // Load that can become cur-value load.
107 bits<1> isCVLoad = 0;
108 let TSFlags{21} = isCVLoad; // Cur-value load insn.
110 // Immediate extender helper fields.
111 bits<1> isExtendable = 0;
112 let TSFlags{22} = isExtendable; // Insn may be extended.
113 bits<1> isExtended = 0;
114 let TSFlags{23} = isExtended; // Insn must be extended.
115 bits<3> opExtendable = 0;
116 let TSFlags{26-24} = opExtendable; // Which operand may be extended.
117 bits<1> isExtentSigned = 0;
118 let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
119 bits<5> opExtentBits = 0;
120 let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending.
121 bits<2> opExtentAlign = 0;
122 let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
124 // Addressing mode for load/store instructions.
125 AddrModeType addrMode = NoAddrMode;
126 let TSFlags{43-41} = addrMode.Value;
128 // Memory access size for mem access instructions (load/store)
129 MemAccessSize accessSize = NoMemAccess;
130 let TSFlags{47-44} = accessSize.Value;
133 let TSFlags {48} = isTaken; // Branch prediction.
136 let TSFlags {49} = isFP; // Floating-point.
138 bits<1> hasNewValue2 = 0;
139 let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
140 bits<3> opNewValue2 = 0;
141 let TSFlags{54-52} = opNewValue2; // Second New-value produced operand.
143 bits<1> isAccumulator = 0;
144 let TSFlags{55} = isAccumulator;
146 bits<1> prefersSlot3 = 0;
147 let TSFlags{56} = prefersSlot3; // Complex XU
150 let TSFlags{60} = cofMax1;
153 let TSFlags{61} = CVINew;
155 // Fields used for relation models.
156 bit isNonTemporal = 0;
157 string isNT = ""; // set to "true" for non-temporal vector stores.
158 string BaseOpcode = "";
159 string CextOpcode = "";
160 string PredSense = "";
161 string PNewValue = "";
162 string NValueST = ""; // Set to "true" for new-value stores.
163 string InputType = ""; // Input is "imm" or "reg" type.
164 string isFloat = "false"; // Set to "true" for the floating-point load/store.
165 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
167 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
169 let PNewValue = !if(isPredicatedNew, "new", "");
170 let NValueST = !if(isNVStore, "true", "false");
171 let isNT = !if(isNonTemporal, "true", "false");
173 let hasSideEffects = 0;
174 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
177 class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
178 InstHexagon<outs, ins, asmstr, [], "", itin, type>;
180 //===----------------------------------------------------------------------===//
181 // Instruction Classes Definitions +
182 //===----------------------------------------------------------------------===//
184 // LD Instruction Class in V2/V3/V4.
185 // Definition of the instruction class NOT CHANGED.
187 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
188 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
189 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
191 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
192 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
193 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
195 // ST Instruction Class in V2/V3 can take SLOT0 only.
196 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
197 // Definition of the instruction class CHANGED from V2/V3 to V4.
199 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
200 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
201 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
203 let isCodeGenOnly = 1, isPseudo = 1 in
204 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
205 string cstr = "", InstrItinClass itin = tc_ENDLOOP>
206 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
209 let isCodeGenOnly = 1, isPseudo = 1 in
210 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
212 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
215 let isCodeGenOnly = 1, isPseudo = 1 in
216 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
218 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
221 //===----------------------------------------------------------------------===//
222 // Instruction Classes Definitions -
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
226 // V4 Instruction Format Definitions +
227 //===----------------------------------------------------------------------===//
229 include "HexagonInstrFormatsV4.td"
231 //===----------------------------------------------------------------------===//
232 // V55 Instruction Format Definitions +
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
236 // V60 Instruction Format Definitions +
237 //===----------------------------------------------------------------------===//
239 include "HexagonInstrFormatsV60.td"
241 //===----------------------------------------------------------------------===//
242 // V62 Instruction Format Definitions +
243 //===----------------------------------------------------------------------===//