1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<6> value> {
32 bits<6> Value = value;
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
37 def HasV55SubT : SubTarget<0x3c>; // 111100
38 def HasV60SubT : SubTarget<0x38>; // 111000
40 // Addressing modes for load/store instructions
41 class AddrModeType<bits<3> value> {
42 bits<3> Value = value;
45 def NoAddrMode : AddrModeType<0>; // No addressing mode
46 def Absolute : AddrModeType<1>; // Absolute addressing mode
47 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
48 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
49 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
50 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
51 def PostInc : AddrModeType<6>; // Post increment addressing mode
53 class MemAccessSize<bits<4> value> {
54 bits<4> Value = value;
57 def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction.
58 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
59 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
60 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
61 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
62 def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
63 def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
66 //===----------------------------------------------------------------------===//
67 // Instruction Class Declaration +
68 //===----------------------------------------------------------------------===//
71 field bits<32> Inst = ?; // Default to an invalid insn.
72 bits<4> IClass = 0; // ICLASS
74 let Inst{31-28} = IClass;
79 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
80 string cstr, InstrItinClass itin, IType type>
82 let Namespace = "Hexagon";
84 dag OutOperandList = outs;
85 dag InOperandList = ins;
86 let AsmString = asmstr;
87 let Pattern = pattern;
88 let Constraints = cstr;
92 // SoftFail is a field the disassembler can use to provide a way for
93 // instructions to not match without killing the whole decode process. It is
94 // mainly used for ARM, but Tablegen expects this field to exist or it fails
95 // to build the decode table.
96 field bits<32> SoftFail = 0;
98 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
100 // Instruction type according to the ISA.
102 let TSFlags{4-0} = Type.Value;
104 // Solo instructions, i.e., those that cannot be in a packet with others.
106 let TSFlags{5} = isSolo;
107 // Packed only with A or X-type instructions.
108 bits<1> isSoloAX = 0;
109 let TSFlags{6} = isSoloAX;
110 // Only A-type instruction in first slot or nothing.
111 bits<1> isSoloAin1 = 0;
112 let TSFlags{7} = isSoloAin1;
114 // Predicated instructions.
115 bits<1> isPredicated = 0;
116 let TSFlags{8} = isPredicated;
117 bits<1> isPredicatedFalse = 0;
118 let TSFlags{9} = isPredicatedFalse;
119 bits<1> isPredicatedNew = 0;
120 let TSFlags{10} = isPredicatedNew;
121 bits<1> isPredicateLate = 0;
122 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
124 // New-value insn helper fields.
125 bits<1> isNewValue = 0;
126 let TSFlags{12} = isNewValue; // New-value consumer insn.
127 bits<1> hasNewValue = 0;
128 let TSFlags{13} = hasNewValue; // New-value producer insn.
129 bits<3> opNewValue = 0;
130 let TSFlags{16-14} = opNewValue; // New-value produced operand.
131 bits<1> isNVStorable = 0;
132 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
133 bits<1> isNVStore = 0;
134 let TSFlags{18} = isNVStore; // New-value store insn.
135 bits<1> isCVLoadable = 0;
136 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
137 bits<1> isCVLoad = 0;
138 let TSFlags{20} = isCVLoad; // Cur-value load insn.
140 // Immediate extender helper fields.
141 bits<1> isExtendable = 0;
142 let TSFlags{21} = isExtendable; // Insn may be extended.
143 bits<1> isExtended = 0;
144 let TSFlags{22} = isExtended; // Insn must be extended.
145 bits<3> opExtendable = 0;
146 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
147 bits<1> isExtentSigned = 0;
148 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
149 bits<5> opExtentBits = 0;
150 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
151 bits<2> opExtentAlign = 0;
152 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
154 // If an instruction is valid on a subtarget, set the corresponding
155 // bit from validSubTargets.
156 // By default, instruction is valid on all subtargets.
157 SubTarget validSubTargets = HasAnySubT;
158 let TSFlags{39-34} = validSubTargets.Value;
160 // Addressing mode for load/store instructions.
161 AddrModeType addrMode = NoAddrMode;
162 let TSFlags{42-40} = addrMode.Value;
164 // Memory access size for mem access instructions (load/store)
165 MemAccessSize accessSize = NoMemAccess;
166 let TSFlags{46-43} = accessSize.Value;
169 let TSFlags {47} = isTaken; // Branch prediction.
172 let TSFlags {48} = isFP; // Floating-point.
174 bits<1> hasNewValue2 = 0;
175 let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
176 bits<3> opNewValue2 = 0;
177 let TSFlags{53-51} = opNewValue2; // Second New-value produced operand.
179 bits<1> isAccumulator = 0;
180 let TSFlags{54} = isAccumulator;
183 let TSFlags{60} = cofMax1;
185 // Fields used for relation models.
186 bit isNonTemporal = 0;
187 string isNT = ""; // set to "true" for non-temporal vector stores.
188 string BaseOpcode = "";
189 string CextOpcode = "";
190 string PredSense = "";
191 string PNewValue = "";
192 string NValueST = ""; // Set to "true" for new-value stores.
193 string InputType = ""; // Input is "imm" or "reg" type.
194 string isFloat = "false"; // Set to "true" for the floating-point load/store.
195 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
197 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
199 let PNewValue = !if(isPredicatedNew, "new", "");
200 let NValueST = !if(isNVStore, "true", "false");
201 let isNT = !if(isNonTemporal, "true", "false");
203 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
206 //===----------------------------------------------------------------------===//
207 // Instruction Classes Definitions +
208 //===----------------------------------------------------------------------===//
210 // LD Instruction Class in V2/V3/V4.
211 // Definition of the instruction class NOT CHANGED.
213 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
214 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
215 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
218 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
220 : LDInst<outs, ins, asmstr, pattern, cstr>;
222 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
224 : LDInst<outs, ins, asmstr, pattern, cstr>;
226 // LD Instruction Class in V2/V3/V4.
227 // Definition of the instruction class NOT CHANGED.
228 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
230 : LDInst<outs, ins, asmstr, pattern, cstr>;
233 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
234 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
235 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
238 class LD1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
239 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
240 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
242 // ST Instruction Class in V2/V3 can take SLOT0 only.
243 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
244 // Definition of the instruction class CHANGED from V2/V3 to V4.
246 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
247 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
248 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
250 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
252 : STInst<outs, ins, asmstr, pattern, cstr>;
255 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
256 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
257 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
259 // Same as ST0Inst but doesn't derive from OpcodeHexagon.
261 class ST1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
262 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
263 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
265 // ST Instruction Class in V2/V3 can take SLOT0 only.
266 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
267 // Definition of the instruction class CHANGED from V2/V3 to V4.
268 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
269 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
270 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
272 // SYSTEM Instruction Class in V4 can take SLOT0 only
273 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
274 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
275 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
276 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>,
279 // ALU32 Instruction Class in V2/V3/V4.
280 // Definition of the instruction class NOT CHANGED.
281 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
282 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
283 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon;
285 // ALU64 Instruction Class in V2/V3.
286 // XTYPE Instruction Class in V4.
287 // Definition of the instruction class NOT CHANGED.
288 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
289 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
290 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
291 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
294 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
295 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
296 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
299 // M Instruction Class in V2/V3.
300 // XTYPE Instruction Class in V4.
301 // Definition of the instruction class NOT CHANGED.
302 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
303 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
304 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
305 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
308 // Same as above but doesn't derive from OpcodeHexagon
309 class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
310 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
311 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
313 // M Instruction Class in V2/V3.
314 // XTYPE Instruction Class in V4.
315 // Definition of the instruction class NOT CHANGED.
316 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
317 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
318 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
319 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
321 // S Instruction Class in V2/V3.
322 // XTYPE Instruction Class in V4.
323 // Definition of the instruction class NOT CHANGED.
324 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
325 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
326 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
327 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
330 class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
331 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
332 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
334 // S Instruction Class in V2/V3.
335 // XTYPE Instruction Class in V4.
336 // Definition of the instruction class NOT CHANGED.
337 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
338 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
339 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
340 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
342 // J Instruction Class in V2/V3/V4.
343 // Definition of the instruction class NOT CHANGED.
344 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
345 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
346 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
348 class JInst_CJUMP_UCJUMP<dag outs, dag ins, string asmstr, list<dag> pattern = [],
349 string cstr = "", InstrItinClass itin = J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>
350 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
352 // JR Instruction Class in V2/V3/V4.
353 // Definition of the instruction class NOT CHANGED.
354 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
355 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
356 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon;
358 // CR Instruction Class in V2/V3/V4.
359 // Definition of the instruction class NOT CHANGED.
360 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
361 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
362 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon;
364 let isCodeGenOnly = 1, isPseudo = 1 in
365 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
366 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
367 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
370 let isCodeGenOnly = 1, isPseudo = 1 in
371 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
373 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
376 let isCodeGenOnly = 1, isPseudo = 1 in
377 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
379 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
382 //===----------------------------------------------------------------------===//
383 // Instruction Classes Definitions -
384 //===----------------------------------------------------------------------===//
390 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
391 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
392 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
394 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
395 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
396 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
398 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
399 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
400 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
402 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
403 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
404 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
409 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
410 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
411 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
413 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
414 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
415 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
417 // Post increment ST Instruction.
418 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
420 : STInst<outs, ins, asmstr, pattern, cstr>;
422 // Post increment LD Instruction.
423 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
425 : LDInst<outs, ins, asmstr, pattern, cstr>;
427 //===----------------------------------------------------------------------===//
428 // V4 Instruction Format Definitions +
429 //===----------------------------------------------------------------------===//
431 include "HexagonInstrFormatsV4.td"
433 //===----------------------------------------------------------------------===//
434 // V4 Instruction Format Definitions +
435 //===----------------------------------------------------------------------===//
437 //===----------------------------------------------------------------------===//
438 // V60 Instruction Format Definitions +
439 //===----------------------------------------------------------------------===//
441 include "HexagonInstrFormatsV60.td"
443 //===----------------------------------------------------------------------===//
444 // V60 Instruction Format Definitions +
445 //===----------------------------------------------------------------------===//