1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(), Subtarget(ST) {}
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
84 if (MI->getOperand(2).isFI() &&
85 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86 FrameIndex = MI->getOperand(2).getIndex();
87 return MI->getOperand(0).getReg();
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
108 if (MI->getOperand(2).isFI() &&
109 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110 FrameIndex = MI->getOperand(0).getIndex();
111 return MI->getOperand(2).getReg();
118 // Find the hardware loop instruction used to set-up the specified loop.
119 // On Hexagon, we have two instructions used to set-up the hardware loop
120 // (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
121 // to indicate the end of a loop.
122 static MachineInstr *
123 findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
124 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
127 if (EndLoopOp == Hexagon::ENDLOOP0) {
128 LOOPi = Hexagon::J2_loop0i;
129 LOOPr = Hexagon::J2_loop0r;
130 } else { // EndLoopOp == Hexagon::EndLOOP1
131 LOOPi = Hexagon::J2_loop1i;
132 LOOPr = Hexagon::J2_loop1r;
135 // The loop set-up instruction will be in a predecessor block
136 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
137 PE = BB->pred_end(); PB != PE; ++PB) {
138 // If this has been visited, already skip it.
139 if (!Visited.insert(*PB).second)
143 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
144 E = (*PB)->instr_rend(); I != E; ++I) {
145 int Opc = I->getOpcode();
146 if (Opc == LOOPi || Opc == LOOPr)
148 // We've reached a different loop, which means the loop0 has been removed.
149 if (Opc == EndLoopOp)
152 // Check the predecessors for the LOOP instruction.
153 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
160 unsigned HexagonInstrInfo::InsertBranch(
161 MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
162 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
164 Opcode_t BOpc = Hexagon::J2_jump;
165 Opcode_t BccOpc = Hexagon::J2_jumpt;
167 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
169 // Check if ReverseBranchCondition has asked to reverse this branch
170 // If we want to reverse the branch an odd number of times, we want
172 if (!Cond.empty() && Cond[0].isImm())
173 BccOpc = Cond[0].getImm();
177 // Due to a bug in TailMerging/CFG Optimization, we need to add a
178 // special case handling of a predicated jump followed by an
179 // unconditional jump. If not, Tail Merging and CFG Optimization go
180 // into an infinite loop.
181 MachineBasicBlock *NewTBB, *NewFBB;
182 SmallVector<MachineOperand, 4> Cond;
183 MachineInstr *Term = MBB.getFirstTerminator();
184 if (Term != MBB.end() && isPredicated(Term) &&
185 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
186 MachineBasicBlock *NextBB =
187 std::next(MachineFunction::iterator(&MBB));
188 if (NewTBB == NextBB) {
189 ReverseBranchCondition(Cond);
191 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
194 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
195 } else if (isEndLoopN(Cond[0].getImm())) {
196 int EndLoopOp = Cond[0].getImm();
197 assert(Cond[1].isMBB());
198 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
199 // Check for it, and change the BB target if needed.
200 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
201 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
202 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
203 Loop->getOperand(0).setMBB(TBB);
204 // Add the ENDLOOP after the finding the LOOP0.
205 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
206 } else if (isNewValueJump(Cond[0].getImm())) {
207 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
209 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
210 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
211 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
212 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
213 if (Cond[2].isReg()) {
214 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
215 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
216 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
217 } else if(Cond[2].isImm()) {
218 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
219 addImm(Cond[2].getImm()).addMBB(TBB);
221 llvm_unreachable("Invalid condition for branching");
223 assert((Cond.size() == 2) && "Malformed cond vector");
224 const MachineOperand &RO = Cond[1];
225 unsigned Flags = getUndefRegState(RO.isUndef());
226 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
230 assert((!Cond.empty()) &&
231 "Cond. cannot be empty when multiple branchings are required");
232 assert((!isNewValueJump(Cond[0].getImm())) &&
233 "NV-jump cannot be inserted with another branch");
234 // Special case for hardware loops. The condition is a basic block.
235 if (isEndLoopN(Cond[0].getImm())) {
236 int EndLoopOp = Cond[0].getImm();
237 assert(Cond[1].isMBB());
238 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
239 // Check for it, and change the BB target if needed.
240 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
241 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
242 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
243 Loop->getOperand(0).setMBB(TBB);
244 // Add the ENDLOOP after the finding the LOOP0.
245 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
247 const MachineOperand &RO = Cond[1];
248 unsigned Flags = getUndefRegState(RO.isUndef());
249 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
251 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
257 /// This function can analyze one/two way branching only and should (mostly) be
258 /// called by target independent side.
259 /// First entry is always the opcode of the branching instruction, except when
260 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
261 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
262 /// e.g. Jump_c p will have
266 /// Cond[0] = ENDLOOP
269 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
272 /// @note Related function is \fn findInstrPredicate which fills in
273 /// Cond. vector when a predicated instruction is passed to it.
274 /// We follow same protocol in that case too.
276 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
277 MachineBasicBlock *&TBB,
278 MachineBasicBlock *&FBB,
279 SmallVectorImpl<MachineOperand> &Cond,
280 bool AllowModify) const {
285 // If the block has no terminators, it just falls into the block after it.
286 MachineBasicBlock::instr_iterator I = MBB.instr_end();
287 if (I == MBB.instr_begin())
290 // A basic block may looks like this:
300 // It has two succs but does not have a terminator
301 // Don't know how to handle it.
305 // Don't analyze EH branches.
307 } while (I != MBB.instr_begin());
312 while (I->isDebugValue()) {
313 if (I == MBB.instr_begin())
318 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
319 I->getOperand(0).isMBB();
320 // Delete the J2_jump if it's equivalent to a fall-through.
321 if (AllowModify && JumpToBlock &&
322 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
323 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
324 I->eraseFromParent();
326 if (I == MBB.instr_begin())
330 if (!isUnpredicatedTerminator(I))
333 // Get the last instruction in the block.
334 MachineInstr *LastInst = I;
335 MachineInstr *SecondLastInst = nullptr;
336 // Find one more terminator if present.
338 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
342 // This is a third branch.
345 if (I == MBB.instr_begin())
350 int LastOpcode = LastInst->getOpcode();
351 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
352 // If the branch target is not a basic block, it could be a tail call.
353 // (It is, if the target is a function.)
354 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
356 if (SecLastOpcode == Hexagon::J2_jump &&
357 !SecondLastInst->getOperand(0).isMBB())
360 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
361 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
363 // If there is only one terminator instruction, process it.
364 if (LastInst && !SecondLastInst) {
365 if (LastOpcode == Hexagon::J2_jump) {
366 TBB = LastInst->getOperand(0).getMBB();
369 if (isEndLoopN(LastOpcode)) {
370 TBB = LastInst->getOperand(0).getMBB();
371 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
372 Cond.push_back(LastInst->getOperand(0));
375 if (LastOpcodeHasJMP_c) {
376 TBB = LastInst->getOperand(1).getMBB();
377 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
378 Cond.push_back(LastInst->getOperand(0));
381 // Only supporting rr/ri versions of new-value jumps.
382 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
383 TBB = LastInst->getOperand(2).getMBB();
384 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
385 Cond.push_back(LastInst->getOperand(0));
386 Cond.push_back(LastInst->getOperand(1));
389 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
390 << " with one jump\n";);
391 // Otherwise, don't know what this is.
395 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
396 bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
397 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
398 TBB = SecondLastInst->getOperand(1).getMBB();
399 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
400 Cond.push_back(SecondLastInst->getOperand(0));
401 FBB = LastInst->getOperand(0).getMBB();
405 // Only supporting rr/ri versions of new-value jumps.
406 if (SecLastOpcodeHasNVJump &&
407 (SecondLastInst->getNumExplicitOperands() == 3) &&
408 (LastOpcode == Hexagon::J2_jump)) {
409 TBB = SecondLastInst->getOperand(2).getMBB();
410 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
411 Cond.push_back(SecondLastInst->getOperand(0));
412 Cond.push_back(SecondLastInst->getOperand(1));
413 FBB = LastInst->getOperand(0).getMBB();
417 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
418 // executed, so remove it.
419 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
420 TBB = SecondLastInst->getOperand(0).getMBB();
423 I->eraseFromParent();
427 // If the block ends with an ENDLOOP, and J2_jump, handle it.
428 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
429 TBB = SecondLastInst->getOperand(0).getMBB();
430 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
431 Cond.push_back(SecondLastInst->getOperand(0));
432 FBB = LastInst->getOperand(0).getMBB();
435 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
436 << " with two jumps";);
437 // Otherwise, can't handle this.
441 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
442 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
443 MachineBasicBlock::iterator I = MBB.end();
445 while (I != MBB.begin()) {
447 if (I->isDebugValue())
449 // Only removing branches from end of MBB.
452 if (Count && (I->getOpcode() == Hexagon::J2_jump))
453 llvm_unreachable("Malformed basic block: unconditional branch not last");
454 MBB.erase(&MBB.back());
461 /// \brief For a comparison instruction, return the source registers in
462 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
463 /// compares against in CmpValue. Return true if the comparison instruction
465 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
466 unsigned &SrcReg, unsigned &SrcReg2,
467 int &Mask, int &Value) const {
468 unsigned Opc = MI->getOpcode();
470 // Set mask and the first source register.
472 case Hexagon::C2_cmpeq:
473 case Hexagon::C2_cmpeqp:
474 case Hexagon::C2_cmpgt:
475 case Hexagon::C2_cmpgtp:
476 case Hexagon::C2_cmpgtu:
477 case Hexagon::C2_cmpgtup:
478 case Hexagon::C4_cmpneq:
479 case Hexagon::C4_cmplte:
480 case Hexagon::C4_cmplteu:
481 case Hexagon::C2_cmpeqi:
482 case Hexagon::C2_cmpgti:
483 case Hexagon::C2_cmpgtui:
484 case Hexagon::C4_cmpneqi:
485 case Hexagon::C4_cmplteui:
486 case Hexagon::C4_cmpltei:
487 SrcReg = MI->getOperand(1).getReg();
490 case Hexagon::A4_cmpbeq:
491 case Hexagon::A4_cmpbgt:
492 case Hexagon::A4_cmpbgtu:
493 case Hexagon::A4_cmpbeqi:
494 case Hexagon::A4_cmpbgti:
495 case Hexagon::A4_cmpbgtui:
496 SrcReg = MI->getOperand(1).getReg();
499 case Hexagon::A4_cmpheq:
500 case Hexagon::A4_cmphgt:
501 case Hexagon::A4_cmphgtu:
502 case Hexagon::A4_cmpheqi:
503 case Hexagon::A4_cmphgti:
504 case Hexagon::A4_cmphgtui:
505 SrcReg = MI->getOperand(1).getReg();
510 // Set the value/second source register.
512 case Hexagon::C2_cmpeq:
513 case Hexagon::C2_cmpeqp:
514 case Hexagon::C2_cmpgt:
515 case Hexagon::C2_cmpgtp:
516 case Hexagon::C2_cmpgtu:
517 case Hexagon::C2_cmpgtup:
518 case Hexagon::A4_cmpbeq:
519 case Hexagon::A4_cmpbgt:
520 case Hexagon::A4_cmpbgtu:
521 case Hexagon::A4_cmpheq:
522 case Hexagon::A4_cmphgt:
523 case Hexagon::A4_cmphgtu:
524 case Hexagon::C4_cmpneq:
525 case Hexagon::C4_cmplte:
526 case Hexagon::C4_cmplteu:
527 SrcReg2 = MI->getOperand(2).getReg();
530 case Hexagon::C2_cmpeqi:
531 case Hexagon::C2_cmpgtui:
532 case Hexagon::C2_cmpgti:
533 case Hexagon::C4_cmpneqi:
534 case Hexagon::C4_cmplteui:
535 case Hexagon::C4_cmpltei:
536 case Hexagon::A4_cmpbeqi:
537 case Hexagon::A4_cmpbgti:
538 case Hexagon::A4_cmpbgtui:
539 case Hexagon::A4_cmpheqi:
540 case Hexagon::A4_cmphgti:
541 case Hexagon::A4_cmphgtui:
543 Value = MI->getOperand(2).getImm();
551 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator I, DebugLoc DL,
553 unsigned DestReg, unsigned SrcReg,
554 bool KillSrc) const {
555 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
556 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
559 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
560 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
563 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
564 // Map Pd = Ps to Pd = or(Ps, Ps).
565 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
566 DestReg).addReg(SrcReg).addReg(SrcReg);
569 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
570 Hexagon::IntRegsRegClass.contains(SrcReg)) {
571 // We can have an overlap between single and double reg: r1:0 = r0.
572 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
574 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
575 Hexagon::subreg_hireg))).addImm(0);
577 // r1:0 = r1 or no overlap.
578 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
579 Hexagon::subreg_loreg))).addReg(SrcReg);
580 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
581 Hexagon::subreg_hireg))).addImm(0);
585 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
586 Hexagon::IntRegsRegClass.contains(SrcReg)) {
587 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
590 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
591 Hexagon::IntRegsRegClass.contains(DestReg)) {
592 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
593 addReg(SrcReg, getKillRegState(KillSrc));
596 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
597 Hexagon::PredRegsRegClass.contains(DestReg)) {
598 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
599 addReg(SrcReg, getKillRegState(KillSrc));
603 llvm_unreachable("Unimplemented");
607 void HexagonInstrInfo::
608 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
609 unsigned SrcReg, bool isKill, int FI,
610 const TargetRegisterClass *RC,
611 const TargetRegisterInfo *TRI) const {
613 DebugLoc DL = MBB.findDebugLoc(I);
614 MachineFunction &MF = *MBB.getParent();
615 MachineFrameInfo &MFI = *MF.getFrameInfo();
616 unsigned Align = MFI.getObjectAlignment(FI);
618 MachineMemOperand *MMO =
619 MF.getMachineMemOperand(
620 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
621 MachineMemOperand::MOStore,
622 MFI.getObjectSize(FI),
625 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
626 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
627 .addFrameIndex(FI).addImm(0)
628 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
629 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
630 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
631 .addFrameIndex(FI).addImm(0)
632 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
633 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
634 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
635 .addFrameIndex(FI).addImm(0)
636 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
638 llvm_unreachable("Unimplemented");
643 void HexagonInstrInfo::storeRegToAddr(
644 MachineFunction &MF, unsigned SrcReg,
646 SmallVectorImpl<MachineOperand> &Addr,
647 const TargetRegisterClass *RC,
648 SmallVectorImpl<MachineInstr*> &NewMIs) const
650 llvm_unreachable("Unimplemented");
654 void HexagonInstrInfo::
655 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
656 unsigned DestReg, int FI,
657 const TargetRegisterClass *RC,
658 const TargetRegisterInfo *TRI) const {
659 DebugLoc DL = MBB.findDebugLoc(I);
660 MachineFunction &MF = *MBB.getParent();
661 MachineFrameInfo &MFI = *MF.getFrameInfo();
662 unsigned Align = MFI.getObjectAlignment(FI);
664 MachineMemOperand *MMO =
665 MF.getMachineMemOperand(
666 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
667 MachineMemOperand::MOLoad,
668 MFI.getObjectSize(FI),
670 if (RC == &Hexagon::IntRegsRegClass) {
671 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
672 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
673 } else if (RC == &Hexagon::DoubleRegsRegClass) {
674 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
675 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
676 } else if (RC == &Hexagon::PredRegsRegClass) {
677 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
678 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
680 llvm_unreachable("Can't store this register to stack slot");
685 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
686 SmallVectorImpl<MachineOperand> &Addr,
687 const TargetRegisterClass *RC,
688 SmallVectorImpl<MachineInstr*> &NewMIs) const {
689 llvm_unreachable("Unimplemented");
692 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
693 const HexagonRegisterInfo &TRI = getRegisterInfo();
694 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
695 MachineBasicBlock &MBB = *MI->getParent();
696 DebugLoc DL = MI->getDebugLoc();
697 unsigned Opc = MI->getOpcode();
700 case Hexagon::ALIGNA:
701 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
702 .addReg(TRI.getFrameRegister())
703 .addImm(-MI->getOperand(1).getImm());
706 case Hexagon::TFR_PdTrue: {
707 unsigned Reg = MI->getOperand(0).getReg();
708 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
709 .addReg(Reg, RegState::Undef)
710 .addReg(Reg, RegState::Undef);
714 case Hexagon::TFR_PdFalse: {
715 unsigned Reg = MI->getOperand(0).getReg();
716 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
717 .addReg(Reg, RegState::Undef)
718 .addReg(Reg, RegState::Undef);
722 case Hexagon::VMULW: {
723 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
724 unsigned DstReg = MI->getOperand(0).getReg();
725 unsigned Src1Reg = MI->getOperand(1).getReg();
726 unsigned Src2Reg = MI->getOperand(2).getReg();
727 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
728 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
729 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
730 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
731 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
732 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
734 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
735 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
738 MRI.clearKillFlags(Src1SubHi);
739 MRI.clearKillFlags(Src1SubLo);
740 MRI.clearKillFlags(Src2SubHi);
741 MRI.clearKillFlags(Src2SubLo);
744 case Hexagon::VMULW_ACC: {
745 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
746 unsigned DstReg = MI->getOperand(0).getReg();
747 unsigned Src1Reg = MI->getOperand(1).getReg();
748 unsigned Src2Reg = MI->getOperand(2).getReg();
749 unsigned Src3Reg = MI->getOperand(3).getReg();
750 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
751 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
752 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
753 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
754 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
755 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
756 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
757 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
758 .addReg(Src2SubHi).addReg(Src3SubHi);
759 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
760 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
761 .addReg(Src2SubLo).addReg(Src3SubLo);
763 MRI.clearKillFlags(Src1SubHi);
764 MRI.clearKillFlags(Src1SubLo);
765 MRI.clearKillFlags(Src2SubHi);
766 MRI.clearKillFlags(Src2SubLo);
767 MRI.clearKillFlags(Src3SubHi);
768 MRI.clearKillFlags(Src3SubLo);
771 case Hexagon::TCRETURNi:
772 MI->setDesc(get(Hexagon::J2_jump));
774 case Hexagon::TCRETURNr:
775 MI->setDesc(get(Hexagon::J2_jumpr));
782 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(
783 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
784 MachineBasicBlock::iterator InsertPt, int FI) const {
785 // Hexagon_TODO: Implement.
789 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
791 MachineRegisterInfo &RegInfo = MF->getRegInfo();
792 const TargetRegisterClass *TRC;
794 TRC = &Hexagon::PredRegsRegClass;
795 } else if (VT == MVT::i32 || VT == MVT::f32) {
796 TRC = &Hexagon::IntRegsRegClass;
797 } else if (VT == MVT::i64 || VT == MVT::f64) {
798 TRC = &Hexagon::DoubleRegsRegClass;
800 llvm_unreachable("Cannot handle this register class");
803 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
807 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
808 const MCInstrDesc &MID = MI->getDesc();
809 const uint64_t F = MID.TSFlags;
810 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
813 // TODO: This is largely obsolete now. Will need to be removed
814 // in consecutive patches.
815 switch(MI->getOpcode()) {
816 // TFR_FI Remains a special case.
817 case Hexagon::TFR_FI:
825 // This returns true in two cases:
826 // - The OP code itself indicates that this is an extended instruction.
827 // - One of MOs has been marked with HMOTF_ConstExtended flag.
828 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
829 // First check if this is permanently extended op code.
830 const uint64_t F = MI->getDesc().TSFlags;
831 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
833 // Use MO operand flags to determine if one of MI's operands
834 // has HMOTF_ConstExtended flag set.
835 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
836 E = MI->operands_end(); I != E; ++I) {
837 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
843 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
844 return MI->getDesc().isBranch();
847 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
848 if (isNewValueJump(MI))
851 if (isNewValueStore(MI))
857 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
858 const uint64_t F = MI->getDesc().TSFlags;
859 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
862 bool HexagonInstrInfo::isNewValue(Opcode_t Opcode) const {
863 const uint64_t F = get(Opcode).TSFlags;
864 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
867 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
868 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
871 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
872 bool isPred = MI->getDesc().isPredicable();
877 const int Opc = MI->getOpcode();
880 case Hexagon::A2_tfrsi:
881 return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
883 case Hexagon::S2_storerd_io:
884 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
886 case Hexagon::S2_storeri_io:
887 case Hexagon::S2_storerinew_io:
888 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
890 case Hexagon::S2_storerh_io:
891 case Hexagon::S2_storerhnew_io:
892 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
894 case Hexagon::S2_storerb_io:
895 case Hexagon::S2_storerbnew_io:
896 return isUInt<6>(MI->getOperand(1).getImm());
898 case Hexagon::L2_loadrd_io:
899 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
901 case Hexagon::L2_loadri_io:
902 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
904 case Hexagon::L2_loadrh_io:
905 case Hexagon::L2_loadruh_io:
906 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
908 case Hexagon::L2_loadrb_io:
909 case Hexagon::L2_loadrub_io:
910 return isUInt<6>(MI->getOperand(2).getImm());
912 case Hexagon::L2_loadrd_pi:
913 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
915 case Hexagon::L2_loadri_pi:
916 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
918 case Hexagon::L2_loadrh_pi:
919 case Hexagon::L2_loadruh_pi:
920 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
922 case Hexagon::L2_loadrb_pi:
923 case Hexagon::L2_loadrub_pi:
924 return isInt<4>(MI->getOperand(3).getImm());
926 case Hexagon::S4_storeirb_io:
927 case Hexagon::S4_storeirh_io:
928 case Hexagon::S4_storeiri_io:
929 return (isUInt<6>(MI->getOperand(1).getImm()) &&
930 isInt<6>(MI->getOperand(2).getImm()));
932 case Hexagon::A2_addi:
933 return isInt<8>(MI->getOperand(2).getImm());
935 case Hexagon::A2_aslh:
936 case Hexagon::A2_asrh:
937 case Hexagon::A2_sxtb:
938 case Hexagon::A2_sxth:
939 case Hexagon::A2_zxtb:
940 case Hexagon::A2_zxth:
947 // This function performs the following inversiones:
952 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
954 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
955 : Hexagon::getTruePredOpcode(Opc);
956 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
957 return InvPredOpcode;
960 default: llvm_unreachable("Unexpected predicated instruction");
961 case Hexagon::C2_ccombinewt:
962 return Hexagon::C2_ccombinewf;
963 case Hexagon::C2_ccombinewf:
964 return Hexagon::C2_ccombinewt;
967 case Hexagon::L4_return_t:
968 return Hexagon::L4_return_f;
969 case Hexagon::L4_return_f:
970 return Hexagon::L4_return_t;
974 // New Value Store instructions.
975 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
976 const uint64_t F = MI->getDesc().TSFlags;
978 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
981 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
982 const uint64_t F = get(Opcode).TSFlags;
984 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
987 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
988 enum Hexagon::PredSense inPredSense;
989 inPredSense = invertPredicate ? Hexagon::PredSense_false :
990 Hexagon::PredSense_true;
991 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
992 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
995 // This switch case will be removed once all the instructions have been
996 // modified to use relation maps.
998 case Hexagon::TFRI_f:
999 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1000 Hexagon::TFRI_cNotPt_f;
1001 case Hexagon::A2_combinew:
1002 return !invertPredicate ? Hexagon::C2_ccombinewt :
1003 Hexagon::C2_ccombinewf;
1006 case Hexagon::L4_return:
1007 return !invertPredicate ? Hexagon::L4_return_t:
1008 Hexagon::L4_return_f;
1010 llvm_unreachable("Unexpected predicable instruction");
1014 bool HexagonInstrInfo::
1015 PredicateInstruction(MachineInstr *MI,
1016 ArrayRef<MachineOperand> Cond) const {
1017 if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
1018 DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1021 int Opc = MI->getOpcode();
1022 assert (isPredicable(MI) && "Expected predicable instruction");
1023 bool invertJump = predOpcodeHasNot(Cond);
1025 // We have to predicate MI "in place", i.e. after this function returns,
1026 // MI will need to be transformed into a predicated form. To avoid com-
1027 // plicated manipulations with the operands (handling tied operands,
1028 // etc.), build a new temporary instruction, then overwrite MI with it.
1030 MachineBasicBlock &B = *MI->getParent();
1031 DebugLoc DL = MI->getDebugLoc();
1032 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1033 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1034 unsigned NOp = 0, NumOps = MI->getNumOperands();
1035 while (NOp < NumOps) {
1036 MachineOperand &Op = MI->getOperand(NOp);
1037 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1043 unsigned PredReg, PredRegPos, PredRegFlags;
1044 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1047 T.addReg(PredReg, PredRegFlags);
1048 while (NOp < NumOps)
1049 T.addOperand(MI->getOperand(NOp++));
1051 MI->setDesc(get(PredOpc));
1052 while (unsigned n = MI->getNumOperands())
1053 MI->RemoveOperand(n-1);
1054 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1055 MI->addOperand(T->getOperand(i));
1057 MachineBasicBlock::instr_iterator TI = &*T;
1060 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1061 MRI.clearKillFlags(PredReg);
1069 isProfitableToIfCvt(MachineBasicBlock &MBB,
1071 unsigned ExtraPredCycles,
1072 const BranchProbability &Probability) const {
1079 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1080 unsigned NumTCycles,
1081 unsigned ExtraTCycles,
1082 MachineBasicBlock &FMBB,
1083 unsigned NumFCycles,
1084 unsigned ExtraFCycles,
1085 const BranchProbability &Probability) const {
1089 // Returns true if an instruction is predicated irrespective of the predicate
1090 // sense. For example, all of the following will return true.
1091 // if (p0) R1 = add(R2, R3)
1092 // if (!p0) R1 = add(R2, R3)
1093 // if (p0.new) R1 = add(R2, R3)
1094 // if (!p0.new) R1 = add(R2, R3)
1095 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1096 const uint64_t F = MI->getDesc().TSFlags;
1098 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1101 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1102 const uint64_t F = get(Opcode).TSFlags;
1104 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1107 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
1108 const uint64_t F = MI->getDesc().TSFlags;
1110 assert(isPredicated(MI));
1111 return (!((F >> HexagonII::PredicatedFalsePos) &
1112 HexagonII::PredicatedFalseMask));
1115 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1116 const uint64_t F = get(Opcode).TSFlags;
1118 // Make sure that the instruction is predicated.
1119 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1120 return (!((F >> HexagonII::PredicatedFalsePos) &
1121 HexagonII::PredicatedFalseMask));
1124 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1125 const uint64_t F = MI->getDesc().TSFlags;
1127 assert(isPredicated(MI));
1128 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1131 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1132 const uint64_t F = get(Opcode).TSFlags;
1134 assert(isPredicated(Opcode));
1135 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1138 // Returns true, if a ST insn can be promoted to a new-value store.
1139 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1140 const uint64_t F = MI->getDesc().TSFlags;
1142 return ((F >> HexagonII::mayNVStorePos) &
1143 HexagonII::mayNVStoreMask);
1147 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1148 std::vector<MachineOperand> &Pred) const {
1149 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1150 MachineOperand MO = MI->getOperand(oper);
1151 if (MO.isReg() && MO.isDef()) {
1152 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1153 if (RC == &Hexagon::PredRegsRegClass) {
1165 SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1166 ArrayRef<MachineOperand> Pred2) const {
1173 // We indicate that we want to reverse the branch by
1174 // inserting the reversed branching opcode.
1176 bool HexagonInstrInfo::ReverseBranchCondition(
1177 SmallVectorImpl<MachineOperand> &Cond) const {
1180 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1181 Opcode_t opcode = Cond[0].getImm();
1183 assert(get(opcode).isBranch() && "Should be a branching condition.");
1184 if (isEndLoopN(opcode))
1186 Opcode_t NewOpcode = getInvertedPredicatedOpcode(opcode);
1187 Cond[0].setImm(NewOpcode);
1192 bool HexagonInstrInfo::
1193 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1194 const BranchProbability &Probability) const {
1195 return (NumInstrs <= 4);
1198 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1199 switch (MI->getOpcode()) {
1200 default: return false;
1201 case Hexagon::L4_return:
1202 case Hexagon::L4_return_t:
1203 case Hexagon::L4_return_f:
1204 case Hexagon::L4_return_tnew_pnt:
1205 case Hexagon::L4_return_fnew_pnt:
1206 case Hexagon::L4_return_tnew_pt:
1207 case Hexagon::L4_return_fnew_pt:
1213 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
1214 bool Extend) const {
1215 // This function is to check whether the "Offset" is in the correct range of
1216 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
1217 // inserted to calculate the final address. Due to this reason, the function
1218 // assumes that the "Offset" has correct alignment.
1219 // We used to assert if the offset was not properly aligned, however,
1220 // there are cases where a misaligned pointer recast can cause this
1221 // problem, and we need to allow for it. The front end warns of such
1222 // misaligns with respect to load size.
1225 case Hexagon::J2_loop0i:
1226 case Hexagon::J2_loop1i:
1227 return isUInt<10>(Offset);
1234 case Hexagon::L2_loadri_io:
1235 case Hexagon::S2_storeri_io:
1236 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1237 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1239 case Hexagon::L2_loadrd_io:
1240 case Hexagon::S2_storerd_io:
1241 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1242 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1244 case Hexagon::L2_loadrh_io:
1245 case Hexagon::L2_loadruh_io:
1246 case Hexagon::S2_storerh_io:
1247 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1248 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1250 case Hexagon::L2_loadrb_io:
1251 case Hexagon::S2_storerb_io:
1252 case Hexagon::L2_loadrub_io:
1253 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1254 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1256 case Hexagon::A2_addi:
1257 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1258 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1260 case Hexagon::L4_iadd_memopw_io:
1261 case Hexagon::L4_isub_memopw_io:
1262 case Hexagon::L4_add_memopw_io:
1263 case Hexagon::L4_sub_memopw_io:
1264 case Hexagon::L4_and_memopw_io:
1265 case Hexagon::L4_or_memopw_io:
1266 return (0 <= Offset && Offset <= 255);
1268 case Hexagon::L4_iadd_memoph_io:
1269 case Hexagon::L4_isub_memoph_io:
1270 case Hexagon::L4_add_memoph_io:
1271 case Hexagon::L4_sub_memoph_io:
1272 case Hexagon::L4_and_memoph_io:
1273 case Hexagon::L4_or_memoph_io:
1274 return (0 <= Offset && Offset <= 127);
1276 case Hexagon::L4_iadd_memopb_io:
1277 case Hexagon::L4_isub_memopb_io:
1278 case Hexagon::L4_add_memopb_io:
1279 case Hexagon::L4_sub_memopb_io:
1280 case Hexagon::L4_and_memopb_io:
1281 case Hexagon::L4_or_memopb_io:
1282 return (0 <= Offset && Offset <= 63);
1284 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1285 // any size. Later pass knows how to handle it.
1286 case Hexagon::STriw_pred:
1287 case Hexagon::LDriw_pred:
1290 case Hexagon::TFR_FI:
1291 case Hexagon::TFR_FIA:
1292 case Hexagon::INLINEASM:
1296 llvm_unreachable("No offset range is defined for this opcode. "
1297 "Please define it in the above switch statement!");
1302 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1304 bool HexagonInstrInfo::
1305 isValidAutoIncImm(const EVT VT, const int Offset) const {
1307 if (VT == MVT::i64) {
1308 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1309 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1310 (Offset & 0x7) == 0);
1312 if (VT == MVT::i32) {
1313 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1314 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1315 (Offset & 0x3) == 0);
1317 if (VT == MVT::i16) {
1318 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1319 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1320 (Offset & 0x1) == 0);
1322 if (VT == MVT::i8) {
1323 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1324 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1326 llvm_unreachable("Not an auto-inc opc!");
1330 bool HexagonInstrInfo::
1331 isMemOp(const MachineInstr *MI) const {
1332 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1334 switch (MI->getOpcode())
1336 default: return false;
1337 case Hexagon::L4_iadd_memopw_io:
1338 case Hexagon::L4_isub_memopw_io:
1339 case Hexagon::L4_add_memopw_io:
1340 case Hexagon::L4_sub_memopw_io:
1341 case Hexagon::L4_and_memopw_io:
1342 case Hexagon::L4_or_memopw_io:
1343 case Hexagon::L4_iadd_memoph_io:
1344 case Hexagon::L4_isub_memoph_io:
1345 case Hexagon::L4_add_memoph_io:
1346 case Hexagon::L4_sub_memoph_io:
1347 case Hexagon::L4_and_memoph_io:
1348 case Hexagon::L4_or_memoph_io:
1349 case Hexagon::L4_iadd_memopb_io:
1350 case Hexagon::L4_isub_memopb_io:
1351 case Hexagon::L4_add_memopb_io:
1352 case Hexagon::L4_sub_memopb_io:
1353 case Hexagon::L4_and_memopb_io:
1354 case Hexagon::L4_or_memopb_io:
1355 case Hexagon::L4_ior_memopb_io:
1356 case Hexagon::L4_ior_memoph_io:
1357 case Hexagon::L4_ior_memopw_io:
1358 case Hexagon::L4_iand_memopb_io:
1359 case Hexagon::L4_iand_memoph_io:
1360 case Hexagon::L4_iand_memopw_io:
1367 bool HexagonInstrInfo::
1368 isSpillPredRegOp(const MachineInstr *MI) const {
1369 switch (MI->getOpcode()) {
1370 default: return false;
1371 case Hexagon::STriw_pred :
1372 case Hexagon::LDriw_pred :
1377 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1378 switch (MI->getOpcode()) {
1379 default: return false;
1380 case Hexagon::C2_cmpeq:
1381 case Hexagon::C2_cmpeqi:
1382 case Hexagon::C2_cmpgt:
1383 case Hexagon::C2_cmpgti:
1384 case Hexagon::C2_cmpgtu:
1385 case Hexagon::C2_cmpgtui:
1390 bool HexagonInstrInfo::
1391 isConditionalTransfer (const MachineInstr *MI) const {
1392 switch (MI->getOpcode()) {
1393 default: return false;
1394 case Hexagon::A2_tfrt:
1395 case Hexagon::A2_tfrf:
1396 case Hexagon::C2_cmoveit:
1397 case Hexagon::C2_cmoveif:
1398 case Hexagon::A2_tfrtnew:
1399 case Hexagon::A2_tfrfnew:
1400 case Hexagon::C2_cmovenewit:
1401 case Hexagon::C2_cmovenewif:
1406 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1407 switch (MI->getOpcode())
1409 default: return false;
1410 case Hexagon::A2_paddf:
1411 case Hexagon::A2_paddfnew:
1412 case Hexagon::A2_paddt:
1413 case Hexagon::A2_paddtnew:
1414 case Hexagon::A2_pandf:
1415 case Hexagon::A2_pandfnew:
1416 case Hexagon::A2_pandt:
1417 case Hexagon::A2_pandtnew:
1418 case Hexagon::A4_paslhf:
1419 case Hexagon::A4_paslhfnew:
1420 case Hexagon::A4_paslht:
1421 case Hexagon::A4_paslhtnew:
1422 case Hexagon::A4_pasrhf:
1423 case Hexagon::A4_pasrhfnew:
1424 case Hexagon::A4_pasrht:
1425 case Hexagon::A4_pasrhtnew:
1426 case Hexagon::A2_porf:
1427 case Hexagon::A2_porfnew:
1428 case Hexagon::A2_port:
1429 case Hexagon::A2_portnew:
1430 case Hexagon::A2_psubf:
1431 case Hexagon::A2_psubfnew:
1432 case Hexagon::A2_psubt:
1433 case Hexagon::A2_psubtnew:
1434 case Hexagon::A2_pxorf:
1435 case Hexagon::A2_pxorfnew:
1436 case Hexagon::A2_pxort:
1437 case Hexagon::A2_pxortnew:
1438 case Hexagon::A4_psxthf:
1439 case Hexagon::A4_psxthfnew:
1440 case Hexagon::A4_psxtht:
1441 case Hexagon::A4_psxthtnew:
1442 case Hexagon::A4_psxtbf:
1443 case Hexagon::A4_psxtbfnew:
1444 case Hexagon::A4_psxtbt:
1445 case Hexagon::A4_psxtbtnew:
1446 case Hexagon::A4_pzxtbf:
1447 case Hexagon::A4_pzxtbfnew:
1448 case Hexagon::A4_pzxtbt:
1449 case Hexagon::A4_pzxtbtnew:
1450 case Hexagon::A4_pzxthf:
1451 case Hexagon::A4_pzxthfnew:
1452 case Hexagon::A4_pzxtht:
1453 case Hexagon::A4_pzxthtnew:
1454 case Hexagon::A2_paddit:
1455 case Hexagon::A2_paddif:
1456 case Hexagon::C2_ccombinewt:
1457 case Hexagon::C2_ccombinewf:
1462 bool HexagonInstrInfo::
1463 isConditionalLoad (const MachineInstr* MI) const {
1464 switch (MI->getOpcode())
1466 default: return false;
1467 case Hexagon::L2_ploadrdt_io :
1468 case Hexagon::L2_ploadrdf_io:
1469 case Hexagon::L2_ploadrit_io:
1470 case Hexagon::L2_ploadrif_io:
1471 case Hexagon::L2_ploadrht_io:
1472 case Hexagon::L2_ploadrhf_io:
1473 case Hexagon::L2_ploadrbt_io:
1474 case Hexagon::L2_ploadrbf_io:
1475 case Hexagon::L2_ploadruht_io:
1476 case Hexagon::L2_ploadruhf_io:
1477 case Hexagon::L2_ploadrubt_io:
1478 case Hexagon::L2_ploadrubf_io:
1479 case Hexagon::L2_ploadrdt_pi:
1480 case Hexagon::L2_ploadrdf_pi:
1481 case Hexagon::L2_ploadrit_pi:
1482 case Hexagon::L2_ploadrif_pi:
1483 case Hexagon::L2_ploadrht_pi:
1484 case Hexagon::L2_ploadrhf_pi:
1485 case Hexagon::L2_ploadrbt_pi:
1486 case Hexagon::L2_ploadrbf_pi:
1487 case Hexagon::L2_ploadruht_pi:
1488 case Hexagon::L2_ploadruhf_pi:
1489 case Hexagon::L2_ploadrubt_pi:
1490 case Hexagon::L2_ploadrubf_pi:
1491 case Hexagon::L4_ploadrdt_rr:
1492 case Hexagon::L4_ploadrdf_rr:
1493 case Hexagon::L4_ploadrbt_rr:
1494 case Hexagon::L4_ploadrbf_rr:
1495 case Hexagon::L4_ploadrubt_rr:
1496 case Hexagon::L4_ploadrubf_rr:
1497 case Hexagon::L4_ploadrht_rr:
1498 case Hexagon::L4_ploadrhf_rr:
1499 case Hexagon::L4_ploadruht_rr:
1500 case Hexagon::L4_ploadruhf_rr:
1501 case Hexagon::L4_ploadrit_rr:
1502 case Hexagon::L4_ploadrif_rr:
1507 // Returns true if an instruction is a conditional store.
1509 // Note: It doesn't include conditional new-value stores as they can't be
1510 // converted to .new predicate.
1512 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1514 // / \ (not OK. it will cause new-value store to be
1515 // / X conditional on p0.new while R2 producer is
1518 // p.new store p.old NV store
1519 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1525 // [if (p0)memw(R0+#0)=R2]
1527 // The above diagram shows the steps involoved in the conversion of a predicated
1528 // store instruction to its .new predicated new-value form.
1530 // The following set of instructions further explains the scenario where
1531 // conditional new-value store becomes invalid when promoted to .new predicate
1534 // { 1) if (p0) r0 = add(r1, r2)
1535 // 2) p0 = cmp.eq(r3, #0) }
1537 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1538 // the first two instructions because in instr 1, r0 is conditional on old value
1539 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1540 // is not valid for new-value stores.
1541 bool HexagonInstrInfo::
1542 isConditionalStore (const MachineInstr* MI) const {
1543 switch (MI->getOpcode())
1545 default: return false;
1546 case Hexagon::S4_storeirbt_io:
1547 case Hexagon::S4_storeirbf_io:
1548 case Hexagon::S4_pstorerbt_rr:
1549 case Hexagon::S4_pstorerbf_rr:
1550 case Hexagon::S2_pstorerbt_io:
1551 case Hexagon::S2_pstorerbf_io:
1552 case Hexagon::S2_pstorerbt_pi:
1553 case Hexagon::S2_pstorerbf_pi:
1554 case Hexagon::S2_pstorerdt_io:
1555 case Hexagon::S2_pstorerdf_io:
1556 case Hexagon::S4_pstorerdt_rr:
1557 case Hexagon::S4_pstorerdf_rr:
1558 case Hexagon::S2_pstorerdt_pi:
1559 case Hexagon::S2_pstorerdf_pi:
1560 case Hexagon::S2_pstorerht_io:
1561 case Hexagon::S2_pstorerhf_io:
1562 case Hexagon::S4_storeirht_io:
1563 case Hexagon::S4_storeirhf_io:
1564 case Hexagon::S4_pstorerht_rr:
1565 case Hexagon::S4_pstorerhf_rr:
1566 case Hexagon::S2_pstorerht_pi:
1567 case Hexagon::S2_pstorerhf_pi:
1568 case Hexagon::S2_pstorerit_io:
1569 case Hexagon::S2_pstorerif_io:
1570 case Hexagon::S4_storeirit_io:
1571 case Hexagon::S4_storeirif_io:
1572 case Hexagon::S4_pstorerit_rr:
1573 case Hexagon::S4_pstorerif_rr:
1574 case Hexagon::S2_pstorerit_pi:
1575 case Hexagon::S2_pstorerif_pi:
1577 // V4 global address store before promoting to dot new.
1578 case Hexagon::S4_pstorerdt_abs:
1579 case Hexagon::S4_pstorerdf_abs:
1580 case Hexagon::S4_pstorerbt_abs:
1581 case Hexagon::S4_pstorerbf_abs:
1582 case Hexagon::S4_pstorerht_abs:
1583 case Hexagon::S4_pstorerhf_abs:
1584 case Hexagon::S4_pstorerit_abs:
1585 case Hexagon::S4_pstorerif_abs:
1588 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1589 // from the "Conditional Store" list. Because a predicated new value store
1590 // would NOT be promoted to a double dot new store. See diagram below:
1591 // This function returns yes for those stores that are predicated but not
1592 // yet promoted to predicate dot new instructions.
1594 // +---------------------+
1595 // /-----| if (p0) memw(..)=r0 |---------\~
1596 // || +---------------------+ ||
1597 // promote || /\ /\ || promote
1599 // \||/ demote || \||/
1601 // +-------------------------+ || +-------------------------+
1602 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1603 // +-------------------------+ || +-------------------------+
1606 // promote || \/ NOT possible
1610 // +-----------------------------+
1611 // | if (p0.new) memw(..)=r0.new |
1612 // +-----------------------------+
1613 // Double Dot New Store
1619 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1620 if (isNewValue(MI) && isBranch(MI))
1625 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
1626 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
1629 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1630 return (getAddrMode(MI) == HexagonII::PostInc);
1633 // Returns true, if any one of the operands is a dot new
1634 // insn, whether it is predicated dot new or register dot new.
1635 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1636 return (isNewValueInst(MI) ||
1637 (isPredicated(MI) && isPredicatedNew(MI)));
1640 // Returns the most basic instruction for the .new predicated instructions and
1641 // new-value stores.
1642 // For example, all of the following instructions will be converted back to the
1643 // same instruction:
1644 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1645 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1646 // 3) if (p0.new) memw(R0+#0) = R1 --->
1649 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1651 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1652 NewOp = Hexagon::getPredOldOpcode(NewOp);
1653 assert(NewOp >= 0 &&
1654 "Couldn't change predicate new instruction to its old form.");
1657 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1658 NewOp = Hexagon::getNonNVStore(NewOp);
1659 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1664 // Return the new value instruction for a given store.
1665 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1666 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1667 if (NVOpcode >= 0) // Valid new-value store instruction.
1670 switch (MI->getOpcode()) {
1671 default: llvm_unreachable("Unknown .new type");
1672 case Hexagon::S4_storerb_ur:
1673 return Hexagon::S4_storerbnew_ur;
1675 case Hexagon::S4_storerh_ur:
1676 return Hexagon::S4_storerhnew_ur;
1678 case Hexagon::S4_storeri_ur:
1679 return Hexagon::S4_storerinew_ur;
1681 case Hexagon::S2_storerb_pci:
1682 return Hexagon::S2_storerb_pci;
1684 case Hexagon::S2_storeri_pci:
1685 return Hexagon::S2_storeri_pci;
1687 case Hexagon::S2_storerh_pci:
1688 return Hexagon::S2_storerh_pci;
1690 case Hexagon::S2_storerd_pci:
1691 return Hexagon::S2_storerd_pci;
1693 case Hexagon::S2_storerf_pci:
1694 return Hexagon::S2_storerf_pci;
1699 // Return .new predicate version for an instruction.
1700 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1701 const MachineBranchProbabilityInfo
1704 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1705 if (NewOpcode >= 0) // Valid predicate new instruction
1708 switch (MI->getOpcode()) {
1709 default: llvm_unreachable("Unknown .new type");
1711 case Hexagon::J2_jumpt:
1712 case Hexagon::J2_jumpf:
1713 return getDotNewPredJumpOp(MI, MBPI);
1715 case Hexagon::J2_jumprt:
1716 return Hexagon::J2_jumptnewpt;
1718 case Hexagon::J2_jumprf:
1719 return Hexagon::J2_jumprfnewpt;
1721 case Hexagon::JMPrett:
1722 return Hexagon::J2_jumprtnewpt;
1724 case Hexagon::JMPretf:
1725 return Hexagon::J2_jumprfnewpt;
1728 // Conditional combine
1729 case Hexagon::C2_ccombinewt:
1730 return Hexagon::C2_ccombinewnewt;
1731 case Hexagon::C2_ccombinewf:
1732 return Hexagon::C2_ccombinewnewf;
1737 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1738 const uint64_t F = MI->getDesc().TSFlags;
1740 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1743 /// immediateExtend - Changes the instruction in place to one using an immediate
1745 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1746 assert((isExtendable(MI)||isConstExtended(MI)) &&
1747 "Instruction must be extendable");
1748 // Find which operand is extendable.
1749 short ExtOpNum = getCExtOpNum(MI);
1750 MachineOperand &MO = MI->getOperand(ExtOpNum);
1751 // This needs to be something we understand.
1752 assert((MO.isMBB() || MO.isImm()) &&
1753 "Branch with unknown extendable field type");
1754 // Mark given operand as extended.
1755 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1758 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1759 const TargetSubtargetInfo &STI) const {
1760 const InstrItineraryData *II = STI.getInstrItineraryData();
1761 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1764 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1765 const MachineBasicBlock *MBB,
1766 const MachineFunction &MF) const {
1767 // Debug info is never a scheduling boundary. It's necessary to be explicit
1768 // due to the special treatment of IT instructions below, otherwise a
1769 // dbg_value followed by an IT will result in the IT instruction being
1770 // considered a scheduling hazard, which is wrong. It should be the actual
1771 // instruction preceding the dbg_value instruction(s), just like it is
1772 // when debug info is not present.
1773 if (MI->isDebugValue())
1776 // Terminators and labels can't be scheduled around.
1777 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1783 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1784 const uint64_t F = MI->getDesc().TSFlags;
1785 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1786 if (isExtended) // Instruction must be extended.
1789 unsigned isExtendable =
1790 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1794 short ExtOpNum = getCExtOpNum(MI);
1795 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1796 // Use MO operand flags to determine if MO
1797 // has the HMOTF_ConstExtended flag set.
1798 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1800 // If this is a Machine BB address we are talking about, and it is
1801 // not marked as extended, say so.
1805 // We could be using an instruction with an extendable immediate and shoehorn
1806 // a global address into it. If it is a global address it will be constant
1807 // extended. We do this for COMBINE.
1808 // We currently only handle isGlobal() because it is the only kind of
1809 // object we are going to end up with here for now.
1810 // In the future we probably should add isSymbol(), etc.
1811 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1812 MO.isJTI() || MO.isCPI())
1815 // If the extendable operand is not 'Immediate' type, the instruction should
1816 // have 'isExtended' flag set.
1817 assert(MO.isImm() && "Extendable operand must be Immediate type");
1819 int MinValue = getMinValue(MI);
1820 int MaxValue = getMaxValue(MI);
1821 int ImmValue = MO.getImm();
1823 return (ImmValue < MinValue || ImmValue > MaxValue);
1826 // Return the number of bytes required to encode the instruction.
1827 // Hexagon instructions are fixed length, 4 bytes, unless they
1828 // use a constant extender, which requires another 4 bytes.
1829 // For debug instructions and prolog labels, return 0.
1830 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
1832 if (MI->isDebugValue() || MI->isPosition())
1835 unsigned Size = MI->getDesc().getSize();
1837 // Assume the default insn size in case it cannot be determined
1838 // for whatever reason.
1839 Size = HEXAGON_INSTR_SIZE;
1841 if (isConstExtended(MI) || isExtended(MI))
1842 Size += HEXAGON_INSTR_SIZE;
1847 // Returns the opcode to use when converting MI, which is a conditional jump,
1848 // into a conditional instruction which uses the .new value of the predicate.
1849 // We also use branch probabilities to add a hint to the jump.
1851 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1853 MachineBranchProbabilityInfo *MBPI) const {
1855 // We assume that block can have at most two successors.
1857 MachineBasicBlock *Src = MI->getParent();
1858 MachineOperand *BrTarget = &MI->getOperand(1);
1859 MachineBasicBlock *Dst = BrTarget->getMBB();
1861 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1862 if (Prediction >= BranchProbability(1,2))
1865 switch (MI->getOpcode()) {
1866 case Hexagon::J2_jumpt:
1867 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1868 case Hexagon::J2_jumpf:
1869 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1872 llvm_unreachable("Unexpected jump instruction.");
1875 // Returns true if a particular operand is extendable for an instruction.
1876 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1877 unsigned short OperandNum) const {
1878 const uint64_t F = MI->getDesc().TSFlags;
1880 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1884 // Returns Operand Index for the constant extended instruction.
1885 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1886 const uint64_t F = MI->getDesc().TSFlags;
1887 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1890 // Returns the min value that doesn't need to be extended.
1891 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1892 const uint64_t F = MI->getDesc().TSFlags;
1893 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1894 & HexagonII::ExtentSignedMask;
1895 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1896 & HexagonII::ExtentBitsMask;
1898 if (isSigned) // if value is signed
1899 return -1U << (bits - 1);
1904 // Returns the max value that doesn't need to be extended.
1905 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1906 const uint64_t F = MI->getDesc().TSFlags;
1907 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1908 & HexagonII::ExtentSignedMask;
1909 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1910 & HexagonII::ExtentBitsMask;
1912 if (isSigned) // if value is signed
1913 return ~(-1U << (bits - 1));
1915 return ~(-1U << bits);
1918 // Returns true if an instruction can be converted into a non-extended
1919 // equivalent instruction.
1920 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1923 // Check if the instruction has a register form that uses register in place
1924 // of the extended operand, if so return that as the non-extended form.
1925 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1928 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1929 // Check addressing mode and retrieve non-ext equivalent instruction.
1931 switch (getAddrMode(MI)) {
1932 case HexagonII::Absolute :
1933 // Load/store with absolute addressing mode can be converted into
1934 // base+offset mode.
1935 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1937 case HexagonII::BaseImmOffset :
1938 // Load/store with base+offset addressing mode can be converted into
1939 // base+register offset addressing mode. However left shift operand should
1941 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1946 if (NonExtOpcode < 0)
1953 // Returns opcode of the non-extended equivalent instruction.
1954 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1956 // Check if the instruction has a register form that uses register in place
1957 // of the extended operand, if so return that as the non-extended form.
1958 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1959 if (NonExtOpcode >= 0)
1960 return NonExtOpcode;
1962 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1963 // Check addressing mode and retrieve non-ext equivalent instruction.
1964 switch (getAddrMode(MI)) {
1965 case HexagonII::Absolute :
1966 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1967 case HexagonII::BaseImmOffset :
1968 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1976 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1977 return (Opcode == Hexagon::J2_jumpt) ||
1978 (Opcode == Hexagon::J2_jumpf) ||
1979 (Opcode == Hexagon::J2_jumptnewpt) ||
1980 (Opcode == Hexagon::J2_jumpfnewpt) ||
1981 (Opcode == Hexagon::J2_jumpt) ||
1982 (Opcode == Hexagon::J2_jumpf);
1985 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
1986 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
1988 return !isPredicatedTrue(Cond[0].getImm());
1991 bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
1992 return (Opcode == Hexagon::ENDLOOP0 ||
1993 Opcode == Hexagon::ENDLOOP1);
1996 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
1997 unsigned &PredReg, unsigned &PredRegPos,
1998 unsigned &PredRegFlags) const {
2001 assert(Cond.size() == 2);
2002 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
2003 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
2006 PredReg = Cond[1].getReg();
2008 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
2010 if (Cond[1].isImplicit())
2011 PredRegFlags = RegState::Implicit;
2012 if (Cond[1].isUndef())
2013 PredRegFlags |= RegState::Undef;