1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonHazardRecognizer.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/CodeGen/DFAPacketizer.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineInstrBundle.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleDAG.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInstrDesc.h"
38 #include "llvm/MC/MCInstrItineraries.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/BranchProbability.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetSubtargetInfo.h"
56 #define DEBUG_TYPE "hexagon-instrinfo"
58 #define GET_INSTRINFO_CTOR_DTOR
59 #define GET_INSTRMAP_INFO
60 #include "HexagonGenInstrInfo.inc"
61 #include "HexagonGenDFAPacketizer.inc"
63 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
64 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
65 "packetization boundary."));
67 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
68 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
70 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
71 cl::Hidden, cl::ZeroOrMore, cl::init(false),
72 cl::desc("Disable schedule adjustment for new value stores."));
74 static cl::opt<bool> EnableTimingClassLatency(
75 "enable-timing-class-latency", cl::Hidden, cl::init(false),
76 cl::desc("Enable timing class latency"));
78 static cl::opt<bool> EnableALUForwarding(
79 "enable-alu-forwarding", cl::Hidden, cl::init(true),
80 cl::desc("Enable vec alu forwarding"));
82 static cl::opt<bool> EnableACCForwarding(
83 "enable-acc-forwarding", cl::Hidden, cl::init(true),
84 cl::desc("Enable vec acc forwarding"));
86 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
87 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
89 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
90 cl::init(true), cl::Hidden, cl::ZeroOrMore,
91 cl::desc("Use the DFA based hazard recognizer."));
94 /// Constants for Hexagon instructions.
96 const int Hexagon_MEMV_OFFSET_MAX_128B = 896; // #s4: -8*128...7*128
97 const int Hexagon_MEMV_OFFSET_MIN_128B = -1024; // #s4
98 const int Hexagon_MEMV_OFFSET_MAX = 448; // #s4: -8*64...7*64
99 const int Hexagon_MEMV_OFFSET_MIN = -512; // #s4
100 const int Hexagon_MEMW_OFFSET_MAX = 4095;
101 const int Hexagon_MEMW_OFFSET_MIN = -4096;
102 const int Hexagon_MEMD_OFFSET_MAX = 8191;
103 const int Hexagon_MEMD_OFFSET_MIN = -8192;
104 const int Hexagon_MEMH_OFFSET_MAX = 2047;
105 const int Hexagon_MEMH_OFFSET_MIN = -2048;
106 const int Hexagon_MEMB_OFFSET_MAX = 1023;
107 const int Hexagon_MEMB_OFFSET_MIN = -1024;
108 const int Hexagon_ADDI_OFFSET_MAX = 32767;
109 const int Hexagon_ADDI_OFFSET_MIN = -32768;
110 const int Hexagon_MEMD_AUTOINC_MAX = 56;
111 const int Hexagon_MEMD_AUTOINC_MIN = -64;
112 const int Hexagon_MEMW_AUTOINC_MAX = 28;
113 const int Hexagon_MEMW_AUTOINC_MIN = -32;
114 const int Hexagon_MEMH_AUTOINC_MAX = 14;
115 const int Hexagon_MEMH_AUTOINC_MIN = -16;
116 const int Hexagon_MEMB_AUTOINC_MAX = 7;
117 const int Hexagon_MEMB_AUTOINC_MIN = -8;
118 const int Hexagon_MEMV_AUTOINC_MAX = 192; // #s3
119 const int Hexagon_MEMV_AUTOINC_MIN = -256; // #s3
120 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384; // #s3
121 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3
123 // Pin the vtable to this file.
124 void HexagonInstrInfo::anchor() {}
126 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
127 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
130 static bool isIntRegForSubInst(unsigned Reg) {
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
135 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
136 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
140 /// Calculate number of instructions excluding the debug instructions.
141 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
142 MachineBasicBlock::const_instr_iterator MIE) {
144 for (; MIB != MIE; ++MIB) {
145 if (!MIB->isDebugValue())
151 /// Find the hardware loop instruction used to set-up the specified loop.
152 /// On Hexagon, we have two instructions used to set-up the hardware loop
153 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
154 /// to indicate the end of a loop.
155 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
156 MachineBasicBlock *TargetBB,
157 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
160 if (EndLoopOp == Hexagon::ENDLOOP0) {
161 LOOPi = Hexagon::J2_loop0i;
162 LOOPr = Hexagon::J2_loop0r;
163 } else { // EndLoopOp == Hexagon::EndLOOP1
164 LOOPi = Hexagon::J2_loop1i;
165 LOOPr = Hexagon::J2_loop1r;
168 // The loop set-up instruction will be in a predecessor block
169 for (MachineBasicBlock *PB : BB->predecessors()) {
170 // If this has been visited, already skip it.
171 if (!Visited.insert(PB).second)
175 for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
176 unsigned Opc = I->getOpcode();
177 if (Opc == LOOPi || Opc == LOOPr)
179 // We've reached a different loop, which means the loop01 has been
181 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
184 // Check the predecessors for the LOOP instruction.
185 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
191 /// Gather register def/uses from MI.
192 /// This treats possible (predicated) defs as actually happening ones
193 /// (conservatively).
194 static inline void parseOperands(const MachineInstr &MI,
195 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
199 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
200 const MachineOperand &MO = MI.getOperand(i);
205 unsigned Reg = MO.getReg();
210 Uses.push_back(MO.getReg());
213 Defs.push_back(MO.getReg());
217 // Position dependent, so check twice for swap.
218 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
220 case HexagonII::HSIG_None:
223 case HexagonII::HSIG_L1:
224 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
225 case HexagonII::HSIG_L2:
226 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
227 Gb == HexagonII::HSIG_A);
228 case HexagonII::HSIG_S1:
229 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
230 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
231 case HexagonII::HSIG_S2:
232 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
233 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
234 Gb == HexagonII::HSIG_A);
235 case HexagonII::HSIG_A:
236 return (Gb == HexagonII::HSIG_A);
237 case HexagonII::HSIG_Compound:
238 return (Gb == HexagonII::HSIG_Compound);
243 /// isLoadFromStackSlot - If the specified machine instruction is a direct
244 /// load from a stack slot, return the virtual or physical register number of
245 /// the destination along with the FrameIndex of the loaded stack slot. If
246 /// not, return 0. This predicate must return 0 if the instruction has
247 /// any side effects other than loading from the stack slot.
248 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
249 int &FrameIndex) const {
250 switch (MI.getOpcode()) {
253 case Hexagon::L2_loadri_io:
254 case Hexagon::L2_loadrd_io:
255 case Hexagon::V6_vL32b_ai:
256 case Hexagon::V6_vL32b_ai_128B:
257 case Hexagon::V6_vL32Ub_ai:
258 case Hexagon::V6_vL32Ub_ai_128B:
259 case Hexagon::LDriw_pred:
260 case Hexagon::LDriw_mod:
261 case Hexagon::PS_vloadrq_ai:
262 case Hexagon::PS_vloadrw_ai:
263 case Hexagon::PS_vloadrq_ai_128B:
264 case Hexagon::PS_vloadrw_ai_128B: {
265 const MachineOperand OpFI = MI.getOperand(1);
268 const MachineOperand OpOff = MI.getOperand(2);
269 if (!OpOff.isImm() || OpOff.getImm() != 0)
271 FrameIndex = OpFI.getIndex();
272 return MI.getOperand(0).getReg();
275 case Hexagon::L2_ploadrit_io:
276 case Hexagon::L2_ploadrif_io:
277 case Hexagon::L2_ploadrdt_io:
278 case Hexagon::L2_ploadrdf_io: {
279 const MachineOperand OpFI = MI.getOperand(2);
282 const MachineOperand OpOff = MI.getOperand(3);
283 if (!OpOff.isImm() || OpOff.getImm() != 0)
285 FrameIndex = OpFI.getIndex();
286 return MI.getOperand(0).getReg();
293 /// isStoreToStackSlot - If the specified machine instruction is a direct
294 /// store to a stack slot, return the virtual or physical register number of
295 /// the source reg along with the FrameIndex of the loaded stack slot. If
296 /// not, return 0. This predicate must return 0 if the instruction has
297 /// any side effects other than storing to the stack slot.
298 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
299 int &FrameIndex) const {
300 switch (MI.getOpcode()) {
303 case Hexagon::S2_storerb_io:
304 case Hexagon::S2_storerh_io:
305 case Hexagon::S2_storeri_io:
306 case Hexagon::S2_storerd_io:
307 case Hexagon::V6_vS32b_ai:
308 case Hexagon::V6_vS32b_ai_128B:
309 case Hexagon::V6_vS32Ub_ai:
310 case Hexagon::V6_vS32Ub_ai_128B:
311 case Hexagon::STriw_pred:
312 case Hexagon::STriw_mod:
313 case Hexagon::PS_vstorerq_ai:
314 case Hexagon::PS_vstorerw_ai:
315 case Hexagon::PS_vstorerq_ai_128B:
316 case Hexagon::PS_vstorerw_ai_128B: {
317 const MachineOperand &OpFI = MI.getOperand(0);
320 const MachineOperand &OpOff = MI.getOperand(1);
321 if (!OpOff.isImm() || OpOff.getImm() != 0)
323 FrameIndex = OpFI.getIndex();
324 return MI.getOperand(2).getReg();
327 case Hexagon::S2_pstorerbt_io:
328 case Hexagon::S2_pstorerbf_io:
329 case Hexagon::S2_pstorerht_io:
330 case Hexagon::S2_pstorerhf_io:
331 case Hexagon::S2_pstorerit_io:
332 case Hexagon::S2_pstorerif_io:
333 case Hexagon::S2_pstorerdt_io:
334 case Hexagon::S2_pstorerdf_io: {
335 const MachineOperand &OpFI = MI.getOperand(1);
338 const MachineOperand &OpOff = MI.getOperand(2);
339 if (!OpOff.isImm() || OpOff.getImm() != 0)
341 FrameIndex = OpFI.getIndex();
342 return MI.getOperand(3).getReg();
349 /// This function can analyze one/two way branching only and should (mostly) be
350 /// called by target independent side.
351 /// First entry is always the opcode of the branching instruction, except when
352 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
353 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
354 /// e.g. Jump_c p will have
358 /// Cond[0] = ENDLOOP
361 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
365 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
366 MachineBasicBlock *&TBB,
367 MachineBasicBlock *&FBB,
368 SmallVectorImpl<MachineOperand> &Cond,
369 bool AllowModify) const {
374 // If the block has no terminators, it just falls into the block after it.
375 MachineBasicBlock::instr_iterator I = MBB.instr_end();
376 if (I == MBB.instr_begin())
379 // A basic block may looks like this:
389 // It has two succs but does not have a terminator
390 // Don't know how to handle it.
394 // Don't analyze EH branches.
396 } while (I != MBB.instr_begin());
401 while (I->isDebugValue()) {
402 if (I == MBB.instr_begin())
407 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
408 I->getOperand(0).isMBB();
409 // Delete the J2_jump if it's equivalent to a fall-through.
410 if (AllowModify && JumpToBlock &&
411 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
412 DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
413 I->eraseFromParent();
415 if (I == MBB.instr_begin())
419 if (!isUnpredicatedTerminator(*I))
422 // Get the last instruction in the block.
423 MachineInstr *LastInst = &*I;
424 MachineInstr *SecondLastInst = nullptr;
425 // Find one more terminator if present.
427 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
429 SecondLastInst = &*I;
431 // This is a third branch.
434 if (I == MBB.instr_begin())
439 int LastOpcode = LastInst->getOpcode();
440 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
441 // If the branch target is not a basic block, it could be a tail call.
442 // (It is, if the target is a function.)
443 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
445 if (SecLastOpcode == Hexagon::J2_jump &&
446 !SecondLastInst->getOperand(0).isMBB())
449 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
450 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
452 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
455 // If there is only one terminator instruction, process it.
456 if (LastInst && !SecondLastInst) {
457 if (LastOpcode == Hexagon::J2_jump) {
458 TBB = LastInst->getOperand(0).getMBB();
461 if (isEndLoopN(LastOpcode)) {
462 TBB = LastInst->getOperand(0).getMBB();
463 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
464 Cond.push_back(LastInst->getOperand(0));
467 if (LastOpcodeHasJMP_c) {
468 TBB = LastInst->getOperand(1).getMBB();
469 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
470 Cond.push_back(LastInst->getOperand(0));
473 // Only supporting rr/ri versions of new-value jumps.
474 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
475 TBB = LastInst->getOperand(2).getMBB();
476 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
477 Cond.push_back(LastInst->getOperand(0));
478 Cond.push_back(LastInst->getOperand(1));
481 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
482 << " with one jump\n";);
483 // Otherwise, don't know what this is.
487 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
488 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
489 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
490 if (!SecondLastInst->getOperand(1).isMBB())
492 TBB = SecondLastInst->getOperand(1).getMBB();
493 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
494 Cond.push_back(SecondLastInst->getOperand(0));
495 FBB = LastInst->getOperand(0).getMBB();
499 // Only supporting rr/ri versions of new-value jumps.
500 if (SecLastOpcodeHasNVJump &&
501 (SecondLastInst->getNumExplicitOperands() == 3) &&
502 (LastOpcode == Hexagon::J2_jump)) {
503 TBB = SecondLastInst->getOperand(2).getMBB();
504 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
505 Cond.push_back(SecondLastInst->getOperand(0));
506 Cond.push_back(SecondLastInst->getOperand(1));
507 FBB = LastInst->getOperand(0).getMBB();
511 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
512 // executed, so remove it.
513 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
514 TBB = SecondLastInst->getOperand(0).getMBB();
515 I = LastInst->getIterator();
517 I->eraseFromParent();
521 // If the block ends with an ENDLOOP, and J2_jump, handle it.
522 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
523 TBB = SecondLastInst->getOperand(0).getMBB();
524 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525 Cond.push_back(SecondLastInst->getOperand(0));
526 FBB = LastInst->getOperand(0).getMBB();
529 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
530 << " with two jumps";);
531 // Otherwise, can't handle this.
535 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
536 int *BytesRemoved) const {
537 assert(!BytesRemoved && "code size not handled");
539 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
540 MachineBasicBlock::iterator I = MBB.end();
542 while (I != MBB.begin()) {
544 if (I->isDebugValue())
546 // Only removing branches from end of MBB.
549 if (Count && (I->getOpcode() == Hexagon::J2_jump))
550 llvm_unreachable("Malformed basic block: unconditional branch not last");
551 MBB.erase(&MBB.back());
558 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
559 MachineBasicBlock *TBB,
560 MachineBasicBlock *FBB,
561 ArrayRef<MachineOperand> Cond,
563 int *BytesAdded) const {
564 unsigned BOpc = Hexagon::J2_jump;
565 unsigned BccOpc = Hexagon::J2_jumpt;
566 assert(validateBranchCond(Cond) && "Invalid branching condition");
567 assert(TBB && "insertBranch must not be told to insert a fallthrough");
568 assert(!BytesAdded && "code size not handled");
570 // Check if reverseBranchCondition has asked to reverse this branch
571 // If we want to reverse the branch an odd number of times, we want
573 if (!Cond.empty() && Cond[0].isImm())
574 BccOpc = Cond[0].getImm();
578 // Due to a bug in TailMerging/CFG Optimization, we need to add a
579 // special case handling of a predicated jump followed by an
580 // unconditional jump. If not, Tail Merging and CFG Optimization go
581 // into an infinite loop.
582 MachineBasicBlock *NewTBB, *NewFBB;
583 SmallVector<MachineOperand, 4> Cond;
584 auto Term = MBB.getFirstTerminator();
585 if (Term != MBB.end() && isPredicated(*Term) &&
586 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
587 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
588 reverseBranchCondition(Cond);
590 return insertBranch(MBB, TBB, nullptr, Cond, DL);
592 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
593 } else if (isEndLoopN(Cond[0].getImm())) {
594 int EndLoopOp = Cond[0].getImm();
595 assert(Cond[1].isMBB());
596 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
597 // Check for it, and change the BB target if needed.
598 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
599 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
601 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
602 Loop->getOperand(0).setMBB(TBB);
603 // Add the ENDLOOP after the finding the LOOP0.
604 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
605 } else if (isNewValueJump(Cond[0].getImm())) {
606 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
608 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
609 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
610 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
611 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
612 if (Cond[2].isReg()) {
613 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
614 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
615 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
616 } else if(Cond[2].isImm()) {
617 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
618 addImm(Cond[2].getImm()).addMBB(TBB);
620 llvm_unreachable("Invalid condition for branching");
622 assert((Cond.size() == 2) && "Malformed cond vector");
623 const MachineOperand &RO = Cond[1];
624 unsigned Flags = getUndefRegState(RO.isUndef());
625 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
629 assert((!Cond.empty()) &&
630 "Cond. cannot be empty when multiple branchings are required");
631 assert((!isNewValueJump(Cond[0].getImm())) &&
632 "NV-jump cannot be inserted with another branch");
633 // Special case for hardware loops. The condition is a basic block.
634 if (isEndLoopN(Cond[0].getImm())) {
635 int EndLoopOp = Cond[0].getImm();
636 assert(Cond[1].isMBB());
637 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
638 // Check for it, and change the BB target if needed.
639 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
640 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
642 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
643 Loop->getOperand(0).setMBB(TBB);
644 // Add the ENDLOOP after the finding the LOOP0.
645 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
647 const MachineOperand &RO = Cond[1];
648 unsigned Flags = getUndefRegState(RO.isUndef());
649 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
651 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
656 /// Analyze the loop code to find the loop induction variable and compare used
657 /// to compute the number of iterations. Currently, we analyze loop that are
658 /// controlled using hardware loops. In this case, the induction variable
659 /// instruction is null. For all other cases, this function returns true, which
660 /// means we're unable to analyze it.
661 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L,
662 MachineInstr *&IndVarInst,
663 MachineInstr *&CmpInst) const {
665 MachineBasicBlock *LoopEnd = L.getBottomBlock();
666 MachineBasicBlock::iterator I = LoopEnd->getFirstTerminator();
667 // We really "analyze" only hardware loops right now.
668 if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
669 IndVarInst = nullptr;
676 /// Generate code to reduce the loop iteration by one and check if the loop is
677 /// finished. Return the value/register of the new loop count. this function
678 /// assumes the nth iteration is peeled first.
679 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
680 MachineInstr *IndVar, MachineInstr &Cmp,
681 SmallVectorImpl<MachineOperand> &Cond,
682 SmallVectorImpl<MachineInstr *> &PrevInsts,
683 unsigned Iter, unsigned MaxIter) const {
684 // We expect a hardware loop currently. This means that IndVar is set
685 // to null, and the compare is the ENDLOOP instruction.
686 assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
687 && "Expecting a hardware loop");
688 MachineFunction *MF = MBB.getParent();
689 DebugLoc DL = Cmp.getDebugLoc();
690 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
691 MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
692 Cmp.getOperand(0).getMBB(), VisitedBBs);
695 // If the loop trip count is a compile-time value, then just change the
697 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
698 Loop->getOpcode() == Hexagon::J2_loop1i) {
699 int64_t Offset = Loop->getOperand(1).getImm();
701 Loop->eraseFromParent();
703 Loop->getOperand(1).setImm(Offset - 1);
706 // The loop trip count is a run-time value. We generate code to subtract
707 // one from the trip count, and update the loop instruction.
708 assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
709 unsigned LoopCount = Loop->getOperand(1).getReg();
710 // Check if we're done with the loop.
711 unsigned LoopEnd = createVR(MF, MVT::i1);
712 MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
713 addReg(LoopCount).addImm(1);
714 unsigned NewLoopCount = createVR(MF, MVT::i32);
715 MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
716 addReg(LoopCount).addImm(-1);
717 // Update the previously generated instructions with the new loop counter.
718 for (SmallVectorImpl<MachineInstr *>::iterator I = PrevInsts.begin(),
719 E = PrevInsts.end(); I != E; ++I)
720 (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo());
722 PrevInsts.push_back(NewCmp);
723 PrevInsts.push_back(NewAdd);
724 // Insert the new loop instruction if this is the last time the loop is
727 BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
728 addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
729 // Delete the old loop instruction.
731 Loop->eraseFromParent();
732 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
733 Cond.push_back(NewCmp->getOperand(0));
737 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
738 unsigned NumCycles, unsigned ExtraPredCycles,
739 BranchProbability Probability) const {
740 return nonDbgBBSize(&MBB) <= 3;
743 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
744 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
745 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
747 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
750 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
751 unsigned NumInstrs, BranchProbability Probability) const {
752 return NumInstrs <= 4;
755 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
756 MachineBasicBlock::iterator I,
757 const DebugLoc &DL, unsigned DestReg,
758 unsigned SrcReg, bool KillSrc) const {
759 auto &HRI = getRegisterInfo();
760 unsigned KillFlag = getKillRegState(KillSrc);
762 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
763 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
764 .addReg(SrcReg, KillFlag);
767 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
768 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
769 .addReg(SrcReg, KillFlag);
772 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
773 // Map Pd = Ps to Pd = or(Ps, Ps).
774 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
775 .addReg(SrcReg).addReg(SrcReg, KillFlag);
778 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
779 Hexagon::IntRegsRegClass.contains(SrcReg)) {
780 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
781 .addReg(SrcReg, KillFlag);
784 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
785 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
786 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
787 .addReg(SrcReg, KillFlag);
790 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
791 Hexagon::IntRegsRegClass.contains(SrcReg)) {
792 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
793 .addReg(SrcReg, KillFlag);
796 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
797 Hexagon::IntRegsRegClass.contains(DestReg)) {
798 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
799 .addReg(SrcReg, KillFlag);
802 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
803 Hexagon::PredRegsRegClass.contains(DestReg)) {
804 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
805 .addReg(SrcReg, KillFlag);
808 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
809 Hexagon::IntRegsRegClass.contains(DestReg)) {
810 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
811 .addReg(SrcReg, KillFlag);
814 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
815 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
816 addReg(SrcReg, KillFlag);
819 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
820 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
821 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
822 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
823 .addReg(HiSrc, KillFlag)
824 .addReg(LoSrc, KillFlag);
827 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
828 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
830 .addReg(SrcReg, KillFlag);
833 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
834 Hexagon::VectorRegsRegClass.contains(DestReg)) {
835 llvm_unreachable("Unimplemented pred to vec");
838 if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
839 Hexagon::VectorRegsRegClass.contains(SrcReg)) {
840 llvm_unreachable("Unimplemented vec to pred");
843 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
844 unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
845 unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
846 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
847 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
848 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
849 .addReg(HiSrc, KillFlag);
850 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
851 .addReg(LoSrc, KillFlag);
856 // Show the invalid registers to ease debugging.
857 dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
858 << ": " << PrintReg(DestReg, &HRI)
859 << " = " << PrintReg(SrcReg, &HRI) << '\n';
861 llvm_unreachable("Unimplemented");
864 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
865 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
866 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
867 DebugLoc DL = MBB.findDebugLoc(I);
868 MachineFunction &MF = *MBB.getParent();
869 MachineFrameInfo &MFI = MF.getFrameInfo();
870 unsigned Align = MFI.getObjectAlignment(FI);
871 unsigned KillFlag = getKillRegState(isKill);
873 MachineMemOperand *MMO = MF.getMachineMemOperand(
874 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
875 MFI.getObjectSize(FI), Align);
877 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
878 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
879 .addFrameIndex(FI).addImm(0)
880 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
881 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
882 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
883 .addFrameIndex(FI).addImm(0)
884 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
885 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
886 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
887 .addFrameIndex(FI).addImm(0)
888 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
889 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
890 BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
891 .addFrameIndex(FI).addImm(0)
892 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
893 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
894 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B))
895 .addFrameIndex(FI).addImm(0)
896 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
897 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
898 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
899 .addFrameIndex(FI).addImm(0)
900 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
901 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
902 unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
903 : Hexagon::V6_vS32b_ai_128B;
904 BuildMI(MBB, I, DL, get(Opc))
905 .addFrameIndex(FI).addImm(0)
906 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
907 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
908 unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
909 : Hexagon::V6_vS32b_ai;
910 BuildMI(MBB, I, DL, get(Opc))
911 .addFrameIndex(FI).addImm(0)
912 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
913 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
914 unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
915 : Hexagon::PS_vstorerw_ai;
916 BuildMI(MBB, I, DL, get(Opc))
917 .addFrameIndex(FI).addImm(0)
918 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
919 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
920 unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
921 : Hexagon::PS_vstorerw_ai_128B;
922 BuildMI(MBB, I, DL, get(Opc))
923 .addFrameIndex(FI).addImm(0)
924 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
926 llvm_unreachable("Unimplemented");
930 void HexagonInstrInfo::loadRegFromStackSlot(
931 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
932 int FI, const TargetRegisterClass *RC,
933 const TargetRegisterInfo *TRI) const {
934 DebugLoc DL = MBB.findDebugLoc(I);
935 MachineFunction &MF = *MBB.getParent();
936 MachineFrameInfo &MFI = MF.getFrameInfo();
937 unsigned Align = MFI.getObjectAlignment(FI);
939 MachineMemOperand *MMO = MF.getMachineMemOperand(
940 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
941 MFI.getObjectSize(FI), Align);
943 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
944 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
945 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
946 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
947 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
948 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
949 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
950 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
951 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
952 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
953 BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
954 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
955 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
956 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg)
957 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
959 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
960 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
962 unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
963 : Hexagon::PS_vloadrw_ai_128B;
964 BuildMI(MBB, I, DL, get(Opc), DestReg)
965 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
966 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
967 unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
968 : Hexagon::V6_vL32b_ai_128B;
969 BuildMI(MBB, I, DL, get(Opc), DestReg)
970 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
972 unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
973 : Hexagon::V6_vL32b_ai;
974 BuildMI(MBB, I, DL, get(Opc), DestReg)
975 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
976 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
977 unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
978 : Hexagon::PS_vloadrw_ai;
979 BuildMI(MBB, I, DL, get(Opc), DestReg)
980 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
982 llvm_unreachable("Can't store this register to stack slot");
986 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
987 const MachineBasicBlock &B = *MI.getParent();
989 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
990 for (auto I = B.rbegin(); I != E; ++I)
991 Regs.stepBackward(*I);
994 /// expandPostRAPseudo - This function is called for all pseudo instructions
995 /// that remain after register allocation. Many pseudo instructions are
996 /// created to help register allocation. This is the place to convert them
997 /// into real instructions. The target can edit MI in place, or it can insert
998 /// new instructions and erase MI. The function should return true if
999 /// anything was changed.
1000 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1001 const HexagonRegisterInfo &HRI = getRegisterInfo();
1002 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1003 MachineBasicBlock &MBB = *MI.getParent();
1004 DebugLoc DL = MI.getDebugLoc();
1005 unsigned Opc = MI.getOpcode();
1006 const unsigned VecOffset = 1;
1009 case TargetOpcode::COPY: {
1010 MachineOperand &MD = MI.getOperand(0);
1011 MachineOperand &MS = MI.getOperand(1);
1012 MachineBasicBlock::iterator MBBI = MI.getIterator();
1013 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1014 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1015 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1020 case Hexagon::PS_aligna:
1021 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1022 .addReg(HRI.getFrameRegister())
1023 .addImm(-MI.getOperand(1).getImm());
1026 case Hexagon::V6_vassignp_128B:
1027 case Hexagon::V6_vassignp: {
1028 unsigned SrcReg = MI.getOperand(1).getReg();
1029 unsigned DstReg = MI.getOperand(0).getReg();
1030 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1031 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1032 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1033 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1037 case Hexagon::V6_lo_128B:
1038 case Hexagon::V6_lo: {
1039 unsigned SrcReg = MI.getOperand(1).getReg();
1040 unsigned DstReg = MI.getOperand(0).getReg();
1041 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1042 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1044 MRI.clearKillFlags(SrcSubLo);
1047 case Hexagon::V6_hi_128B:
1048 case Hexagon::V6_hi: {
1049 unsigned SrcReg = MI.getOperand(1).getReg();
1050 unsigned DstReg = MI.getOperand(0).getReg();
1051 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1052 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1054 MRI.clearKillFlags(SrcSubHi);
1057 case Hexagon::PS_vstorerw_ai:
1058 case Hexagon::PS_vstorerwu_ai:
1059 case Hexagon::PS_vstorerw_ai_128B:
1060 case Hexagon::PS_vstorerwu_ai_128B: {
1061 bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
1062 Opc == Hexagon::PS_vstorerwu_ai_128B);
1063 bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
1064 Opc == Hexagon::PS_vstorerw_ai_128B);
1065 unsigned SrcReg = MI.getOperand(2).getReg();
1066 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1067 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1070 NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1071 : Hexagon::V6_vS32b_ai;
1073 NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
1074 : Hexagon::V6_vS32Ub_ai;
1076 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1077 MachineInstr *MI1New =
1078 BuildMI(MBB, MI, DL, get(NewOpc))
1079 .add(MI.getOperand(0))
1080 .addImm(MI.getOperand(1).getImm())
1082 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1083 MI1New->getOperand(0).setIsKill(false);
1084 BuildMI(MBB, MI, DL, get(NewOpc))
1085 .add(MI.getOperand(0))
1086 // The Vectors are indexed in multiples of vector size.
1087 .addImm(MI.getOperand(1).getImm() + Offset)
1089 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1093 case Hexagon::PS_vloadrw_ai:
1094 case Hexagon::PS_vloadrwu_ai:
1095 case Hexagon::PS_vloadrw_ai_128B:
1096 case Hexagon::PS_vloadrwu_ai_128B: {
1097 bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
1098 Opc == Hexagon::PS_vloadrwu_ai_128B);
1099 bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
1100 Opc == Hexagon::PS_vloadrw_ai_128B);
1103 NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1104 : Hexagon::V6_vL32b_ai;
1106 NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
1107 : Hexagon::V6_vL32Ub_ai;
1109 unsigned DstReg = MI.getOperand(0).getReg();
1110 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1111 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1112 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1113 .add(MI.getOperand(1))
1114 .addImm(MI.getOperand(2).getImm());
1115 MI1New->getOperand(1).setIsKill(false);
1116 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1117 .add(MI.getOperand(1))
1118 // The Vectors are indexed in multiples of vector size.
1119 .addImm(MI.getOperand(2).getImm() + Offset)
1120 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1124 case Hexagon::PS_true: {
1125 unsigned Reg = MI.getOperand(0).getReg();
1126 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1127 .addReg(Reg, RegState::Undef)
1128 .addReg(Reg, RegState::Undef);
1132 case Hexagon::PS_false: {
1133 unsigned Reg = MI.getOperand(0).getReg();
1134 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1135 .addReg(Reg, RegState::Undef)
1136 .addReg(Reg, RegState::Undef);
1140 case Hexagon::PS_vmulw: {
1141 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1142 unsigned DstReg = MI.getOperand(0).getReg();
1143 unsigned Src1Reg = MI.getOperand(1).getReg();
1144 unsigned Src2Reg = MI.getOperand(2).getReg();
1145 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1146 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1147 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1148 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1149 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1150 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1153 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1154 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1158 MRI.clearKillFlags(Src1SubHi);
1159 MRI.clearKillFlags(Src1SubLo);
1160 MRI.clearKillFlags(Src2SubHi);
1161 MRI.clearKillFlags(Src2SubLo);
1164 case Hexagon::PS_vmulw_acc: {
1165 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1166 unsigned DstReg = MI.getOperand(0).getReg();
1167 unsigned Src1Reg = MI.getOperand(1).getReg();
1168 unsigned Src2Reg = MI.getOperand(2).getReg();
1169 unsigned Src3Reg = MI.getOperand(3).getReg();
1170 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1171 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1172 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1173 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1174 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1175 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1176 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1177 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1181 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1182 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1187 MRI.clearKillFlags(Src1SubHi);
1188 MRI.clearKillFlags(Src1SubLo);
1189 MRI.clearKillFlags(Src2SubHi);
1190 MRI.clearKillFlags(Src2SubLo);
1191 MRI.clearKillFlags(Src3SubHi);
1192 MRI.clearKillFlags(Src3SubLo);
1195 case Hexagon::PS_pselect: {
1196 const MachineOperand &Op0 = MI.getOperand(0);
1197 const MachineOperand &Op1 = MI.getOperand(1);
1198 const MachineOperand &Op2 = MI.getOperand(2);
1199 const MachineOperand &Op3 = MI.getOperand(3);
1200 unsigned Rd = Op0.getReg();
1201 unsigned Pu = Op1.getReg();
1202 unsigned Rs = Op2.getReg();
1203 unsigned Rt = Op3.getReg();
1204 DebugLoc DL = MI.getDebugLoc();
1205 unsigned K1 = getKillRegState(Op1.isKill());
1206 unsigned K2 = getKillRegState(Op2.isKill());
1207 unsigned K3 = getKillRegState(Op3.isKill());
1209 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1210 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1213 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1219 case Hexagon::PS_vselect:
1220 case Hexagon::PS_vselect_128B: {
1221 const MachineOperand &Op0 = MI.getOperand(0);
1222 const MachineOperand &Op1 = MI.getOperand(1);
1223 const MachineOperand &Op2 = MI.getOperand(2);
1224 const MachineOperand &Op3 = MI.getOperand(3);
1225 LivePhysRegs LiveAtMI(&HRI);
1226 getLiveRegsAt(LiveAtMI, MI);
1227 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1228 if (Op0.getReg() != Op2.getReg()) {
1229 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1234 T.addReg(Op0.getReg(), RegState::Implicit);
1237 if (Op0.getReg() != Op3.getReg()) {
1238 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1243 T.addReg(Op0.getReg(), RegState::Implicit);
1248 case Hexagon::PS_wselect:
1249 case Hexagon::PS_wselect_128B: {
1250 MachineOperand &Op0 = MI.getOperand(0);
1251 MachineOperand &Op1 = MI.getOperand(1);
1252 MachineOperand &Op2 = MI.getOperand(2);
1253 MachineOperand &Op3 = MI.getOperand(3);
1254 LivePhysRegs LiveAtMI(&HRI);
1255 getLiveRegsAt(LiveAtMI, MI);
1256 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1258 if (Op0.getReg() != Op2.getReg()) {
1259 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1260 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1261 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1267 T.addReg(Op0.getReg(), RegState::Implicit);
1270 if (Op0.getReg() != Op3.getReg()) {
1271 unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1272 unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1273 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1279 T.addReg(Op0.getReg(), RegState::Implicit);
1284 case Hexagon::PS_tailcall_i:
1285 MI.setDesc(get(Hexagon::J2_jump));
1287 case Hexagon::PS_tailcall_r:
1288 case Hexagon::PS_jmpret:
1289 MI.setDesc(get(Hexagon::J2_jumpr));
1291 case Hexagon::PS_jmprett:
1292 MI.setDesc(get(Hexagon::J2_jumprt));
1294 case Hexagon::PS_jmpretf:
1295 MI.setDesc(get(Hexagon::J2_jumprf));
1297 case Hexagon::PS_jmprettnewpt:
1298 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1300 case Hexagon::PS_jmpretfnewpt:
1301 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1303 case Hexagon::PS_jmprettnew:
1304 MI.setDesc(get(Hexagon::J2_jumprtnew));
1306 case Hexagon::PS_jmpretfnew:
1307 MI.setDesc(get(Hexagon::J2_jumprfnew));
1314 // We indicate that we want to reverse the branch by
1315 // inserting the reversed branching opcode.
1316 bool HexagonInstrInfo::reverseBranchCondition(
1317 SmallVectorImpl<MachineOperand> &Cond) const {
1320 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1321 unsigned opcode = Cond[0].getImm();
1323 assert(get(opcode).isBranch() && "Should be a branching condition.");
1324 if (isEndLoopN(opcode))
1326 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1327 Cond[0].setImm(NewOpcode);
1331 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1332 MachineBasicBlock::iterator MI) const {
1334 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1337 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1338 return getAddrMode(MI) == HexagonII::PostInc;
1341 // Returns true if an instruction is predicated irrespective of the predicate
1342 // sense. For example, all of the following will return true.
1343 // if (p0) R1 = add(R2, R3)
1344 // if (!p0) R1 = add(R2, R3)
1345 // if (p0.new) R1 = add(R2, R3)
1346 // if (!p0.new) R1 = add(R2, R3)
1347 // Note: New-value stores are not included here as in the current
1348 // implementation, we don't need to check their predicate sense.
1349 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1350 const uint64_t F = MI.getDesc().TSFlags;
1351 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1354 bool HexagonInstrInfo::PredicateInstruction(
1355 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1356 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1357 isEndLoopN(Cond[0].getImm())) {
1358 DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1361 int Opc = MI.getOpcode();
1362 assert (isPredicable(MI) && "Expected predicable instruction");
1363 bool invertJump = predOpcodeHasNot(Cond);
1365 // We have to predicate MI "in place", i.e. after this function returns,
1366 // MI will need to be transformed into a predicated form. To avoid com-
1367 // plicated manipulations with the operands (handling tied operands,
1368 // etc.), build a new temporary instruction, then overwrite MI with it.
1370 MachineBasicBlock &B = *MI.getParent();
1371 DebugLoc DL = MI.getDebugLoc();
1372 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1373 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1374 unsigned NOp = 0, NumOps = MI.getNumOperands();
1375 while (NOp < NumOps) {
1376 MachineOperand &Op = MI.getOperand(NOp);
1377 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1383 unsigned PredReg, PredRegPos, PredRegFlags;
1384 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1387 T.addReg(PredReg, PredRegFlags);
1388 while (NOp < NumOps)
1389 T.add(MI.getOperand(NOp++));
1391 MI.setDesc(get(PredOpc));
1392 while (unsigned n = MI.getNumOperands())
1393 MI.RemoveOperand(n-1);
1394 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1395 MI.addOperand(T->getOperand(i));
1397 MachineBasicBlock::instr_iterator TI = T->getIterator();
1400 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1401 MRI.clearKillFlags(PredReg);
1405 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1406 ArrayRef<MachineOperand> Pred2) const {
1411 bool HexagonInstrInfo::DefinesPredicate(
1412 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
1413 auto &HRI = getRegisterInfo();
1414 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1415 MachineOperand MO = MI.getOperand(oper);
1419 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1420 if (RC == &Hexagon::PredRegsRegClass) {
1425 } else if (MO.isRegMask()) {
1426 for (unsigned PR : Hexagon::PredRegsRegClass) {
1427 if (!MI.modifiesRegister(PR, &HRI))
1437 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1438 return MI.getDesc().isPredicable();
1441 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1442 const MachineBasicBlock *MBB,
1443 const MachineFunction &MF) const {
1444 // Debug info is never a scheduling boundary. It's necessary to be explicit
1445 // due to the special treatment of IT instructions below, otherwise a
1446 // dbg_value followed by an IT will result in the IT instruction being
1447 // considered a scheduling hazard, which is wrong. It should be the actual
1448 // instruction preceding the dbg_value instruction(s), just like it is
1449 // when debug info is not present.
1450 if (MI.isDebugValue())
1453 // Throwing call is a boundary.
1455 // Don't mess around with no return calls.
1456 if (doesNotReturn(MI))
1458 // If any of the block's successors is a landing pad, this could be a
1460 for (auto I : MBB->successors())
1465 // Terminators and labels can't be scheduled around.
1466 if (MI.getDesc().isTerminator() || MI.isPosition())
1469 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1475 /// Measure the specified inline asm to determine an approximation of its
1477 /// Comments (which run till the next SeparatorString or newline) do not
1478 /// count as an instruction.
1479 /// Any other non-whitespace text is considered an instruction, with
1480 /// multiple instructions separated by SeparatorString or newlines.
1481 /// Variable-length instructions are not handled here; this function
1482 /// may be overloaded in the target code to do that.
1483 /// Hexagon counts the number of ##'s and adjust for that many
1484 /// constant exenders.
1485 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1486 const MCAsmInfo &MAI) const {
1487 StringRef AStr(Str);
1488 // Count the number of instructions in the asm.
1489 bool atInsnStart = true;
1490 unsigned Length = 0;
1491 for (; *Str; ++Str) {
1492 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1493 strlen(MAI.getSeparatorString())) == 0)
1495 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1496 Length += MAI.getMaxInstLength();
1497 atInsnStart = false;
1499 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1500 MAI.getCommentString().size()) == 0)
1501 atInsnStart = false;
1504 // Add to size number of constant extenders seen * 4.
1505 StringRef Occ("##");
1506 Length += AStr.count(Occ)*4;
1510 ScheduleHazardRecognizer*
1511 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1512 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1513 if (UseDFAHazardRec) {
1514 auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
1515 return new HexagonHazardRecognizer(II, this, HST);
1517 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1520 /// \brief For a comparison instruction, return the source registers in
1521 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1522 /// compares against in CmpValue. Return true if the comparison instruction
1523 /// can be analyzed.
1524 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1525 unsigned &SrcReg2, int &Mask,
1527 unsigned Opc = MI.getOpcode();
1529 // Set mask and the first source register.
1531 case Hexagon::C2_cmpeq:
1532 case Hexagon::C2_cmpeqp:
1533 case Hexagon::C2_cmpgt:
1534 case Hexagon::C2_cmpgtp:
1535 case Hexagon::C2_cmpgtu:
1536 case Hexagon::C2_cmpgtup:
1537 case Hexagon::C4_cmpneq:
1538 case Hexagon::C4_cmplte:
1539 case Hexagon::C4_cmplteu:
1540 case Hexagon::C2_cmpeqi:
1541 case Hexagon::C2_cmpgti:
1542 case Hexagon::C2_cmpgtui:
1543 case Hexagon::C4_cmpneqi:
1544 case Hexagon::C4_cmplteui:
1545 case Hexagon::C4_cmpltei:
1546 SrcReg = MI.getOperand(1).getReg();
1549 case Hexagon::A4_cmpbeq:
1550 case Hexagon::A4_cmpbgt:
1551 case Hexagon::A4_cmpbgtu:
1552 case Hexagon::A4_cmpbeqi:
1553 case Hexagon::A4_cmpbgti:
1554 case Hexagon::A4_cmpbgtui:
1555 SrcReg = MI.getOperand(1).getReg();
1558 case Hexagon::A4_cmpheq:
1559 case Hexagon::A4_cmphgt:
1560 case Hexagon::A4_cmphgtu:
1561 case Hexagon::A4_cmpheqi:
1562 case Hexagon::A4_cmphgti:
1563 case Hexagon::A4_cmphgtui:
1564 SrcReg = MI.getOperand(1).getReg();
1569 // Set the value/second source register.
1571 case Hexagon::C2_cmpeq:
1572 case Hexagon::C2_cmpeqp:
1573 case Hexagon::C2_cmpgt:
1574 case Hexagon::C2_cmpgtp:
1575 case Hexagon::C2_cmpgtu:
1576 case Hexagon::C2_cmpgtup:
1577 case Hexagon::A4_cmpbeq:
1578 case Hexagon::A4_cmpbgt:
1579 case Hexagon::A4_cmpbgtu:
1580 case Hexagon::A4_cmpheq:
1581 case Hexagon::A4_cmphgt:
1582 case Hexagon::A4_cmphgtu:
1583 case Hexagon::C4_cmpneq:
1584 case Hexagon::C4_cmplte:
1585 case Hexagon::C4_cmplteu:
1586 SrcReg2 = MI.getOperand(2).getReg();
1589 case Hexagon::C2_cmpeqi:
1590 case Hexagon::C2_cmpgtui:
1591 case Hexagon::C2_cmpgti:
1592 case Hexagon::C4_cmpneqi:
1593 case Hexagon::C4_cmplteui:
1594 case Hexagon::C4_cmpltei:
1595 case Hexagon::A4_cmpbeqi:
1596 case Hexagon::A4_cmpbgti:
1597 case Hexagon::A4_cmpbgtui:
1598 case Hexagon::A4_cmpheqi:
1599 case Hexagon::A4_cmphgti:
1600 case Hexagon::A4_cmphgtui:
1602 Value = MI.getOperand(2).getImm();
1609 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1610 const MachineInstr &MI,
1611 unsigned *PredCost) const {
1612 return getInstrTimingClassLatency(ItinData, MI);
1615 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1616 const TargetSubtargetInfo &STI) const {
1617 const InstrItineraryData *II = STI.getInstrItineraryData();
1618 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1621 // Inspired by this pair:
1622 // %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1623 // S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1624 // Currently AA considers the addresses in these instructions to be aliasing.
1625 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1626 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1627 int OffsetA = 0, OffsetB = 0;
1628 unsigned SizeA = 0, SizeB = 0;
1630 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1631 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1634 // Instructions that are pure loads, not loads and stores like memops are not
1636 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1639 // Get base, offset, and access size in MIa.
1640 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1641 if (!BaseRegA || !SizeA)
1644 // Get base, offset, and access size in MIb.
1645 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
1646 if (!BaseRegB || !SizeB)
1649 if (BaseRegA != BaseRegB)
1652 // This is a mem access with the same base register and known offsets from it.
1654 if (OffsetA > OffsetB) {
1655 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1656 return (SizeB <= offDiff);
1657 } else if (OffsetA < OffsetB) {
1658 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1659 return (SizeA <= offDiff);
1665 /// If the instruction is an increment of a constant value, return the amount.
1666 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
1668 if (isPostIncrement(MI)) {
1669 unsigned AccessSize;
1670 return getBaseAndOffset(MI, Value, AccessSize);
1672 if (MI.getOpcode() == Hexagon::A2_addi) {
1673 Value = MI.getOperand(2).getImm();
1680 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
1681 MachineRegisterInfo &MRI = MF->getRegInfo();
1682 const TargetRegisterClass *TRC;
1683 if (VT == MVT::i1) {
1684 TRC = &Hexagon::PredRegsRegClass;
1685 } else if (VT == MVT::i32 || VT == MVT::f32) {
1686 TRC = &Hexagon::IntRegsRegClass;
1687 } else if (VT == MVT::i64 || VT == MVT::f64) {
1688 TRC = &Hexagon::DoubleRegsRegClass;
1690 llvm_unreachable("Cannot handle this register class");
1693 unsigned NewReg = MRI.createVirtualRegister(TRC);
1697 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
1698 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1701 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
1702 const uint64_t F = MI.getDesc().TSFlags;
1703 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
1706 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
1707 const MachineFunction *MF = MI.getParent()->getParent();
1708 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1709 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1712 && !(QII->isTC2Early(MI))
1713 && !(MI.getDesc().mayLoad())
1714 && !(MI.getDesc().mayStore())
1715 && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
1716 && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
1717 && !(QII->isMemOp(MI))
1726 // Return true if the instruction is a compund branch instruction.
1727 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
1728 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1731 bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const {
1732 return (MI.isBranch() && isPredicated(MI)) ||
1733 isConditionalTransfer(MI) ||
1734 isConditionalALU32(MI) ||
1735 isConditionalLoad(MI) ||
1736 // Predicated stores which don't have a .new on any operands.
1737 (MI.mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
1738 !isPredicatedNew(MI));
1741 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr &MI) const {
1742 switch (MI.getOpcode()) {
1743 case Hexagon::A2_paddf:
1744 case Hexagon::A2_paddfnew:
1745 case Hexagon::A2_paddif:
1746 case Hexagon::A2_paddifnew:
1747 case Hexagon::A2_paddit:
1748 case Hexagon::A2_padditnew:
1749 case Hexagon::A2_paddt:
1750 case Hexagon::A2_paddtnew:
1751 case Hexagon::A2_pandf:
1752 case Hexagon::A2_pandfnew:
1753 case Hexagon::A2_pandt:
1754 case Hexagon::A2_pandtnew:
1755 case Hexagon::A2_porf:
1756 case Hexagon::A2_porfnew:
1757 case Hexagon::A2_port:
1758 case Hexagon::A2_portnew:
1759 case Hexagon::A2_psubf:
1760 case Hexagon::A2_psubfnew:
1761 case Hexagon::A2_psubt:
1762 case Hexagon::A2_psubtnew:
1763 case Hexagon::A2_pxorf:
1764 case Hexagon::A2_pxorfnew:
1765 case Hexagon::A2_pxort:
1766 case Hexagon::A2_pxortnew:
1767 case Hexagon::A4_paslhf:
1768 case Hexagon::A4_paslhfnew:
1769 case Hexagon::A4_paslht:
1770 case Hexagon::A4_paslhtnew:
1771 case Hexagon::A4_pasrhf:
1772 case Hexagon::A4_pasrhfnew:
1773 case Hexagon::A4_pasrht:
1774 case Hexagon::A4_pasrhtnew:
1775 case Hexagon::A4_psxtbf:
1776 case Hexagon::A4_psxtbfnew:
1777 case Hexagon::A4_psxtbt:
1778 case Hexagon::A4_psxtbtnew:
1779 case Hexagon::A4_psxthf:
1780 case Hexagon::A4_psxthfnew:
1781 case Hexagon::A4_psxtht:
1782 case Hexagon::A4_psxthtnew:
1783 case Hexagon::A4_pzxtbf:
1784 case Hexagon::A4_pzxtbfnew:
1785 case Hexagon::A4_pzxtbt:
1786 case Hexagon::A4_pzxtbtnew:
1787 case Hexagon::A4_pzxthf:
1788 case Hexagon::A4_pzxthfnew:
1789 case Hexagon::A4_pzxtht:
1790 case Hexagon::A4_pzxthtnew:
1791 case Hexagon::C2_ccombinewf:
1792 case Hexagon::C2_ccombinewt:
1798 // FIXME - Function name and it's functionality don't match.
1799 // It should be renamed to hasPredNewOpcode()
1800 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr &MI) const {
1801 if (!MI.getDesc().mayLoad() || !isPredicated(MI))
1804 int PNewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
1805 // Instruction with valid predicated-new opcode can be promoted to .new.
1806 return PNewOpcode >= 0;
1809 // Returns true if an instruction is a conditional store.
1811 // Note: It doesn't include conditional new-value stores as they can't be
1812 // converted to .new predicate.
1813 bool HexagonInstrInfo::isConditionalStore(const MachineInstr &MI) const {
1814 switch (MI.getOpcode()) {
1815 default: return false;
1816 case Hexagon::S4_storeirbt_io:
1817 case Hexagon::S4_storeirbf_io:
1818 case Hexagon::S4_pstorerbt_rr:
1819 case Hexagon::S4_pstorerbf_rr:
1820 case Hexagon::S2_pstorerbt_io:
1821 case Hexagon::S2_pstorerbf_io:
1822 case Hexagon::S2_pstorerbt_pi:
1823 case Hexagon::S2_pstorerbf_pi:
1824 case Hexagon::S2_pstorerdt_io:
1825 case Hexagon::S2_pstorerdf_io:
1826 case Hexagon::S4_pstorerdt_rr:
1827 case Hexagon::S4_pstorerdf_rr:
1828 case Hexagon::S2_pstorerdt_pi:
1829 case Hexagon::S2_pstorerdf_pi:
1830 case Hexagon::S2_pstorerht_io:
1831 case Hexagon::S2_pstorerhf_io:
1832 case Hexagon::S4_storeirht_io:
1833 case Hexagon::S4_storeirhf_io:
1834 case Hexagon::S4_pstorerht_rr:
1835 case Hexagon::S4_pstorerhf_rr:
1836 case Hexagon::S2_pstorerht_pi:
1837 case Hexagon::S2_pstorerhf_pi:
1838 case Hexagon::S2_pstorerit_io:
1839 case Hexagon::S2_pstorerif_io:
1840 case Hexagon::S4_storeirit_io:
1841 case Hexagon::S4_storeirif_io:
1842 case Hexagon::S4_pstorerit_rr:
1843 case Hexagon::S4_pstorerif_rr:
1844 case Hexagon::S2_pstorerit_pi:
1845 case Hexagon::S2_pstorerif_pi:
1847 // V4 global address store before promoting to dot new.
1848 case Hexagon::S4_pstorerdt_abs:
1849 case Hexagon::S4_pstorerdf_abs:
1850 case Hexagon::S4_pstorerbt_abs:
1851 case Hexagon::S4_pstorerbf_abs:
1852 case Hexagon::S4_pstorerht_abs:
1853 case Hexagon::S4_pstorerhf_abs:
1854 case Hexagon::S4_pstorerit_abs:
1855 case Hexagon::S4_pstorerif_abs:
1858 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1859 // from the "Conditional Store" list. Because a predicated new value store
1860 // would NOT be promoted to a double dot new store.
1861 // This function returns yes for those stores that are predicated but not
1862 // yet promoted to predicate dot new instructions.
1866 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr &MI) const {
1867 switch (MI.getOpcode()) {
1868 case Hexagon::A2_tfrt:
1869 case Hexagon::A2_tfrf:
1870 case Hexagon::C2_cmoveit:
1871 case Hexagon::C2_cmoveif:
1872 case Hexagon::A2_tfrtnew:
1873 case Hexagon::A2_tfrfnew:
1874 case Hexagon::C2_cmovenewit:
1875 case Hexagon::C2_cmovenewif:
1876 case Hexagon::A2_tfrpt:
1877 case Hexagon::A2_tfrpf:
1886 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1887 // isFPImm and later getFPImm as well.
1888 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
1889 const uint64_t F = MI.getDesc().TSFlags;
1890 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1891 if (isExtended) // Instruction must be extended.
1894 unsigned isExtendable =
1895 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1902 short ExtOpNum = getCExtOpNum(MI);
1903 const MachineOperand &MO = MI.getOperand(ExtOpNum);
1904 // Use MO operand flags to determine if MO
1905 // has the HMOTF_ConstExtended flag set.
1906 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1908 // If this is a Machine BB address we are talking about, and it is
1909 // not marked as extended, say so.
1913 // We could be using an instruction with an extendable immediate and shoehorn
1914 // a global address into it. If it is a global address it will be constant
1915 // extended. We do this for COMBINE.
1916 // We currently only handle isGlobal() because it is the only kind of
1917 // object we are going to end up with here for now.
1918 // In the future we probably should add isSymbol(), etc.
1919 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1920 MO.isJTI() || MO.isCPI() || MO.isFPImm())
1923 // If the extendable operand is not 'Immediate' type, the instruction should
1924 // have 'isExtended' flag set.
1925 assert(MO.isImm() && "Extendable operand must be Immediate type");
1927 int MinValue = getMinValue(MI);
1928 int MaxValue = getMaxValue(MI);
1929 int ImmValue = MO.getImm();
1931 return (ImmValue < MinValue || ImmValue > MaxValue);
1934 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
1935 switch (MI.getOpcode()) {
1936 case Hexagon::L4_return :
1937 case Hexagon::L4_return_t :
1938 case Hexagon::L4_return_f :
1939 case Hexagon::L4_return_tnew_pnt :
1940 case Hexagon::L4_return_fnew_pnt :
1941 case Hexagon::L4_return_tnew_pt :
1942 case Hexagon::L4_return_fnew_pt :
1948 // Return true when ConsMI uses a register defined by ProdMI.
1949 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
1950 const MachineInstr &ConsMI) const {
1951 if (!ProdMI.getDesc().getNumDefs())
1954 auto &HRI = getRegisterInfo();
1956 SmallVector<unsigned, 4> DefsA;
1957 SmallVector<unsigned, 4> DefsB;
1958 SmallVector<unsigned, 8> UsesA;
1959 SmallVector<unsigned, 8> UsesB;
1961 parseOperands(ProdMI, DefsA, UsesA);
1962 parseOperands(ConsMI, DefsB, UsesB);
1964 for (auto &RegA : DefsA)
1965 for (auto &RegB : UsesB) {
1966 // True data dependency.
1970 if (Hexagon::DoubleRegsRegClass.contains(RegA))
1971 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1972 if (RegB == *SubRegs)
1975 if (Hexagon::DoubleRegsRegClass.contains(RegB))
1976 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1977 if (RegA == *SubRegs)
1984 // Returns true if the instruction is alread a .cur.
1985 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
1986 switch (MI.getOpcode()) {
1987 case Hexagon::V6_vL32b_cur_pi:
1988 case Hexagon::V6_vL32b_cur_ai:
1989 case Hexagon::V6_vL32b_cur_pi_128B:
1990 case Hexagon::V6_vL32b_cur_ai_128B:
1996 // Returns true, if any one of the operands is a dot new
1997 // insn, whether it is predicated dot new or register dot new.
1998 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
1999 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2005 /// Symmetrical. See if these two instructions are fit for duplex pair.
2006 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2007 const MachineInstr &MIb) const {
2008 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
2009 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
2010 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2013 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
2014 if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2018 unsigned SchedClass = MI.getDesc().getSchedClass();
2019 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
2024 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2025 return (Opcode == Hexagon::ENDLOOP0 ||
2026 Opcode == Hexagon::ENDLOOP1);
2029 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2031 case MachineOperand::MO_MachineBasicBlock:
2032 case MachineOperand::MO_GlobalAddress:
2033 case MachineOperand::MO_ExternalSymbol:
2034 case MachineOperand::MO_JumpTableIndex:
2035 case MachineOperand::MO_ConstantPoolIndex:
2036 case MachineOperand::MO_BlockAddress:
2043 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2044 const MCInstrDesc &MID = MI.getDesc();
2045 const uint64_t F = MID.TSFlags;
2046 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2049 // TODO: This is largely obsolete now. Will need to be removed
2050 // in consecutive patches.
2051 switch (MI.getOpcode()) {
2052 // PS_fi and PS_fia remain special cases.
2053 case Hexagon::PS_fi:
2054 case Hexagon::PS_fia:
2062 // This returns true in two cases:
2063 // - The OP code itself indicates that this is an extended instruction.
2064 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2065 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2066 // First check if this is permanently extended op code.
2067 const uint64_t F = MI.getDesc().TSFlags;
2068 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2070 // Use MO operand flags to determine if one of MI's operands
2071 // has HMOTF_ConstExtended flag set.
2072 for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
2073 E = MI.operands_end(); I != E; ++I) {
2074 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2080 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2081 unsigned Opcode = MI.getOpcode();
2082 const uint64_t F = get(Opcode).TSFlags;
2083 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2086 // No V60 HVX VMEM with A_INDIRECT.
2087 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2088 const MachineInstr &J) const {
2089 if (!isV60VectorInstruction(I))
2091 if (!I.mayLoad() && !I.mayStore())
2093 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2096 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2097 switch (MI.getOpcode()) {
2098 case Hexagon::J2_callr :
2099 case Hexagon::J2_callrf :
2100 case Hexagon::J2_callrt :
2101 case Hexagon::PS_call_nr :
2107 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2108 switch (MI.getOpcode()) {
2109 case Hexagon::L4_return :
2110 case Hexagon::L4_return_t :
2111 case Hexagon::L4_return_f :
2112 case Hexagon::L4_return_fnew_pnt :
2113 case Hexagon::L4_return_fnew_pt :
2114 case Hexagon::L4_return_tnew_pnt :
2115 case Hexagon::L4_return_tnew_pt :
2121 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2122 switch (MI.getOpcode()) {
2123 case Hexagon::J2_jumpr :
2124 case Hexagon::J2_jumprt :
2125 case Hexagon::J2_jumprf :
2126 case Hexagon::J2_jumprtnewpt :
2127 case Hexagon::J2_jumprfnewpt :
2128 case Hexagon::J2_jumprtnew :
2129 case Hexagon::J2_jumprfnew :
2135 // Return true if a given MI can accommodate given offset.
2136 // Use abs estimate as oppose to the exact number.
2137 // TODO: This will need to be changed to use MC level
2138 // definition of instruction extendable field size.
2139 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2140 unsigned offset) const {
2141 // This selection of jump instructions matches to that what
2142 // AnalyzeBranch can parse, plus NVJ.
2143 if (isNewValueJump(MI)) // r9:2
2144 return isInt<11>(offset);
2146 switch (MI.getOpcode()) {
2147 // Still missing Jump to address condition on register value.
2150 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2151 case Hexagon::J2_call:
2152 case Hexagon::PS_call_nr:
2153 return isInt<24>(offset);
2154 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2155 case Hexagon::J2_jumpf:
2156 case Hexagon::J2_jumptnew:
2157 case Hexagon::J2_jumptnewpt:
2158 case Hexagon::J2_jumpfnew:
2159 case Hexagon::J2_jumpfnewpt:
2160 case Hexagon::J2_callt:
2161 case Hexagon::J2_callf:
2162 return isInt<17>(offset);
2163 case Hexagon::J2_loop0i:
2164 case Hexagon::J2_loop0iext:
2165 case Hexagon::J2_loop0r:
2166 case Hexagon::J2_loop0rext:
2167 case Hexagon::J2_loop1i:
2168 case Hexagon::J2_loop1iext:
2169 case Hexagon::J2_loop1r:
2170 case Hexagon::J2_loop1rext:
2171 return isInt<9>(offset);
2172 // TODO: Add all the compound branches here. Can we do this in Relation model?
2173 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2174 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2175 return isInt<11>(offset);
2179 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
2180 const MachineInstr &ESMI) const {
2181 bool isLate = isLateResultInstr(LRMI);
2182 bool isEarly = isEarlySourceInstr(ESMI);
2184 DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2186 DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2189 if (isLate && isEarly) {
2190 DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2197 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
2198 switch (MI.getOpcode()) {
2199 case TargetOpcode::EXTRACT_SUBREG:
2200 case TargetOpcode::INSERT_SUBREG:
2201 case TargetOpcode::SUBREG_TO_REG:
2202 case TargetOpcode::REG_SEQUENCE:
2203 case TargetOpcode::IMPLICIT_DEF:
2204 case TargetOpcode::COPY:
2205 case TargetOpcode::INLINEASM:
2206 case TargetOpcode::PHI:
2212 unsigned SchedClass = MI.getDesc().getSchedClass();
2214 switch (SchedClass) {
2215 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2216 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2217 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2218 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2219 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2220 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2221 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2222 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
2223 case Hexagon::Sched::V2LDST_tc_st_SLOT0:
2224 case Hexagon::Sched::V2LDST_tc_st_SLOT01:
2225 case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
2226 case Hexagon::Sched::V4LDST_tc_st_SLOT0:
2227 case Hexagon::Sched::V4LDST_tc_st_SLOT01:
2233 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2234 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2235 // resource, but all operands can be received late like an ALU instruction.
2236 return MI.getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
2239 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2240 unsigned Opcode = MI.getOpcode();
2241 return Opcode == Hexagon::J2_loop0i ||
2242 Opcode == Hexagon::J2_loop0r ||
2243 Opcode == Hexagon::J2_loop0iext ||
2244 Opcode == Hexagon::J2_loop0rext ||
2245 Opcode == Hexagon::J2_loop1i ||
2246 Opcode == Hexagon::J2_loop1r ||
2247 Opcode == Hexagon::J2_loop1iext ||
2248 Opcode == Hexagon::J2_loop1rext;
2251 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2252 switch (MI.getOpcode()) {
2253 default: return false;
2254 case Hexagon::L4_iadd_memopw_io :
2255 case Hexagon::L4_isub_memopw_io :
2256 case Hexagon::L4_add_memopw_io :
2257 case Hexagon::L4_sub_memopw_io :
2258 case Hexagon::L4_and_memopw_io :
2259 case Hexagon::L4_or_memopw_io :
2260 case Hexagon::L4_iadd_memoph_io :
2261 case Hexagon::L4_isub_memoph_io :
2262 case Hexagon::L4_add_memoph_io :
2263 case Hexagon::L4_sub_memoph_io :
2264 case Hexagon::L4_and_memoph_io :
2265 case Hexagon::L4_or_memoph_io :
2266 case Hexagon::L4_iadd_memopb_io :
2267 case Hexagon::L4_isub_memopb_io :
2268 case Hexagon::L4_add_memopb_io :
2269 case Hexagon::L4_sub_memopb_io :
2270 case Hexagon::L4_and_memopb_io :
2271 case Hexagon::L4_or_memopb_io :
2272 case Hexagon::L4_ior_memopb_io:
2273 case Hexagon::L4_ior_memoph_io:
2274 case Hexagon::L4_ior_memopw_io:
2275 case Hexagon::L4_iand_memopb_io:
2276 case Hexagon::L4_iand_memoph_io:
2277 case Hexagon::L4_iand_memopw_io:
2283 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2284 const uint64_t F = MI.getDesc().TSFlags;
2285 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2288 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2289 const uint64_t F = get(Opcode).TSFlags;
2290 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2293 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2294 return isNewValueJump(MI) || isNewValueStore(MI);
2297 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2298 return isNewValue(MI) && MI.isBranch();
2301 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2302 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2305 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2306 const uint64_t F = MI.getDesc().TSFlags;
2307 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2310 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2311 const uint64_t F = get(Opcode).TSFlags;
2312 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2315 // Returns true if a particular operand is extendable for an instruction.
2316 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2317 unsigned OperandNum) const {
2318 const uint64_t F = MI.getDesc().TSFlags;
2319 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2323 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2324 const uint64_t F = MI.getDesc().TSFlags;
2325 assert(isPredicated(MI));
2326 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2329 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2330 const uint64_t F = get(Opcode).TSFlags;
2331 assert(isPredicated(Opcode));
2332 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2335 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2336 const uint64_t F = MI.getDesc().TSFlags;
2337 return !((F >> HexagonII::PredicatedFalsePos) &
2338 HexagonII::PredicatedFalseMask);
2341 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2342 const uint64_t F = get(Opcode).TSFlags;
2343 // Make sure that the instruction is predicated.
2344 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2345 return !((F >> HexagonII::PredicatedFalsePos) &
2346 HexagonII::PredicatedFalseMask);
2349 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2350 const uint64_t F = get(Opcode).TSFlags;
2351 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2354 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2355 const uint64_t F = get(Opcode).TSFlags;
2356 return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2359 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2360 const uint64_t F = get(Opcode).TSFlags;
2361 assert(get(Opcode).isBranch() &&
2362 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2363 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2366 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2367 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2368 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2369 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2370 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2373 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2374 switch (MI.getOpcode()) {
2376 case Hexagon::L2_loadrb_io:
2377 case Hexagon::L4_loadrb_ur:
2378 case Hexagon::L4_loadrb_ap:
2379 case Hexagon::L2_loadrb_pr:
2380 case Hexagon::L2_loadrb_pbr:
2381 case Hexagon::L2_loadrb_pi:
2382 case Hexagon::L2_loadrb_pci:
2383 case Hexagon::L2_loadrb_pcr:
2384 case Hexagon::L2_loadbsw2_io:
2385 case Hexagon::L4_loadbsw2_ur:
2386 case Hexagon::L4_loadbsw2_ap:
2387 case Hexagon::L2_loadbsw2_pr:
2388 case Hexagon::L2_loadbsw2_pbr:
2389 case Hexagon::L2_loadbsw2_pi:
2390 case Hexagon::L2_loadbsw2_pci:
2391 case Hexagon::L2_loadbsw2_pcr:
2392 case Hexagon::L2_loadbsw4_io:
2393 case Hexagon::L4_loadbsw4_ur:
2394 case Hexagon::L4_loadbsw4_ap:
2395 case Hexagon::L2_loadbsw4_pr:
2396 case Hexagon::L2_loadbsw4_pbr:
2397 case Hexagon::L2_loadbsw4_pi:
2398 case Hexagon::L2_loadbsw4_pci:
2399 case Hexagon::L2_loadbsw4_pcr:
2400 case Hexagon::L4_loadrb_rr:
2401 case Hexagon::L2_ploadrbt_io:
2402 case Hexagon::L2_ploadrbt_pi:
2403 case Hexagon::L2_ploadrbf_io:
2404 case Hexagon::L2_ploadrbf_pi:
2405 case Hexagon::L2_ploadrbtnew_io:
2406 case Hexagon::L2_ploadrbfnew_io:
2407 case Hexagon::L4_ploadrbt_rr:
2408 case Hexagon::L4_ploadrbf_rr:
2409 case Hexagon::L4_ploadrbtnew_rr:
2410 case Hexagon::L4_ploadrbfnew_rr:
2411 case Hexagon::L2_ploadrbtnew_pi:
2412 case Hexagon::L2_ploadrbfnew_pi:
2413 case Hexagon::L4_ploadrbt_abs:
2414 case Hexagon::L4_ploadrbf_abs:
2415 case Hexagon::L4_ploadrbtnew_abs:
2416 case Hexagon::L4_ploadrbfnew_abs:
2417 case Hexagon::L2_loadrbgp:
2419 case Hexagon::L2_loadrh_io:
2420 case Hexagon::L4_loadrh_ur:
2421 case Hexagon::L4_loadrh_ap:
2422 case Hexagon::L2_loadrh_pr:
2423 case Hexagon::L2_loadrh_pbr:
2424 case Hexagon::L2_loadrh_pi:
2425 case Hexagon::L2_loadrh_pci:
2426 case Hexagon::L2_loadrh_pcr:
2427 case Hexagon::L4_loadrh_rr:
2428 case Hexagon::L2_ploadrht_io:
2429 case Hexagon::L2_ploadrht_pi:
2430 case Hexagon::L2_ploadrhf_io:
2431 case Hexagon::L2_ploadrhf_pi:
2432 case Hexagon::L2_ploadrhtnew_io:
2433 case Hexagon::L2_ploadrhfnew_io:
2434 case Hexagon::L4_ploadrht_rr:
2435 case Hexagon::L4_ploadrhf_rr:
2436 case Hexagon::L4_ploadrhtnew_rr:
2437 case Hexagon::L4_ploadrhfnew_rr:
2438 case Hexagon::L2_ploadrhtnew_pi:
2439 case Hexagon::L2_ploadrhfnew_pi:
2440 case Hexagon::L4_ploadrht_abs:
2441 case Hexagon::L4_ploadrhf_abs:
2442 case Hexagon::L4_ploadrhtnew_abs:
2443 case Hexagon::L4_ploadrhfnew_abs:
2444 case Hexagon::L2_loadrhgp:
2451 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2452 const uint64_t F = MI.getDesc().TSFlags;
2453 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2456 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2457 switch (MI.getOpcode()) {
2458 case Hexagon::STriw_pred :
2459 case Hexagon::LDriw_pred :
2466 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2470 for (auto &Op : MI.operands())
2471 if (Op.isGlobal() || Op.isSymbol())
2476 // Returns true when SU has a timing class TC1.
2477 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2478 unsigned SchedClass = MI.getDesc().getSchedClass();
2479 switch (SchedClass) {
2480 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2481 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2482 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2483 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2484 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2485 //case Hexagon::Sched::M_tc_1_SLOT23:
2486 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2487 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2495 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2496 unsigned SchedClass = MI.getDesc().getSchedClass();
2497 switch (SchedClass) {
2498 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
2499 case Hexagon::Sched::ALU64_tc_2_SLOT23:
2500 case Hexagon::Sched::CR_tc_2_SLOT3:
2501 case Hexagon::Sched::M_tc_2_SLOT23:
2502 case Hexagon::Sched::S_2op_tc_2_SLOT23:
2503 case Hexagon::Sched::S_3op_tc_2_SLOT23:
2511 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2512 unsigned SchedClass = MI.getDesc().getSchedClass();
2513 switch (SchedClass) {
2514 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
2515 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
2516 case Hexagon::Sched::ALU64_tc_2early_SLOT23:
2517 case Hexagon::Sched::CR_tc_2early_SLOT23:
2518 case Hexagon::Sched::CR_tc_2early_SLOT3:
2519 case Hexagon::Sched::J_tc_2early_SLOT0123:
2520 case Hexagon::Sched::J_tc_2early_SLOT2:
2521 case Hexagon::Sched::J_tc_2early_SLOT23:
2522 case Hexagon::Sched::S_2op_tc_2early_SLOT23:
2523 case Hexagon::Sched::S_3op_tc_2early_SLOT23:
2531 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2532 unsigned SchedClass = MI.getDesc().getSchedClass();
2533 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
2536 // Schedule this ASAP.
2537 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2538 const MachineInstr &MI2) const {
2539 if (mayBeCurLoad(MI1)) {
2540 // if (result of SU is used in Next) return true;
2541 unsigned DstReg = MI1.getOperand(0).getReg();
2542 int N = MI2.getNumOperands();
2543 for (int I = 0; I < N; I++)
2544 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2547 if (mayBeNewStore(MI2))
2548 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2549 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2550 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2555 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr &MI) const {
2556 const uint64_t V = getType(MI);
2557 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2560 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2562 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2563 if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2564 VT == MVT::v32i16 || VT == MVT::v64i8) {
2565 return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2566 Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2567 (Offset & 0x3f) == 0);
2570 if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2571 VT == MVT::v64i16 || VT == MVT::v128i8) {
2572 return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2573 Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2574 (Offset & 0x7f) == 0);
2576 if (VT == MVT::i64) {
2577 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2578 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2579 (Offset & 0x7) == 0);
2581 if (VT == MVT::i32) {
2582 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2583 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2584 (Offset & 0x3) == 0);
2586 if (VT == MVT::i16) {
2587 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2588 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2589 (Offset & 0x1) == 0);
2591 if (VT == MVT::i8) {
2592 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2593 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2595 llvm_unreachable("Not an auto-inc opc!");
2598 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2599 bool Extend) const {
2600 // This function is to check whether the "Offset" is in the correct range of
2601 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2602 // inserted to calculate the final address. Due to this reason, the function
2603 // assumes that the "Offset" has correct alignment.
2604 // We used to assert if the offset was not properly aligned, however,
2605 // there are cases where a misaligned pointer recast can cause this
2606 // problem, and we need to allow for it. The front end warns of such
2607 // misaligns with respect to load size.
2610 case Hexagon::PS_vstorerq_ai:
2611 case Hexagon::PS_vstorerw_ai:
2612 case Hexagon::PS_vloadrq_ai:
2613 case Hexagon::PS_vloadrw_ai:
2614 case Hexagon::V6_vL32b_ai:
2615 case Hexagon::V6_vS32b_ai:
2616 case Hexagon::V6_vL32Ub_ai:
2617 case Hexagon::V6_vS32Ub_ai:
2618 return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
2619 (Offset <= Hexagon_MEMV_OFFSET_MAX);
2621 case Hexagon::PS_vstorerq_ai_128B:
2622 case Hexagon::PS_vstorerw_ai_128B:
2623 case Hexagon::PS_vloadrq_ai_128B:
2624 case Hexagon::PS_vloadrw_ai_128B:
2625 case Hexagon::V6_vL32b_ai_128B:
2626 case Hexagon::V6_vS32b_ai_128B:
2627 case Hexagon::V6_vL32Ub_ai_128B:
2628 case Hexagon::V6_vS32Ub_ai_128B:
2629 return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
2630 (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
2632 case Hexagon::J2_loop0i:
2633 case Hexagon::J2_loop1i:
2634 return isUInt<10>(Offset);
2636 case Hexagon::S4_storeirb_io:
2637 case Hexagon::S4_storeirbt_io:
2638 case Hexagon::S4_storeirbf_io:
2639 return isUInt<6>(Offset);
2641 case Hexagon::S4_storeirh_io:
2642 case Hexagon::S4_storeirht_io:
2643 case Hexagon::S4_storeirhf_io:
2644 return isShiftedUInt<6,1>(Offset);
2646 case Hexagon::S4_storeiri_io:
2647 case Hexagon::S4_storeirit_io:
2648 case Hexagon::S4_storeirif_io:
2649 return isShiftedUInt<6,2>(Offset);
2656 case Hexagon::L2_loadri_io:
2657 case Hexagon::S2_storeri_io:
2658 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2659 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2661 case Hexagon::L2_loadrd_io:
2662 case Hexagon::S2_storerd_io:
2663 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2664 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2666 case Hexagon::L2_loadrh_io:
2667 case Hexagon::L2_loadruh_io:
2668 case Hexagon::S2_storerh_io:
2669 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2670 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2672 case Hexagon::L2_loadrb_io:
2673 case Hexagon::L2_loadrub_io:
2674 case Hexagon::S2_storerb_io:
2675 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2676 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2678 case Hexagon::A2_addi:
2679 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2680 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2682 case Hexagon::L4_iadd_memopw_io :
2683 case Hexagon::L4_isub_memopw_io :
2684 case Hexagon::L4_add_memopw_io :
2685 case Hexagon::L4_sub_memopw_io :
2686 case Hexagon::L4_and_memopw_io :
2687 case Hexagon::L4_or_memopw_io :
2688 return (0 <= Offset && Offset <= 255);
2690 case Hexagon::L4_iadd_memoph_io :
2691 case Hexagon::L4_isub_memoph_io :
2692 case Hexagon::L4_add_memoph_io :
2693 case Hexagon::L4_sub_memoph_io :
2694 case Hexagon::L4_and_memoph_io :
2695 case Hexagon::L4_or_memoph_io :
2696 return (0 <= Offset && Offset <= 127);
2698 case Hexagon::L4_iadd_memopb_io :
2699 case Hexagon::L4_isub_memopb_io :
2700 case Hexagon::L4_add_memopb_io :
2701 case Hexagon::L4_sub_memopb_io :
2702 case Hexagon::L4_and_memopb_io :
2703 case Hexagon::L4_or_memopb_io :
2704 return (0 <= Offset && Offset <= 63);
2706 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2707 // any size. Later pass knows how to handle it.
2708 case Hexagon::STriw_pred:
2709 case Hexagon::LDriw_pred:
2710 case Hexagon::STriw_mod:
2711 case Hexagon::LDriw_mod:
2714 case Hexagon::PS_fi:
2715 case Hexagon::PS_fia:
2716 case Hexagon::INLINEASM:
2719 case Hexagon::L2_ploadrbt_io:
2720 case Hexagon::L2_ploadrbf_io:
2721 case Hexagon::L2_ploadrubt_io:
2722 case Hexagon::L2_ploadrubf_io:
2723 case Hexagon::S2_pstorerbt_io:
2724 case Hexagon::S2_pstorerbf_io:
2725 return isUInt<6>(Offset);
2727 case Hexagon::L2_ploadrht_io:
2728 case Hexagon::L2_ploadrhf_io:
2729 case Hexagon::L2_ploadruht_io:
2730 case Hexagon::L2_ploadruhf_io:
2731 case Hexagon::S2_pstorerht_io:
2732 case Hexagon::S2_pstorerhf_io:
2733 return isShiftedUInt<6,1>(Offset);
2735 case Hexagon::L2_ploadrit_io:
2736 case Hexagon::L2_ploadrif_io:
2737 case Hexagon::S2_pstorerit_io:
2738 case Hexagon::S2_pstorerif_io:
2739 return isShiftedUInt<6,2>(Offset);
2741 case Hexagon::L2_ploadrdt_io:
2742 case Hexagon::L2_ploadrdf_io:
2743 case Hexagon::S2_pstorerdt_io:
2744 case Hexagon::S2_pstorerdf_io:
2745 return isShiftedUInt<6,3>(Offset);
2748 llvm_unreachable("No offset range is defined for this opcode. "
2749 "Please define it in the above switch statement!");
2752 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2753 return isV60VectorInstruction(MI) && isAccumulator(MI);
2756 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2757 const uint64_t F = get(MI.getOpcode()).TSFlags;
2758 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2760 V == HexagonII::TypeCVI_VA ||
2761 V == HexagonII::TypeCVI_VA_DV;
2764 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2765 const MachineInstr &ConsMI) const {
2766 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2769 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2772 if (mayBeNewStore(ConsMI))
2778 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2779 switch (MI.getOpcode()) {
2781 case Hexagon::L2_loadrub_io:
2782 case Hexagon::L4_loadrub_ur:
2783 case Hexagon::L4_loadrub_ap:
2784 case Hexagon::L2_loadrub_pr:
2785 case Hexagon::L2_loadrub_pbr:
2786 case Hexagon::L2_loadrub_pi:
2787 case Hexagon::L2_loadrub_pci:
2788 case Hexagon::L2_loadrub_pcr:
2789 case Hexagon::L2_loadbzw2_io:
2790 case Hexagon::L4_loadbzw2_ur:
2791 case Hexagon::L4_loadbzw2_ap:
2792 case Hexagon::L2_loadbzw2_pr:
2793 case Hexagon::L2_loadbzw2_pbr:
2794 case Hexagon::L2_loadbzw2_pi:
2795 case Hexagon::L2_loadbzw2_pci:
2796 case Hexagon::L2_loadbzw2_pcr:
2797 case Hexagon::L2_loadbzw4_io:
2798 case Hexagon::L4_loadbzw4_ur:
2799 case Hexagon::L4_loadbzw4_ap:
2800 case Hexagon::L2_loadbzw4_pr:
2801 case Hexagon::L2_loadbzw4_pbr:
2802 case Hexagon::L2_loadbzw4_pi:
2803 case Hexagon::L2_loadbzw4_pci:
2804 case Hexagon::L2_loadbzw4_pcr:
2805 case Hexagon::L4_loadrub_rr:
2806 case Hexagon::L2_ploadrubt_io:
2807 case Hexagon::L2_ploadrubt_pi:
2808 case Hexagon::L2_ploadrubf_io:
2809 case Hexagon::L2_ploadrubf_pi:
2810 case Hexagon::L2_ploadrubtnew_io:
2811 case Hexagon::L2_ploadrubfnew_io:
2812 case Hexagon::L4_ploadrubt_rr:
2813 case Hexagon::L4_ploadrubf_rr:
2814 case Hexagon::L4_ploadrubtnew_rr:
2815 case Hexagon::L4_ploadrubfnew_rr:
2816 case Hexagon::L2_ploadrubtnew_pi:
2817 case Hexagon::L2_ploadrubfnew_pi:
2818 case Hexagon::L4_ploadrubt_abs:
2819 case Hexagon::L4_ploadrubf_abs:
2820 case Hexagon::L4_ploadrubtnew_abs:
2821 case Hexagon::L4_ploadrubfnew_abs:
2822 case Hexagon::L2_loadrubgp:
2824 case Hexagon::L2_loadruh_io:
2825 case Hexagon::L4_loadruh_ur:
2826 case Hexagon::L4_loadruh_ap:
2827 case Hexagon::L2_loadruh_pr:
2828 case Hexagon::L2_loadruh_pbr:
2829 case Hexagon::L2_loadruh_pi:
2830 case Hexagon::L2_loadruh_pci:
2831 case Hexagon::L2_loadruh_pcr:
2832 case Hexagon::L4_loadruh_rr:
2833 case Hexagon::L2_ploadruht_io:
2834 case Hexagon::L2_ploadruht_pi:
2835 case Hexagon::L2_ploadruhf_io:
2836 case Hexagon::L2_ploadruhf_pi:
2837 case Hexagon::L2_ploadruhtnew_io:
2838 case Hexagon::L2_ploadruhfnew_io:
2839 case Hexagon::L4_ploadruht_rr:
2840 case Hexagon::L4_ploadruhf_rr:
2841 case Hexagon::L4_ploadruhtnew_rr:
2842 case Hexagon::L4_ploadruhfnew_rr:
2843 case Hexagon::L2_ploadruhtnew_pi:
2844 case Hexagon::L2_ploadruhfnew_pi:
2845 case Hexagon::L4_ploadruht_abs:
2846 case Hexagon::L4_ploadruhf_abs:
2847 case Hexagon::L4_ploadruhtnew_abs:
2848 case Hexagon::L4_ploadruhfnew_abs:
2849 case Hexagon::L2_loadruhgp:
2856 // Add latency to instruction.
2857 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
2858 const MachineInstr &MI2) const {
2859 if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2))
2860 if (!isVecUsableNextPacket(MI1, MI2))
2865 /// \brief Get the base register and byte offset of a load/store instr.
2866 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt,
2867 unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2869 unsigned AccessSize = 0;
2871 BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2873 return BaseReg != 0;
2876 /// \brief Can these instructions execute at the same time in a bundle.
2877 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
2878 const MachineInstr &Second) const {
2879 if (DisableNVSchedule)
2881 if (mayBeNewStore(Second)) {
2882 // Make sure the definition of the first instruction is the value being
2884 const MachineOperand &Stored =
2885 Second.getOperand(Second.getNumOperands() - 1);
2886 if (!Stored.isReg())
2888 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2889 const MachineOperand &Op = First.getOperand(i);
2890 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2897 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
2898 unsigned Opc = CallMI.getOpcode();
2899 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2902 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2909 // Returns true if an instruction can be converted into a non-extended
2910 // equivalent instruction.
2911 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
2913 // Check if the instruction has a register form that uses register in place
2914 // of the extended operand, if so return that as the non-extended form.
2915 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2918 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2919 // Check addressing mode and retrieve non-ext equivalent instruction.
2921 switch (getAddrMode(MI)) {
2922 case HexagonII::Absolute :
2923 // Load/store with absolute addressing mode can be converted into
2924 // base+offset mode.
2925 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
2927 case HexagonII::BaseImmOffset :
2928 // Load/store with base+offset addressing mode can be converted into
2929 // base+register offset addressing mode. However left shift operand should
2931 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
2933 case HexagonII::BaseLongOffset:
2934 NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
2939 if (NonExtOpcode < 0)
2946 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
2947 return Hexagon::getRealHWInstr(MI.getOpcode(),
2948 Hexagon::InstrType_Pseudo) >= 0;
2951 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
2953 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
2962 // Returns true, if a LD insn can be promoted to a cur load.
2963 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
2964 auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
2965 const uint64_t F = MI.getDesc().TSFlags;
2966 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
2970 // Returns true, if a ST insn can be promoted to a new-value store.
2971 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
2972 const uint64_t F = MI.getDesc().TSFlags;
2973 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
2976 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
2977 const MachineInstr &ConsMI) const {
2978 // There is no stall when ProdMI is not a V60 vector.
2979 if (!isV60VectorInstruction(ProdMI))
2982 // There is no stall when ProdMI and ConsMI are not dependent.
2983 if (!isDependent(ProdMI, ConsMI))
2986 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2987 // are scheduled in consecutive packets.
2988 if (isVecUsableNextPacket(ProdMI, ConsMI))
2994 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
2995 MachineBasicBlock::const_instr_iterator BII) const {
2996 // There is no stall when I is not a V60 vector.
2997 if (!isV60VectorInstruction(MI))
3000 MachineBasicBlock::const_instr_iterator MII = BII;
3001 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3003 if (!MII->isBundle()) {
3004 const MachineInstr &J = *MII;
3005 if (!isV60VectorInstruction(J))
3007 else if (isVecUsableNextPacket(J, MI))
3012 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3013 const MachineInstr &J = *MII;
3014 if (producesStall(J, MI))
3020 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3021 unsigned PredReg) const {
3022 for (const MachineOperand &MO : MI.operands()) {
3023 // Predicate register must be explicitly defined.
3024 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3026 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3030 // Hexagon Programmer's Reference says that decbin, memw_locked, and
3031 // memd_locked cannot be used as .new as well,
3032 // but we don't seem to have these instructions defined.
3033 return MI.getOpcode() != Hexagon::A4_tlbmatch;
3036 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3037 return (Opcode == Hexagon::J2_jumpt) ||
3038 (Opcode == Hexagon::J2_jumpf) ||
3039 (Opcode == Hexagon::J2_jumptnew) ||
3040 (Opcode == Hexagon::J2_jumpfnew) ||
3041 (Opcode == Hexagon::J2_jumptnewpt) ||
3042 (Opcode == Hexagon::J2_jumpfnewpt);
3045 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3046 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3048 return !isPredicatedTrue(Cond[0].getImm());
3051 short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const {
3052 return Hexagon::getAbsoluteForm(MI.getOpcode());
3055 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3056 const uint64_t F = MI.getDesc().TSFlags;
3057 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3060 // Returns the base register in a memory access (load/store). The offset is
3061 // returned in Offset and the access size is returned in AccessSize.
3062 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3063 int &Offset, unsigned &AccessSize) const {
3064 // Return if it is not a base+offset type instruction or a MemOp.
3065 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3066 getAddrMode(MI) != HexagonII::BaseLongOffset &&
3067 !isMemOp(MI) && !isPostIncrement(MI))
3070 // Since it is a memory access instruction, getMemAccessSize() should never
3072 assert (getMemAccessSize(MI) &&
3073 "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
3075 // Return Values of getMemAccessSize() are
3076 // 0 - Checked in the assert above.
3077 // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
3078 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
3079 AccessSize = (1U << (getMemAccessSize(MI) - 1));
3081 unsigned basePos = 0, offsetPos = 0;
3082 if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
3085 // Post increment updates its EA after the mem access,
3086 // so we need to treat its offset as zero.
3087 if (isPostIncrement(MI))
3090 Offset = MI.getOperand(offsetPos).getImm();
3093 return MI.getOperand(basePos).getReg();
3096 /// Return the position of the base and offset operands for this instruction.
3097 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3098 unsigned &BasePos, unsigned &OffsetPos) const {
3099 // Deal with memops first.
3103 } else if (MI.mayStore()) {
3106 } else if (MI.mayLoad()) {
3112 if (isPredicated(MI)) {
3116 if (isPostIncrement(MI)) {
3121 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3127 // Inserts branching instructions in reverse order of their occurrence.
3128 // e.g. jump_t t1 (i1)
3130 // Jumpers = {i2, i1}
3131 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3132 MachineBasicBlock& MBB) const {
3133 SmallVector<MachineInstr*, 2> Jumpers;
3134 // If the block has no terminators, it just falls into the block after it.
3135 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3136 if (I == MBB.instr_begin())
3139 // A basic block may looks like this:
3149 // It has two succs but does not have a terminator
3150 // Don't know how to handle it.
3155 } while (I != MBB.instr_begin());
3157 I = MBB.instr_end();
3160 while (I->isDebugValue()) {
3161 if (I == MBB.instr_begin())
3165 if (!isUnpredicatedTerminator(*I))
3168 // Get the last instruction in the block.
3169 MachineInstr *LastInst = &*I;
3170 Jumpers.push_back(LastInst);
3171 MachineInstr *SecondLastInst = nullptr;
3172 // Find one more terminator if present.
3174 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3175 if (!SecondLastInst) {
3176 SecondLastInst = &*I;
3177 Jumpers.push_back(SecondLastInst);
3178 } else // This is a third branch.
3181 if (I == MBB.instr_begin())
3188 short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
3191 return Hexagon::getBaseWithLongOffset(Opcode);
3194 short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const {
3195 return Hexagon::getBaseWithLongOffset(MI.getOpcode());
3198 short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const {
3199 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
3202 // Returns Operand Index for the constant extended instruction.
3203 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3204 const uint64_t F = MI.getDesc().TSFlags;
3205 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3208 // See if instruction could potentially be a duplex candidate.
3209 // If so, return its group. Zero otherwise.
3210 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3211 const MachineInstr &MI) const {
3212 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3214 switch (MI.getOpcode()) {
3216 return HexagonII::HCG_None;
3219 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3220 // "Rd16=#U6 ; jump #r9:2"
3221 // "Rd16=Rs16 ; jump #r9:2"
3223 case Hexagon::C2_cmpeq:
3224 case Hexagon::C2_cmpgt:
3225 case Hexagon::C2_cmpgtu:
3226 DstReg = MI.getOperand(0).getReg();
3227 Src1Reg = MI.getOperand(1).getReg();
3228 Src2Reg = MI.getOperand(2).getReg();
3229 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3230 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3231 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3232 return HexagonII::HCG_A;
3234 case Hexagon::C2_cmpeqi:
3235 case Hexagon::C2_cmpgti:
3236 case Hexagon::C2_cmpgtui:
3237 // P0 = cmp.eq(Rs,#u2)
3238 DstReg = MI.getOperand(0).getReg();
3239 SrcReg = MI.getOperand(1).getReg();
3240 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3241 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3242 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3243 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3244 (MI.getOperand(2).getImm() == -1)))
3245 return HexagonII::HCG_A;
3247 case Hexagon::A2_tfr:
3249 DstReg = MI.getOperand(0).getReg();
3250 SrcReg = MI.getOperand(1).getReg();
3251 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3252 return HexagonII::HCG_A;
3254 case Hexagon::A2_tfrsi:
3256 // Do not test for #u6 size since the const is getting extended
3257 // regardless and compound could be formed.
3258 DstReg = MI.getOperand(0).getReg();
3259 if (isIntRegForSubInst(DstReg))
3260 return HexagonII::HCG_A;
3262 case Hexagon::S2_tstbit_i:
3263 DstReg = MI.getOperand(0).getReg();
3264 Src1Reg = MI.getOperand(1).getReg();
3265 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3266 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3267 MI.getOperand(2).isImm() &&
3268 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3269 return HexagonII::HCG_A;
3271 // The fact that .new form is used pretty much guarantees
3272 // that predicate register will match. Nevertheless,
3273 // there could be some false positives without additional
3275 case Hexagon::J2_jumptnew:
3276 case Hexagon::J2_jumpfnew:
3277 case Hexagon::J2_jumptnewpt:
3278 case Hexagon::J2_jumpfnewpt:
3279 Src1Reg = MI.getOperand(0).getReg();
3280 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3281 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3282 return HexagonII::HCG_B;
3284 // Transfer and jump:
3285 // Rd=#U6 ; jump #r9:2
3286 // Rd=Rs ; jump #r9:2
3287 // Do not test for jump range here.
3288 case Hexagon::J2_jump:
3289 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3290 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3291 return HexagonII::HCG_C;
3295 return HexagonII::HCG_None;
3298 // Returns -1 when there is no opcode found.
3299 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3300 const MachineInstr &GB) const {
3301 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3302 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3303 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3304 (GB.getOpcode() != Hexagon::J2_jumptnew))
3306 unsigned DestReg = GA.getOperand(0).getReg();
3307 if (!GB.readsRegister(DestReg))
3309 if (DestReg == Hexagon::P0)
3310 return Hexagon::J4_cmpeqi_tp0_jump_nt;
3311 if (DestReg == Hexagon::P1)
3312 return Hexagon::J4_cmpeqi_tp1_jump_nt;
3316 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3317 enum Hexagon::PredSense inPredSense;
3318 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3319 Hexagon::PredSense_true;
3320 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3321 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3324 llvm_unreachable("Unexpected predicable instruction");
3327 // Return the cur value instruction for a given store.
3328 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3329 switch (MI.getOpcode()) {
3330 default: llvm_unreachable("Unknown .cur type");
3331 case Hexagon::V6_vL32b_pi:
3332 return Hexagon::V6_vL32b_cur_pi;
3333 case Hexagon::V6_vL32b_ai:
3334 return Hexagon::V6_vL32b_cur_ai;
3336 case Hexagon::V6_vL32b_pi_128B:
3337 return Hexagon::V6_vL32b_cur_pi_128B;
3338 case Hexagon::V6_vL32b_ai_128B:
3339 return Hexagon::V6_vL32b_cur_ai_128B;
3344 // The diagram below shows the steps involved in the conversion of a predicated
3345 // store instruction to its .new predicated new-value form.
3347 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3349 // / \ (not OK. it will cause new-value store to be
3350 // / X conditional on p0.new while R2 producer is
3353 // p.new store p.old NV store
3354 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3360 // [if (p0)memw(R0+#0)=R2]
3363 // The following set of instructions further explains the scenario where
3364 // conditional new-value store becomes invalid when promoted to .new predicate
3367 // { 1) if (p0) r0 = add(r1, r2)
3368 // 2) p0 = cmp.eq(r3, #0) }
3370 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3371 // the first two instructions because in instr 1, r0 is conditional on old value
3372 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3373 // is not valid for new-value stores.
3374 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3375 // from the "Conditional Store" list. Because a predicated new value store
3376 // would NOT be promoted to a double dot new store. See diagram below:
3377 // This function returns yes for those stores that are predicated but not
3378 // yet promoted to predicate dot new instructions.
3380 // +---------------------+
3381 // /-----| if (p0) memw(..)=r0 |---------\~
3382 // || +---------------------+ ||
3383 // promote || /\ /\ || promote
3385 // \||/ demote || \||/
3387 // +-------------------------+ || +-------------------------+
3388 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3389 // +-------------------------+ || +-------------------------+
3392 // promote || \/ NOT possible
3396 // +-----------------------------+
3397 // | if (p0.new) memw(..)=r0.new |
3398 // +-----------------------------+
3399 // Double Dot New Store
3401 // Returns the most basic instruction for the .new predicated instructions and
3402 // new-value stores.
3403 // For example, all of the following instructions will be converted back to the
3404 // same instruction:
3405 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3406 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3407 // 3) if (p0.new) memw(R0+#0) = R1 --->
3409 // To understand the translation of instruction 1 to its original form, consider
3410 // a packet with 3 instructions.
3411 // { p0 = cmp.eq(R0,R1)
3412 // if (p0.new) R2 = add(R3, R4)
3413 // R5 = add (R3, R1)
3415 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3417 // This instruction can be part of the previous packet only if both p0 and R2
3418 // are promoted to .new values. This promotion happens in steps, first
3419 // predicate register is promoted to .new and in the next iteration R2 is
3420 // promoted. Therefore, in case of dependence check failure (due to R5) during
3421 // next iteration, it should be converted back to its most basic form.
3423 // Return the new value instruction for a given store.
3424 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3425 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3426 if (NVOpcode >= 0) // Valid new-value store instruction.
3429 switch (MI.getOpcode()) {
3431 llvm::report_fatal_error(std::string("Unknown .new type: ") +
3432 std::to_string(MI.getOpcode()).c_str());
3433 case Hexagon::S4_storerb_ur:
3434 return Hexagon::S4_storerbnew_ur;
3436 case Hexagon::S2_storerb_pci:
3437 return Hexagon::S2_storerb_pci;
3439 case Hexagon::S2_storeri_pci:
3440 return Hexagon::S2_storeri_pci;
3442 case Hexagon::S2_storerh_pci:
3443 return Hexagon::S2_storerh_pci;
3445 case Hexagon::S2_storerd_pci:
3446 return Hexagon::S2_storerd_pci;
3448 case Hexagon::S2_storerf_pci:
3449 return Hexagon::S2_storerf_pci;
3451 case Hexagon::V6_vS32b_ai:
3452 return Hexagon::V6_vS32b_new_ai;
3454 case Hexagon::V6_vS32b_pi:
3455 return Hexagon::V6_vS32b_new_pi;
3458 case Hexagon::V6_vS32b_ai_128B:
3459 return Hexagon::V6_vS32b_new_ai_128B;
3461 case Hexagon::V6_vS32b_pi_128B:
3462 return Hexagon::V6_vS32b_new_pi_128B;
3467 // Returns the opcode to use when converting MI, which is a conditional jump,
3468 // into a conditional instruction which uses the .new value of the predicate.
3469 // We also use branch probabilities to add a hint to the jump.
3470 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3471 const MachineBranchProbabilityInfo *MBPI) const {
3472 // We assume that block can have at most two successors.
3473 const MachineBasicBlock *Src = MI.getParent();
3474 const MachineOperand &BrTarget = MI.getOperand(1);
3476 const BranchProbability OneHalf(1, 2);
3478 if (BrTarget.isMBB()) {
3479 const MachineBasicBlock *Dst = BrTarget.getMBB();
3480 Taken = MBPI->getEdgeProbability(Src, Dst) >= OneHalf;
3482 // The branch target is not a basic block (most likely a function).
3483 // Since BPI only gives probabilities for targets that are basic blocks,
3484 // try to identify another target of this branch (potentially a fall-
3485 // -through) and check the probability of that target.
3487 // The only handled branch combinations are:
3488 // - one conditional branch,
3489 // - one conditional branch followed by one unconditional branch.
3490 // Otherwise, assume not-taken.
3491 assert(MI.isConditionalBranch());
3492 const MachineBasicBlock &B = *MI.getParent();
3493 bool SawCond = false, Bad = false;
3494 for (const MachineInstr &I : B) {
3497 if (I.isConditionalBranch()) {
3504 if (I.isUnconditionalBranch() && !SawCond) {
3510 MachineBasicBlock::const_instr_iterator It(MI);
3511 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3512 if (NextIt == B.instr_end()) {
3513 // If this branch is the last, look for the fall-through block.
3514 for (const MachineBasicBlock *SB : B.successors()) {
3515 if (!B.isLayoutSuccessor(SB))
3517 Taken = MBPI->getEdgeProbability(Src, SB) < OneHalf;
3521 assert(NextIt->isUnconditionalBranch());
3522 // Find the first MBB operand and assume it's the target.
3523 const MachineBasicBlock *BT = nullptr;
3524 for (const MachineOperand &Op : NextIt->operands()) {
3530 Taken = BT && MBPI->getEdgeProbability(Src, BT) < OneHalf;
3535 // The Taken flag should be set to something reasonable by this point.
3537 switch (MI.getOpcode()) {
3538 case Hexagon::J2_jumpt:
3539 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3540 case Hexagon::J2_jumpf:
3541 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3544 llvm_unreachable("Unexpected jump instruction.");
3548 // Return .new predicate version for an instruction.
3549 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3550 const MachineBranchProbabilityInfo *MBPI) const {
3551 switch (MI.getOpcode()) {
3553 case Hexagon::J2_jumpt:
3554 case Hexagon::J2_jumpf:
3555 return getDotNewPredJumpOp(MI, MBPI);
3558 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3562 dbgs() << "Cannot convert to .new: " << getName(MI.getOpcode()) << '\n';
3563 llvm_unreachable(nullptr);
3566 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3567 int NewOp = MI.getOpcode();
3568 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3569 NewOp = Hexagon::getPredOldOpcode(NewOp);
3570 const MachineFunction &MF = *MI.getParent()->getParent();
3571 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
3572 // All Hexagon architectures have prediction bits on dot-new branches,
3573 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3574 // to pick the right opcode when converting back to dot-old.
3575 if (!HST.getFeatureBits()[Hexagon::ArchV60]) {
3577 case Hexagon::J2_jumptpt:
3578 NewOp = Hexagon::J2_jumpt;
3580 case Hexagon::J2_jumpfpt:
3581 NewOp = Hexagon::J2_jumpf;
3583 case Hexagon::J2_jumprtpt:
3584 NewOp = Hexagon::J2_jumprt;
3586 case Hexagon::J2_jumprfpt:
3587 NewOp = Hexagon::J2_jumprf;
3591 assert(NewOp >= 0 &&
3592 "Couldn't change predicate new instruction to its old form.");
3595 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3596 NewOp = Hexagon::getNonNVStore(NewOp);
3597 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3602 // See if instruction could potentially be a duplex candidate.
3603 // If so, return its group. Zero otherwise.
3604 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3605 const MachineInstr &MI) const {
3606 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3607 auto &HRI = getRegisterInfo();
3609 switch (MI.getOpcode()) {
3611 return HexagonII::HSIG_None;
3615 // Rd = memw(Rs+#u4:2)
3616 // Rd = memub(Rs+#u4:0)
3617 case Hexagon::L2_loadri_io:
3618 DstReg = MI.getOperand(0).getReg();
3619 SrcReg = MI.getOperand(1).getReg();
3620 // Special case this one from Group L2.
3621 // Rd = memw(r29+#u5:2)
3622 if (isIntRegForSubInst(DstReg)) {
3623 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3624 HRI.getStackRegister() == SrcReg &&
3625 MI.getOperand(2).isImm() &&
3626 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3627 return HexagonII::HSIG_L2;
3628 // Rd = memw(Rs+#u4:2)
3629 if (isIntRegForSubInst(SrcReg) &&
3630 (MI.getOperand(2).isImm() &&
3631 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3632 return HexagonII::HSIG_L1;
3635 case Hexagon::L2_loadrub_io:
3636 // Rd = memub(Rs+#u4:0)
3637 DstReg = MI.getOperand(0).getReg();
3638 SrcReg = MI.getOperand(1).getReg();
3639 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3640 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3641 return HexagonII::HSIG_L1;
3646 // Rd = memh/memuh(Rs+#u3:1)
3647 // Rd = memb(Rs+#u3:0)
3648 // Rd = memw(r29+#u5:2) - Handled above.
3649 // Rdd = memd(r29+#u5:3)
3651 // [if ([!]p0[.new])] dealloc_return
3652 // [if ([!]p0[.new])] jumpr r31
3653 case Hexagon::L2_loadrh_io:
3654 case Hexagon::L2_loadruh_io:
3655 // Rd = memh/memuh(Rs+#u3:1)
3656 DstReg = MI.getOperand(0).getReg();
3657 SrcReg = MI.getOperand(1).getReg();
3658 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3659 MI.getOperand(2).isImm() &&
3660 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3661 return HexagonII::HSIG_L2;
3663 case Hexagon::L2_loadrb_io:
3664 // Rd = memb(Rs+#u3:0)
3665 DstReg = MI.getOperand(0).getReg();
3666 SrcReg = MI.getOperand(1).getReg();
3667 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3668 MI.getOperand(2).isImm() &&
3669 isUInt<3>(MI.getOperand(2).getImm()))
3670 return HexagonII::HSIG_L2;
3672 case Hexagon::L2_loadrd_io:
3673 // Rdd = memd(r29+#u5:3)
3674 DstReg = MI.getOperand(0).getReg();
3675 SrcReg = MI.getOperand(1).getReg();
3676 if (isDblRegForSubInst(DstReg, HRI) &&
3677 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3678 HRI.getStackRegister() == SrcReg &&
3679 MI.getOperand(2).isImm() &&
3680 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3681 return HexagonII::HSIG_L2;
3683 // dealloc_return is not documented in Hexagon Manual, but marked
3684 // with A_SUBINSN attribute in iset_v4classic.py.
3685 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3686 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3687 case Hexagon::L4_return:
3688 case Hexagon::L2_deallocframe:
3689 return HexagonII::HSIG_L2;
3690 case Hexagon::EH_RETURN_JMPR:
3691 case Hexagon::PS_jmpret:
3693 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3694 DstReg = MI.getOperand(0).getReg();
3695 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3696 return HexagonII::HSIG_L2;
3698 case Hexagon::PS_jmprett:
3699 case Hexagon::PS_jmpretf:
3700 case Hexagon::PS_jmprettnewpt:
3701 case Hexagon::PS_jmpretfnewpt:
3702 case Hexagon::PS_jmprettnew:
3703 case Hexagon::PS_jmpretfnew:
3704 DstReg = MI.getOperand(1).getReg();
3705 SrcReg = MI.getOperand(0).getReg();
3706 // [if ([!]p0[.new])] jumpr r31
3707 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3708 (Hexagon::P0 == SrcReg)) &&
3709 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3710 return HexagonII::HSIG_L2;
3712 case Hexagon::L4_return_t :
3713 case Hexagon::L4_return_f :
3714 case Hexagon::L4_return_tnew_pnt :
3715 case Hexagon::L4_return_fnew_pnt :
3716 case Hexagon::L4_return_tnew_pt :
3717 case Hexagon::L4_return_fnew_pt :
3718 // [if ([!]p0[.new])] dealloc_return
3719 SrcReg = MI.getOperand(0).getReg();
3720 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3721 return HexagonII::HSIG_L2;
3726 // memw(Rs+#u4:2) = Rt
3727 // memb(Rs+#u4:0) = Rt
3728 case Hexagon::S2_storeri_io:
3729 // Special case this one from Group S2.
3730 // memw(r29+#u5:2) = Rt
3731 Src1Reg = MI.getOperand(0).getReg();
3732 Src2Reg = MI.getOperand(2).getReg();
3733 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3734 isIntRegForSubInst(Src2Reg) &&
3735 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3736 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3737 return HexagonII::HSIG_S2;
3738 // memw(Rs+#u4:2) = Rt
3739 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3740 MI.getOperand(1).isImm() &&
3741 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3742 return HexagonII::HSIG_S1;
3744 case Hexagon::S2_storerb_io:
3745 // memb(Rs+#u4:0) = Rt
3746 Src1Reg = MI.getOperand(0).getReg();
3747 Src2Reg = MI.getOperand(2).getReg();
3748 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3749 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3750 return HexagonII::HSIG_S1;
3755 // memh(Rs+#u3:1) = Rt
3756 // memw(r29+#u5:2) = Rt
3757 // memd(r29+#s6:3) = Rtt
3758 // memw(Rs+#u4:2) = #U1
3759 // memb(Rs+#u4) = #U1
3760 // allocframe(#u5:3)
3761 case Hexagon::S2_storerh_io:
3762 // memh(Rs+#u3:1) = Rt
3763 Src1Reg = MI.getOperand(0).getReg();
3764 Src2Reg = MI.getOperand(2).getReg();
3765 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3766 MI.getOperand(1).isImm() &&
3767 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3768 return HexagonII::HSIG_S1;
3770 case Hexagon::S2_storerd_io:
3771 // memd(r29+#s6:3) = Rtt
3772 Src1Reg = MI.getOperand(0).getReg();
3773 Src2Reg = MI.getOperand(2).getReg();
3774 if (isDblRegForSubInst(Src2Reg, HRI) &&
3775 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3776 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3777 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3778 return HexagonII::HSIG_S2;
3780 case Hexagon::S4_storeiri_io:
3781 // memw(Rs+#u4:2) = #U1
3782 Src1Reg = MI.getOperand(0).getReg();
3783 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3784 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3785 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3786 return HexagonII::HSIG_S2;
3788 case Hexagon::S4_storeirb_io:
3789 // memb(Rs+#u4) = #U1
3790 Src1Reg = MI.getOperand(0).getReg();
3791 if (isIntRegForSubInst(Src1Reg) &&
3792 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3793 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3794 return HexagonII::HSIG_S2;
3796 case Hexagon::S2_allocframe:
3797 if (MI.getOperand(0).isImm() &&
3798 isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
3799 return HexagonII::HSIG_S1;
3808 // if ([!]P0[.new]) Rd = #0
3809 // Rd = add(r29,#u6:2)
3811 // P0 = cmp.eq(Rs,#u2)
3812 // Rdd = combine(#0,Rs)
3813 // Rdd = combine(Rs,#0)
3814 // Rdd = combine(#u2,#U2)
3817 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3819 case Hexagon::A2_addi:
3820 DstReg = MI.getOperand(0).getReg();
3821 SrcReg = MI.getOperand(1).getReg();
3822 if (isIntRegForSubInst(DstReg)) {
3823 // Rd = add(r29,#u6:2)
3824 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3825 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3826 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3827 return HexagonII::HSIG_A;
3829 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3830 isInt<7>(MI.getOperand(2).getImm()))
3831 return HexagonII::HSIG_A;
3834 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3835 ((MI.getOperand(2).getImm() == 1) ||
3836 (MI.getOperand(2).getImm() == -1)))
3837 return HexagonII::HSIG_A;
3840 case Hexagon::A2_add:
3842 DstReg = MI.getOperand(0).getReg();
3843 Src1Reg = MI.getOperand(1).getReg();
3844 Src2Reg = MI.getOperand(2).getReg();
3845 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3846 isIntRegForSubInst(Src2Reg))
3847 return HexagonII::HSIG_A;
3849 case Hexagon::A2_andir:
3851 // Rd16=and(Rs16,#255)
3852 // Rd16=and(Rs16,#1)
3853 DstReg = MI.getOperand(0).getReg();
3854 SrcReg = MI.getOperand(1).getReg();
3855 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3856 MI.getOperand(2).isImm() &&
3857 ((MI.getOperand(2).getImm() == 1) ||
3858 (MI.getOperand(2).getImm() == 255)))
3859 return HexagonII::HSIG_A;
3861 case Hexagon::A2_tfr:
3863 DstReg = MI.getOperand(0).getReg();
3864 SrcReg = MI.getOperand(1).getReg();
3865 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3866 return HexagonII::HSIG_A;
3868 case Hexagon::A2_tfrsi:
3870 // Do not test for #u6 size since the const is getting extended
3871 // regardless and compound could be formed.
3873 DstReg = MI.getOperand(0).getReg();
3874 if (isIntRegForSubInst(DstReg))
3875 return HexagonII::HSIG_A;
3877 case Hexagon::C2_cmoveit:
3878 case Hexagon::C2_cmovenewit:
3879 case Hexagon::C2_cmoveif:
3880 case Hexagon::C2_cmovenewif:
3881 // if ([!]P0[.new]) Rd = #0
3883 // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3884 DstReg = MI.getOperand(0).getReg();
3885 SrcReg = MI.getOperand(1).getReg();
3886 if (isIntRegForSubInst(DstReg) &&
3887 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3888 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3889 return HexagonII::HSIG_A;
3891 case Hexagon::C2_cmpeqi:
3892 // P0 = cmp.eq(Rs,#u2)
3893 DstReg = MI.getOperand(0).getReg();
3894 SrcReg = MI.getOperand(1).getReg();
3895 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3896 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3897 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3898 return HexagonII::HSIG_A;
3900 case Hexagon::A2_combineii:
3901 case Hexagon::A4_combineii:
3902 // Rdd = combine(#u2,#U2)
3903 DstReg = MI.getOperand(0).getReg();
3904 if (isDblRegForSubInst(DstReg, HRI) &&
3905 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3906 (MI.getOperand(1).isGlobal() &&
3907 isUInt<2>(MI.getOperand(1).getOffset()))) &&
3908 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3909 (MI.getOperand(2).isGlobal() &&
3910 isUInt<2>(MI.getOperand(2).getOffset()))))
3911 return HexagonII::HSIG_A;
3913 case Hexagon::A4_combineri:
3914 // Rdd = combine(Rs,#0)
3915 DstReg = MI.getOperand(0).getReg();
3916 SrcReg = MI.getOperand(1).getReg();
3917 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3918 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3919 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3920 return HexagonII::HSIG_A;
3922 case Hexagon::A4_combineir:
3923 // Rdd = combine(#0,Rs)
3924 DstReg = MI.getOperand(0).getReg();
3925 SrcReg = MI.getOperand(2).getReg();
3926 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3927 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3928 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3929 return HexagonII::HSIG_A;
3931 case Hexagon::A2_sxtb:
3932 case Hexagon::A2_sxth:
3933 case Hexagon::A2_zxtb:
3934 case Hexagon::A2_zxth:
3935 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3936 DstReg = MI.getOperand(0).getReg();
3937 SrcReg = MI.getOperand(1).getReg();
3938 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3939 return HexagonII::HSIG_A;
3943 return HexagonII::HSIG_None;
3946 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
3947 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3950 // Return first non-debug instruction in the basic block.
3951 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
3953 for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
3954 MachineInstr &MI = *MII;
3955 if (MI.isDebugValue())
3962 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
3963 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3964 // Default to one cycle for no itinerary. However, an "empty" itinerary may
3965 // still have a MinLatency property, which getStageLatency checks.
3967 return getInstrLatency(ItinData, MI);
3969 // Get the latency embedded in the itinerary. If we're not using timing class
3970 // latencies or if we using BSB scheduling, then restrict the maximum latency
3971 // to 1 (that is, either 0 or 1).
3972 if (MI.isTransient())
3974 unsigned Latency = ItinData->getStageLatency(MI.getDesc().getSchedClass());
3975 if (!EnableTimingClassLatency ||
3976 MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>().
3983 // inverts the predication logic.
3986 bool HexagonInstrInfo::getInvertedPredSense(
3987 SmallVectorImpl<MachineOperand> &Cond) const {
3990 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3991 Cond[0].setImm(Opc);
3995 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3997 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3998 : Hexagon::getTruePredOpcode(Opc);
3999 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4000 return InvPredOpcode;
4002 llvm_unreachable("Unexpected predicated instruction");
4005 // Returns the max value that doesn't need to be extended.
4006 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4007 const uint64_t F = MI.getDesc().TSFlags;
4008 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4009 & HexagonII::ExtentSignedMask;
4010 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4011 & HexagonII::ExtentBitsMask;
4013 if (isSigned) // if value is signed
4014 return ~(-1U << (bits - 1));
4016 return ~(-1U << bits);
4019 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4020 const uint64_t F = MI.getDesc().TSFlags;
4021 return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
4024 // Returns the min value that doesn't need to be extended.
4025 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4026 const uint64_t F = MI.getDesc().TSFlags;
4027 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4028 & HexagonII::ExtentSignedMask;
4029 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4030 & HexagonII::ExtentBitsMask;
4032 if (isSigned) // if value is signed
4033 return -1U << (bits - 1);
4038 // Returns opcode of the non-extended equivalent instruction.
4039 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4040 // Check if the instruction has a register form that uses register in place
4041 // of the extended operand, if so return that as the non-extended form.
4042 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4043 if (NonExtOpcode >= 0)
4044 return NonExtOpcode;
4046 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4047 // Check addressing mode and retrieve non-ext equivalent instruction.
4048 switch (getAddrMode(MI)) {
4049 case HexagonII::Absolute :
4050 return Hexagon::getBaseWithImmOffset(MI.getOpcode());
4051 case HexagonII::BaseImmOffset :
4052 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
4053 case HexagonII::BaseLongOffset:
4054 return Hexagon::getRegShlForm(MI.getOpcode());
4063 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4064 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4067 assert(Cond.size() == 2);
4068 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4069 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4072 PredReg = Cond[1].getReg();
4074 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4076 if (Cond[1].isImplicit())
4077 PredRegFlags = RegState::Implicit;
4078 if (Cond[1].isUndef())
4079 PredRegFlags |= RegState::Undef;
4083 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4084 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4087 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4088 return Hexagon::getRegForm(MI.getOpcode());
4091 // Return the number of bytes required to encode the instruction.
4092 // Hexagon instructions are fixed length, 4 bytes, unless they
4093 // use a constant extender, which requires another 4 bytes.
4094 // For debug instructions and prolog labels, return 0.
4095 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4096 if (MI.isDebugValue() || MI.isPosition())
4099 unsigned Size = MI.getDesc().getSize();
4101 // Assume the default insn size in case it cannot be determined
4102 // for whatever reason.
4103 Size = HEXAGON_INSTR_SIZE;
4105 if (isConstExtended(MI) || isExtended(MI))
4106 Size += HEXAGON_INSTR_SIZE;
4108 // Try and compute number of instructions in asm.
4109 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4110 const MachineBasicBlock &MBB = *MI.getParent();
4111 const MachineFunction *MF = MBB.getParent();
4112 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4114 // Count the number of register definitions to find the asm string.
4115 unsigned NumDefs = 0;
4116 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4118 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4120 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4121 // Disassemble the AsmStr and approximate number of instructions.
4122 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4123 Size = getInlineAsmLength(AsmStr, *MAI);
4129 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4130 const uint64_t F = MI.getDesc().TSFlags;
4131 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4134 unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4135 const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
4136 const InstrItineraryData &II = *ST.getInstrItineraryData();
4137 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4139 return IS.getUnits();
4142 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
4143 const uint64_t F = get(Opcode).TSFlags;
4144 return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
4147 // Calculate size of the basic block without debug instructions.
4148 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4149 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4152 unsigned HexagonInstrInfo::nonDbgBundleSize(
4153 MachineBasicBlock::const_iterator BundleHead) const {
4154 assert(BundleHead->isBundle() && "Not a bundle header");
4155 auto MII = BundleHead.getInstrIterator();
4156 // Skip the bundle header.
4157 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4160 /// immediateExtend - Changes the instruction in place to one using an immediate
4162 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4163 assert((isExtendable(MI)||isConstExtended(MI)) &&
4164 "Instruction must be extendable");
4165 // Find which operand is extendable.
4166 short ExtOpNum = getCExtOpNum(MI);
4167 MachineOperand &MO = MI.getOperand(ExtOpNum);
4168 // This needs to be something we understand.
4169 assert((MO.isMBB() || MO.isImm()) &&
4170 "Branch with unknown extendable field type");
4171 // Mark given operand as extended.
4172 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4175 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4176 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4177 DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
4178 << NewTarget->getNumber(); MI.dump(););
4179 assert(MI.isBranch());
4180 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4181 int TargetPos = MI.getNumOperands() - 1;
4182 // In general branch target is the last operand,
4183 // but some implicit defs added at the end might change it.
4184 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4186 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4187 MI.getOperand(TargetPos).setMBB(NewTarget);
4188 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4189 NewOpcode = reversePrediction(NewOpcode);
4191 MI.setDesc(get(NewOpcode));
4195 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4196 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4197 MachineFunction::iterator A = MF.begin();
4198 MachineBasicBlock &B = *A;
4199 MachineBasicBlock::iterator I = B.begin();
4200 DebugLoc DL = I->getDebugLoc();
4201 MachineInstr *NewMI;
4203 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4204 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4205 NewMI = BuildMI(B, I, DL, get(insn));
4206 DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
4207 " Class: " << NewMI->getDesc().getSchedClass());
4208 NewMI->eraseFromParent();
4210 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4213 // inverts the predication logic.
4216 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4217 DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4218 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4222 // Reverse the branch prediction.
4223 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4224 int PredRevOpcode = -1;
4225 if (isPredictedTaken(Opcode))
4226 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4228 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4229 assert(PredRevOpcode > 0);
4230 return PredRevOpcode;
4233 // TODO: Add more rigorous validation.
4234 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4236 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4239 short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const {
4240 return Hexagon::xformRegToImmOffset(MI.getOpcode());