1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonHazardRecognizer.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/ScheduleDAG.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
37 #define DEBUG_TYPE "hexagon-instrinfo"
39 #define GET_INSTRINFO_CTOR_DTOR
40 #define GET_INSTRMAP_INFO
41 #include "HexagonGenInstrInfo.inc"
42 #include "HexagonGenDFAPacketizer.inc"
44 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
45 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
46 "packetization boundary."));
48 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
49 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
51 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
52 cl::Hidden, cl::ZeroOrMore, cl::init(false),
53 cl::desc("Disable schedule adjustment for new value stores."));
55 static cl::opt<bool> EnableTimingClassLatency(
56 "enable-timing-class-latency", cl::Hidden, cl::init(false),
57 cl::desc("Enable timing class latency"));
59 static cl::opt<bool> EnableALUForwarding(
60 "enable-alu-forwarding", cl::Hidden, cl::init(true),
61 cl::desc("Enable vec alu forwarding"));
63 static cl::opt<bool> EnableACCForwarding(
64 "enable-acc-forwarding", cl::Hidden, cl::init(true),
65 cl::desc("Enable vec acc forwarding"));
67 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
68 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
70 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
71 cl::init(true), cl::Hidden, cl::ZeroOrMore,
72 cl::desc("Use the DFA based hazard recognizer."));
75 /// Constants for Hexagon instructions.
77 const int Hexagon_MEMV_OFFSET_MAX_128B = 896; // #s4: -8*128...7*128
78 const int Hexagon_MEMV_OFFSET_MIN_128B = -1024; // #s4
79 const int Hexagon_MEMV_OFFSET_MAX = 448; // #s4: -8*64...7*64
80 const int Hexagon_MEMV_OFFSET_MIN = -512; // #s4
81 const int Hexagon_MEMW_OFFSET_MAX = 4095;
82 const int Hexagon_MEMW_OFFSET_MIN = -4096;
83 const int Hexagon_MEMD_OFFSET_MAX = 8191;
84 const int Hexagon_MEMD_OFFSET_MIN = -8192;
85 const int Hexagon_MEMH_OFFSET_MAX = 2047;
86 const int Hexagon_MEMH_OFFSET_MIN = -2048;
87 const int Hexagon_MEMB_OFFSET_MAX = 1023;
88 const int Hexagon_MEMB_OFFSET_MIN = -1024;
89 const int Hexagon_ADDI_OFFSET_MAX = 32767;
90 const int Hexagon_ADDI_OFFSET_MIN = -32768;
91 const int Hexagon_MEMD_AUTOINC_MAX = 56;
92 const int Hexagon_MEMD_AUTOINC_MIN = -64;
93 const int Hexagon_MEMW_AUTOINC_MAX = 28;
94 const int Hexagon_MEMW_AUTOINC_MIN = -32;
95 const int Hexagon_MEMH_AUTOINC_MAX = 14;
96 const int Hexagon_MEMH_AUTOINC_MIN = -16;
97 const int Hexagon_MEMB_AUTOINC_MAX = 7;
98 const int Hexagon_MEMB_AUTOINC_MIN = -8;
99 const int Hexagon_MEMV_AUTOINC_MAX = 192; // #s3
100 const int Hexagon_MEMV_AUTOINC_MIN = -256; // #s3
101 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384; // #s3
102 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3
104 // Pin the vtable to this file.
105 void HexagonInstrInfo::anchor() {}
107 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
108 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
112 static bool isIntRegForSubInst(unsigned Reg) {
113 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
114 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
118 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
119 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
120 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
124 /// Calculate number of instructions excluding the debug instructions.
125 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
126 MachineBasicBlock::const_instr_iterator MIE) {
128 for (; MIB != MIE; ++MIB) {
129 if (!MIB->isDebugValue())
136 /// Find the hardware loop instruction used to set-up the specified loop.
137 /// On Hexagon, we have two instructions used to set-up the hardware loop
138 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
139 /// to indicate the end of a loop.
140 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
141 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
144 if (EndLoopOp == Hexagon::ENDLOOP0) {
145 LOOPi = Hexagon::J2_loop0i;
146 LOOPr = Hexagon::J2_loop0r;
147 } else { // EndLoopOp == Hexagon::EndLOOP1
148 LOOPi = Hexagon::J2_loop1i;
149 LOOPr = Hexagon::J2_loop1r;
152 // The loop set-up instruction will be in a predecessor block
153 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
154 PE = BB->pred_end(); PB != PE; ++PB) {
155 // If this has been visited, already skip it.
156 if (!Visited.insert(*PB).second)
160 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
161 E = (*PB)->instr_rend(); I != E; ++I) {
162 int Opc = I->getOpcode();
163 if (Opc == LOOPi || Opc == LOOPr)
165 // We've reached a different loop, which means the loop0 has been removed.
166 if (Opc == EndLoopOp)
169 // Check the predecessors for the LOOP instruction.
170 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
178 /// Gather register def/uses from MI.
179 /// This treats possible (predicated) defs as actually happening ones
180 /// (conservatively).
181 static inline void parseOperands(const MachineInstr &MI,
182 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
186 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
187 const MachineOperand &MO = MI.getOperand(i);
192 unsigned Reg = MO.getReg();
197 Uses.push_back(MO.getReg());
200 Defs.push_back(MO.getReg());
205 // Position dependent, so check twice for swap.
206 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
208 case HexagonII::HSIG_None:
211 case HexagonII::HSIG_L1:
212 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
213 case HexagonII::HSIG_L2:
214 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
215 Gb == HexagonII::HSIG_A);
216 case HexagonII::HSIG_S1:
217 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
219 case HexagonII::HSIG_S2:
220 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
222 Gb == HexagonII::HSIG_A);
223 case HexagonII::HSIG_A:
224 return (Gb == HexagonII::HSIG_A);
225 case HexagonII::HSIG_Compound:
226 return (Gb == HexagonII::HSIG_Compound);
233 /// isLoadFromStackSlot - If the specified machine instruction is a direct
234 /// load from a stack slot, return the virtual or physical register number of
235 /// the destination along with the FrameIndex of the loaded stack slot. If
236 /// not, return 0. This predicate must return 0 if the instruction has
237 /// any side effects other than loading from the stack slot.
238 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
239 int &FrameIndex) const {
240 switch (MI.getOpcode()) {
243 case Hexagon::L2_loadri_io:
244 case Hexagon::L2_loadrd_io:
245 case Hexagon::V6_vL32b_ai:
246 case Hexagon::V6_vL32b_ai_128B:
247 case Hexagon::V6_vL32Ub_ai:
248 case Hexagon::V6_vL32Ub_ai_128B:
249 case Hexagon::LDriw_pred:
250 case Hexagon::LDriw_mod:
251 case Hexagon::PS_vloadrq_ai:
252 case Hexagon::PS_vloadrw_ai:
253 case Hexagon::PS_vloadrq_ai_128B:
254 case Hexagon::PS_vloadrw_ai_128B: {
255 const MachineOperand OpFI = MI.getOperand(1);
258 const MachineOperand OpOff = MI.getOperand(2);
259 if (!OpOff.isImm() || OpOff.getImm() != 0)
261 FrameIndex = OpFI.getIndex();
262 return MI.getOperand(0).getReg();
265 case Hexagon::L2_ploadrit_io:
266 case Hexagon::L2_ploadrif_io:
267 case Hexagon::L2_ploadrdt_io:
268 case Hexagon::L2_ploadrdf_io: {
269 const MachineOperand OpFI = MI.getOperand(2);
272 const MachineOperand OpOff = MI.getOperand(3);
273 if (!OpOff.isImm() || OpOff.getImm() != 0)
275 FrameIndex = OpFI.getIndex();
276 return MI.getOperand(0).getReg();
284 /// isStoreToStackSlot - If the specified machine instruction is a direct
285 /// store to a stack slot, return the virtual or physical register number of
286 /// the source reg along with the FrameIndex of the loaded stack slot. If
287 /// not, return 0. This predicate must return 0 if the instruction has
288 /// any side effects other than storing to the stack slot.
289 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
290 int &FrameIndex) const {
291 switch (MI.getOpcode()) {
294 case Hexagon::S2_storerb_io:
295 case Hexagon::S2_storerh_io:
296 case Hexagon::S2_storeri_io:
297 case Hexagon::S2_storerd_io:
298 case Hexagon::V6_vS32b_ai:
299 case Hexagon::V6_vS32b_ai_128B:
300 case Hexagon::V6_vS32Ub_ai:
301 case Hexagon::V6_vS32Ub_ai_128B:
302 case Hexagon::STriw_pred:
303 case Hexagon::STriw_mod:
304 case Hexagon::PS_vstorerq_ai:
305 case Hexagon::PS_vstorerw_ai:
306 case Hexagon::PS_vstorerq_ai_128B:
307 case Hexagon::PS_vstorerw_ai_128B: {
308 const MachineOperand &OpFI = MI.getOperand(0);
311 const MachineOperand &OpOff = MI.getOperand(1);
312 if (!OpOff.isImm() || OpOff.getImm() != 0)
314 FrameIndex = OpFI.getIndex();
315 return MI.getOperand(2).getReg();
318 case Hexagon::S2_pstorerbt_io:
319 case Hexagon::S2_pstorerbf_io:
320 case Hexagon::S2_pstorerht_io:
321 case Hexagon::S2_pstorerhf_io:
322 case Hexagon::S2_pstorerit_io:
323 case Hexagon::S2_pstorerif_io:
324 case Hexagon::S2_pstorerdt_io:
325 case Hexagon::S2_pstorerdf_io: {
326 const MachineOperand &OpFI = MI.getOperand(1);
329 const MachineOperand &OpOff = MI.getOperand(2);
330 if (!OpOff.isImm() || OpOff.getImm() != 0)
332 FrameIndex = OpFI.getIndex();
333 return MI.getOperand(3).getReg();
341 /// This function can analyze one/two way branching only and should (mostly) be
342 /// called by target independent side.
343 /// First entry is always the opcode of the branching instruction, except when
344 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
345 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
346 /// e.g. Jump_c p will have
350 /// Cond[0] = ENDLOOP
353 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
357 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
358 MachineBasicBlock *&TBB,
359 MachineBasicBlock *&FBB,
360 SmallVectorImpl<MachineOperand> &Cond,
361 bool AllowModify) const {
366 // If the block has no terminators, it just falls into the block after it.
367 MachineBasicBlock::instr_iterator I = MBB.instr_end();
368 if (I == MBB.instr_begin())
371 // A basic block may looks like this:
381 // It has two succs but does not have a terminator
382 // Don't know how to handle it.
386 // Don't analyze EH branches.
388 } while (I != MBB.instr_begin());
393 while (I->isDebugValue()) {
394 if (I == MBB.instr_begin())
399 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
400 I->getOperand(0).isMBB();
401 // Delete the J2_jump if it's equivalent to a fall-through.
402 if (AllowModify && JumpToBlock &&
403 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
404 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
405 I->eraseFromParent();
407 if (I == MBB.instr_begin())
411 if (!isUnpredicatedTerminator(*I))
414 // Get the last instruction in the block.
415 MachineInstr *LastInst = &*I;
416 MachineInstr *SecondLastInst = nullptr;
417 // Find one more terminator if present.
419 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
421 SecondLastInst = &*I;
423 // This is a third branch.
426 if (I == MBB.instr_begin())
431 int LastOpcode = LastInst->getOpcode();
432 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
433 // If the branch target is not a basic block, it could be a tail call.
434 // (It is, if the target is a function.)
435 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
437 if (SecLastOpcode == Hexagon::J2_jump &&
438 !SecondLastInst->getOperand(0).isMBB())
441 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
442 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
444 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
447 // If there is only one terminator instruction, process it.
448 if (LastInst && !SecondLastInst) {
449 if (LastOpcode == Hexagon::J2_jump) {
450 TBB = LastInst->getOperand(0).getMBB();
453 if (isEndLoopN(LastOpcode)) {
454 TBB = LastInst->getOperand(0).getMBB();
455 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
456 Cond.push_back(LastInst->getOperand(0));
459 if (LastOpcodeHasJMP_c) {
460 TBB = LastInst->getOperand(1).getMBB();
461 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
462 Cond.push_back(LastInst->getOperand(0));
465 // Only supporting rr/ri versions of new-value jumps.
466 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
467 TBB = LastInst->getOperand(2).getMBB();
468 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
469 Cond.push_back(LastInst->getOperand(0));
470 Cond.push_back(LastInst->getOperand(1));
473 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
474 << " with one jump\n";);
475 // Otherwise, don't know what this is.
479 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
480 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
481 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
482 if (!SecondLastInst->getOperand(1).isMBB())
484 TBB = SecondLastInst->getOperand(1).getMBB();
485 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
486 Cond.push_back(SecondLastInst->getOperand(0));
487 FBB = LastInst->getOperand(0).getMBB();
491 // Only supporting rr/ri versions of new-value jumps.
492 if (SecLastOpcodeHasNVJump &&
493 (SecondLastInst->getNumExplicitOperands() == 3) &&
494 (LastOpcode == Hexagon::J2_jump)) {
495 TBB = SecondLastInst->getOperand(2).getMBB();
496 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
497 Cond.push_back(SecondLastInst->getOperand(0));
498 Cond.push_back(SecondLastInst->getOperand(1));
499 FBB = LastInst->getOperand(0).getMBB();
503 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
504 // executed, so remove it.
505 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
506 TBB = SecondLastInst->getOperand(0).getMBB();
507 I = LastInst->getIterator();
509 I->eraseFromParent();
513 // If the block ends with an ENDLOOP, and J2_jump, handle it.
514 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
515 TBB = SecondLastInst->getOperand(0).getMBB();
516 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
517 Cond.push_back(SecondLastInst->getOperand(0));
518 FBB = LastInst->getOperand(0).getMBB();
521 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
522 << " with two jumps";);
523 // Otherwise, can't handle this.
528 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
529 int *BytesRemoved) const {
530 assert(!BytesRemoved && "code size not handled");
532 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
533 MachineBasicBlock::iterator I = MBB.end();
535 while (I != MBB.begin()) {
537 if (I->isDebugValue())
539 // Only removing branches from end of MBB.
542 if (Count && (I->getOpcode() == Hexagon::J2_jump))
543 llvm_unreachable("Malformed basic block: unconditional branch not last");
544 MBB.erase(&MBB.back());
551 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
552 MachineBasicBlock *TBB,
553 MachineBasicBlock *FBB,
554 ArrayRef<MachineOperand> Cond,
556 int *BytesAdded) const {
557 unsigned BOpc = Hexagon::J2_jump;
558 unsigned BccOpc = Hexagon::J2_jumpt;
559 assert(validateBranchCond(Cond) && "Invalid branching condition");
560 assert(TBB && "insertBranch must not be told to insert a fallthrough");
561 assert(!BytesAdded && "code size not handled");
563 // Check if reverseBranchCondition has asked to reverse this branch
564 // If we want to reverse the branch an odd number of times, we want
566 if (!Cond.empty() && Cond[0].isImm())
567 BccOpc = Cond[0].getImm();
571 // Due to a bug in TailMerging/CFG Optimization, we need to add a
572 // special case handling of a predicated jump followed by an
573 // unconditional jump. If not, Tail Merging and CFG Optimization go
574 // into an infinite loop.
575 MachineBasicBlock *NewTBB, *NewFBB;
576 SmallVector<MachineOperand, 4> Cond;
577 auto Term = MBB.getFirstTerminator();
578 if (Term != MBB.end() && isPredicated(*Term) &&
579 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
580 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
581 reverseBranchCondition(Cond);
583 return insertBranch(MBB, TBB, nullptr, Cond, DL);
585 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
586 } else if (isEndLoopN(Cond[0].getImm())) {
587 int EndLoopOp = Cond[0].getImm();
588 assert(Cond[1].isMBB());
589 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
590 // Check for it, and change the BB target if needed.
591 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
592 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
593 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
594 Loop->getOperand(0).setMBB(TBB);
595 // Add the ENDLOOP after the finding the LOOP0.
596 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
597 } else if (isNewValueJump(Cond[0].getImm())) {
598 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
600 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
601 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
602 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
603 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
604 if (Cond[2].isReg()) {
605 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
606 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
607 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
608 } else if(Cond[2].isImm()) {
609 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
610 addImm(Cond[2].getImm()).addMBB(TBB);
612 llvm_unreachable("Invalid condition for branching");
614 assert((Cond.size() == 2) && "Malformed cond vector");
615 const MachineOperand &RO = Cond[1];
616 unsigned Flags = getUndefRegState(RO.isUndef());
617 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
621 assert((!Cond.empty()) &&
622 "Cond. cannot be empty when multiple branchings are required");
623 assert((!isNewValueJump(Cond[0].getImm())) &&
624 "NV-jump cannot be inserted with another branch");
625 // Special case for hardware loops. The condition is a basic block.
626 if (isEndLoopN(Cond[0].getImm())) {
627 int EndLoopOp = Cond[0].getImm();
628 assert(Cond[1].isMBB());
629 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
630 // Check for it, and change the BB target if needed.
631 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
632 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
633 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
634 Loop->getOperand(0).setMBB(TBB);
635 // Add the ENDLOOP after the finding the LOOP0.
636 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
638 const MachineOperand &RO = Cond[1];
639 unsigned Flags = getUndefRegState(RO.isUndef());
640 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
642 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
647 /// Analyze the loop code to find the loop induction variable and compare used
648 /// to compute the number of iterations. Currently, we analyze loop that are
649 /// controlled using hardware loops. In this case, the induction variable
650 /// instruction is null. For all other cases, this function returns true, which
651 /// means we're unable to analyze it.
652 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L,
653 MachineInstr *&IndVarInst,
654 MachineInstr *&CmpInst) const {
656 MachineBasicBlock *LoopEnd = L.getBottomBlock();
657 MachineBasicBlock::iterator I = LoopEnd->getFirstTerminator();
658 // We really "analyze" only hardware loops right now.
659 if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
660 IndVarInst = nullptr;
667 /// Generate code to reduce the loop iteration by one and check if the loop is
668 /// finished. Return the value/register of the new loop count. this function
669 /// assumes the nth iteration is peeled first.
670 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
671 MachineInstr *IndVar, MachineInstr &Cmp,
672 SmallVectorImpl<MachineOperand> &Cond,
673 SmallVectorImpl<MachineInstr *> &PrevInsts,
674 unsigned Iter, unsigned MaxIter) const {
675 // We expect a hardware loop currently. This means that IndVar is set
676 // to null, and the compare is the ENDLOOP instruction.
677 assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
678 && "Expecting a hardware loop");
679 MachineFunction *MF = MBB.getParent();
680 DebugLoc DL = Cmp.getDebugLoc();
681 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
682 MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(), VisitedBBs);
685 // If the loop trip count is a compile-time value, then just change the
687 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
688 Loop->getOpcode() == Hexagon::J2_loop1i) {
689 int64_t Offset = Loop->getOperand(1).getImm();
691 Loop->eraseFromParent();
693 Loop->getOperand(1).setImm(Offset - 1);
696 // The loop trip count is a run-time value. We generate code to subtract
697 // one from the trip count, and update the loop instruction.
698 assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
699 unsigned LoopCount = Loop->getOperand(1).getReg();
700 // Check if we're done with the loop.
701 unsigned LoopEnd = createVR(MF, MVT::i1);
702 MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
703 addReg(LoopCount).addImm(1);
704 unsigned NewLoopCount = createVR(MF, MVT::i32);
705 MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
706 addReg(LoopCount).addImm(-1);
707 // Update the previously generated instructions with the new loop counter.
708 for (SmallVectorImpl<MachineInstr *>::iterator I = PrevInsts.begin(),
709 E = PrevInsts.end(); I != E; ++I)
710 (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo());
712 PrevInsts.push_back(NewCmp);
713 PrevInsts.push_back(NewAdd);
714 // Insert the new loop instruction if this is the last time the loop is
717 BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
718 addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
719 // Delete the old loop instruction.
721 Loop->eraseFromParent();
722 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
723 Cond.push_back(NewCmp->getOperand(0));
727 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
728 unsigned NumCycles, unsigned ExtraPredCycles,
729 BranchProbability Probability) const {
730 return nonDbgBBSize(&MBB) <= 3;
734 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
735 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
736 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
738 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
742 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
743 unsigned NumInstrs, BranchProbability Probability) const {
744 return NumInstrs <= 4;
747 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
748 MachineBasicBlock::iterator I,
749 const DebugLoc &DL, unsigned DestReg,
750 unsigned SrcReg, bool KillSrc) const {
751 auto &HRI = getRegisterInfo();
752 unsigned KillFlag = getKillRegState(KillSrc);
754 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
755 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
756 .addReg(SrcReg, KillFlag);
759 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
760 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
761 .addReg(SrcReg, KillFlag);
764 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
765 // Map Pd = Ps to Pd = or(Ps, Ps).
766 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
767 .addReg(SrcReg).addReg(SrcReg, KillFlag);
770 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
771 Hexagon::IntRegsRegClass.contains(SrcReg)) {
772 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
773 .addReg(SrcReg, KillFlag);
776 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
777 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
778 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
779 .addReg(SrcReg, KillFlag);
782 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
783 Hexagon::IntRegsRegClass.contains(SrcReg)) {
784 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
785 .addReg(SrcReg, KillFlag);
788 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
789 Hexagon::IntRegsRegClass.contains(DestReg)) {
790 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
791 .addReg(SrcReg, KillFlag);
794 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
795 Hexagon::PredRegsRegClass.contains(DestReg)) {
796 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
797 .addReg(SrcReg, KillFlag);
800 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
801 Hexagon::IntRegsRegClass.contains(DestReg)) {
802 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
803 .addReg(SrcReg, KillFlag);
806 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
807 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
808 addReg(SrcReg, KillFlag);
811 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
812 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
813 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
814 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
815 .addReg(HiSrc, KillFlag)
816 .addReg(LoSrc, KillFlag);
819 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
820 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
822 .addReg(SrcReg, KillFlag);
825 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
826 Hexagon::VectorRegsRegClass.contains(DestReg)) {
827 llvm_unreachable("Unimplemented pred to vec");
830 if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
831 Hexagon::VectorRegsRegClass.contains(SrcReg)) {
832 llvm_unreachable("Unimplemented vec to pred");
835 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
836 unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
837 unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
838 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
839 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
840 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
841 .addReg(HiSrc, KillFlag);
842 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
843 .addReg(LoSrc, KillFlag);
848 // Show the invalid registers to ease debugging.
849 dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
850 << ": " << PrintReg(DestReg, &HRI)
851 << " = " << PrintReg(SrcReg, &HRI) << '\n';
853 llvm_unreachable("Unimplemented");
857 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
858 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
859 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
860 DebugLoc DL = MBB.findDebugLoc(I);
861 MachineFunction &MF = *MBB.getParent();
862 MachineFrameInfo &MFI = MF.getFrameInfo();
863 unsigned Align = MFI.getObjectAlignment(FI);
864 unsigned KillFlag = getKillRegState(isKill);
866 MachineMemOperand *MMO = MF.getMachineMemOperand(
867 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
868 MFI.getObjectSize(FI), Align);
870 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
871 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
872 .addFrameIndex(FI).addImm(0)
873 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
874 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
875 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
876 .addFrameIndex(FI).addImm(0)
877 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
878 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
879 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
880 .addFrameIndex(FI).addImm(0)
881 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
882 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
883 BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
884 .addFrameIndex(FI).addImm(0)
885 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
886 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
887 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B))
888 .addFrameIndex(FI).addImm(0)
889 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
890 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
891 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
892 .addFrameIndex(FI).addImm(0)
893 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
894 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
895 unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
896 : Hexagon::V6_vS32b_ai_128B;
897 BuildMI(MBB, I, DL, get(Opc))
898 .addFrameIndex(FI).addImm(0)
899 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
900 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
901 unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
902 : Hexagon::V6_vS32b_ai;
903 BuildMI(MBB, I, DL, get(Opc))
904 .addFrameIndex(FI).addImm(0)
905 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
906 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
907 unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
908 : Hexagon::PS_vstorerw_ai;
909 BuildMI(MBB, I, DL, get(Opc))
910 .addFrameIndex(FI).addImm(0)
911 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
912 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
913 unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
914 : Hexagon::PS_vstorerw_ai_128B;
915 BuildMI(MBB, I, DL, get(Opc))
916 .addFrameIndex(FI).addImm(0)
917 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
919 llvm_unreachable("Unimplemented");
923 void HexagonInstrInfo::loadRegFromStackSlot(
924 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
925 int FI, const TargetRegisterClass *RC,
926 const TargetRegisterInfo *TRI) const {
927 DebugLoc DL = MBB.findDebugLoc(I);
928 MachineFunction &MF = *MBB.getParent();
929 MachineFrameInfo &MFI = MF.getFrameInfo();
930 unsigned Align = MFI.getObjectAlignment(FI);
932 MachineMemOperand *MMO = MF.getMachineMemOperand(
933 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
934 MFI.getObjectSize(FI), Align);
936 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
937 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
938 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
939 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
940 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
941 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
942 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
943 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
944 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
945 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
946 BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
947 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
948 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
949 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg)
950 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
951 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
952 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
953 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
954 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
955 unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
956 : Hexagon::PS_vloadrw_ai_128B;
957 BuildMI(MBB, I, DL, get(Opc), DestReg)
958 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
959 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
960 unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
961 : Hexagon::V6_vL32b_ai_128B;
962 BuildMI(MBB, I, DL, get(Opc), DestReg)
963 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
965 unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
966 : Hexagon::V6_vL32b_ai;
967 BuildMI(MBB, I, DL, get(Opc), DestReg)
968 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
969 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
970 unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
971 : Hexagon::PS_vloadrw_ai;
972 BuildMI(MBB, I, DL, get(Opc), DestReg)
973 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
975 llvm_unreachable("Can't store this register to stack slot");
980 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
981 const MachineBasicBlock &B = *MI.getParent();
983 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
984 for (auto I = B.rbegin(); I != E; ++I)
985 Regs.stepBackward(*I);
988 /// expandPostRAPseudo - This function is called for all pseudo instructions
989 /// that remain after register allocation. Many pseudo instructions are
990 /// created to help register allocation. This is the place to convert them
991 /// into real instructions. The target can edit MI in place, or it can insert
992 /// new instructions and erase MI. The function should return true if
993 /// anything was changed.
994 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
995 const HexagonRegisterInfo &HRI = getRegisterInfo();
996 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
997 MachineBasicBlock &MBB = *MI.getParent();
998 DebugLoc DL = MI.getDebugLoc();
999 unsigned Opc = MI.getOpcode();
1000 const unsigned VecOffset = 1;
1003 case TargetOpcode::COPY: {
1004 MachineOperand &MD = MI.getOperand(0);
1005 MachineOperand &MS = MI.getOperand(1);
1006 MachineBasicBlock::iterator MBBI = MI.getIterator();
1007 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1008 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1009 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1014 case Hexagon::PS_aligna:
1015 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1016 .addReg(HRI.getFrameRegister())
1017 .addImm(-MI.getOperand(1).getImm());
1020 case Hexagon::V6_vassignp_128B:
1021 case Hexagon::V6_vassignp: {
1022 unsigned SrcReg = MI.getOperand(1).getReg();
1023 unsigned DstReg = MI.getOperand(0).getReg();
1024 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1025 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1026 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1027 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1031 case Hexagon::V6_lo_128B:
1032 case Hexagon::V6_lo: {
1033 unsigned SrcReg = MI.getOperand(1).getReg();
1034 unsigned DstReg = MI.getOperand(0).getReg();
1035 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1036 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1038 MRI.clearKillFlags(SrcSubLo);
1041 case Hexagon::V6_hi_128B:
1042 case Hexagon::V6_hi: {
1043 unsigned SrcReg = MI.getOperand(1).getReg();
1044 unsigned DstReg = MI.getOperand(0).getReg();
1045 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1046 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1048 MRI.clearKillFlags(SrcSubHi);
1051 case Hexagon::PS_vstorerw_ai:
1052 case Hexagon::PS_vstorerwu_ai:
1053 case Hexagon::PS_vstorerw_ai_128B:
1054 case Hexagon::PS_vstorerwu_ai_128B: {
1055 bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
1056 Opc == Hexagon::PS_vstorerwu_ai_128B);
1057 bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
1058 Opc == Hexagon::PS_vstorerw_ai_128B);
1059 unsigned SrcReg = MI.getOperand(2).getReg();
1060 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1061 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1064 NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1065 : Hexagon::V6_vS32b_ai;
1067 NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
1068 : Hexagon::V6_vS32Ub_ai;
1070 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1071 MachineInstr *MI1New =
1072 BuildMI(MBB, MI, DL, get(NewOpc))
1073 .addOperand(MI.getOperand(0))
1074 .addImm(MI.getOperand(1).getImm())
1076 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1077 MI1New->getOperand(0).setIsKill(false);
1078 BuildMI(MBB, MI, DL, get(NewOpc))
1079 .addOperand(MI.getOperand(0))
1080 // The Vectors are indexed in multiples of vector size.
1081 .addImm(MI.getOperand(1).getImm() + Offset)
1083 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1087 case Hexagon::PS_vloadrw_ai:
1088 case Hexagon::PS_vloadrwu_ai:
1089 case Hexagon::PS_vloadrw_ai_128B:
1090 case Hexagon::PS_vloadrwu_ai_128B: {
1091 bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
1092 Opc == Hexagon::PS_vloadrwu_ai_128B);
1093 bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
1094 Opc == Hexagon::PS_vloadrw_ai_128B);
1097 NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1098 : Hexagon::V6_vL32b_ai;
1100 NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
1101 : Hexagon::V6_vL32Ub_ai;
1103 unsigned DstReg = MI.getOperand(0).getReg();
1104 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1105 MachineInstr *MI1New =
1106 BuildMI(MBB, MI, DL, get(NewOpc),
1107 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1108 .addOperand(MI.getOperand(1))
1109 .addImm(MI.getOperand(2).getImm());
1110 MI1New->getOperand(1).setIsKill(false);
1111 BuildMI(MBB, MI, DL, get(NewOpc),
1112 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1113 .addOperand(MI.getOperand(1))
1114 // The Vectors are indexed in multiples of vector size.
1115 .addImm(MI.getOperand(2).getImm() + Offset)
1116 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1120 case Hexagon::PS_true: {
1121 unsigned Reg = MI.getOperand(0).getReg();
1122 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1123 .addReg(Reg, RegState::Undef)
1124 .addReg(Reg, RegState::Undef);
1128 case Hexagon::PS_false: {
1129 unsigned Reg = MI.getOperand(0).getReg();
1130 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1131 .addReg(Reg, RegState::Undef)
1132 .addReg(Reg, RegState::Undef);
1136 case Hexagon::PS_vmulw: {
1137 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1138 unsigned DstReg = MI.getOperand(0).getReg();
1139 unsigned Src1Reg = MI.getOperand(1).getReg();
1140 unsigned Src2Reg = MI.getOperand(2).getReg();
1141 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1142 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1143 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1144 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1145 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1146 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1149 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1150 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1154 MRI.clearKillFlags(Src1SubHi);
1155 MRI.clearKillFlags(Src1SubLo);
1156 MRI.clearKillFlags(Src2SubHi);
1157 MRI.clearKillFlags(Src2SubLo);
1160 case Hexagon::PS_vmulw_acc: {
1161 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1162 unsigned DstReg = MI.getOperand(0).getReg();
1163 unsigned Src1Reg = MI.getOperand(1).getReg();
1164 unsigned Src2Reg = MI.getOperand(2).getReg();
1165 unsigned Src3Reg = MI.getOperand(3).getReg();
1166 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1167 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1168 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1169 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1170 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1171 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1172 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1173 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1177 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1178 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1183 MRI.clearKillFlags(Src1SubHi);
1184 MRI.clearKillFlags(Src1SubLo);
1185 MRI.clearKillFlags(Src2SubHi);
1186 MRI.clearKillFlags(Src2SubLo);
1187 MRI.clearKillFlags(Src3SubHi);
1188 MRI.clearKillFlags(Src3SubLo);
1191 case Hexagon::PS_pselect: {
1192 const MachineOperand &Op0 = MI.getOperand(0);
1193 const MachineOperand &Op1 = MI.getOperand(1);
1194 const MachineOperand &Op2 = MI.getOperand(2);
1195 const MachineOperand &Op3 = MI.getOperand(3);
1196 unsigned Rd = Op0.getReg();
1197 unsigned Pu = Op1.getReg();
1198 unsigned Rs = Op2.getReg();
1199 unsigned Rt = Op3.getReg();
1200 DebugLoc DL = MI.getDebugLoc();
1201 unsigned K1 = getKillRegState(Op1.isKill());
1202 unsigned K2 = getKillRegState(Op2.isKill());
1203 unsigned K3 = getKillRegState(Op3.isKill());
1205 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1206 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1209 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1215 case Hexagon::PS_vselect:
1216 case Hexagon::PS_vselect_128B: {
1217 const MachineOperand &Op0 = MI.getOperand(0);
1218 const MachineOperand &Op1 = MI.getOperand(1);
1219 const MachineOperand &Op2 = MI.getOperand(2);
1220 const MachineOperand &Op3 = MI.getOperand(3);
1221 LivePhysRegs LiveAtMI(&HRI);
1222 getLiveRegsAt(LiveAtMI, MI);
1223 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1224 if (Op0.getReg() != Op2.getReg()) {
1225 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1230 T.addReg(Op0.getReg(), RegState::Implicit);
1233 if (Op0.getReg() != Op3.getReg()) {
1234 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1239 T.addReg(Op0.getReg(), RegState::Implicit);
1244 case Hexagon::PS_wselect:
1245 case Hexagon::PS_wselect_128B: {
1246 MachineOperand &Op0 = MI.getOperand(0);
1247 MachineOperand &Op1 = MI.getOperand(1);
1248 MachineOperand &Op2 = MI.getOperand(2);
1249 MachineOperand &Op3 = MI.getOperand(3);
1250 LivePhysRegs LiveAtMI(&HRI);
1251 getLiveRegsAt(LiveAtMI, MI);
1252 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1254 if (Op0.getReg() != Op2.getReg()) {
1255 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1256 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1257 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1263 T.addReg(Op0.getReg(), RegState::Implicit);
1266 if (Op0.getReg() != Op3.getReg()) {
1267 unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1268 unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1269 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1275 T.addReg(Op0.getReg(), RegState::Implicit);
1280 case Hexagon::PS_tailcall_i:
1281 MI.setDesc(get(Hexagon::J2_jump));
1283 case Hexagon::PS_tailcall_r:
1284 case Hexagon::PS_jmpret:
1285 MI.setDesc(get(Hexagon::J2_jumpr));
1287 case Hexagon::PS_jmprett:
1288 MI.setDesc(get(Hexagon::J2_jumprt));
1290 case Hexagon::PS_jmpretf:
1291 MI.setDesc(get(Hexagon::J2_jumprf));
1293 case Hexagon::PS_jmprettnewpt:
1294 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1296 case Hexagon::PS_jmpretfnewpt:
1297 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1299 case Hexagon::PS_jmprettnew:
1300 MI.setDesc(get(Hexagon::J2_jumprtnew));
1302 case Hexagon::PS_jmpretfnew:
1303 MI.setDesc(get(Hexagon::J2_jumprfnew));
1311 // We indicate that we want to reverse the branch by
1312 // inserting the reversed branching opcode.
1313 bool HexagonInstrInfo::reverseBranchCondition(
1314 SmallVectorImpl<MachineOperand> &Cond) const {
1317 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1318 unsigned opcode = Cond[0].getImm();
1320 assert(get(opcode).isBranch() && "Should be a branching condition.");
1321 if (isEndLoopN(opcode))
1323 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1324 Cond[0].setImm(NewOpcode);
1329 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1330 MachineBasicBlock::iterator MI) const {
1332 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1336 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1337 return getAddrMode(MI) == HexagonII::PostInc;
1341 // Returns true if an instruction is predicated irrespective of the predicate
1342 // sense. For example, all of the following will return true.
1343 // if (p0) R1 = add(R2, R3)
1344 // if (!p0) R1 = add(R2, R3)
1345 // if (p0.new) R1 = add(R2, R3)
1346 // if (!p0.new) R1 = add(R2, R3)
1347 // Note: New-value stores are not included here as in the current
1348 // implementation, we don't need to check their predicate sense.
1349 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1350 const uint64_t F = MI.getDesc().TSFlags;
1351 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1355 bool HexagonInstrInfo::PredicateInstruction(
1356 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1357 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1358 isEndLoopN(Cond[0].getImm())) {
1359 DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1362 int Opc = MI.getOpcode();
1363 assert (isPredicable(MI) && "Expected predicable instruction");
1364 bool invertJump = predOpcodeHasNot(Cond);
1366 // We have to predicate MI "in place", i.e. after this function returns,
1367 // MI will need to be transformed into a predicated form. To avoid com-
1368 // plicated manipulations with the operands (handling tied operands,
1369 // etc.), build a new temporary instruction, then overwrite MI with it.
1371 MachineBasicBlock &B = *MI.getParent();
1372 DebugLoc DL = MI.getDebugLoc();
1373 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1374 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1375 unsigned NOp = 0, NumOps = MI.getNumOperands();
1376 while (NOp < NumOps) {
1377 MachineOperand &Op = MI.getOperand(NOp);
1378 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1384 unsigned PredReg, PredRegPos, PredRegFlags;
1385 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1388 T.addReg(PredReg, PredRegFlags);
1389 while (NOp < NumOps)
1390 T.addOperand(MI.getOperand(NOp++));
1392 MI.setDesc(get(PredOpc));
1393 while (unsigned n = MI.getNumOperands())
1394 MI.RemoveOperand(n-1);
1395 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1396 MI.addOperand(T->getOperand(i));
1398 MachineBasicBlock::instr_iterator TI = T->getIterator();
1401 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1402 MRI.clearKillFlags(PredReg);
1407 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1408 ArrayRef<MachineOperand> Pred2) const {
1414 bool HexagonInstrInfo::DefinesPredicate(
1415 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
1416 auto &HRI = getRegisterInfo();
1417 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1418 MachineOperand MO = MI.getOperand(oper);
1419 if (MO.isReg() && MO.isDef()) {
1420 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1421 if (RC == &Hexagon::PredRegsRegClass) {
1431 bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
1432 return MI.getDesc().isPredicable();
1435 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1436 const MachineBasicBlock *MBB,
1437 const MachineFunction &MF) const {
1438 // Debug info is never a scheduling boundary. It's necessary to be explicit
1439 // due to the special treatment of IT instructions below, otherwise a
1440 // dbg_value followed by an IT will result in the IT instruction being
1441 // considered a scheduling hazard, which is wrong. It should be the actual
1442 // instruction preceding the dbg_value instruction(s), just like it is
1443 // when debug info is not present.
1444 if (MI.isDebugValue())
1447 // Throwing call is a boundary.
1449 // Don't mess around with no return calls.
1450 if (doesNotReturn(MI))
1452 // If any of the block's successors is a landing pad, this could be a
1454 for (auto I : MBB->successors())
1459 // Terminators and labels can't be scheduled around.
1460 if (MI.getDesc().isTerminator() || MI.isPosition())
1463 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1470 /// Measure the specified inline asm to determine an approximation of its
1472 /// Comments (which run till the next SeparatorString or newline) do not
1473 /// count as an instruction.
1474 /// Any other non-whitespace text is considered an instruction, with
1475 /// multiple instructions separated by SeparatorString or newlines.
1476 /// Variable-length instructions are not handled here; this function
1477 /// may be overloaded in the target code to do that.
1478 /// Hexagon counts the number of ##'s and adjust for that many
1479 /// constant exenders.
1480 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1481 const MCAsmInfo &MAI) const {
1482 StringRef AStr(Str);
1483 // Count the number of instructions in the asm.
1484 bool atInsnStart = true;
1485 unsigned Length = 0;
1486 for (; *Str; ++Str) {
1487 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1488 strlen(MAI.getSeparatorString())) == 0)
1490 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1491 Length += MAI.getMaxInstLength();
1492 atInsnStart = false;
1494 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1495 MAI.getCommentString().size()) == 0)
1496 atInsnStart = false;
1499 // Add to size number of constant extenders seen * 4.
1500 StringRef Occ("##");
1501 Length += AStr.count(Occ)*4;
1506 ScheduleHazardRecognizer*
1507 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1508 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1509 if (UseDFAHazardRec) {
1510 auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
1511 return new HexagonHazardRecognizer(II, this, HST);
1513 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1517 /// \brief For a comparison instruction, return the source registers in
1518 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1519 /// compares against in CmpValue. Return true if the comparison instruction
1520 /// can be analyzed.
1521 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1522 unsigned &SrcReg2, int &Mask,
1524 unsigned Opc = MI.getOpcode();
1526 // Set mask and the first source register.
1528 case Hexagon::C2_cmpeq:
1529 case Hexagon::C2_cmpeqp:
1530 case Hexagon::C2_cmpgt:
1531 case Hexagon::C2_cmpgtp:
1532 case Hexagon::C2_cmpgtu:
1533 case Hexagon::C2_cmpgtup:
1534 case Hexagon::C4_cmpneq:
1535 case Hexagon::C4_cmplte:
1536 case Hexagon::C4_cmplteu:
1537 case Hexagon::C2_cmpeqi:
1538 case Hexagon::C2_cmpgti:
1539 case Hexagon::C2_cmpgtui:
1540 case Hexagon::C4_cmpneqi:
1541 case Hexagon::C4_cmplteui:
1542 case Hexagon::C4_cmpltei:
1543 SrcReg = MI.getOperand(1).getReg();
1546 case Hexagon::A4_cmpbeq:
1547 case Hexagon::A4_cmpbgt:
1548 case Hexagon::A4_cmpbgtu:
1549 case Hexagon::A4_cmpbeqi:
1550 case Hexagon::A4_cmpbgti:
1551 case Hexagon::A4_cmpbgtui:
1552 SrcReg = MI.getOperand(1).getReg();
1555 case Hexagon::A4_cmpheq:
1556 case Hexagon::A4_cmphgt:
1557 case Hexagon::A4_cmphgtu:
1558 case Hexagon::A4_cmpheqi:
1559 case Hexagon::A4_cmphgti:
1560 case Hexagon::A4_cmphgtui:
1561 SrcReg = MI.getOperand(1).getReg();
1566 // Set the value/second source register.
1568 case Hexagon::C2_cmpeq:
1569 case Hexagon::C2_cmpeqp:
1570 case Hexagon::C2_cmpgt:
1571 case Hexagon::C2_cmpgtp:
1572 case Hexagon::C2_cmpgtu:
1573 case Hexagon::C2_cmpgtup:
1574 case Hexagon::A4_cmpbeq:
1575 case Hexagon::A4_cmpbgt:
1576 case Hexagon::A4_cmpbgtu:
1577 case Hexagon::A4_cmpheq:
1578 case Hexagon::A4_cmphgt:
1579 case Hexagon::A4_cmphgtu:
1580 case Hexagon::C4_cmpneq:
1581 case Hexagon::C4_cmplte:
1582 case Hexagon::C4_cmplteu:
1583 SrcReg2 = MI.getOperand(2).getReg();
1586 case Hexagon::C2_cmpeqi:
1587 case Hexagon::C2_cmpgtui:
1588 case Hexagon::C2_cmpgti:
1589 case Hexagon::C4_cmpneqi:
1590 case Hexagon::C4_cmplteui:
1591 case Hexagon::C4_cmpltei:
1592 case Hexagon::A4_cmpbeqi:
1593 case Hexagon::A4_cmpbgti:
1594 case Hexagon::A4_cmpbgtui:
1595 case Hexagon::A4_cmpheqi:
1596 case Hexagon::A4_cmphgti:
1597 case Hexagon::A4_cmphgtui:
1599 Value = MI.getOperand(2).getImm();
1606 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1607 const MachineInstr &MI,
1608 unsigned *PredCost) const {
1609 return getInstrTimingClassLatency(ItinData, MI);
1613 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1614 const TargetSubtargetInfo &STI) const {
1615 const InstrItineraryData *II = STI.getInstrItineraryData();
1616 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1620 // Inspired by this pair:
1621 // %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1622 // S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1623 // Currently AA considers the addresses in these instructions to be aliasing.
1624 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1625 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1626 int OffsetA = 0, OffsetB = 0;
1627 unsigned SizeA = 0, SizeB = 0;
1629 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1630 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1633 // Instructions that are pure loads, not loads and stores like memops are not
1635 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1638 // Get base, offset, and access size in MIa.
1639 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1640 if (!BaseRegA || !SizeA)
1643 // Get base, offset, and access size in MIb.
1644 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
1645 if (!BaseRegB || !SizeB)
1648 if (BaseRegA != BaseRegB)
1651 // This is a mem access with the same base register and known offsets from it.
1653 if (OffsetA > OffsetB) {
1654 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1655 return (SizeB <= offDiff);
1656 } else if (OffsetA < OffsetB) {
1657 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1658 return (SizeA <= offDiff);
1665 /// If the instruction is an increment of a constant value, return the amount.
1666 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
1668 if (isPostIncrement(MI)) {
1669 unsigned AccessSize;
1670 return getBaseAndOffset(MI, Value, AccessSize);
1672 if (MI.getOpcode() == Hexagon::A2_addi) {
1673 Value = MI.getOperand(2).getImm();
1681 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
1682 MachineRegisterInfo &MRI = MF->getRegInfo();
1683 const TargetRegisterClass *TRC;
1684 if (VT == MVT::i1) {
1685 TRC = &Hexagon::PredRegsRegClass;
1686 } else if (VT == MVT::i32 || VT == MVT::f32) {
1687 TRC = &Hexagon::IntRegsRegClass;
1688 } else if (VT == MVT::i64 || VT == MVT::f64) {
1689 TRC = &Hexagon::DoubleRegsRegClass;
1691 llvm_unreachable("Cannot handle this register class");
1694 unsigned NewReg = MRI.createVirtualRegister(TRC);
1699 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
1700 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1704 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
1705 const uint64_t F = MI.getDesc().TSFlags;
1706 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
1710 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
1711 const MachineFunction *MF = MI.getParent()->getParent();
1712 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1713 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1716 && !(QII->isTC2Early(MI))
1717 && !(MI.getDesc().mayLoad())
1718 && !(MI.getDesc().mayStore())
1719 && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
1720 && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
1721 && !(QII->isMemOp(MI))
1731 // Return true if the instruction is a compund branch instruction.
1732 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
1733 return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch());
1737 bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const {
1738 return (MI.isBranch() && isPredicated(MI)) ||
1739 isConditionalTransfer(MI) ||
1740 isConditionalALU32(MI) ||
1741 isConditionalLoad(MI) ||
1742 // Predicated stores which don't have a .new on any operands.
1743 (MI.mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
1744 !isPredicatedNew(MI));
1748 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr &MI) const {
1749 switch (MI.getOpcode()) {
1750 case Hexagon::A2_paddf:
1751 case Hexagon::A2_paddfnew:
1752 case Hexagon::A2_paddif:
1753 case Hexagon::A2_paddifnew:
1754 case Hexagon::A2_paddit:
1755 case Hexagon::A2_padditnew:
1756 case Hexagon::A2_paddt:
1757 case Hexagon::A2_paddtnew:
1758 case Hexagon::A2_pandf:
1759 case Hexagon::A2_pandfnew:
1760 case Hexagon::A2_pandt:
1761 case Hexagon::A2_pandtnew:
1762 case Hexagon::A2_porf:
1763 case Hexagon::A2_porfnew:
1764 case Hexagon::A2_port:
1765 case Hexagon::A2_portnew:
1766 case Hexagon::A2_psubf:
1767 case Hexagon::A2_psubfnew:
1768 case Hexagon::A2_psubt:
1769 case Hexagon::A2_psubtnew:
1770 case Hexagon::A2_pxorf:
1771 case Hexagon::A2_pxorfnew:
1772 case Hexagon::A2_pxort:
1773 case Hexagon::A2_pxortnew:
1774 case Hexagon::A4_paslhf:
1775 case Hexagon::A4_paslhfnew:
1776 case Hexagon::A4_paslht:
1777 case Hexagon::A4_paslhtnew:
1778 case Hexagon::A4_pasrhf:
1779 case Hexagon::A4_pasrhfnew:
1780 case Hexagon::A4_pasrht:
1781 case Hexagon::A4_pasrhtnew:
1782 case Hexagon::A4_psxtbf:
1783 case Hexagon::A4_psxtbfnew:
1784 case Hexagon::A4_psxtbt:
1785 case Hexagon::A4_psxtbtnew:
1786 case Hexagon::A4_psxthf:
1787 case Hexagon::A4_psxthfnew:
1788 case Hexagon::A4_psxtht:
1789 case Hexagon::A4_psxthtnew:
1790 case Hexagon::A4_pzxtbf:
1791 case Hexagon::A4_pzxtbfnew:
1792 case Hexagon::A4_pzxtbt:
1793 case Hexagon::A4_pzxtbtnew:
1794 case Hexagon::A4_pzxthf:
1795 case Hexagon::A4_pzxthfnew:
1796 case Hexagon::A4_pzxtht:
1797 case Hexagon::A4_pzxthtnew:
1798 case Hexagon::C2_ccombinewf:
1799 case Hexagon::C2_ccombinewt:
1806 // FIXME - Function name and it's functionality don't match.
1807 // It should be renamed to hasPredNewOpcode()
1808 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr &MI) const {
1809 if (!MI.getDesc().mayLoad() || !isPredicated(MI))
1812 int PNewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
1813 // Instruction with valid predicated-new opcode can be promoted to .new.
1814 return PNewOpcode >= 0;
1818 // Returns true if an instruction is a conditional store.
1820 // Note: It doesn't include conditional new-value stores as they can't be
1821 // converted to .new predicate.
1822 bool HexagonInstrInfo::isConditionalStore(const MachineInstr &MI) const {
1823 switch (MI.getOpcode()) {
1824 default: return false;
1825 case Hexagon::S4_storeirbt_io:
1826 case Hexagon::S4_storeirbf_io:
1827 case Hexagon::S4_pstorerbt_rr:
1828 case Hexagon::S4_pstorerbf_rr:
1829 case Hexagon::S2_pstorerbt_io:
1830 case Hexagon::S2_pstorerbf_io:
1831 case Hexagon::S2_pstorerbt_pi:
1832 case Hexagon::S2_pstorerbf_pi:
1833 case Hexagon::S2_pstorerdt_io:
1834 case Hexagon::S2_pstorerdf_io:
1835 case Hexagon::S4_pstorerdt_rr:
1836 case Hexagon::S4_pstorerdf_rr:
1837 case Hexagon::S2_pstorerdt_pi:
1838 case Hexagon::S2_pstorerdf_pi:
1839 case Hexagon::S2_pstorerht_io:
1840 case Hexagon::S2_pstorerhf_io:
1841 case Hexagon::S4_storeirht_io:
1842 case Hexagon::S4_storeirhf_io:
1843 case Hexagon::S4_pstorerht_rr:
1844 case Hexagon::S4_pstorerhf_rr:
1845 case Hexagon::S2_pstorerht_pi:
1846 case Hexagon::S2_pstorerhf_pi:
1847 case Hexagon::S2_pstorerit_io:
1848 case Hexagon::S2_pstorerif_io:
1849 case Hexagon::S4_storeirit_io:
1850 case Hexagon::S4_storeirif_io:
1851 case Hexagon::S4_pstorerit_rr:
1852 case Hexagon::S4_pstorerif_rr:
1853 case Hexagon::S2_pstorerit_pi:
1854 case Hexagon::S2_pstorerif_pi:
1856 // V4 global address store before promoting to dot new.
1857 case Hexagon::S4_pstorerdt_abs:
1858 case Hexagon::S4_pstorerdf_abs:
1859 case Hexagon::S4_pstorerbt_abs:
1860 case Hexagon::S4_pstorerbf_abs:
1861 case Hexagon::S4_pstorerht_abs:
1862 case Hexagon::S4_pstorerhf_abs:
1863 case Hexagon::S4_pstorerit_abs:
1864 case Hexagon::S4_pstorerif_abs:
1867 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1868 // from the "Conditional Store" list. Because a predicated new value store
1869 // would NOT be promoted to a double dot new store.
1870 // This function returns yes for those stores that are predicated but not
1871 // yet promoted to predicate dot new instructions.
1876 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr &MI) const {
1877 switch (MI.getOpcode()) {
1878 case Hexagon::A2_tfrt:
1879 case Hexagon::A2_tfrf:
1880 case Hexagon::C2_cmoveit:
1881 case Hexagon::C2_cmoveif:
1882 case Hexagon::A2_tfrtnew:
1883 case Hexagon::A2_tfrfnew:
1884 case Hexagon::C2_cmovenewit:
1885 case Hexagon::C2_cmovenewif:
1886 case Hexagon::A2_tfrpt:
1887 case Hexagon::A2_tfrpf:
1897 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1898 // isFPImm and later getFPImm as well.
1899 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
1900 const uint64_t F = MI.getDesc().TSFlags;
1901 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1902 if (isExtended) // Instruction must be extended.
1905 unsigned isExtendable =
1906 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1913 short ExtOpNum = getCExtOpNum(MI);
1914 const MachineOperand &MO = MI.getOperand(ExtOpNum);
1915 // Use MO operand flags to determine if MO
1916 // has the HMOTF_ConstExtended flag set.
1917 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1919 // If this is a Machine BB address we are talking about, and it is
1920 // not marked as extended, say so.
1924 // We could be using an instruction with an extendable immediate and shoehorn
1925 // a global address into it. If it is a global address it will be constant
1926 // extended. We do this for COMBINE.
1927 // We currently only handle isGlobal() because it is the only kind of
1928 // object we are going to end up with here for now.
1929 // In the future we probably should add isSymbol(), etc.
1930 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1931 MO.isJTI() || MO.isCPI() || MO.isFPImm())
1934 // If the extendable operand is not 'Immediate' type, the instruction should
1935 // have 'isExtended' flag set.
1936 assert(MO.isImm() && "Extendable operand must be Immediate type");
1938 int MinValue = getMinValue(MI);
1939 int MaxValue = getMaxValue(MI);
1940 int ImmValue = MO.getImm();
1942 return (ImmValue < MinValue || ImmValue > MaxValue);
1946 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
1947 switch (MI.getOpcode()) {
1948 case Hexagon::L4_return :
1949 case Hexagon::L4_return_t :
1950 case Hexagon::L4_return_f :
1951 case Hexagon::L4_return_tnew_pnt :
1952 case Hexagon::L4_return_fnew_pnt :
1953 case Hexagon::L4_return_tnew_pt :
1954 case Hexagon::L4_return_fnew_pt :
1961 // Return true when ConsMI uses a register defined by ProdMI.
1962 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
1963 const MachineInstr &ConsMI) const {
1964 if (!ProdMI.getDesc().getNumDefs())
1967 auto &HRI = getRegisterInfo();
1969 SmallVector<unsigned, 4> DefsA;
1970 SmallVector<unsigned, 4> DefsB;
1971 SmallVector<unsigned, 8> UsesA;
1972 SmallVector<unsigned, 8> UsesB;
1974 parseOperands(ProdMI, DefsA, UsesA);
1975 parseOperands(ConsMI, DefsB, UsesB);
1977 for (auto &RegA : DefsA)
1978 for (auto &RegB : UsesB) {
1979 // True data dependency.
1983 if (Hexagon::DoubleRegsRegClass.contains(RegA))
1984 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1985 if (RegB == *SubRegs)
1988 if (Hexagon::DoubleRegsRegClass.contains(RegB))
1989 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1990 if (RegA == *SubRegs)
1998 // Returns true if the instruction is alread a .cur.
1999 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2000 switch (MI.getOpcode()) {
2001 case Hexagon::V6_vL32b_cur_pi:
2002 case Hexagon::V6_vL32b_cur_ai:
2003 case Hexagon::V6_vL32b_cur_pi_128B:
2004 case Hexagon::V6_vL32b_cur_ai_128B:
2011 // Returns true, if any one of the operands is a dot new
2012 // insn, whether it is predicated dot new or register dot new.
2013 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2014 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2021 /// Symmetrical. See if these two instructions are fit for duplex pair.
2022 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2023 const MachineInstr &MIb) const {
2024 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
2025 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
2026 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2030 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
2031 if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2035 unsigned SchedClass = MI.getDesc().getSchedClass();
2036 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
2042 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2043 return (Opcode == Hexagon::ENDLOOP0 ||
2044 Opcode == Hexagon::ENDLOOP1);
2048 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2050 case MachineOperand::MO_MachineBasicBlock:
2051 case MachineOperand::MO_GlobalAddress:
2052 case MachineOperand::MO_ExternalSymbol:
2053 case MachineOperand::MO_JumpTableIndex:
2054 case MachineOperand::MO_ConstantPoolIndex:
2055 case MachineOperand::MO_BlockAddress:
2063 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2064 const MCInstrDesc &MID = MI.getDesc();
2065 const uint64_t F = MID.TSFlags;
2066 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2069 // TODO: This is largely obsolete now. Will need to be removed
2070 // in consecutive patches.
2071 switch (MI.getOpcode()) {
2072 // PS_fi and PS_fia remain special cases.
2073 case Hexagon::PS_fi:
2074 case Hexagon::PS_fia:
2083 // This returns true in two cases:
2084 // - The OP code itself indicates that this is an extended instruction.
2085 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2086 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2087 // First check if this is permanently extended op code.
2088 const uint64_t F = MI.getDesc().TSFlags;
2089 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2091 // Use MO operand flags to determine if one of MI's operands
2092 // has HMOTF_ConstExtended flag set.
2093 for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
2094 E = MI.operands_end(); I != E; ++I) {
2095 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2102 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2103 unsigned Opcode = MI.getOpcode();
2104 const uint64_t F = get(Opcode).TSFlags;
2105 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2109 // No V60 HVX VMEM with A_INDIRECT.
2110 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2111 const MachineInstr &J) const {
2112 if (!isV60VectorInstruction(I))
2114 if (!I.mayLoad() && !I.mayStore())
2116 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2120 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2121 switch (MI.getOpcode()) {
2122 case Hexagon::J2_callr :
2123 case Hexagon::J2_callrf :
2124 case Hexagon::J2_callrt :
2125 case Hexagon::PS_call_nr :
2132 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2133 switch (MI.getOpcode()) {
2134 case Hexagon::L4_return :
2135 case Hexagon::L4_return_t :
2136 case Hexagon::L4_return_f :
2137 case Hexagon::L4_return_fnew_pnt :
2138 case Hexagon::L4_return_fnew_pt :
2139 case Hexagon::L4_return_tnew_pnt :
2140 case Hexagon::L4_return_tnew_pt :
2147 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2148 switch (MI.getOpcode()) {
2149 case Hexagon::J2_jumpr :
2150 case Hexagon::J2_jumprt :
2151 case Hexagon::J2_jumprf :
2152 case Hexagon::J2_jumprtnewpt :
2153 case Hexagon::J2_jumprfnewpt :
2154 case Hexagon::J2_jumprtnew :
2155 case Hexagon::J2_jumprfnew :
2162 // Return true if a given MI can accommodate given offset.
2163 // Use abs estimate as oppose to the exact number.
2164 // TODO: This will need to be changed to use MC level
2165 // definition of instruction extendable field size.
2166 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2167 unsigned offset) const {
2168 // This selection of jump instructions matches to that what
2169 // AnalyzeBranch can parse, plus NVJ.
2170 if (isNewValueJump(MI)) // r9:2
2171 return isInt<11>(offset);
2173 switch (MI.getOpcode()) {
2174 // Still missing Jump to address condition on register value.
2177 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2178 case Hexagon::J2_call:
2179 case Hexagon::PS_call_nr:
2180 return isInt<24>(offset);
2181 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2182 case Hexagon::J2_jumpf:
2183 case Hexagon::J2_jumptnew:
2184 case Hexagon::J2_jumptnewpt:
2185 case Hexagon::J2_jumpfnew:
2186 case Hexagon::J2_jumpfnewpt:
2187 case Hexagon::J2_callt:
2188 case Hexagon::J2_callf:
2189 return isInt<17>(offset);
2190 case Hexagon::J2_loop0i:
2191 case Hexagon::J2_loop0iext:
2192 case Hexagon::J2_loop0r:
2193 case Hexagon::J2_loop0rext:
2194 case Hexagon::J2_loop1i:
2195 case Hexagon::J2_loop1iext:
2196 case Hexagon::J2_loop1r:
2197 case Hexagon::J2_loop1rext:
2198 return isInt<9>(offset);
2199 // TODO: Add all the compound branches here. Can we do this in Relation model?
2200 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2201 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2202 return isInt<11>(offset);
2207 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
2208 const MachineInstr &ESMI) const {
2209 bool isLate = isLateResultInstr(LRMI);
2210 bool isEarly = isEarlySourceInstr(ESMI);
2212 DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2214 DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2217 if (isLate && isEarly) {
2218 DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2226 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
2227 switch (MI.getOpcode()) {
2228 case TargetOpcode::EXTRACT_SUBREG:
2229 case TargetOpcode::INSERT_SUBREG:
2230 case TargetOpcode::SUBREG_TO_REG:
2231 case TargetOpcode::REG_SEQUENCE:
2232 case TargetOpcode::IMPLICIT_DEF:
2233 case TargetOpcode::COPY:
2234 case TargetOpcode::INLINEASM:
2235 case TargetOpcode::PHI:
2241 unsigned SchedClass = MI.getDesc().getSchedClass();
2243 switch (SchedClass) {
2244 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2245 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2246 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2247 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2248 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2249 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2250 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2251 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
2252 case Hexagon::Sched::V2LDST_tc_st_SLOT0:
2253 case Hexagon::Sched::V2LDST_tc_st_SLOT01:
2254 case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
2255 case Hexagon::Sched::V4LDST_tc_st_SLOT0:
2256 case Hexagon::Sched::V4LDST_tc_st_SLOT01:
2263 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2264 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2265 // resource, but all operands can be received late like an ALU instruction.
2266 return MI.getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
2270 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2271 unsigned Opcode = MI.getOpcode();
2272 return Opcode == Hexagon::J2_loop0i ||
2273 Opcode == Hexagon::J2_loop0r ||
2274 Opcode == Hexagon::J2_loop0iext ||
2275 Opcode == Hexagon::J2_loop0rext ||
2276 Opcode == Hexagon::J2_loop1i ||
2277 Opcode == Hexagon::J2_loop1r ||
2278 Opcode == Hexagon::J2_loop1iext ||
2279 Opcode == Hexagon::J2_loop1rext;
2283 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2284 switch (MI.getOpcode()) {
2285 default: return false;
2286 case Hexagon::L4_iadd_memopw_io :
2287 case Hexagon::L4_isub_memopw_io :
2288 case Hexagon::L4_add_memopw_io :
2289 case Hexagon::L4_sub_memopw_io :
2290 case Hexagon::L4_and_memopw_io :
2291 case Hexagon::L4_or_memopw_io :
2292 case Hexagon::L4_iadd_memoph_io :
2293 case Hexagon::L4_isub_memoph_io :
2294 case Hexagon::L4_add_memoph_io :
2295 case Hexagon::L4_sub_memoph_io :
2296 case Hexagon::L4_and_memoph_io :
2297 case Hexagon::L4_or_memoph_io :
2298 case Hexagon::L4_iadd_memopb_io :
2299 case Hexagon::L4_isub_memopb_io :
2300 case Hexagon::L4_add_memopb_io :
2301 case Hexagon::L4_sub_memopb_io :
2302 case Hexagon::L4_and_memopb_io :
2303 case Hexagon::L4_or_memopb_io :
2304 case Hexagon::L4_ior_memopb_io:
2305 case Hexagon::L4_ior_memoph_io:
2306 case Hexagon::L4_ior_memopw_io:
2307 case Hexagon::L4_iand_memopb_io:
2308 case Hexagon::L4_iand_memoph_io:
2309 case Hexagon::L4_iand_memopw_io:
2316 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2317 const uint64_t F = MI.getDesc().TSFlags;
2318 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2322 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2323 const uint64_t F = get(Opcode).TSFlags;
2324 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2328 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2329 return isNewValueJump(MI) || isNewValueStore(MI);
2333 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2334 return isNewValue(MI) && MI.isBranch();
2338 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2339 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2343 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2344 const uint64_t F = MI.getDesc().TSFlags;
2345 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2349 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2350 const uint64_t F = get(Opcode).TSFlags;
2351 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2355 // Returns true if a particular operand is extendable for an instruction.
2356 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2357 unsigned OperandNum) const {
2358 const uint64_t F = MI.getDesc().TSFlags;
2359 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2364 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2365 const uint64_t F = MI.getDesc().TSFlags;
2366 assert(isPredicated(MI));
2367 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2371 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2372 const uint64_t F = get(Opcode).TSFlags;
2373 assert(isPredicated(Opcode));
2374 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2378 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2379 const uint64_t F = MI.getDesc().TSFlags;
2380 return !((F >> HexagonII::PredicatedFalsePos) &
2381 HexagonII::PredicatedFalseMask);
2385 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2386 const uint64_t F = get(Opcode).TSFlags;
2387 // Make sure that the instruction is predicated.
2388 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2389 return !((F >> HexagonII::PredicatedFalsePos) &
2390 HexagonII::PredicatedFalseMask);
2394 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2395 const uint64_t F = get(Opcode).TSFlags;
2396 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2400 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2401 const uint64_t F = get(Opcode).TSFlags;
2402 return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2406 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2407 const uint64_t F = get(Opcode).TSFlags;
2408 assert(get(Opcode).isBranch() &&
2409 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2410 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2414 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2415 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2416 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2417 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2418 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2421 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2422 switch (MI.getOpcode()) {
2424 case Hexagon::L2_loadrb_io:
2425 case Hexagon::L4_loadrb_ur:
2426 case Hexagon::L4_loadrb_ap:
2427 case Hexagon::L2_loadrb_pr:
2428 case Hexagon::L2_loadrb_pbr:
2429 case Hexagon::L2_loadrb_pi:
2430 case Hexagon::L2_loadrb_pci:
2431 case Hexagon::L2_loadrb_pcr:
2432 case Hexagon::L2_loadbsw2_io:
2433 case Hexagon::L4_loadbsw2_ur:
2434 case Hexagon::L4_loadbsw2_ap:
2435 case Hexagon::L2_loadbsw2_pr:
2436 case Hexagon::L2_loadbsw2_pbr:
2437 case Hexagon::L2_loadbsw2_pi:
2438 case Hexagon::L2_loadbsw2_pci:
2439 case Hexagon::L2_loadbsw2_pcr:
2440 case Hexagon::L2_loadbsw4_io:
2441 case Hexagon::L4_loadbsw4_ur:
2442 case Hexagon::L4_loadbsw4_ap:
2443 case Hexagon::L2_loadbsw4_pr:
2444 case Hexagon::L2_loadbsw4_pbr:
2445 case Hexagon::L2_loadbsw4_pi:
2446 case Hexagon::L2_loadbsw4_pci:
2447 case Hexagon::L2_loadbsw4_pcr:
2448 case Hexagon::L4_loadrb_rr:
2449 case Hexagon::L2_ploadrbt_io:
2450 case Hexagon::L2_ploadrbt_pi:
2451 case Hexagon::L2_ploadrbf_io:
2452 case Hexagon::L2_ploadrbf_pi:
2453 case Hexagon::L2_ploadrbtnew_io:
2454 case Hexagon::L2_ploadrbfnew_io:
2455 case Hexagon::L4_ploadrbt_rr:
2456 case Hexagon::L4_ploadrbf_rr:
2457 case Hexagon::L4_ploadrbtnew_rr:
2458 case Hexagon::L4_ploadrbfnew_rr:
2459 case Hexagon::L2_ploadrbtnew_pi:
2460 case Hexagon::L2_ploadrbfnew_pi:
2461 case Hexagon::L4_ploadrbt_abs:
2462 case Hexagon::L4_ploadrbf_abs:
2463 case Hexagon::L4_ploadrbtnew_abs:
2464 case Hexagon::L4_ploadrbfnew_abs:
2465 case Hexagon::L2_loadrbgp:
2467 case Hexagon::L2_loadrh_io:
2468 case Hexagon::L4_loadrh_ur:
2469 case Hexagon::L4_loadrh_ap:
2470 case Hexagon::L2_loadrh_pr:
2471 case Hexagon::L2_loadrh_pbr:
2472 case Hexagon::L2_loadrh_pi:
2473 case Hexagon::L2_loadrh_pci:
2474 case Hexagon::L2_loadrh_pcr:
2475 case Hexagon::L4_loadrh_rr:
2476 case Hexagon::L2_ploadrht_io:
2477 case Hexagon::L2_ploadrht_pi:
2478 case Hexagon::L2_ploadrhf_io:
2479 case Hexagon::L2_ploadrhf_pi:
2480 case Hexagon::L2_ploadrhtnew_io:
2481 case Hexagon::L2_ploadrhfnew_io:
2482 case Hexagon::L4_ploadrht_rr:
2483 case Hexagon::L4_ploadrhf_rr:
2484 case Hexagon::L4_ploadrhtnew_rr:
2485 case Hexagon::L4_ploadrhfnew_rr:
2486 case Hexagon::L2_ploadrhtnew_pi:
2487 case Hexagon::L2_ploadrhfnew_pi:
2488 case Hexagon::L4_ploadrht_abs:
2489 case Hexagon::L4_ploadrhf_abs:
2490 case Hexagon::L4_ploadrhtnew_abs:
2491 case Hexagon::L4_ploadrhfnew_abs:
2492 case Hexagon::L2_loadrhgp:
2500 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2501 const uint64_t F = MI.getDesc().TSFlags;
2502 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2506 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2507 switch (MI.getOpcode()) {
2508 case Hexagon::STriw_pred :
2509 case Hexagon::LDriw_pred :
2517 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2521 for (auto &Op : MI.operands())
2522 if (Op.isGlobal() || Op.isSymbol())
2528 // Returns true when SU has a timing class TC1.
2529 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2530 unsigned SchedClass = MI.getDesc().getSchedClass();
2531 switch (SchedClass) {
2532 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2533 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2534 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2535 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2536 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2537 //case Hexagon::Sched::M_tc_1_SLOT23:
2538 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2539 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2548 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2549 unsigned SchedClass = MI.getDesc().getSchedClass();
2550 switch (SchedClass) {
2551 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
2552 case Hexagon::Sched::ALU64_tc_2_SLOT23:
2553 case Hexagon::Sched::CR_tc_2_SLOT3:
2554 case Hexagon::Sched::M_tc_2_SLOT23:
2555 case Hexagon::Sched::S_2op_tc_2_SLOT23:
2556 case Hexagon::Sched::S_3op_tc_2_SLOT23:
2565 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2566 unsigned SchedClass = MI.getDesc().getSchedClass();
2567 switch (SchedClass) {
2568 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
2569 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
2570 case Hexagon::Sched::ALU64_tc_2early_SLOT23:
2571 case Hexagon::Sched::CR_tc_2early_SLOT23:
2572 case Hexagon::Sched::CR_tc_2early_SLOT3:
2573 case Hexagon::Sched::J_tc_2early_SLOT0123:
2574 case Hexagon::Sched::J_tc_2early_SLOT2:
2575 case Hexagon::Sched::J_tc_2early_SLOT23:
2576 case Hexagon::Sched::S_2op_tc_2early_SLOT23:
2577 case Hexagon::Sched::S_3op_tc_2early_SLOT23:
2586 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2587 unsigned SchedClass = MI.getDesc().getSchedClass();
2588 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
2592 // Schedule this ASAP.
2593 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2594 const MachineInstr &MI2) const {
2595 if (mayBeCurLoad(MI1)) {
2596 // if (result of SU is used in Next) return true;
2597 unsigned DstReg = MI1.getOperand(0).getReg();
2598 int N = MI2.getNumOperands();
2599 for (int I = 0; I < N; I++)
2600 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2603 if (mayBeNewStore(MI2))
2604 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2605 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2606 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2612 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr &MI) const {
2613 const uint64_t V = getType(MI);
2614 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2618 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2620 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2621 if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2622 VT == MVT::v32i16 || VT == MVT::v64i8) {
2623 return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2624 Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2625 (Offset & 0x3f) == 0);
2628 if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2629 VT == MVT::v64i16 || VT == MVT::v128i8) {
2630 return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2631 Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2632 (Offset & 0x7f) == 0);
2634 if (VT == MVT::i64) {
2635 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2636 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2637 (Offset & 0x7) == 0);
2639 if (VT == MVT::i32) {
2640 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2641 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2642 (Offset & 0x3) == 0);
2644 if (VT == MVT::i16) {
2645 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2646 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2647 (Offset & 0x1) == 0);
2649 if (VT == MVT::i8) {
2650 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2651 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2653 llvm_unreachable("Not an auto-inc opc!");
2657 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2658 bool Extend) const {
2659 // This function is to check whether the "Offset" is in the correct range of
2660 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2661 // inserted to calculate the final address. Due to this reason, the function
2662 // assumes that the "Offset" has correct alignment.
2663 // We used to assert if the offset was not properly aligned, however,
2664 // there are cases where a misaligned pointer recast can cause this
2665 // problem, and we need to allow for it. The front end warns of such
2666 // misaligns with respect to load size.
2669 case Hexagon::PS_vstorerq_ai:
2670 case Hexagon::PS_vstorerw_ai:
2671 case Hexagon::PS_vloadrq_ai:
2672 case Hexagon::PS_vloadrw_ai:
2673 case Hexagon::V6_vL32b_ai:
2674 case Hexagon::V6_vS32b_ai:
2675 case Hexagon::V6_vL32Ub_ai:
2676 case Hexagon::V6_vS32Ub_ai:
2677 return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
2678 (Offset <= Hexagon_MEMV_OFFSET_MAX);
2680 case Hexagon::PS_vstorerq_ai_128B:
2681 case Hexagon::PS_vstorerw_ai_128B:
2682 case Hexagon::PS_vloadrq_ai_128B:
2683 case Hexagon::PS_vloadrw_ai_128B:
2684 case Hexagon::V6_vL32b_ai_128B:
2685 case Hexagon::V6_vS32b_ai_128B:
2686 case Hexagon::V6_vL32Ub_ai_128B:
2687 case Hexagon::V6_vS32Ub_ai_128B:
2688 return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
2689 (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
2691 case Hexagon::J2_loop0i:
2692 case Hexagon::J2_loop1i:
2693 return isUInt<10>(Offset);
2695 case Hexagon::S4_storeirb_io:
2696 case Hexagon::S4_storeirbt_io:
2697 case Hexagon::S4_storeirbf_io:
2698 return isUInt<6>(Offset);
2700 case Hexagon::S4_storeirh_io:
2701 case Hexagon::S4_storeirht_io:
2702 case Hexagon::S4_storeirhf_io:
2703 return isShiftedUInt<6,1>(Offset);
2705 case Hexagon::S4_storeiri_io:
2706 case Hexagon::S4_storeirit_io:
2707 case Hexagon::S4_storeirif_io:
2708 return isShiftedUInt<6,2>(Offset);
2715 case Hexagon::L2_loadri_io:
2716 case Hexagon::S2_storeri_io:
2717 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2718 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2720 case Hexagon::L2_loadrd_io:
2721 case Hexagon::S2_storerd_io:
2722 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2723 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2725 case Hexagon::L2_loadrh_io:
2726 case Hexagon::L2_loadruh_io:
2727 case Hexagon::S2_storerh_io:
2728 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2729 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2731 case Hexagon::L2_loadrb_io:
2732 case Hexagon::L2_loadrub_io:
2733 case Hexagon::S2_storerb_io:
2734 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2735 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2737 case Hexagon::A2_addi:
2738 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2739 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2741 case Hexagon::L4_iadd_memopw_io :
2742 case Hexagon::L4_isub_memopw_io :
2743 case Hexagon::L4_add_memopw_io :
2744 case Hexagon::L4_sub_memopw_io :
2745 case Hexagon::L4_and_memopw_io :
2746 case Hexagon::L4_or_memopw_io :
2747 return (0 <= Offset && Offset <= 255);
2749 case Hexagon::L4_iadd_memoph_io :
2750 case Hexagon::L4_isub_memoph_io :
2751 case Hexagon::L4_add_memoph_io :
2752 case Hexagon::L4_sub_memoph_io :
2753 case Hexagon::L4_and_memoph_io :
2754 case Hexagon::L4_or_memoph_io :
2755 return (0 <= Offset && Offset <= 127);
2757 case Hexagon::L4_iadd_memopb_io :
2758 case Hexagon::L4_isub_memopb_io :
2759 case Hexagon::L4_add_memopb_io :
2760 case Hexagon::L4_sub_memopb_io :
2761 case Hexagon::L4_and_memopb_io :
2762 case Hexagon::L4_or_memopb_io :
2763 return (0 <= Offset && Offset <= 63);
2765 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2766 // any size. Later pass knows how to handle it.
2767 case Hexagon::STriw_pred:
2768 case Hexagon::LDriw_pred:
2769 case Hexagon::STriw_mod:
2770 case Hexagon::LDriw_mod:
2773 case Hexagon::PS_fi:
2774 case Hexagon::PS_fia:
2775 case Hexagon::INLINEASM:
2778 case Hexagon::L2_ploadrbt_io:
2779 case Hexagon::L2_ploadrbf_io:
2780 case Hexagon::L2_ploadrubt_io:
2781 case Hexagon::L2_ploadrubf_io:
2782 case Hexagon::S2_pstorerbt_io:
2783 case Hexagon::S2_pstorerbf_io:
2784 return isUInt<6>(Offset);
2786 case Hexagon::L2_ploadrht_io:
2787 case Hexagon::L2_ploadrhf_io:
2788 case Hexagon::L2_ploadruht_io:
2789 case Hexagon::L2_ploadruhf_io:
2790 case Hexagon::S2_pstorerht_io:
2791 case Hexagon::S2_pstorerhf_io:
2792 return isShiftedUInt<6,1>(Offset);
2794 case Hexagon::L2_ploadrit_io:
2795 case Hexagon::L2_ploadrif_io:
2796 case Hexagon::S2_pstorerit_io:
2797 case Hexagon::S2_pstorerif_io:
2798 return isShiftedUInt<6,2>(Offset);
2800 case Hexagon::L2_ploadrdt_io:
2801 case Hexagon::L2_ploadrdf_io:
2802 case Hexagon::S2_pstorerdt_io:
2803 case Hexagon::S2_pstorerdf_io:
2804 return isShiftedUInt<6,3>(Offset);
2807 llvm_unreachable("No offset range is defined for this opcode. "
2808 "Please define it in the above switch statement!");
2812 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2813 return isV60VectorInstruction(MI) && isAccumulator(MI);
2817 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2818 const uint64_t F = get(MI.getOpcode()).TSFlags;
2819 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2821 V == HexagonII::TypeCVI_VA ||
2822 V == HexagonII::TypeCVI_VA_DV;
2826 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2827 const MachineInstr &ConsMI) const {
2828 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2831 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2834 if (mayBeNewStore(ConsMI))
2840 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2841 switch (MI.getOpcode()) {
2843 case Hexagon::L2_loadrub_io:
2844 case Hexagon::L4_loadrub_ur:
2845 case Hexagon::L4_loadrub_ap:
2846 case Hexagon::L2_loadrub_pr:
2847 case Hexagon::L2_loadrub_pbr:
2848 case Hexagon::L2_loadrub_pi:
2849 case Hexagon::L2_loadrub_pci:
2850 case Hexagon::L2_loadrub_pcr:
2851 case Hexagon::L2_loadbzw2_io:
2852 case Hexagon::L4_loadbzw2_ur:
2853 case Hexagon::L4_loadbzw2_ap:
2854 case Hexagon::L2_loadbzw2_pr:
2855 case Hexagon::L2_loadbzw2_pbr:
2856 case Hexagon::L2_loadbzw2_pi:
2857 case Hexagon::L2_loadbzw2_pci:
2858 case Hexagon::L2_loadbzw2_pcr:
2859 case Hexagon::L2_loadbzw4_io:
2860 case Hexagon::L4_loadbzw4_ur:
2861 case Hexagon::L4_loadbzw4_ap:
2862 case Hexagon::L2_loadbzw4_pr:
2863 case Hexagon::L2_loadbzw4_pbr:
2864 case Hexagon::L2_loadbzw4_pi:
2865 case Hexagon::L2_loadbzw4_pci:
2866 case Hexagon::L2_loadbzw4_pcr:
2867 case Hexagon::L4_loadrub_rr:
2868 case Hexagon::L2_ploadrubt_io:
2869 case Hexagon::L2_ploadrubt_pi:
2870 case Hexagon::L2_ploadrubf_io:
2871 case Hexagon::L2_ploadrubf_pi:
2872 case Hexagon::L2_ploadrubtnew_io:
2873 case Hexagon::L2_ploadrubfnew_io:
2874 case Hexagon::L4_ploadrubt_rr:
2875 case Hexagon::L4_ploadrubf_rr:
2876 case Hexagon::L4_ploadrubtnew_rr:
2877 case Hexagon::L4_ploadrubfnew_rr:
2878 case Hexagon::L2_ploadrubtnew_pi:
2879 case Hexagon::L2_ploadrubfnew_pi:
2880 case Hexagon::L4_ploadrubt_abs:
2881 case Hexagon::L4_ploadrubf_abs:
2882 case Hexagon::L4_ploadrubtnew_abs:
2883 case Hexagon::L4_ploadrubfnew_abs:
2884 case Hexagon::L2_loadrubgp:
2886 case Hexagon::L2_loadruh_io:
2887 case Hexagon::L4_loadruh_ur:
2888 case Hexagon::L4_loadruh_ap:
2889 case Hexagon::L2_loadruh_pr:
2890 case Hexagon::L2_loadruh_pbr:
2891 case Hexagon::L2_loadruh_pi:
2892 case Hexagon::L2_loadruh_pci:
2893 case Hexagon::L2_loadruh_pcr:
2894 case Hexagon::L4_loadruh_rr:
2895 case Hexagon::L2_ploadruht_io:
2896 case Hexagon::L2_ploadruht_pi:
2897 case Hexagon::L2_ploadruhf_io:
2898 case Hexagon::L2_ploadruhf_pi:
2899 case Hexagon::L2_ploadruhtnew_io:
2900 case Hexagon::L2_ploadruhfnew_io:
2901 case Hexagon::L4_ploadruht_rr:
2902 case Hexagon::L4_ploadruhf_rr:
2903 case Hexagon::L4_ploadruhtnew_rr:
2904 case Hexagon::L4_ploadruhfnew_rr:
2905 case Hexagon::L2_ploadruhtnew_pi:
2906 case Hexagon::L2_ploadruhfnew_pi:
2907 case Hexagon::L4_ploadruht_abs:
2908 case Hexagon::L4_ploadruhf_abs:
2909 case Hexagon::L4_ploadruhtnew_abs:
2910 case Hexagon::L4_ploadruhfnew_abs:
2911 case Hexagon::L2_loadruhgp:
2919 // Add latency to instruction.
2920 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
2921 const MachineInstr &MI2) const {
2922 if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2))
2923 if (!isVecUsableNextPacket(MI1, MI2))
2929 /// \brief Get the base register and byte offset of a load/store instr.
2930 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt,
2931 unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2933 unsigned AccessSize = 0;
2935 BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2937 return BaseReg != 0;
2941 /// \brief Can these instructions execute at the same time in a bundle.
2942 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
2943 const MachineInstr &Second) const {
2944 if (DisableNVSchedule)
2946 if (mayBeNewStore(Second)) {
2947 // Make sure the definition of the first instruction is the value being
2949 const MachineOperand &Stored =
2950 Second.getOperand(Second.getNumOperands() - 1);
2951 if (!Stored.isReg())
2953 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2954 const MachineOperand &Op = First.getOperand(i);
2955 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2963 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
2964 unsigned Opc = CallMI.getOpcode();
2965 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2969 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2977 // Returns true if an instruction can be converted into a non-extended
2978 // equivalent instruction.
2979 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
2981 // Check if the instruction has a register form that uses register in place
2982 // of the extended operand, if so return that as the non-extended form.
2983 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2986 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2987 // Check addressing mode and retrieve non-ext equivalent instruction.
2989 switch (getAddrMode(MI)) {
2990 case HexagonII::Absolute :
2991 // Load/store with absolute addressing mode can be converted into
2992 // base+offset mode.
2993 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
2995 case HexagonII::BaseImmOffset :
2996 // Load/store with base+offset addressing mode can be converted into
2997 // base+register offset addressing mode. However left shift operand should
2999 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
3001 case HexagonII::BaseLongOffset:
3002 NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
3007 if (NonExtOpcode < 0)
3015 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3016 return Hexagon::getRealHWInstr(MI.getOpcode(),
3017 Hexagon::InstrType_Pseudo) >= 0;
3021 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3023 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3033 // Returns true, if a LD insn can be promoted to a cur load.
3034 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3035 auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
3036 const uint64_t F = MI.getDesc().TSFlags;
3037 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
3042 // Returns true, if a ST insn can be promoted to a new-value store.
3043 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3044 const uint64_t F = MI.getDesc().TSFlags;
3045 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
3049 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3050 const MachineInstr &ConsMI) const {
3051 // There is no stall when ProdMI is not a V60 vector.
3052 if (!isV60VectorInstruction(ProdMI))
3055 // There is no stall when ProdMI and ConsMI are not dependent.
3056 if (!isDependent(ProdMI, ConsMI))
3059 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3060 // are scheduled in consecutive packets.
3061 if (isVecUsableNextPacket(ProdMI, ConsMI))
3068 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3069 MachineBasicBlock::const_instr_iterator BII) const {
3070 // There is no stall when I is not a V60 vector.
3071 if (!isV60VectorInstruction(MI))
3074 MachineBasicBlock::const_instr_iterator MII = BII;
3075 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3077 if (!MII->isBundle()) {
3078 const MachineInstr &J = *MII;
3079 if (!isV60VectorInstruction(J))
3081 else if (isVecUsableNextPacket(J, MI))
3086 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3087 const MachineInstr &J = *MII;
3088 if (producesStall(J, MI))
3095 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3096 unsigned PredReg) const {
3097 for (unsigned opNum = 0; opNum < MI.getNumOperands(); opNum++) {
3098 const MachineOperand &MO = MI.getOperand(opNum);
3099 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3100 return false; // Predicate register must be explicitly defined.
3103 // Hexagon Programmer's Reference says that decbin, memw_locked, and
3104 // memd_locked cannot be used as .new as well,
3105 // but we don't seem to have these instructions defined.
3106 return MI.getOpcode() != Hexagon::A4_tlbmatch;
3110 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3111 return (Opcode == Hexagon::J2_jumpt) ||
3112 (Opcode == Hexagon::J2_jumpf) ||
3113 (Opcode == Hexagon::J2_jumptnew) ||
3114 (Opcode == Hexagon::J2_jumpfnew) ||
3115 (Opcode == Hexagon::J2_jumptnewpt) ||
3116 (Opcode == Hexagon::J2_jumpfnewpt);
3120 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3121 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3123 return !isPredicatedTrue(Cond[0].getImm());
3127 short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const {
3128 return Hexagon::getAbsoluteForm(MI.getOpcode());
3132 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3133 const uint64_t F = MI.getDesc().TSFlags;
3134 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3138 // Returns the base register in a memory access (load/store). The offset is
3139 // returned in Offset and the access size is returned in AccessSize.
3140 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3141 int &Offset, unsigned &AccessSize) const {
3142 // Return if it is not a base+offset type instruction or a MemOp.
3143 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3144 getAddrMode(MI) != HexagonII::BaseLongOffset &&
3145 !isMemOp(MI) && !isPostIncrement(MI))
3148 // Since it is a memory access instruction, getMemAccessSize() should never
3150 assert (getMemAccessSize(MI) &&
3151 "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
3153 // Return Values of getMemAccessSize() are
3154 // 0 - Checked in the assert above.
3155 // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
3156 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
3157 AccessSize = (1U << (getMemAccessSize(MI) - 1));
3159 unsigned basePos = 0, offsetPos = 0;
3160 if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
3163 // Post increment updates its EA after the mem access,
3164 // so we need to treat its offset as zero.
3165 if (isPostIncrement(MI))
3168 Offset = MI.getOperand(offsetPos).getImm();
3171 return MI.getOperand(basePos).getReg();
3175 /// Return the position of the base and offset operands for this instruction.
3176 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3177 unsigned &BasePos, unsigned &OffsetPos) const {
3178 // Deal with memops first.
3182 } else if (MI.mayStore()) {
3185 } else if (MI.mayLoad()) {
3191 if (isPredicated(MI)) {
3195 if (isPostIncrement(MI)) {
3200 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3207 // Inserts branching instructions in reverse order of their occurrence.
3208 // e.g. jump_t t1 (i1)
3210 // Jumpers = {i2, i1}
3211 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3212 MachineBasicBlock& MBB) const {
3213 SmallVector<MachineInstr*, 2> Jumpers;
3214 // If the block has no terminators, it just falls into the block after it.
3215 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3216 if (I == MBB.instr_begin())
3219 // A basic block may looks like this:
3229 // It has two succs but does not have a terminator
3230 // Don't know how to handle it.
3235 } while (I != MBB.instr_begin());
3237 I = MBB.instr_end();
3240 while (I->isDebugValue()) {
3241 if (I == MBB.instr_begin())
3245 if (!isUnpredicatedTerminator(*I))
3248 // Get the last instruction in the block.
3249 MachineInstr *LastInst = &*I;
3250 Jumpers.push_back(LastInst);
3251 MachineInstr *SecondLastInst = nullptr;
3252 // Find one more terminator if present.
3254 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3255 if (!SecondLastInst) {
3256 SecondLastInst = &*I;
3257 Jumpers.push_back(SecondLastInst);
3258 } else // This is a third branch.
3261 if (I == MBB.instr_begin())
3269 short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
3272 return Hexagon::getBaseWithLongOffset(Opcode);
3276 short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const {
3277 return Hexagon::getBaseWithLongOffset(MI.getOpcode());
3281 short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const {
3282 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
3286 // Returns Operand Index for the constant extended instruction.
3287 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3288 const uint64_t F = MI.getDesc().TSFlags;
3289 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3292 // See if instruction could potentially be a duplex candidate.
3293 // If so, return its group. Zero otherwise.
3294 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3295 const MachineInstr &MI) const {
3296 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3298 switch (MI.getOpcode()) {
3300 return HexagonII::HCG_None;
3303 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3304 // "Rd16=#U6 ; jump #r9:2"
3305 // "Rd16=Rs16 ; jump #r9:2"
3307 case Hexagon::C2_cmpeq:
3308 case Hexagon::C2_cmpgt:
3309 case Hexagon::C2_cmpgtu:
3310 DstReg = MI.getOperand(0).getReg();
3311 Src1Reg = MI.getOperand(1).getReg();
3312 Src2Reg = MI.getOperand(2).getReg();
3313 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3314 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3315 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3316 return HexagonII::HCG_A;
3318 case Hexagon::C2_cmpeqi:
3319 case Hexagon::C2_cmpgti:
3320 case Hexagon::C2_cmpgtui:
3321 // P0 = cmp.eq(Rs,#u2)
3322 DstReg = MI.getOperand(0).getReg();
3323 SrcReg = MI.getOperand(1).getReg();
3324 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3325 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3326 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3327 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3328 (MI.getOperand(2).getImm() == -1)))
3329 return HexagonII::HCG_A;
3331 case Hexagon::A2_tfr:
3333 DstReg = MI.getOperand(0).getReg();
3334 SrcReg = MI.getOperand(1).getReg();
3335 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3336 return HexagonII::HCG_A;
3338 case Hexagon::A2_tfrsi:
3340 // Do not test for #u6 size since the const is getting extended
3341 // regardless and compound could be formed.
3342 DstReg = MI.getOperand(0).getReg();
3343 if (isIntRegForSubInst(DstReg))
3344 return HexagonII::HCG_A;
3346 case Hexagon::S2_tstbit_i:
3347 DstReg = MI.getOperand(0).getReg();
3348 Src1Reg = MI.getOperand(1).getReg();
3349 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3350 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3351 MI.getOperand(2).isImm() &&
3352 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3353 return HexagonII::HCG_A;
3355 // The fact that .new form is used pretty much guarantees
3356 // that predicate register will match. Nevertheless,
3357 // there could be some false positives without additional
3359 case Hexagon::J2_jumptnew:
3360 case Hexagon::J2_jumpfnew:
3361 case Hexagon::J2_jumptnewpt:
3362 case Hexagon::J2_jumpfnewpt:
3363 Src1Reg = MI.getOperand(0).getReg();
3364 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3365 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3366 return HexagonII::HCG_B;
3368 // Transfer and jump:
3369 // Rd=#U6 ; jump #r9:2
3370 // Rd=Rs ; jump #r9:2
3371 // Do not test for jump range here.
3372 case Hexagon::J2_jump:
3373 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3374 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3375 return HexagonII::HCG_C;
3379 return HexagonII::HCG_None;
3383 // Returns -1 when there is no opcode found.
3384 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3385 const MachineInstr &GB) const {
3386 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3387 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3388 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3389 (GB.getOpcode() != Hexagon::J2_jumptnew))
3391 unsigned DestReg = GA.getOperand(0).getReg();
3392 if (!GB.readsRegister(DestReg))
3394 if (DestReg == Hexagon::P0)
3395 return Hexagon::J4_cmpeqi_tp0_jump_nt;
3396 if (DestReg == Hexagon::P1)
3397 return Hexagon::J4_cmpeqi_tp1_jump_nt;
3402 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3403 enum Hexagon::PredSense inPredSense;
3404 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3405 Hexagon::PredSense_true;
3406 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3407 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3410 llvm_unreachable("Unexpected predicable instruction");
3414 // Return the cur value instruction for a given store.
3415 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3416 switch (MI.getOpcode()) {
3417 default: llvm_unreachable("Unknown .cur type");
3418 case Hexagon::V6_vL32b_pi:
3419 return Hexagon::V6_vL32b_cur_pi;
3420 case Hexagon::V6_vL32b_ai:
3421 return Hexagon::V6_vL32b_cur_ai;
3423 case Hexagon::V6_vL32b_pi_128B:
3424 return Hexagon::V6_vL32b_cur_pi_128B;
3425 case Hexagon::V6_vL32b_ai_128B:
3426 return Hexagon::V6_vL32b_cur_ai_128B;
3433 // The diagram below shows the steps involved in the conversion of a predicated
3434 // store instruction to its .new predicated new-value form.
3436 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3438 // / \ (not OK. it will cause new-value store to be
3439 // / X conditional on p0.new while R2 producer is
3442 // p.new store p.old NV store
3443 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3449 // [if (p0)memw(R0+#0)=R2]
3452 // The following set of instructions further explains the scenario where
3453 // conditional new-value store becomes invalid when promoted to .new predicate
3456 // { 1) if (p0) r0 = add(r1, r2)
3457 // 2) p0 = cmp.eq(r3, #0) }
3459 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3460 // the first two instructions because in instr 1, r0 is conditional on old value
3461 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3462 // is not valid for new-value stores.
3463 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3464 // from the "Conditional Store" list. Because a predicated new value store
3465 // would NOT be promoted to a double dot new store. See diagram below:
3466 // This function returns yes for those stores that are predicated but not
3467 // yet promoted to predicate dot new instructions.
3469 // +---------------------+
3470 // /-----| if (p0) memw(..)=r0 |---------\~
3471 // || +---------------------+ ||
3472 // promote || /\ /\ || promote
3474 // \||/ demote || \||/
3476 // +-------------------------+ || +-------------------------+
3477 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3478 // +-------------------------+ || +-------------------------+
3481 // promote || \/ NOT possible
3485 // +-----------------------------+
3486 // | if (p0.new) memw(..)=r0.new |
3487 // +-----------------------------+
3488 // Double Dot New Store
3490 // Returns the most basic instruction for the .new predicated instructions and
3491 // new-value stores.
3492 // For example, all of the following instructions will be converted back to the
3493 // same instruction:
3494 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3495 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3496 // 3) if (p0.new) memw(R0+#0) = R1 --->
3498 // To understand the translation of instruction 1 to its original form, consider
3499 // a packet with 3 instructions.
3500 // { p0 = cmp.eq(R0,R1)
3501 // if (p0.new) R2 = add(R3, R4)
3502 // R5 = add (R3, R1)
3504 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3506 // This instruction can be part of the previous packet only if both p0 and R2
3507 // are promoted to .new values. This promotion happens in steps, first
3508 // predicate register is promoted to .new and in the next iteration R2 is
3509 // promoted. Therefore, in case of dependence check failure (due to R5) during
3510 // next iteration, it should be converted back to its most basic form.
3513 // Return the new value instruction for a given store.
3514 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3515 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3516 if (NVOpcode >= 0) // Valid new-value store instruction.
3519 switch (MI.getOpcode()) {
3520 default: llvm_unreachable("Unknown .new type");
3521 case Hexagon::S4_storerb_ur:
3522 return Hexagon::S4_storerbnew_ur;
3524 case Hexagon::S2_storerb_pci:
3525 return Hexagon::S2_storerb_pci;
3527 case Hexagon::S2_storeri_pci:
3528 return Hexagon::S2_storeri_pci;
3530 case Hexagon::S2_storerh_pci:
3531 return Hexagon::S2_storerh_pci;
3533 case Hexagon::S2_storerd_pci:
3534 return Hexagon::S2_storerd_pci;
3536 case Hexagon::S2_storerf_pci:
3537 return Hexagon::S2_storerf_pci;
3539 case Hexagon::V6_vS32b_ai:
3540 return Hexagon::V6_vS32b_new_ai;
3542 case Hexagon::V6_vS32b_pi:
3543 return Hexagon::V6_vS32b_new_pi;
3546 case Hexagon::V6_vS32b_ai_128B:
3547 return Hexagon::V6_vS32b_new_ai_128B;
3549 case Hexagon::V6_vS32b_pi_128B:
3550 return Hexagon::V6_vS32b_new_pi_128B;
3556 // Returns the opcode to use when converting MI, which is a conditional jump,
3557 // into a conditional instruction which uses the .new value of the predicate.
3558 // We also use branch probabilities to add a hint to the jump.
3559 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3560 const MachineBranchProbabilityInfo *MBPI) const {
3561 // We assume that block can have at most two successors.
3563 const MachineBasicBlock *Src = MI.getParent();
3564 const MachineOperand &BrTarget = MI.getOperand(1);
3565 const MachineBasicBlock *Dst = BrTarget.getMBB();
3567 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
3568 if (Prediction >= BranchProbability(1,2))
3571 switch (MI.getOpcode()) {
3572 case Hexagon::J2_jumpt:
3573 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3574 case Hexagon::J2_jumpf:
3575 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3578 llvm_unreachable("Unexpected jump instruction.");
3583 // Return .new predicate version for an instruction.
3584 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3585 const MachineBranchProbabilityInfo *MBPI) const {
3586 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3587 if (NewOpcode >= 0) // Valid predicate new instruction
3590 switch (MI.getOpcode()) {
3592 case Hexagon::J2_jumpt:
3593 case Hexagon::J2_jumpf:
3594 return getDotNewPredJumpOp(MI, MBPI);
3597 assert(0 && "Unknown .new type");
3603 int HexagonInstrInfo::getDotOldOp(const int opc) const {
3605 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3606 NewOp = Hexagon::getPredOldOpcode(NewOp);
3607 assert(NewOp >= 0 &&
3608 "Couldn't change predicate new instruction to its old form.");
3611 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3612 NewOp = Hexagon::getNonNVStore(NewOp);
3613 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3619 // See if instruction could potentially be a duplex candidate.
3620 // If so, return its group. Zero otherwise.
3621 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3622 const MachineInstr &MI) const {
3623 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3624 auto &HRI = getRegisterInfo();
3626 switch (MI.getOpcode()) {
3628 return HexagonII::HSIG_None;
3632 // Rd = memw(Rs+#u4:2)
3633 // Rd = memub(Rs+#u4:0)
3634 case Hexagon::L2_loadri_io:
3635 DstReg = MI.getOperand(0).getReg();
3636 SrcReg = MI.getOperand(1).getReg();
3637 // Special case this one from Group L2.
3638 // Rd = memw(r29+#u5:2)
3639 if (isIntRegForSubInst(DstReg)) {
3640 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3641 HRI.getStackRegister() == SrcReg &&
3642 MI.getOperand(2).isImm() &&
3643 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3644 return HexagonII::HSIG_L2;
3645 // Rd = memw(Rs+#u4:2)
3646 if (isIntRegForSubInst(SrcReg) &&
3647 (MI.getOperand(2).isImm() &&
3648 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3649 return HexagonII::HSIG_L1;
3652 case Hexagon::L2_loadrub_io:
3653 // Rd = memub(Rs+#u4:0)
3654 DstReg = MI.getOperand(0).getReg();
3655 SrcReg = MI.getOperand(1).getReg();
3656 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3657 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3658 return HexagonII::HSIG_L1;
3663 // Rd = memh/memuh(Rs+#u3:1)
3664 // Rd = memb(Rs+#u3:0)
3665 // Rd = memw(r29+#u5:2) - Handled above.
3666 // Rdd = memd(r29+#u5:3)
3668 // [if ([!]p0[.new])] dealloc_return
3669 // [if ([!]p0[.new])] jumpr r31
3670 case Hexagon::L2_loadrh_io:
3671 case Hexagon::L2_loadruh_io:
3672 // Rd = memh/memuh(Rs+#u3:1)
3673 DstReg = MI.getOperand(0).getReg();
3674 SrcReg = MI.getOperand(1).getReg();
3675 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3676 MI.getOperand(2).isImm() &&
3677 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3678 return HexagonII::HSIG_L2;
3680 case Hexagon::L2_loadrb_io:
3681 // Rd = memb(Rs+#u3:0)
3682 DstReg = MI.getOperand(0).getReg();
3683 SrcReg = MI.getOperand(1).getReg();
3684 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3685 MI.getOperand(2).isImm() &&
3686 isUInt<3>(MI.getOperand(2).getImm()))
3687 return HexagonII::HSIG_L2;
3689 case Hexagon::L2_loadrd_io:
3690 // Rdd = memd(r29+#u5:3)
3691 DstReg = MI.getOperand(0).getReg();
3692 SrcReg = MI.getOperand(1).getReg();
3693 if (isDblRegForSubInst(DstReg, HRI) &&
3694 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3695 HRI.getStackRegister() == SrcReg &&
3696 MI.getOperand(2).isImm() &&
3697 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3698 return HexagonII::HSIG_L2;
3700 // dealloc_return is not documented in Hexagon Manual, but marked
3701 // with A_SUBINSN attribute in iset_v4classic.py.
3702 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3703 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3704 case Hexagon::L4_return:
3705 case Hexagon::L2_deallocframe:
3706 return HexagonII::HSIG_L2;
3707 case Hexagon::EH_RETURN_JMPR:
3708 case Hexagon::PS_jmpret:
3710 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3711 DstReg = MI.getOperand(0).getReg();
3712 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3713 return HexagonII::HSIG_L2;
3715 case Hexagon::PS_jmprett:
3716 case Hexagon::PS_jmpretf:
3717 case Hexagon::PS_jmprettnewpt:
3718 case Hexagon::PS_jmpretfnewpt:
3719 case Hexagon::PS_jmprettnew:
3720 case Hexagon::PS_jmpretfnew:
3721 DstReg = MI.getOperand(1).getReg();
3722 SrcReg = MI.getOperand(0).getReg();
3723 // [if ([!]p0[.new])] jumpr r31
3724 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3725 (Hexagon::P0 == SrcReg)) &&
3726 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3727 return HexagonII::HSIG_L2;
3729 case Hexagon::L4_return_t :
3730 case Hexagon::L4_return_f :
3731 case Hexagon::L4_return_tnew_pnt :
3732 case Hexagon::L4_return_fnew_pnt :
3733 case Hexagon::L4_return_tnew_pt :
3734 case Hexagon::L4_return_fnew_pt :
3735 // [if ([!]p0[.new])] dealloc_return
3736 SrcReg = MI.getOperand(0).getReg();
3737 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3738 return HexagonII::HSIG_L2;
3743 // memw(Rs+#u4:2) = Rt
3744 // memb(Rs+#u4:0) = Rt
3745 case Hexagon::S2_storeri_io:
3746 // Special case this one from Group S2.
3747 // memw(r29+#u5:2) = Rt
3748 Src1Reg = MI.getOperand(0).getReg();
3749 Src2Reg = MI.getOperand(2).getReg();
3750 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3751 isIntRegForSubInst(Src2Reg) &&
3752 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3753 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3754 return HexagonII::HSIG_S2;
3755 // memw(Rs+#u4:2) = Rt
3756 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3757 MI.getOperand(1).isImm() &&
3758 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3759 return HexagonII::HSIG_S1;
3761 case Hexagon::S2_storerb_io:
3762 // memb(Rs+#u4:0) = Rt
3763 Src1Reg = MI.getOperand(0).getReg();
3764 Src2Reg = MI.getOperand(2).getReg();
3765 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3766 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3767 return HexagonII::HSIG_S1;
3772 // memh(Rs+#u3:1) = Rt
3773 // memw(r29+#u5:2) = Rt
3774 // memd(r29+#s6:3) = Rtt
3775 // memw(Rs+#u4:2) = #U1
3776 // memb(Rs+#u4) = #U1
3777 // allocframe(#u5:3)
3778 case Hexagon::S2_storerh_io:
3779 // memh(Rs+#u3:1) = Rt
3780 Src1Reg = MI.getOperand(0).getReg();
3781 Src2Reg = MI.getOperand(2).getReg();
3782 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3783 MI.getOperand(1).isImm() &&
3784 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3785 return HexagonII::HSIG_S1;
3787 case Hexagon::S2_storerd_io:
3788 // memd(r29+#s6:3) = Rtt
3789 Src1Reg = MI.getOperand(0).getReg();
3790 Src2Reg = MI.getOperand(2).getReg();
3791 if (isDblRegForSubInst(Src2Reg, HRI) &&
3792 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3793 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3794 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3795 return HexagonII::HSIG_S2;
3797 case Hexagon::S4_storeiri_io:
3798 // memw(Rs+#u4:2) = #U1
3799 Src1Reg = MI.getOperand(0).getReg();
3800 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3801 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3802 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3803 return HexagonII::HSIG_S2;
3805 case Hexagon::S4_storeirb_io:
3806 // memb(Rs+#u4) = #U1
3807 Src1Reg = MI.getOperand(0).getReg();
3808 if (isIntRegForSubInst(Src1Reg) &&
3809 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3810 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3811 return HexagonII::HSIG_S2;
3813 case Hexagon::S2_allocframe:
3814 if (MI.getOperand(0).isImm() &&
3815 isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
3816 return HexagonII::HSIG_S1;
3825 // if ([!]P0[.new]) Rd = #0
3826 // Rd = add(r29,#u6:2)
3828 // P0 = cmp.eq(Rs,#u2)
3829 // Rdd = combine(#0,Rs)
3830 // Rdd = combine(Rs,#0)
3831 // Rdd = combine(#u2,#U2)
3834 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3836 case Hexagon::A2_addi:
3837 DstReg = MI.getOperand(0).getReg();
3838 SrcReg = MI.getOperand(1).getReg();
3839 if (isIntRegForSubInst(DstReg)) {
3840 // Rd = add(r29,#u6:2)
3841 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3842 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3843 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3844 return HexagonII::HSIG_A;
3846 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3847 isInt<7>(MI.getOperand(2).getImm()))
3848 return HexagonII::HSIG_A;
3851 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3852 ((MI.getOperand(2).getImm() == 1) ||
3853 (MI.getOperand(2).getImm() == -1)))
3854 return HexagonII::HSIG_A;
3857 case Hexagon::A2_add:
3859 DstReg = MI.getOperand(0).getReg();
3860 Src1Reg = MI.getOperand(1).getReg();
3861 Src2Reg = MI.getOperand(2).getReg();
3862 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3863 isIntRegForSubInst(Src2Reg))
3864 return HexagonII::HSIG_A;
3866 case Hexagon::A2_andir:
3868 // Rd16=and(Rs16,#255)
3869 // Rd16=and(Rs16,#1)
3870 DstReg = MI.getOperand(0).getReg();
3871 SrcReg = MI.getOperand(1).getReg();
3872 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3873 MI.getOperand(2).isImm() &&
3874 ((MI.getOperand(2).getImm() == 1) ||
3875 (MI.getOperand(2).getImm() == 255)))
3876 return HexagonII::HSIG_A;
3878 case Hexagon::A2_tfr:
3880 DstReg = MI.getOperand(0).getReg();
3881 SrcReg = MI.getOperand(1).getReg();
3882 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3883 return HexagonII::HSIG_A;
3885 case Hexagon::A2_tfrsi:
3887 // Do not test for #u6 size since the const is getting extended
3888 // regardless and compound could be formed.
3890 DstReg = MI.getOperand(0).getReg();
3891 if (isIntRegForSubInst(DstReg))
3892 return HexagonII::HSIG_A;
3894 case Hexagon::C2_cmoveit:
3895 case Hexagon::C2_cmovenewit:
3896 case Hexagon::C2_cmoveif:
3897 case Hexagon::C2_cmovenewif:
3898 // if ([!]P0[.new]) Rd = #0
3900 // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3901 DstReg = MI.getOperand(0).getReg();
3902 SrcReg = MI.getOperand(1).getReg();
3903 if (isIntRegForSubInst(DstReg) &&
3904 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3905 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3906 return HexagonII::HSIG_A;
3908 case Hexagon::C2_cmpeqi:
3909 // P0 = cmp.eq(Rs,#u2)
3910 DstReg = MI.getOperand(0).getReg();
3911 SrcReg = MI.getOperand(1).getReg();
3912 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3913 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3914 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3915 return HexagonII::HSIG_A;
3917 case Hexagon::A2_combineii:
3918 case Hexagon::A4_combineii:
3919 // Rdd = combine(#u2,#U2)
3920 DstReg = MI.getOperand(0).getReg();
3921 if (isDblRegForSubInst(DstReg, HRI) &&
3922 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3923 (MI.getOperand(1).isGlobal() &&
3924 isUInt<2>(MI.getOperand(1).getOffset()))) &&
3925 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3926 (MI.getOperand(2).isGlobal() &&
3927 isUInt<2>(MI.getOperand(2).getOffset()))))
3928 return HexagonII::HSIG_A;
3930 case Hexagon::A4_combineri:
3931 // Rdd = combine(Rs,#0)
3932 DstReg = MI.getOperand(0).getReg();
3933 SrcReg = MI.getOperand(1).getReg();
3934 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3935 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3936 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3937 return HexagonII::HSIG_A;
3939 case Hexagon::A4_combineir:
3940 // Rdd = combine(#0,Rs)
3941 DstReg = MI.getOperand(0).getReg();
3942 SrcReg = MI.getOperand(2).getReg();
3943 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3944 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3945 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3946 return HexagonII::HSIG_A;
3948 case Hexagon::A2_sxtb:
3949 case Hexagon::A2_sxth:
3950 case Hexagon::A2_zxtb:
3951 case Hexagon::A2_zxth:
3952 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3953 DstReg = MI.getOperand(0).getReg();
3954 SrcReg = MI.getOperand(1).getReg();
3955 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3956 return HexagonII::HSIG_A;
3960 return HexagonII::HSIG_None;
3964 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
3965 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3969 // Return first non-debug instruction in the basic block.
3970 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
3972 for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
3973 MachineInstr &MI = *MII;
3974 if (MI.isDebugValue())
3982 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
3983 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3984 // Default to one cycle for no itinerary. However, an "empty" itinerary may
3985 // still have a MinLatency property, which getStageLatency checks.
3987 return getInstrLatency(ItinData, MI);
3989 // Get the latency embedded in the itinerary. If we're not using timing class
3990 // latencies or if we using BSB scheduling, then restrict the maximum latency
3991 // to 1 (that is, either 0 or 1).
3992 if (MI.isTransient())
3994 unsigned Latency = ItinData->getStageLatency(MI.getDesc().getSchedClass());
3995 if (!EnableTimingClassLatency ||
3996 MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>().
4004 // inverts the predication logic.
4007 bool HexagonInstrInfo::getInvertedPredSense(
4008 SmallVectorImpl<MachineOperand> &Cond) const {
4011 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4012 Cond[0].setImm(Opc);
4017 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4019 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4020 : Hexagon::getTruePredOpcode(Opc);
4021 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4022 return InvPredOpcode;
4024 llvm_unreachable("Unexpected predicated instruction");
4028 // Returns the max value that doesn't need to be extended.
4029 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4030 const uint64_t F = MI.getDesc().TSFlags;
4031 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4032 & HexagonII::ExtentSignedMask;
4033 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4034 & HexagonII::ExtentBitsMask;
4036 if (isSigned) // if value is signed
4037 return ~(-1U << (bits - 1));
4039 return ~(-1U << bits);
4043 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4044 const uint64_t F = MI.getDesc().TSFlags;
4045 return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
4049 // Returns the min value that doesn't need to be extended.
4050 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4051 const uint64_t F = MI.getDesc().TSFlags;
4052 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4053 & HexagonII::ExtentSignedMask;
4054 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4055 & HexagonII::ExtentBitsMask;
4057 if (isSigned) // if value is signed
4058 return -1U << (bits - 1);
4064 // Returns opcode of the non-extended equivalent instruction.
4065 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4066 // Check if the instruction has a register form that uses register in place
4067 // of the extended operand, if so return that as the non-extended form.
4068 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4069 if (NonExtOpcode >= 0)
4070 return NonExtOpcode;
4072 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4073 // Check addressing mode and retrieve non-ext equivalent instruction.
4074 switch (getAddrMode(MI)) {
4075 case HexagonII::Absolute :
4076 return Hexagon::getBaseWithImmOffset(MI.getOpcode());
4077 case HexagonII::BaseImmOffset :
4078 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
4079 case HexagonII::BaseLongOffset:
4080 return Hexagon::getRegShlForm(MI.getOpcode());
4090 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4091 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4094 assert(Cond.size() == 2);
4095 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4096 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4099 PredReg = Cond[1].getReg();
4101 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4103 if (Cond[1].isImplicit())
4104 PredRegFlags = RegState::Implicit;
4105 if (Cond[1].isUndef())
4106 PredRegFlags |= RegState::Undef;
4111 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4112 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4116 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4117 return Hexagon::getRegForm(MI.getOpcode());
4121 // Return the number of bytes required to encode the instruction.
4122 // Hexagon instructions are fixed length, 4 bytes, unless they
4123 // use a constant extender, which requires another 4 bytes.
4124 // For debug instructions and prolog labels, return 0.
4125 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4126 if (MI.isDebugValue() || MI.isPosition())
4129 unsigned Size = MI.getDesc().getSize();
4131 // Assume the default insn size in case it cannot be determined
4132 // for whatever reason.
4133 Size = HEXAGON_INSTR_SIZE;
4135 if (isConstExtended(MI) || isExtended(MI))
4136 Size += HEXAGON_INSTR_SIZE;
4138 // Try and compute number of instructions in asm.
4139 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4140 const MachineBasicBlock &MBB = *MI.getParent();
4141 const MachineFunction *MF = MBB.getParent();
4142 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4144 // Count the number of register definitions to find the asm string.
4145 unsigned NumDefs = 0;
4146 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4148 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4150 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4151 // Disassemble the AsmStr and approximate number of instructions.
4152 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4153 Size = getInlineAsmLength(AsmStr, *MAI);
4160 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4161 const uint64_t F = MI.getDesc().TSFlags;
4162 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4166 unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4167 const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
4168 const InstrItineraryData &II = *ST.getInstrItineraryData();
4169 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4171 return IS.getUnits();
4175 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
4176 const uint64_t F = get(Opcode).TSFlags;
4177 return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
4181 // Calculate size of the basic block without debug instructions.
4182 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4183 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4187 unsigned HexagonInstrInfo::nonDbgBundleSize(
4188 MachineBasicBlock::const_iterator BundleHead) const {
4189 assert(BundleHead->isBundle() && "Not a bundle header");
4190 auto MII = BundleHead.getInstrIterator();
4191 // Skip the bundle header.
4192 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4196 /// immediateExtend - Changes the instruction in place to one using an immediate
4198 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4199 assert((isExtendable(MI)||isConstExtended(MI)) &&
4200 "Instruction must be extendable");
4201 // Find which operand is extendable.
4202 short ExtOpNum = getCExtOpNum(MI);
4203 MachineOperand &MO = MI.getOperand(ExtOpNum);
4204 // This needs to be something we understand.
4205 assert((MO.isMBB() || MO.isImm()) &&
4206 "Branch with unknown extendable field type");
4207 // Mark given operand as extended.
4208 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4212 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4213 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4214 DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
4215 << NewTarget->getNumber(); MI.dump(););
4216 assert(MI.isBranch());
4217 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4218 int TargetPos = MI.getNumOperands() - 1;
4219 // In general branch target is the last operand,
4220 // but some implicit defs added at the end might change it.
4221 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4223 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4224 MI.getOperand(TargetPos).setMBB(NewTarget);
4225 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4226 NewOpcode = reversePrediction(NewOpcode);
4228 MI.setDesc(get(NewOpcode));
4233 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4234 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4235 MachineFunction::iterator A = MF.begin();
4236 MachineBasicBlock &B = *A;
4237 MachineBasicBlock::iterator I = B.begin();
4238 DebugLoc DL = I->getDebugLoc();
4239 MachineInstr *NewMI;
4241 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4242 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4243 NewMI = BuildMI(B, I, DL, get(insn));
4244 DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
4245 " Class: " << NewMI->getDesc().getSchedClass());
4246 NewMI->eraseFromParent();
4248 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4252 // inverts the predication logic.
4255 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4256 DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4257 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4262 // Reverse the branch prediction.
4263 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4264 int PredRevOpcode = -1;
4265 if (isPredictedTaken(Opcode))
4266 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4268 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4269 assert(PredRevOpcode > 0);
4270 return PredRevOpcode;
4274 // TODO: Add more rigorous validation.
4275 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4277 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4281 short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const {
4282 return Hexagon::xformRegToImmOffset(MI.getOpcode());