1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonHazardRecognizer.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/CodeGen/DFAPacketizer.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineInstrBundle.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleDAG.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInstrDesc.h"
38 #include "llvm/MC/MCInstrItineraries.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/BranchProbability.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetSubtargetInfo.h"
56 #define DEBUG_TYPE "hexagon-instrinfo"
58 #define GET_INSTRINFO_CTOR_DTOR
59 #define GET_INSTRMAP_INFO
60 #include "HexagonDepTimingClasses.h"
61 #include "HexagonGenDFAPacketizer.inc"
62 #include "HexagonGenInstrInfo.inc"
64 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
65 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
66 "packetization boundary."));
68 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
69 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
71 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
72 cl::Hidden, cl::ZeroOrMore, cl::init(false),
73 cl::desc("Disable schedule adjustment for new value stores."));
75 static cl::opt<bool> EnableTimingClassLatency(
76 "enable-timing-class-latency", cl::Hidden, cl::init(false),
77 cl::desc("Enable timing class latency"));
79 static cl::opt<bool> EnableALUForwarding(
80 "enable-alu-forwarding", cl::Hidden, cl::init(true),
81 cl::desc("Enable vec alu forwarding"));
83 static cl::opt<bool> EnableACCForwarding(
84 "enable-acc-forwarding", cl::Hidden, cl::init(true),
85 cl::desc("Enable vec acc forwarding"));
87 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
88 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
90 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
91 cl::init(true), cl::Hidden, cl::ZeroOrMore,
92 cl::desc("Use the DFA based hazard recognizer."));
95 /// Constants for Hexagon instructions.
97 const int Hexagon_MEMW_OFFSET_MAX = 4095;
98 const int Hexagon_MEMW_OFFSET_MIN = -4096;
99 const int Hexagon_MEMD_OFFSET_MAX = 8191;
100 const int Hexagon_MEMD_OFFSET_MIN = -8192;
101 const int Hexagon_MEMH_OFFSET_MAX = 2047;
102 const int Hexagon_MEMH_OFFSET_MIN = -2048;
103 const int Hexagon_MEMB_OFFSET_MAX = 1023;
104 const int Hexagon_MEMB_OFFSET_MIN = -1024;
105 const int Hexagon_ADDI_OFFSET_MAX = 32767;
106 const int Hexagon_ADDI_OFFSET_MIN = -32768;
107 const int Hexagon_MEMD_AUTOINC_MAX = 56;
108 const int Hexagon_MEMD_AUTOINC_MIN = -64;
109 const int Hexagon_MEMW_AUTOINC_MAX = 28;
110 const int Hexagon_MEMW_AUTOINC_MIN = -32;
111 const int Hexagon_MEMH_AUTOINC_MAX = 14;
112 const int Hexagon_MEMH_AUTOINC_MIN = -16;
113 const int Hexagon_MEMB_AUTOINC_MAX = 7;
114 const int Hexagon_MEMB_AUTOINC_MIN = -8;
115 const int Hexagon_MEMV_AUTOINC_MAX = 192; // #s3
116 const int Hexagon_MEMV_AUTOINC_MIN = -256; // #s3
117 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384; // #s3
118 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3
120 // Pin the vtable to this file.
121 void HexagonInstrInfo::anchor() {}
123 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
124 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
127 static bool isIntRegForSubInst(unsigned Reg) {
128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
132 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
137 /// Calculate number of instructions excluding the debug instructions.
138 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
139 MachineBasicBlock::const_instr_iterator MIE) {
141 for (; MIB != MIE; ++MIB) {
142 if (!MIB->isDebugValue())
148 /// Find the hardware loop instruction used to set-up the specified loop.
149 /// On Hexagon, we have two instructions used to set-up the hardware loop
150 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
151 /// to indicate the end of a loop.
152 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
153 MachineBasicBlock *TargetBB,
154 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
157 if (EndLoopOp == Hexagon::ENDLOOP0) {
158 LOOPi = Hexagon::J2_loop0i;
159 LOOPr = Hexagon::J2_loop0r;
160 } else { // EndLoopOp == Hexagon::EndLOOP1
161 LOOPi = Hexagon::J2_loop1i;
162 LOOPr = Hexagon::J2_loop1r;
165 // The loop set-up instruction will be in a predecessor block
166 for (MachineBasicBlock *PB : BB->predecessors()) {
167 // If this has been visited, already skip it.
168 if (!Visited.insert(PB).second)
172 for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
173 unsigned Opc = I->getOpcode();
174 if (Opc == LOOPi || Opc == LOOPr)
176 // We've reached a different loop, which means the loop01 has been
178 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
181 // Check the predecessors for the LOOP instruction.
182 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
188 /// Gather register def/uses from MI.
189 /// This treats possible (predicated) defs as actually happening ones
190 /// (conservatively).
191 static inline void parseOperands(const MachineInstr &MI,
192 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
196 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
197 const MachineOperand &MO = MI.getOperand(i);
202 unsigned Reg = MO.getReg();
207 Uses.push_back(MO.getReg());
210 Defs.push_back(MO.getReg());
214 // Position dependent, so check twice for swap.
215 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
217 case HexagonII::HSIG_None:
220 case HexagonII::HSIG_L1:
221 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
222 case HexagonII::HSIG_L2:
223 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224 Gb == HexagonII::HSIG_A);
225 case HexagonII::HSIG_S1:
226 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
227 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
228 case HexagonII::HSIG_S2:
229 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
230 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
231 Gb == HexagonII::HSIG_A);
232 case HexagonII::HSIG_A:
233 return (Gb == HexagonII::HSIG_A);
234 case HexagonII::HSIG_Compound:
235 return (Gb == HexagonII::HSIG_Compound);
240 /// isLoadFromStackSlot - If the specified machine instruction is a direct
241 /// load from a stack slot, return the virtual or physical register number of
242 /// the destination along with the FrameIndex of the loaded stack slot. If
243 /// not, return 0. This predicate must return 0 if the instruction has
244 /// any side effects other than loading from the stack slot.
245 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
246 int &FrameIndex) const {
247 switch (MI.getOpcode()) {
250 case Hexagon::L2_loadri_io:
251 case Hexagon::L2_loadrd_io:
252 case Hexagon::V6_vL32b_ai:
253 case Hexagon::V6_vL32b_nt_ai:
254 case Hexagon::V6_vL32b_ai_128B:
255 case Hexagon::V6_vL32b_nt_ai_128B:
256 case Hexagon::V6_vL32Ub_ai:
257 case Hexagon::V6_vL32Ub_ai_128B:
258 case Hexagon::LDriw_pred:
259 case Hexagon::LDriw_mod:
260 case Hexagon::PS_vloadrq_ai:
261 case Hexagon::PS_vloadrw_ai:
262 case Hexagon::PS_vloadrw_nt_ai:
263 case Hexagon::PS_vloadrq_ai_128B:
264 case Hexagon::PS_vloadrw_ai_128B:
265 case Hexagon::PS_vloadrw_nt_ai_128B: {
266 const MachineOperand OpFI = MI.getOperand(1);
269 const MachineOperand OpOff = MI.getOperand(2);
270 if (!OpOff.isImm() || OpOff.getImm() != 0)
272 FrameIndex = OpFI.getIndex();
273 return MI.getOperand(0).getReg();
276 case Hexagon::L2_ploadrit_io:
277 case Hexagon::L2_ploadrif_io:
278 case Hexagon::L2_ploadrdt_io:
279 case Hexagon::L2_ploadrdf_io: {
280 const MachineOperand OpFI = MI.getOperand(2);
283 const MachineOperand OpOff = MI.getOperand(3);
284 if (!OpOff.isImm() || OpOff.getImm() != 0)
286 FrameIndex = OpFI.getIndex();
287 return MI.getOperand(0).getReg();
294 /// isStoreToStackSlot - If the specified machine instruction is a direct
295 /// store to a stack slot, return the virtual or physical register number of
296 /// the source reg along with the FrameIndex of the loaded stack slot. If
297 /// not, return 0. This predicate must return 0 if the instruction has
298 /// any side effects other than storing to the stack slot.
299 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
300 int &FrameIndex) const {
301 switch (MI.getOpcode()) {
304 case Hexagon::S2_storerb_io:
305 case Hexagon::S2_storerh_io:
306 case Hexagon::S2_storeri_io:
307 case Hexagon::S2_storerd_io:
308 case Hexagon::V6_vS32b_ai:
309 case Hexagon::V6_vS32b_ai_128B:
310 case Hexagon::V6_vS32Ub_ai:
311 case Hexagon::V6_vS32Ub_ai_128B:
312 case Hexagon::STriw_pred:
313 case Hexagon::STriw_mod:
314 case Hexagon::PS_vstorerq_ai:
315 case Hexagon::PS_vstorerw_ai:
316 case Hexagon::PS_vstorerq_ai_128B:
317 case Hexagon::PS_vstorerw_ai_128B: {
318 const MachineOperand &OpFI = MI.getOperand(0);
321 const MachineOperand &OpOff = MI.getOperand(1);
322 if (!OpOff.isImm() || OpOff.getImm() != 0)
324 FrameIndex = OpFI.getIndex();
325 return MI.getOperand(2).getReg();
328 case Hexagon::S2_pstorerbt_io:
329 case Hexagon::S2_pstorerbf_io:
330 case Hexagon::S2_pstorerht_io:
331 case Hexagon::S2_pstorerhf_io:
332 case Hexagon::S2_pstorerit_io:
333 case Hexagon::S2_pstorerif_io:
334 case Hexagon::S2_pstorerdt_io:
335 case Hexagon::S2_pstorerdf_io: {
336 const MachineOperand &OpFI = MI.getOperand(1);
339 const MachineOperand &OpOff = MI.getOperand(2);
340 if (!OpOff.isImm() || OpOff.getImm() != 0)
342 FrameIndex = OpFI.getIndex();
343 return MI.getOperand(3).getReg();
350 /// This function can analyze one/two way branching only and should (mostly) be
351 /// called by target independent side.
352 /// First entry is always the opcode of the branching instruction, except when
353 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
354 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
355 /// e.g. Jump_c p will have
359 /// Cond[0] = ENDLOOP
362 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
366 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
367 MachineBasicBlock *&TBB,
368 MachineBasicBlock *&FBB,
369 SmallVectorImpl<MachineOperand> &Cond,
370 bool AllowModify) const {
375 // If the block has no terminators, it just falls into the block after it.
376 MachineBasicBlock::instr_iterator I = MBB.instr_end();
377 if (I == MBB.instr_begin())
380 // A basic block may looks like this:
390 // It has two succs but does not have a terminator
391 // Don't know how to handle it.
395 // Don't analyze EH branches.
397 } while (I != MBB.instr_begin());
402 while (I->isDebugValue()) {
403 if (I == MBB.instr_begin())
408 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
409 I->getOperand(0).isMBB();
410 // Delete the J2_jump if it's equivalent to a fall-through.
411 if (AllowModify && JumpToBlock &&
412 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
413 DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
414 I->eraseFromParent();
416 if (I == MBB.instr_begin())
420 if (!isUnpredicatedTerminator(*I))
423 // Get the last instruction in the block.
424 MachineInstr *LastInst = &*I;
425 MachineInstr *SecondLastInst = nullptr;
426 // Find one more terminator if present.
428 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
430 SecondLastInst = &*I;
432 // This is a third branch.
435 if (I == MBB.instr_begin())
440 int LastOpcode = LastInst->getOpcode();
441 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
442 // If the branch target is not a basic block, it could be a tail call.
443 // (It is, if the target is a function.)
444 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
446 if (SecLastOpcode == Hexagon::J2_jump &&
447 !SecondLastInst->getOperand(0).isMBB())
450 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
451 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
453 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
456 // If there is only one terminator instruction, process it.
457 if (LastInst && !SecondLastInst) {
458 if (LastOpcode == Hexagon::J2_jump) {
459 TBB = LastInst->getOperand(0).getMBB();
462 if (isEndLoopN(LastOpcode)) {
463 TBB = LastInst->getOperand(0).getMBB();
464 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
465 Cond.push_back(LastInst->getOperand(0));
468 if (LastOpcodeHasJMP_c) {
469 TBB = LastInst->getOperand(1).getMBB();
470 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
471 Cond.push_back(LastInst->getOperand(0));
474 // Only supporting rr/ri versions of new-value jumps.
475 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
476 TBB = LastInst->getOperand(2).getMBB();
477 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
478 Cond.push_back(LastInst->getOperand(0));
479 Cond.push_back(LastInst->getOperand(1));
482 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
483 << " with one jump\n";);
484 // Otherwise, don't know what this is.
488 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
489 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
490 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
491 if (!SecondLastInst->getOperand(1).isMBB())
493 TBB = SecondLastInst->getOperand(1).getMBB();
494 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
495 Cond.push_back(SecondLastInst->getOperand(0));
496 FBB = LastInst->getOperand(0).getMBB();
500 // Only supporting rr/ri versions of new-value jumps.
501 if (SecLastOpcodeHasNVJump &&
502 (SecondLastInst->getNumExplicitOperands() == 3) &&
503 (LastOpcode == Hexagon::J2_jump)) {
504 TBB = SecondLastInst->getOperand(2).getMBB();
505 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
506 Cond.push_back(SecondLastInst->getOperand(0));
507 Cond.push_back(SecondLastInst->getOperand(1));
508 FBB = LastInst->getOperand(0).getMBB();
512 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
513 // executed, so remove it.
514 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
515 TBB = SecondLastInst->getOperand(0).getMBB();
516 I = LastInst->getIterator();
518 I->eraseFromParent();
522 // If the block ends with an ENDLOOP, and J2_jump, handle it.
523 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
524 TBB = SecondLastInst->getOperand(0).getMBB();
525 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
526 Cond.push_back(SecondLastInst->getOperand(0));
527 FBB = LastInst->getOperand(0).getMBB();
530 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
531 << " with two jumps";);
532 // Otherwise, can't handle this.
536 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
537 int *BytesRemoved) const {
538 assert(!BytesRemoved && "code size not handled");
540 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
541 MachineBasicBlock::iterator I = MBB.end();
543 while (I != MBB.begin()) {
545 if (I->isDebugValue())
547 // Only removing branches from end of MBB.
550 if (Count && (I->getOpcode() == Hexagon::J2_jump))
551 llvm_unreachable("Malformed basic block: unconditional branch not last");
552 MBB.erase(&MBB.back());
559 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
560 MachineBasicBlock *TBB,
561 MachineBasicBlock *FBB,
562 ArrayRef<MachineOperand> Cond,
564 int *BytesAdded) const {
565 unsigned BOpc = Hexagon::J2_jump;
566 unsigned BccOpc = Hexagon::J2_jumpt;
567 assert(validateBranchCond(Cond) && "Invalid branching condition");
568 assert(TBB && "insertBranch must not be told to insert a fallthrough");
569 assert(!BytesAdded && "code size not handled");
571 // Check if reverseBranchCondition has asked to reverse this branch
572 // If we want to reverse the branch an odd number of times, we want
574 if (!Cond.empty() && Cond[0].isImm())
575 BccOpc = Cond[0].getImm();
579 // Due to a bug in TailMerging/CFG Optimization, we need to add a
580 // special case handling of a predicated jump followed by an
581 // unconditional jump. If not, Tail Merging and CFG Optimization go
582 // into an infinite loop.
583 MachineBasicBlock *NewTBB, *NewFBB;
584 SmallVector<MachineOperand, 4> Cond;
585 auto Term = MBB.getFirstTerminator();
586 if (Term != MBB.end() && isPredicated(*Term) &&
587 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
588 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
589 reverseBranchCondition(Cond);
591 return insertBranch(MBB, TBB, nullptr, Cond, DL);
593 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
594 } else if (isEndLoopN(Cond[0].getImm())) {
595 int EndLoopOp = Cond[0].getImm();
596 assert(Cond[1].isMBB());
597 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
598 // Check for it, and change the BB target if needed.
599 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
600 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
602 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
603 Loop->getOperand(0).setMBB(TBB);
604 // Add the ENDLOOP after the finding the LOOP0.
605 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
606 } else if (isNewValueJump(Cond[0].getImm())) {
607 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
609 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
610 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
611 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
612 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
613 if (Cond[2].isReg()) {
614 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
615 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
616 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
617 } else if(Cond[2].isImm()) {
618 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
619 addImm(Cond[2].getImm()).addMBB(TBB);
621 llvm_unreachable("Invalid condition for branching");
623 assert((Cond.size() == 2) && "Malformed cond vector");
624 const MachineOperand &RO = Cond[1];
625 unsigned Flags = getUndefRegState(RO.isUndef());
626 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
630 assert((!Cond.empty()) &&
631 "Cond. cannot be empty when multiple branchings are required");
632 assert((!isNewValueJump(Cond[0].getImm())) &&
633 "NV-jump cannot be inserted with another branch");
634 // Special case for hardware loops. The condition is a basic block.
635 if (isEndLoopN(Cond[0].getImm())) {
636 int EndLoopOp = Cond[0].getImm();
637 assert(Cond[1].isMBB());
638 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
639 // Check for it, and change the BB target if needed.
640 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
641 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
643 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
644 Loop->getOperand(0).setMBB(TBB);
645 // Add the ENDLOOP after the finding the LOOP0.
646 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
648 const MachineOperand &RO = Cond[1];
649 unsigned Flags = getUndefRegState(RO.isUndef());
650 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
652 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
657 /// Analyze the loop code to find the loop induction variable and compare used
658 /// to compute the number of iterations. Currently, we analyze loop that are
659 /// controlled using hardware loops. In this case, the induction variable
660 /// instruction is null. For all other cases, this function returns true, which
661 /// means we're unable to analyze it.
662 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L,
663 MachineInstr *&IndVarInst,
664 MachineInstr *&CmpInst) const {
666 MachineBasicBlock *LoopEnd = L.getBottomBlock();
667 MachineBasicBlock::iterator I = LoopEnd->getFirstTerminator();
668 // We really "analyze" only hardware loops right now.
669 if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
670 IndVarInst = nullptr;
677 /// Generate code to reduce the loop iteration by one and check if the loop is
678 /// finished. Return the value/register of the new loop count. this function
679 /// assumes the nth iteration is peeled first.
680 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
681 MachineInstr *IndVar, MachineInstr &Cmp,
682 SmallVectorImpl<MachineOperand> &Cond,
683 SmallVectorImpl<MachineInstr *> &PrevInsts,
684 unsigned Iter, unsigned MaxIter) const {
685 // We expect a hardware loop currently. This means that IndVar is set
686 // to null, and the compare is the ENDLOOP instruction.
687 assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
688 && "Expecting a hardware loop");
689 MachineFunction *MF = MBB.getParent();
690 DebugLoc DL = Cmp.getDebugLoc();
691 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
692 MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
693 Cmp.getOperand(0).getMBB(), VisitedBBs);
696 // If the loop trip count is a compile-time value, then just change the
698 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
699 Loop->getOpcode() == Hexagon::J2_loop1i) {
700 int64_t Offset = Loop->getOperand(1).getImm();
702 Loop->eraseFromParent();
704 Loop->getOperand(1).setImm(Offset - 1);
707 // The loop trip count is a run-time value. We generate code to subtract
708 // one from the trip count, and update the loop instruction.
709 assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
710 unsigned LoopCount = Loop->getOperand(1).getReg();
711 // Check if we're done with the loop.
712 unsigned LoopEnd = createVR(MF, MVT::i1);
713 MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
714 addReg(LoopCount).addImm(1);
715 unsigned NewLoopCount = createVR(MF, MVT::i32);
716 MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
717 addReg(LoopCount).addImm(-1);
718 // Update the previously generated instructions with the new loop counter.
719 for (SmallVectorImpl<MachineInstr *>::iterator I = PrevInsts.begin(),
720 E = PrevInsts.end(); I != E; ++I)
721 (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo());
723 PrevInsts.push_back(NewCmp);
724 PrevInsts.push_back(NewAdd);
725 // Insert the new loop instruction if this is the last time the loop is
728 BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
729 addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
730 // Delete the old loop instruction.
732 Loop->eraseFromParent();
733 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
734 Cond.push_back(NewCmp->getOperand(0));
738 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
739 unsigned NumCycles, unsigned ExtraPredCycles,
740 BranchProbability Probability) const {
741 return nonDbgBBSize(&MBB) <= 3;
744 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
745 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
746 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
748 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
751 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
752 unsigned NumInstrs, BranchProbability Probability) const {
753 return NumInstrs <= 4;
756 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
757 MachineBasicBlock::iterator I,
758 const DebugLoc &DL, unsigned DestReg,
759 unsigned SrcReg, bool KillSrc) const {
760 auto &HRI = getRegisterInfo();
761 unsigned KillFlag = getKillRegState(KillSrc);
763 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
764 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
765 .addReg(SrcReg, KillFlag);
768 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
769 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
770 .addReg(SrcReg, KillFlag);
773 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
774 // Map Pd = Ps to Pd = or(Ps, Ps).
775 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
776 .addReg(SrcReg).addReg(SrcReg, KillFlag);
779 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
780 Hexagon::IntRegsRegClass.contains(SrcReg)) {
781 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
782 .addReg(SrcReg, KillFlag);
785 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
786 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
787 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
788 .addReg(SrcReg, KillFlag);
791 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
792 Hexagon::IntRegsRegClass.contains(SrcReg)) {
793 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
794 .addReg(SrcReg, KillFlag);
797 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
798 Hexagon::IntRegsRegClass.contains(DestReg)) {
799 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
800 .addReg(SrcReg, KillFlag);
803 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
804 Hexagon::PredRegsRegClass.contains(DestReg)) {
805 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
806 .addReg(SrcReg, KillFlag);
809 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
810 Hexagon::IntRegsRegClass.contains(DestReg)) {
811 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
812 .addReg(SrcReg, KillFlag);
815 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
816 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
817 addReg(SrcReg, KillFlag);
820 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
821 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
822 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
823 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
824 .addReg(HiSrc, KillFlag)
825 .addReg(LoSrc, KillFlag);
828 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
829 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
831 .addReg(SrcReg, KillFlag);
834 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
835 Hexagon::VectorRegsRegClass.contains(DestReg)) {
836 llvm_unreachable("Unimplemented pred to vec");
839 if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
840 Hexagon::VectorRegsRegClass.contains(SrcReg)) {
841 llvm_unreachable("Unimplemented vec to pred");
844 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
845 unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
846 unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
847 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
848 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
849 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
850 .addReg(HiSrc, KillFlag);
851 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
852 .addReg(LoSrc, KillFlag);
857 // Show the invalid registers to ease debugging.
858 dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
859 << ": " << PrintReg(DestReg, &HRI)
860 << " = " << PrintReg(SrcReg, &HRI) << '\n';
862 llvm_unreachable("Unimplemented");
865 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
866 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
867 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
868 DebugLoc DL = MBB.findDebugLoc(I);
869 MachineFunction &MF = *MBB.getParent();
870 MachineFrameInfo &MFI = MF.getFrameInfo();
871 unsigned Align = MFI.getObjectAlignment(FI);
872 unsigned KillFlag = getKillRegState(isKill);
873 bool HasAlloca = MFI.hasVarSizedObjects();
874 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
875 const HexagonFrameLowering &HFI = *HST.getFrameLowering();
877 MachineMemOperand *MMO = MF.getMachineMemOperand(
878 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
879 MFI.getObjectSize(FI), Align);
881 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
882 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
883 .addFrameIndex(FI).addImm(0)
884 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
885 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
886 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
887 .addFrameIndex(FI).addImm(0)
888 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
889 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
890 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
891 .addFrameIndex(FI).addImm(0)
892 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
893 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
894 BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
895 .addFrameIndex(FI).addImm(0)
896 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
897 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
898 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B))
899 .addFrameIndex(FI).addImm(0)
900 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
901 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
902 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
903 .addFrameIndex(FI).addImm(0)
904 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
905 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
906 // If there are variable-sized objects, spills will not be aligned.
908 Align = HFI.getStackAlignment();
909 unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
910 : Hexagon::V6_vS32b_ai_128B;
911 BuildMI(MBB, I, DL, get(Opc))
912 .addFrameIndex(FI).addImm(0)
913 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
914 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
915 // If there are variable-sized objects, spills will not be aligned.
917 Align = HFI.getStackAlignment();
918 unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
919 : Hexagon::V6_vS32b_ai;
920 BuildMI(MBB, I, DL, get(Opc))
921 .addFrameIndex(FI).addImm(0)
922 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
923 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
924 // If there are variable-sized objects, spills will not be aligned.
926 Align = HFI.getStackAlignment();
927 unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
928 : Hexagon::PS_vstorerw_ai;
929 BuildMI(MBB, I, DL, get(Opc))
930 .addFrameIndex(FI).addImm(0)
931 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
932 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
933 // If there are variable-sized objects, spills will not be aligned.
935 Align = HFI.getStackAlignment();
936 unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
937 : Hexagon::PS_vstorerw_ai_128B;
938 BuildMI(MBB, I, DL, get(Opc))
939 .addFrameIndex(FI).addImm(0)
940 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
942 llvm_unreachable("Unimplemented");
946 void HexagonInstrInfo::loadRegFromStackSlot(
947 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
948 int FI, const TargetRegisterClass *RC,
949 const TargetRegisterInfo *TRI) const {
950 DebugLoc DL = MBB.findDebugLoc(I);
951 MachineFunction &MF = *MBB.getParent();
952 MachineFrameInfo &MFI = MF.getFrameInfo();
953 unsigned Align = MFI.getObjectAlignment(FI);
954 bool HasAlloca = MFI.hasVarSizedObjects();
955 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
956 const HexagonFrameLowering &HFI = *HST.getFrameLowering();
958 MachineMemOperand *MMO = MF.getMachineMemOperand(
959 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
960 MFI.getObjectSize(FI), Align);
962 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
963 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
964 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
965 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
966 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
967 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
969 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
970 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
972 BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
973 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
974 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
975 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg)
976 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
977 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
978 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
979 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
980 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
981 // If there are variable-sized objects, spills will not be aligned.
983 Align = HFI.getStackAlignment();
984 unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
985 : Hexagon::PS_vloadrw_ai_128B;
986 BuildMI(MBB, I, DL, get(Opc), DestReg)
987 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
988 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
989 // If there are variable-sized objects, spills will not be aligned.
991 Align = HFI.getStackAlignment();
992 unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
993 : Hexagon::V6_vL32b_ai_128B;
994 BuildMI(MBB, I, DL, get(Opc), DestReg)
995 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
996 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
997 // If there are variable-sized objects, spills will not be aligned.
999 Align = HFI.getStackAlignment();
1000 unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
1001 : Hexagon::V6_vL32b_ai;
1002 BuildMI(MBB, I, DL, get(Opc), DestReg)
1003 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1004 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
1005 // If there are variable-sized objects, spills will not be aligned.
1007 Align = HFI.getStackAlignment();
1008 unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
1009 : Hexagon::PS_vloadrw_ai;
1010 BuildMI(MBB, I, DL, get(Opc), DestReg)
1011 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1013 llvm_unreachable("Can't store this register to stack slot");
1017 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
1018 const MachineBasicBlock &B = *MI.getParent();
1019 Regs.addLiveOuts(B);
1020 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1021 for (auto I = B.rbegin(); I != E; ++I)
1022 Regs.stepBackward(*I);
1025 /// expandPostRAPseudo - This function is called for all pseudo instructions
1026 /// that remain after register allocation. Many pseudo instructions are
1027 /// created to help register allocation. This is the place to convert them
1028 /// into real instructions. The target can edit MI in place, or it can insert
1029 /// new instructions and erase MI. The function should return true if
1030 /// anything was changed.
1031 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1032 const HexagonRegisterInfo &HRI = getRegisterInfo();
1033 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1034 MachineBasicBlock &MBB = *MI.getParent();
1035 DebugLoc DL = MI.getDebugLoc();
1036 unsigned Opc = MI.getOpcode();
1037 const unsigned VecOffset = 1;
1040 case TargetOpcode::COPY: {
1041 MachineOperand &MD = MI.getOperand(0);
1042 MachineOperand &MS = MI.getOperand(1);
1043 MachineBasicBlock::iterator MBBI = MI.getIterator();
1044 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1045 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1046 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1051 case Hexagon::PS_aligna:
1052 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1053 .addReg(HRI.getFrameRegister())
1054 .addImm(-MI.getOperand(1).getImm());
1057 case Hexagon::V6_vassignp_128B:
1058 case Hexagon::V6_vassignp: {
1059 unsigned SrcReg = MI.getOperand(1).getReg();
1060 unsigned DstReg = MI.getOperand(0).getReg();
1061 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1062 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1063 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1064 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1068 case Hexagon::V6_lo_128B:
1069 case Hexagon::V6_lo: {
1070 unsigned SrcReg = MI.getOperand(1).getReg();
1071 unsigned DstReg = MI.getOperand(0).getReg();
1072 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1073 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1075 MRI.clearKillFlags(SrcSubLo);
1078 case Hexagon::V6_hi_128B:
1079 case Hexagon::V6_hi: {
1080 unsigned SrcReg = MI.getOperand(1).getReg();
1081 unsigned DstReg = MI.getOperand(0).getReg();
1082 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1083 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1085 MRI.clearKillFlags(SrcSubHi);
1088 case Hexagon::PS_vstorerw_ai:
1089 case Hexagon::PS_vstorerwu_ai:
1090 case Hexagon::PS_vstorerw_ai_128B:
1091 case Hexagon::PS_vstorerwu_ai_128B: {
1092 bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
1093 Opc == Hexagon::PS_vstorerwu_ai_128B);
1094 bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
1095 Opc == Hexagon::PS_vstorerw_ai_128B);
1096 unsigned SrcReg = MI.getOperand(2).getReg();
1097 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1098 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1101 NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1102 : Hexagon::V6_vS32b_ai;
1104 NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
1105 : Hexagon::V6_vS32Ub_ai;
1107 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1108 MachineInstr *MI1New =
1109 BuildMI(MBB, MI, DL, get(NewOpc))
1110 .add(MI.getOperand(0))
1111 .addImm(MI.getOperand(1).getImm())
1113 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1114 MI1New->getOperand(0).setIsKill(false);
1115 BuildMI(MBB, MI, DL, get(NewOpc))
1116 .add(MI.getOperand(0))
1117 // The Vectors are indexed in multiples of vector size.
1118 .addImm(MI.getOperand(1).getImm() + Offset)
1120 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1124 case Hexagon::PS_vloadrw_ai:
1125 case Hexagon::PS_vloadrwu_ai:
1126 case Hexagon::PS_vloadrw_ai_128B:
1127 case Hexagon::PS_vloadrwu_ai_128B: {
1128 bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
1129 Opc == Hexagon::PS_vloadrwu_ai_128B);
1130 bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
1131 Opc == Hexagon::PS_vloadrw_ai_128B);
1134 NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1135 : Hexagon::V6_vL32b_ai;
1137 NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
1138 : Hexagon::V6_vL32Ub_ai;
1140 unsigned DstReg = MI.getOperand(0).getReg();
1141 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1142 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1143 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1144 .add(MI.getOperand(1))
1145 .addImm(MI.getOperand(2).getImm())
1146 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1147 MI1New->getOperand(1).setIsKill(false);
1148 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1149 .add(MI.getOperand(1))
1150 // The Vectors are indexed in multiples of vector size.
1151 .addImm(MI.getOperand(2).getImm() + Offset)
1152 .setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1156 case Hexagon::PS_true: {
1157 unsigned Reg = MI.getOperand(0).getReg();
1158 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1159 .addReg(Reg, RegState::Undef)
1160 .addReg(Reg, RegState::Undef);
1164 case Hexagon::PS_false: {
1165 unsigned Reg = MI.getOperand(0).getReg();
1166 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1167 .addReg(Reg, RegState::Undef)
1168 .addReg(Reg, RegState::Undef);
1172 case Hexagon::PS_vmulw: {
1173 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1174 unsigned DstReg = MI.getOperand(0).getReg();
1175 unsigned Src1Reg = MI.getOperand(1).getReg();
1176 unsigned Src2Reg = MI.getOperand(2).getReg();
1177 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1178 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1179 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1180 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1181 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1182 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1185 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1186 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1190 MRI.clearKillFlags(Src1SubHi);
1191 MRI.clearKillFlags(Src1SubLo);
1192 MRI.clearKillFlags(Src2SubHi);
1193 MRI.clearKillFlags(Src2SubLo);
1196 case Hexagon::PS_vmulw_acc: {
1197 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1198 unsigned DstReg = MI.getOperand(0).getReg();
1199 unsigned Src1Reg = MI.getOperand(1).getReg();
1200 unsigned Src2Reg = MI.getOperand(2).getReg();
1201 unsigned Src3Reg = MI.getOperand(3).getReg();
1202 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1203 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1204 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1205 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1206 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1207 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1208 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1209 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1213 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1214 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1219 MRI.clearKillFlags(Src1SubHi);
1220 MRI.clearKillFlags(Src1SubLo);
1221 MRI.clearKillFlags(Src2SubHi);
1222 MRI.clearKillFlags(Src2SubLo);
1223 MRI.clearKillFlags(Src3SubHi);
1224 MRI.clearKillFlags(Src3SubLo);
1227 case Hexagon::PS_pselect: {
1228 const MachineOperand &Op0 = MI.getOperand(0);
1229 const MachineOperand &Op1 = MI.getOperand(1);
1230 const MachineOperand &Op2 = MI.getOperand(2);
1231 const MachineOperand &Op3 = MI.getOperand(3);
1232 unsigned Rd = Op0.getReg();
1233 unsigned Pu = Op1.getReg();
1234 unsigned Rs = Op2.getReg();
1235 unsigned Rt = Op3.getReg();
1236 DebugLoc DL = MI.getDebugLoc();
1237 unsigned K1 = getKillRegState(Op1.isKill());
1238 unsigned K2 = getKillRegState(Op2.isKill());
1239 unsigned K3 = getKillRegState(Op3.isKill());
1241 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1242 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1245 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1251 case Hexagon::PS_vselect:
1252 case Hexagon::PS_vselect_128B: {
1253 const MachineOperand &Op0 = MI.getOperand(0);
1254 const MachineOperand &Op1 = MI.getOperand(1);
1255 const MachineOperand &Op2 = MI.getOperand(2);
1256 const MachineOperand &Op3 = MI.getOperand(3);
1257 LivePhysRegs LiveAtMI(HRI);
1258 getLiveRegsAt(LiveAtMI, MI);
1259 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1260 unsigned PReg = Op1.getReg();
1261 assert(Op1.getSubReg() == 0);
1262 unsigned PState = getRegState(Op1);
1264 if (Op0.getReg() != Op2.getReg()) {
1265 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1267 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1272 T.addReg(Op0.getReg(), RegState::Implicit);
1275 if (Op0.getReg() != Op3.getReg()) {
1276 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1278 .addReg(PReg, PState)
1281 T.addReg(Op0.getReg(), RegState::Implicit);
1286 case Hexagon::PS_wselect:
1287 case Hexagon::PS_wselect_128B: {
1288 MachineOperand &Op0 = MI.getOperand(0);
1289 MachineOperand &Op1 = MI.getOperand(1);
1290 MachineOperand &Op2 = MI.getOperand(2);
1291 MachineOperand &Op3 = MI.getOperand(3);
1292 LivePhysRegs LiveAtMI(HRI);
1293 getLiveRegsAt(LiveAtMI, MI);
1294 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1295 unsigned PReg = Op1.getReg();
1296 assert(Op1.getSubReg() == 0);
1297 unsigned PState = getRegState(Op1);
1299 if (Op0.getReg() != Op2.getReg()) {
1300 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1302 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1303 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1304 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1311 T.addReg(Op0.getReg(), RegState::Implicit);
1314 if (Op0.getReg() != Op3.getReg()) {
1315 unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1316 unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1317 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1319 .addReg(PReg, PState)
1323 T.addReg(Op0.getReg(), RegState::Implicit);
1328 case Hexagon::PS_tailcall_i:
1329 MI.setDesc(get(Hexagon::J2_jump));
1331 case Hexagon::PS_tailcall_r:
1332 case Hexagon::PS_jmpret:
1333 MI.setDesc(get(Hexagon::J2_jumpr));
1335 case Hexagon::PS_jmprett:
1336 MI.setDesc(get(Hexagon::J2_jumprt));
1338 case Hexagon::PS_jmpretf:
1339 MI.setDesc(get(Hexagon::J2_jumprf));
1341 case Hexagon::PS_jmprettnewpt:
1342 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1344 case Hexagon::PS_jmpretfnewpt:
1345 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1347 case Hexagon::PS_jmprettnew:
1348 MI.setDesc(get(Hexagon::J2_jumprtnew));
1350 case Hexagon::PS_jmpretfnew:
1351 MI.setDesc(get(Hexagon::J2_jumprfnew));
1358 // We indicate that we want to reverse the branch by
1359 // inserting the reversed branching opcode.
1360 bool HexagonInstrInfo::reverseBranchCondition(
1361 SmallVectorImpl<MachineOperand> &Cond) const {
1364 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1365 unsigned opcode = Cond[0].getImm();
1367 assert(get(opcode).isBranch() && "Should be a branching condition.");
1368 if (isEndLoopN(opcode))
1370 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1371 Cond[0].setImm(NewOpcode);
1375 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1376 MachineBasicBlock::iterator MI) const {
1378 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1381 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1382 return getAddrMode(MI) == HexagonII::PostInc;
1385 // Returns true if an instruction is predicated irrespective of the predicate
1386 // sense. For example, all of the following will return true.
1387 // if (p0) R1 = add(R2, R3)
1388 // if (!p0) R1 = add(R2, R3)
1389 // if (p0.new) R1 = add(R2, R3)
1390 // if (!p0.new) R1 = add(R2, R3)
1391 // Note: New-value stores are not included here as in the current
1392 // implementation, we don't need to check their predicate sense.
1393 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1394 const uint64_t F = MI.getDesc().TSFlags;
1395 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1398 bool HexagonInstrInfo::PredicateInstruction(
1399 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1400 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1401 isEndLoopN(Cond[0].getImm())) {
1402 DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1405 int Opc = MI.getOpcode();
1406 assert (isPredicable(MI) && "Expected predicable instruction");
1407 bool invertJump = predOpcodeHasNot(Cond);
1409 // We have to predicate MI "in place", i.e. after this function returns,
1410 // MI will need to be transformed into a predicated form. To avoid com-
1411 // plicated manipulations with the operands (handling tied operands,
1412 // etc.), build a new temporary instruction, then overwrite MI with it.
1414 MachineBasicBlock &B = *MI.getParent();
1415 DebugLoc DL = MI.getDebugLoc();
1416 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1417 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1418 unsigned NOp = 0, NumOps = MI.getNumOperands();
1419 while (NOp < NumOps) {
1420 MachineOperand &Op = MI.getOperand(NOp);
1421 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1427 unsigned PredReg, PredRegPos, PredRegFlags;
1428 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1431 T.addReg(PredReg, PredRegFlags);
1432 while (NOp < NumOps)
1433 T.add(MI.getOperand(NOp++));
1435 MI.setDesc(get(PredOpc));
1436 while (unsigned n = MI.getNumOperands())
1437 MI.RemoveOperand(n-1);
1438 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1439 MI.addOperand(T->getOperand(i));
1441 MachineBasicBlock::instr_iterator TI = T->getIterator();
1444 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1445 MRI.clearKillFlags(PredReg);
1449 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1450 ArrayRef<MachineOperand> Pred2) const {
1455 bool HexagonInstrInfo::DefinesPredicate(
1456 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
1457 auto &HRI = getRegisterInfo();
1458 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1459 MachineOperand MO = MI.getOperand(oper);
1463 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1464 if (RC == &Hexagon::PredRegsRegClass) {
1469 } else if (MO.isRegMask()) {
1470 for (unsigned PR : Hexagon::PredRegsRegClass) {
1471 if (!MI.modifiesRegister(PR, &HRI))
1481 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1482 if (!MI.getDesc().isPredicable())
1485 if (MI.isCall() || isTailCall(MI)) {
1486 const MachineFunction &MF = *MI.getParent()->getParent();
1487 if (!MF.getSubtarget<HexagonSubtarget>().usePredicatedCalls())
1493 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1494 const MachineBasicBlock *MBB,
1495 const MachineFunction &MF) const {
1496 // Debug info is never a scheduling boundary. It's necessary to be explicit
1497 // due to the special treatment of IT instructions below, otherwise a
1498 // dbg_value followed by an IT will result in the IT instruction being
1499 // considered a scheduling hazard, which is wrong. It should be the actual
1500 // instruction preceding the dbg_value instruction(s), just like it is
1501 // when debug info is not present.
1502 if (MI.isDebugValue())
1505 // Throwing call is a boundary.
1507 // Don't mess around with no return calls.
1508 if (doesNotReturn(MI))
1510 // If any of the block's successors is a landing pad, this could be a
1512 for (auto I : MBB->successors())
1517 // Terminators and labels can't be scheduled around.
1518 if (MI.getDesc().isTerminator() || MI.isPosition())
1521 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1527 /// Measure the specified inline asm to determine an approximation of its
1529 /// Comments (which run till the next SeparatorString or newline) do not
1530 /// count as an instruction.
1531 /// Any other non-whitespace text is considered an instruction, with
1532 /// multiple instructions separated by SeparatorString or newlines.
1533 /// Variable-length instructions are not handled here; this function
1534 /// may be overloaded in the target code to do that.
1535 /// Hexagon counts the number of ##'s and adjust for that many
1536 /// constant exenders.
1537 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1538 const MCAsmInfo &MAI) const {
1539 StringRef AStr(Str);
1540 // Count the number of instructions in the asm.
1541 bool atInsnStart = true;
1542 unsigned Length = 0;
1543 for (; *Str; ++Str) {
1544 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1545 strlen(MAI.getSeparatorString())) == 0)
1547 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1548 Length += MAI.getMaxInstLength();
1549 atInsnStart = false;
1551 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1552 MAI.getCommentString().size()) == 0)
1553 atInsnStart = false;
1556 // Add to size number of constant extenders seen * 4.
1557 StringRef Occ("##");
1558 Length += AStr.count(Occ)*4;
1562 ScheduleHazardRecognizer*
1563 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1564 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1565 if (UseDFAHazardRec) {
1566 auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
1567 return new HexagonHazardRecognizer(II, this, HST);
1569 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1572 /// \brief For a comparison instruction, return the source registers in
1573 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1574 /// compares against in CmpValue. Return true if the comparison instruction
1575 /// can be analyzed.
1576 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1577 unsigned &SrcReg2, int &Mask,
1579 unsigned Opc = MI.getOpcode();
1581 // Set mask and the first source register.
1583 case Hexagon::C2_cmpeq:
1584 case Hexagon::C2_cmpeqp:
1585 case Hexagon::C2_cmpgt:
1586 case Hexagon::C2_cmpgtp:
1587 case Hexagon::C2_cmpgtu:
1588 case Hexagon::C2_cmpgtup:
1589 case Hexagon::C4_cmpneq:
1590 case Hexagon::C4_cmplte:
1591 case Hexagon::C4_cmplteu:
1592 case Hexagon::C2_cmpeqi:
1593 case Hexagon::C2_cmpgti:
1594 case Hexagon::C2_cmpgtui:
1595 case Hexagon::C4_cmpneqi:
1596 case Hexagon::C4_cmplteui:
1597 case Hexagon::C4_cmpltei:
1598 SrcReg = MI.getOperand(1).getReg();
1601 case Hexagon::A4_cmpbeq:
1602 case Hexagon::A4_cmpbgt:
1603 case Hexagon::A4_cmpbgtu:
1604 case Hexagon::A4_cmpbeqi:
1605 case Hexagon::A4_cmpbgti:
1606 case Hexagon::A4_cmpbgtui:
1607 SrcReg = MI.getOperand(1).getReg();
1610 case Hexagon::A4_cmpheq:
1611 case Hexagon::A4_cmphgt:
1612 case Hexagon::A4_cmphgtu:
1613 case Hexagon::A4_cmpheqi:
1614 case Hexagon::A4_cmphgti:
1615 case Hexagon::A4_cmphgtui:
1616 SrcReg = MI.getOperand(1).getReg();
1621 // Set the value/second source register.
1623 case Hexagon::C2_cmpeq:
1624 case Hexagon::C2_cmpeqp:
1625 case Hexagon::C2_cmpgt:
1626 case Hexagon::C2_cmpgtp:
1627 case Hexagon::C2_cmpgtu:
1628 case Hexagon::C2_cmpgtup:
1629 case Hexagon::A4_cmpbeq:
1630 case Hexagon::A4_cmpbgt:
1631 case Hexagon::A4_cmpbgtu:
1632 case Hexagon::A4_cmpheq:
1633 case Hexagon::A4_cmphgt:
1634 case Hexagon::A4_cmphgtu:
1635 case Hexagon::C4_cmpneq:
1636 case Hexagon::C4_cmplte:
1637 case Hexagon::C4_cmplteu:
1638 SrcReg2 = MI.getOperand(2).getReg();
1641 case Hexagon::C2_cmpeqi:
1642 case Hexagon::C2_cmpgtui:
1643 case Hexagon::C2_cmpgti:
1644 case Hexagon::C4_cmpneqi:
1645 case Hexagon::C4_cmplteui:
1646 case Hexagon::C4_cmpltei:
1647 case Hexagon::A4_cmpbeqi:
1648 case Hexagon::A4_cmpbgti:
1649 case Hexagon::A4_cmpbgtui:
1650 case Hexagon::A4_cmpheqi:
1651 case Hexagon::A4_cmphgti:
1652 case Hexagon::A4_cmphgtui:
1654 Value = MI.getOperand(2).getImm();
1661 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1662 const MachineInstr &MI,
1663 unsigned *PredCost) const {
1664 return getInstrTimingClassLatency(ItinData, MI);
1668 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1669 const TargetSubtargetInfo &STI) const {
1670 const InstrItineraryData *II = STI.getInstrItineraryData();
1671 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1674 // Inspired by this pair:
1675 // %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1676 // S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1677 // Currently AA considers the addresses in these instructions to be aliasing.
1678 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1679 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1680 int OffsetA = 0, OffsetB = 0;
1681 unsigned SizeA = 0, SizeB = 0;
1683 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1684 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1687 // Instructions that are pure loads, not loads and stores like memops are not
1689 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1692 // Get base, offset, and access size in MIa.
1693 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1694 if (!BaseRegA || !SizeA)
1697 // Get base, offset, and access size in MIb.
1698 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
1699 if (!BaseRegB || !SizeB)
1702 if (BaseRegA != BaseRegB)
1705 // This is a mem access with the same base register and known offsets from it.
1707 if (OffsetA > OffsetB) {
1708 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1709 return (SizeB <= offDiff);
1710 } else if (OffsetA < OffsetB) {
1711 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1712 return (SizeA <= offDiff);
1718 /// If the instruction is an increment of a constant value, return the amount.
1719 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
1721 if (isPostIncrement(MI)) {
1722 unsigned AccessSize;
1723 return getBaseAndOffset(MI, Value, AccessSize);
1725 if (MI.getOpcode() == Hexagon::A2_addi) {
1726 Value = MI.getOperand(2).getImm();
1733 std::pair<unsigned, unsigned>
1734 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1735 return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1736 TF & HexagonII::MO_Bitmasks);
1739 ArrayRef<std::pair<unsigned, const char*>>
1740 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1741 using namespace HexagonII;
1742 static const std::pair<unsigned, const char*> Flags[] = {
1743 {MO_PCREL, "hexagon-pcrel"},
1744 {MO_GOT, "hexagon-got"},
1745 {MO_LO16, "hexagon-lo16"},
1746 {MO_HI16, "hexagon-hi16"},
1747 {MO_GPREL, "hexagon-gprel"},
1748 {MO_GDGOT, "hexagon-gdgot"},
1749 {MO_GDPLT, "hexagon-gdplt"},
1750 {MO_IE, "hexagon-ie"},
1751 {MO_IEGOT, "hexagon-iegot"},
1752 {MO_TPREL, "hexagon-tprel"}
1754 return makeArrayRef(Flags);
1757 ArrayRef<std::pair<unsigned, const char*>>
1758 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1759 using namespace HexagonII;
1760 static const std::pair<unsigned, const char*> Flags[] = {
1761 {HMOTF_ConstExtended, "hexagon-ext"}
1763 return makeArrayRef(Flags);
1766 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
1767 MachineRegisterInfo &MRI = MF->getRegInfo();
1768 const TargetRegisterClass *TRC;
1769 if (VT == MVT::i1) {
1770 TRC = &Hexagon::PredRegsRegClass;
1771 } else if (VT == MVT::i32 || VT == MVT::f32) {
1772 TRC = &Hexagon::IntRegsRegClass;
1773 } else if (VT == MVT::i64 || VT == MVT::f64) {
1774 TRC = &Hexagon::DoubleRegsRegClass;
1776 llvm_unreachable("Cannot handle this register class");
1779 unsigned NewReg = MRI.createVirtualRegister(TRC);
1783 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
1784 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1787 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
1788 const uint64_t F = MI.getDesc().TSFlags;
1789 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
1792 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
1793 const MachineFunction *MF = MI.getParent()->getParent();
1794 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1795 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1798 && !(QII->isTC2Early(MI))
1799 && !(MI.getDesc().mayLoad())
1800 && !(MI.getDesc().mayStore())
1801 && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
1802 && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
1803 && !(QII->isMemOp(MI))
1812 // Return true if the instruction is a compund branch instruction.
1813 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
1814 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
1817 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1818 // isFPImm and later getFPImm as well.
1819 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
1820 const uint64_t F = MI.getDesc().TSFlags;
1821 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1822 if (isExtended) // Instruction must be extended.
1825 unsigned isExtendable =
1826 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1833 short ExtOpNum = getCExtOpNum(MI);
1834 const MachineOperand &MO = MI.getOperand(ExtOpNum);
1835 // Use MO operand flags to determine if MO
1836 // has the HMOTF_ConstExtended flag set.
1837 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
1839 // If this is a Machine BB address we are talking about, and it is
1840 // not marked as extended, say so.
1844 // We could be using an instruction with an extendable immediate and shoehorn
1845 // a global address into it. If it is a global address it will be constant
1846 // extended. We do this for COMBINE.
1847 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1848 MO.isJTI() || MO.isCPI() || MO.isFPImm())
1851 // If the extendable operand is not 'Immediate' type, the instruction should
1852 // have 'isExtended' flag set.
1853 assert(MO.isImm() && "Extendable operand must be Immediate type");
1855 int MinValue = getMinValue(MI);
1856 int MaxValue = getMaxValue(MI);
1857 int ImmValue = MO.getImm();
1859 return (ImmValue < MinValue || ImmValue > MaxValue);
1862 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
1863 switch (MI.getOpcode()) {
1864 case Hexagon::L4_return :
1865 case Hexagon::L4_return_t :
1866 case Hexagon::L4_return_f :
1867 case Hexagon::L4_return_tnew_pnt :
1868 case Hexagon::L4_return_fnew_pnt :
1869 case Hexagon::L4_return_tnew_pt :
1870 case Hexagon::L4_return_fnew_pt :
1876 // Return true when ConsMI uses a register defined by ProdMI.
1877 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
1878 const MachineInstr &ConsMI) const {
1879 if (!ProdMI.getDesc().getNumDefs())
1882 auto &HRI = getRegisterInfo();
1884 SmallVector<unsigned, 4> DefsA;
1885 SmallVector<unsigned, 4> DefsB;
1886 SmallVector<unsigned, 8> UsesA;
1887 SmallVector<unsigned, 8> UsesB;
1889 parseOperands(ProdMI, DefsA, UsesA);
1890 parseOperands(ConsMI, DefsB, UsesB);
1892 for (auto &RegA : DefsA)
1893 for (auto &RegB : UsesB) {
1894 // True data dependency.
1898 if (TargetRegisterInfo::isPhysicalRegister(RegA))
1899 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1900 if (RegB == *SubRegs)
1903 if (TargetRegisterInfo::isPhysicalRegister(RegB))
1904 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1905 if (RegA == *SubRegs)
1912 // Returns true if the instruction is alread a .cur.
1913 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
1914 switch (MI.getOpcode()) {
1915 case Hexagon::V6_vL32b_cur_pi:
1916 case Hexagon::V6_vL32b_cur_ai:
1917 case Hexagon::V6_vL32b_cur_pi_128B:
1918 case Hexagon::V6_vL32b_cur_ai_128B:
1924 // Returns true, if any one of the operands is a dot new
1925 // insn, whether it is predicated dot new or register dot new.
1926 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
1927 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
1933 /// Symmetrical. See if these two instructions are fit for duplex pair.
1934 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
1935 const MachineInstr &MIb) const {
1936 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
1937 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
1938 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
1941 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
1942 if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
1946 unsigned SchedClass = MI.getDesc().getSchedClass();
1947 return is_TC4x(SchedClass) || is_TC3x(SchedClass);
1950 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
1951 return (Opcode == Hexagon::ENDLOOP0 ||
1952 Opcode == Hexagon::ENDLOOP1);
1955 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
1957 case MachineOperand::MO_MachineBasicBlock:
1958 case MachineOperand::MO_GlobalAddress:
1959 case MachineOperand::MO_ExternalSymbol:
1960 case MachineOperand::MO_JumpTableIndex:
1961 case MachineOperand::MO_ConstantPoolIndex:
1962 case MachineOperand::MO_BlockAddress:
1969 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
1970 const MCInstrDesc &MID = MI.getDesc();
1971 const uint64_t F = MID.TSFlags;
1972 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
1975 // TODO: This is largely obsolete now. Will need to be removed
1976 // in consecutive patches.
1977 switch (MI.getOpcode()) {
1978 // PS_fi and PS_fia remain special cases.
1979 case Hexagon::PS_fi:
1980 case Hexagon::PS_fia:
1988 // This returns true in two cases:
1989 // - The OP code itself indicates that this is an extended instruction.
1990 // - One of MOs has been marked with HMOTF_ConstExtended flag.
1991 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
1992 // First check if this is permanently extended op code.
1993 const uint64_t F = MI.getDesc().TSFlags;
1994 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
1996 // Use MO operand flags to determine if one of MI's operands
1997 // has HMOTF_ConstExtended flag set.
1998 for (const MachineOperand &MO : MI.operands())
1999 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2004 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2005 unsigned Opcode = MI.getOpcode();
2006 const uint64_t F = get(Opcode).TSFlags;
2007 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2010 // No V60 HVX VMEM with A_INDIRECT.
2011 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2012 const MachineInstr &J) const {
2015 if (!I.mayLoad() && !I.mayStore())
2017 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2020 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2021 switch (MI.getOpcode()) {
2022 case Hexagon::J2_callr :
2023 case Hexagon::J2_callrf :
2024 case Hexagon::J2_callrt :
2025 case Hexagon::PS_call_nr :
2031 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2032 switch (MI.getOpcode()) {
2033 case Hexagon::L4_return :
2034 case Hexagon::L4_return_t :
2035 case Hexagon::L4_return_f :
2036 case Hexagon::L4_return_fnew_pnt :
2037 case Hexagon::L4_return_fnew_pt :
2038 case Hexagon::L4_return_tnew_pnt :
2039 case Hexagon::L4_return_tnew_pt :
2045 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2046 switch (MI.getOpcode()) {
2047 case Hexagon::J2_jumpr :
2048 case Hexagon::J2_jumprt :
2049 case Hexagon::J2_jumprf :
2050 case Hexagon::J2_jumprtnewpt :
2051 case Hexagon::J2_jumprfnewpt :
2052 case Hexagon::J2_jumprtnew :
2053 case Hexagon::J2_jumprfnew :
2059 // Return true if a given MI can accommodate given offset.
2060 // Use abs estimate as oppose to the exact number.
2061 // TODO: This will need to be changed to use MC level
2062 // definition of instruction extendable field size.
2063 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2064 unsigned offset) const {
2065 // This selection of jump instructions matches to that what
2066 // analyzeBranch can parse, plus NVJ.
2067 if (isNewValueJump(MI)) // r9:2
2068 return isInt<11>(offset);
2070 switch (MI.getOpcode()) {
2071 // Still missing Jump to address condition on register value.
2074 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2075 case Hexagon::J2_call:
2076 case Hexagon::PS_call_nr:
2077 return isInt<24>(offset);
2078 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2079 case Hexagon::J2_jumpf:
2080 case Hexagon::J2_jumptnew:
2081 case Hexagon::J2_jumptnewpt:
2082 case Hexagon::J2_jumpfnew:
2083 case Hexagon::J2_jumpfnewpt:
2084 case Hexagon::J2_callt:
2085 case Hexagon::J2_callf:
2086 return isInt<17>(offset);
2087 case Hexagon::J2_loop0i:
2088 case Hexagon::J2_loop0iext:
2089 case Hexagon::J2_loop0r:
2090 case Hexagon::J2_loop0rext:
2091 case Hexagon::J2_loop1i:
2092 case Hexagon::J2_loop1iext:
2093 case Hexagon::J2_loop1r:
2094 case Hexagon::J2_loop1rext:
2095 return isInt<9>(offset);
2096 // TODO: Add all the compound branches here. Can we do this in Relation model?
2097 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2098 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2099 return isInt<11>(offset);
2103 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
2104 const MachineInstr &ESMI) const {
2105 bool isLate = isLateResultInstr(LRMI);
2106 bool isEarly = isEarlySourceInstr(ESMI);
2108 DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2110 DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2113 if (isLate && isEarly) {
2114 DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2121 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
2122 switch (MI.getOpcode()) {
2123 case TargetOpcode::EXTRACT_SUBREG:
2124 case TargetOpcode::INSERT_SUBREG:
2125 case TargetOpcode::SUBREG_TO_REG:
2126 case TargetOpcode::REG_SEQUENCE:
2127 case TargetOpcode::IMPLICIT_DEF:
2128 case TargetOpcode::COPY:
2129 case TargetOpcode::INLINEASM:
2130 case TargetOpcode::PHI:
2136 unsigned SchedClass = MI.getDesc().getSchedClass();
2137 return !is_TC1(SchedClass);
2140 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2141 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2142 // resource, but all operands can be received late like an ALU instruction.
2143 return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2146 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2147 unsigned Opcode = MI.getOpcode();
2148 return Opcode == Hexagon::J2_loop0i ||
2149 Opcode == Hexagon::J2_loop0r ||
2150 Opcode == Hexagon::J2_loop0iext ||
2151 Opcode == Hexagon::J2_loop0rext ||
2152 Opcode == Hexagon::J2_loop1i ||
2153 Opcode == Hexagon::J2_loop1r ||
2154 Opcode == Hexagon::J2_loop1iext ||
2155 Opcode == Hexagon::J2_loop1rext;
2158 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2159 switch (MI.getOpcode()) {
2160 default: return false;
2161 case Hexagon::L4_iadd_memopw_io :
2162 case Hexagon::L4_isub_memopw_io :
2163 case Hexagon::L4_add_memopw_io :
2164 case Hexagon::L4_sub_memopw_io :
2165 case Hexagon::L4_and_memopw_io :
2166 case Hexagon::L4_or_memopw_io :
2167 case Hexagon::L4_iadd_memoph_io :
2168 case Hexagon::L4_isub_memoph_io :
2169 case Hexagon::L4_add_memoph_io :
2170 case Hexagon::L4_sub_memoph_io :
2171 case Hexagon::L4_and_memoph_io :
2172 case Hexagon::L4_or_memoph_io :
2173 case Hexagon::L4_iadd_memopb_io :
2174 case Hexagon::L4_isub_memopb_io :
2175 case Hexagon::L4_add_memopb_io :
2176 case Hexagon::L4_sub_memopb_io :
2177 case Hexagon::L4_and_memopb_io :
2178 case Hexagon::L4_or_memopb_io :
2179 case Hexagon::L4_ior_memopb_io:
2180 case Hexagon::L4_ior_memoph_io:
2181 case Hexagon::L4_ior_memopw_io:
2182 case Hexagon::L4_iand_memopb_io:
2183 case Hexagon::L4_iand_memoph_io:
2184 case Hexagon::L4_iand_memopw_io:
2190 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2191 const uint64_t F = MI.getDesc().TSFlags;
2192 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2195 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2196 const uint64_t F = get(Opcode).TSFlags;
2197 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2200 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2201 return isNewValueJump(MI) || isNewValueStore(MI);
2204 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2205 return isNewValue(MI) && MI.isBranch();
2208 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2209 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2212 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2213 const uint64_t F = MI.getDesc().TSFlags;
2214 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2217 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2218 const uint64_t F = get(Opcode).TSFlags;
2219 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2222 // Returns true if a particular operand is extendable for an instruction.
2223 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2224 unsigned OperandNum) const {
2225 const uint64_t F = MI.getDesc().TSFlags;
2226 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2230 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2231 const uint64_t F = MI.getDesc().TSFlags;
2232 assert(isPredicated(MI));
2233 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2236 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2237 const uint64_t F = get(Opcode).TSFlags;
2238 assert(isPredicated(Opcode));
2239 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2242 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2243 const uint64_t F = MI.getDesc().TSFlags;
2244 return !((F >> HexagonII::PredicatedFalsePos) &
2245 HexagonII::PredicatedFalseMask);
2248 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2249 const uint64_t F = get(Opcode).TSFlags;
2250 // Make sure that the instruction is predicated.
2251 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2252 return !((F >> HexagonII::PredicatedFalsePos) &
2253 HexagonII::PredicatedFalseMask);
2256 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2257 const uint64_t F = get(Opcode).TSFlags;
2258 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2261 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2262 const uint64_t F = get(Opcode).TSFlags;
2263 return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2266 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2267 const uint64_t F = get(Opcode).TSFlags;
2268 assert(get(Opcode).isBranch() &&
2269 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2270 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2273 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2274 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2275 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2276 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2277 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2280 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2281 switch (MI.getOpcode()) {
2283 case Hexagon::L2_loadrb_io:
2284 case Hexagon::L4_loadrb_ur:
2285 case Hexagon::L4_loadrb_ap:
2286 case Hexagon::L2_loadrb_pr:
2287 case Hexagon::L2_loadrb_pbr:
2288 case Hexagon::L2_loadrb_pi:
2289 case Hexagon::L2_loadrb_pci:
2290 case Hexagon::L2_loadrb_pcr:
2291 case Hexagon::L2_loadbsw2_io:
2292 case Hexagon::L4_loadbsw2_ur:
2293 case Hexagon::L4_loadbsw2_ap:
2294 case Hexagon::L2_loadbsw2_pr:
2295 case Hexagon::L2_loadbsw2_pbr:
2296 case Hexagon::L2_loadbsw2_pi:
2297 case Hexagon::L2_loadbsw2_pci:
2298 case Hexagon::L2_loadbsw2_pcr:
2299 case Hexagon::L2_loadbsw4_io:
2300 case Hexagon::L4_loadbsw4_ur:
2301 case Hexagon::L4_loadbsw4_ap:
2302 case Hexagon::L2_loadbsw4_pr:
2303 case Hexagon::L2_loadbsw4_pbr:
2304 case Hexagon::L2_loadbsw4_pi:
2305 case Hexagon::L2_loadbsw4_pci:
2306 case Hexagon::L2_loadbsw4_pcr:
2307 case Hexagon::L4_loadrb_rr:
2308 case Hexagon::L2_ploadrbt_io:
2309 case Hexagon::L2_ploadrbt_pi:
2310 case Hexagon::L2_ploadrbf_io:
2311 case Hexagon::L2_ploadrbf_pi:
2312 case Hexagon::L2_ploadrbtnew_io:
2313 case Hexagon::L2_ploadrbfnew_io:
2314 case Hexagon::L4_ploadrbt_rr:
2315 case Hexagon::L4_ploadrbf_rr:
2316 case Hexagon::L4_ploadrbtnew_rr:
2317 case Hexagon::L4_ploadrbfnew_rr:
2318 case Hexagon::L2_ploadrbtnew_pi:
2319 case Hexagon::L2_ploadrbfnew_pi:
2320 case Hexagon::L4_ploadrbt_abs:
2321 case Hexagon::L4_ploadrbf_abs:
2322 case Hexagon::L4_ploadrbtnew_abs:
2323 case Hexagon::L4_ploadrbfnew_abs:
2324 case Hexagon::L2_loadrbgp:
2326 case Hexagon::L2_loadrh_io:
2327 case Hexagon::L4_loadrh_ur:
2328 case Hexagon::L4_loadrh_ap:
2329 case Hexagon::L2_loadrh_pr:
2330 case Hexagon::L2_loadrh_pbr:
2331 case Hexagon::L2_loadrh_pi:
2332 case Hexagon::L2_loadrh_pci:
2333 case Hexagon::L2_loadrh_pcr:
2334 case Hexagon::L4_loadrh_rr:
2335 case Hexagon::L2_ploadrht_io:
2336 case Hexagon::L2_ploadrht_pi:
2337 case Hexagon::L2_ploadrhf_io:
2338 case Hexagon::L2_ploadrhf_pi:
2339 case Hexagon::L2_ploadrhtnew_io:
2340 case Hexagon::L2_ploadrhfnew_io:
2341 case Hexagon::L4_ploadrht_rr:
2342 case Hexagon::L4_ploadrhf_rr:
2343 case Hexagon::L4_ploadrhtnew_rr:
2344 case Hexagon::L4_ploadrhfnew_rr:
2345 case Hexagon::L2_ploadrhtnew_pi:
2346 case Hexagon::L2_ploadrhfnew_pi:
2347 case Hexagon::L4_ploadrht_abs:
2348 case Hexagon::L4_ploadrhf_abs:
2349 case Hexagon::L4_ploadrhtnew_abs:
2350 case Hexagon::L4_ploadrhfnew_abs:
2351 case Hexagon::L2_loadrhgp:
2358 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2359 const uint64_t F = MI.getDesc().TSFlags;
2360 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2363 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2364 switch (MI.getOpcode()) {
2365 case Hexagon::STriw_pred :
2366 case Hexagon::LDriw_pred :
2373 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2377 for (auto &Op : MI.operands())
2378 if (Op.isGlobal() || Op.isSymbol())
2383 // Returns true when SU has a timing class TC1.
2384 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2385 unsigned SchedClass = MI.getDesc().getSchedClass();
2386 return is_TC1(SchedClass);
2389 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2390 unsigned SchedClass = MI.getDesc().getSchedClass();
2391 return is_TC2(SchedClass);
2394 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2395 unsigned SchedClass = MI.getDesc().getSchedClass();
2396 return is_TC2early(SchedClass);
2399 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2400 unsigned SchedClass = MI.getDesc().getSchedClass();
2401 return is_TC4x(SchedClass);
2404 // Schedule this ASAP.
2405 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2406 const MachineInstr &MI2) const {
2407 if (mayBeCurLoad(MI1)) {
2408 // if (result of SU is used in Next) return true;
2409 unsigned DstReg = MI1.getOperand(0).getReg();
2410 int N = MI2.getNumOperands();
2411 for (int I = 0; I < N; I++)
2412 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2415 if (mayBeNewStore(MI2))
2416 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2417 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2418 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2423 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2424 const uint64_t V = getType(MI);
2425 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2428 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2430 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2431 if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2432 VT == MVT::v32i16 || VT == MVT::v64i8) {
2433 return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2434 Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2435 (Offset & 0x3f) == 0);
2438 if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2439 VT == MVT::v64i16 || VT == MVT::v128i8) {
2440 return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2441 Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2442 (Offset & 0x7f) == 0);
2444 if (VT == MVT::i64) {
2445 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2446 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2447 (Offset & 0x7) == 0);
2449 if (VT == MVT::i32) {
2450 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2451 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2452 (Offset & 0x3) == 0);
2454 if (VT == MVT::i16) {
2455 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2456 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2457 (Offset & 0x1) == 0);
2459 if (VT == MVT::i8) {
2460 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2461 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2463 llvm_unreachable("Not an auto-inc opc!");
2466 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2467 bool Extend) const {
2468 // This function is to check whether the "Offset" is in the correct range of
2469 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2470 // inserted to calculate the final address. Due to this reason, the function
2471 // assumes that the "Offset" has correct alignment.
2472 // We used to assert if the offset was not properly aligned, however,
2473 // there are cases where a misaligned pointer recast can cause this
2474 // problem, and we need to allow for it. The front end warns of such
2475 // misaligns with respect to load size.
2478 case Hexagon::PS_vstorerq_ai:
2479 case Hexagon::PS_vstorerw_ai:
2480 case Hexagon::PS_vstorerw_nt_ai:
2481 case Hexagon::PS_vloadrq_ai:
2482 case Hexagon::PS_vloadrw_ai:
2483 case Hexagon::PS_vloadrw_nt_ai:
2484 case Hexagon::V6_vL32b_ai:
2485 case Hexagon::V6_vS32b_ai:
2486 case Hexagon::V6_vL32b_nt_ai:
2487 case Hexagon::V6_vS32b_nt_ai:
2488 case Hexagon::V6_vL32Ub_ai:
2489 case Hexagon::V6_vS32Ub_ai:
2490 return isShiftedInt<4,6>(Offset);
2492 case Hexagon::PS_vstorerq_ai_128B:
2493 case Hexagon::PS_vstorerw_ai_128B:
2494 case Hexagon::PS_vstorerw_nt_ai_128B:
2495 case Hexagon::PS_vloadrq_ai_128B:
2496 case Hexagon::PS_vloadrw_ai_128B:
2497 case Hexagon::PS_vloadrw_nt_ai_128B:
2498 case Hexagon::V6_vL32b_ai_128B:
2499 case Hexagon::V6_vS32b_ai_128B:
2500 case Hexagon::V6_vL32b_nt_ai_128B:
2501 case Hexagon::V6_vS32b_nt_ai_128B:
2502 case Hexagon::V6_vL32Ub_ai_128B:
2503 case Hexagon::V6_vS32Ub_ai_128B:
2504 return isShiftedInt<4,7>(Offset);
2506 case Hexagon::J2_loop0i:
2507 case Hexagon::J2_loop1i:
2508 return isUInt<10>(Offset);
2510 case Hexagon::S4_storeirb_io:
2511 case Hexagon::S4_storeirbt_io:
2512 case Hexagon::S4_storeirbf_io:
2513 return isUInt<6>(Offset);
2515 case Hexagon::S4_storeirh_io:
2516 case Hexagon::S4_storeirht_io:
2517 case Hexagon::S4_storeirhf_io:
2518 return isShiftedUInt<6,1>(Offset);
2520 case Hexagon::S4_storeiri_io:
2521 case Hexagon::S4_storeirit_io:
2522 case Hexagon::S4_storeirif_io:
2523 return isShiftedUInt<6,2>(Offset);
2530 case Hexagon::L2_loadri_io:
2531 case Hexagon::S2_storeri_io:
2532 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2533 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2535 case Hexagon::L2_loadrd_io:
2536 case Hexagon::S2_storerd_io:
2537 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2538 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2540 case Hexagon::L2_loadrh_io:
2541 case Hexagon::L2_loadruh_io:
2542 case Hexagon::S2_storerh_io:
2543 case Hexagon::S2_storerf_io:
2544 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2545 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2547 case Hexagon::L2_loadrb_io:
2548 case Hexagon::L2_loadrub_io:
2549 case Hexagon::S2_storerb_io:
2550 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2551 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2553 case Hexagon::A2_addi:
2554 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2555 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2557 case Hexagon::L4_iadd_memopw_io :
2558 case Hexagon::L4_isub_memopw_io :
2559 case Hexagon::L4_add_memopw_io :
2560 case Hexagon::L4_sub_memopw_io :
2561 case Hexagon::L4_and_memopw_io :
2562 case Hexagon::L4_or_memopw_io :
2563 return (0 <= Offset && Offset <= 255);
2565 case Hexagon::L4_iadd_memoph_io :
2566 case Hexagon::L4_isub_memoph_io :
2567 case Hexagon::L4_add_memoph_io :
2568 case Hexagon::L4_sub_memoph_io :
2569 case Hexagon::L4_and_memoph_io :
2570 case Hexagon::L4_or_memoph_io :
2571 return (0 <= Offset && Offset <= 127);
2573 case Hexagon::L4_iadd_memopb_io :
2574 case Hexagon::L4_isub_memopb_io :
2575 case Hexagon::L4_add_memopb_io :
2576 case Hexagon::L4_sub_memopb_io :
2577 case Hexagon::L4_and_memopb_io :
2578 case Hexagon::L4_or_memopb_io :
2579 return (0 <= Offset && Offset <= 63);
2581 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2582 // any size. Later pass knows how to handle it.
2583 case Hexagon::STriw_pred:
2584 case Hexagon::LDriw_pred:
2585 case Hexagon::STriw_mod:
2586 case Hexagon::LDriw_mod:
2589 case Hexagon::PS_fi:
2590 case Hexagon::PS_fia:
2591 case Hexagon::INLINEASM:
2594 case Hexagon::L2_ploadrbt_io:
2595 case Hexagon::L2_ploadrbf_io:
2596 case Hexagon::L2_ploadrubt_io:
2597 case Hexagon::L2_ploadrubf_io:
2598 case Hexagon::S2_pstorerbt_io:
2599 case Hexagon::S2_pstorerbf_io:
2600 return isUInt<6>(Offset);
2602 case Hexagon::L2_ploadrht_io:
2603 case Hexagon::L2_ploadrhf_io:
2604 case Hexagon::L2_ploadruht_io:
2605 case Hexagon::L2_ploadruhf_io:
2606 case Hexagon::S2_pstorerht_io:
2607 case Hexagon::S2_pstorerhf_io:
2608 return isShiftedUInt<6,1>(Offset);
2610 case Hexagon::L2_ploadrit_io:
2611 case Hexagon::L2_ploadrif_io:
2612 case Hexagon::S2_pstorerit_io:
2613 case Hexagon::S2_pstorerif_io:
2614 return isShiftedUInt<6,2>(Offset);
2616 case Hexagon::L2_ploadrdt_io:
2617 case Hexagon::L2_ploadrdf_io:
2618 case Hexagon::S2_pstorerdt_io:
2619 case Hexagon::S2_pstorerdf_io:
2620 return isShiftedUInt<6,3>(Offset);
2623 llvm_unreachable("No offset range is defined for this opcode. "
2624 "Please define it in the above switch statement!");
2627 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2628 return isHVXVec(MI) && isAccumulator(MI);
2631 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2632 const uint64_t F = get(MI.getOpcode()).TSFlags;
2633 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2635 V == HexagonII::TypeCVI_VA ||
2636 V == HexagonII::TypeCVI_VA_DV;
2639 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2640 const MachineInstr &ConsMI) const {
2641 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2644 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2647 if (mayBeNewStore(ConsMI))
2653 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2654 switch (MI.getOpcode()) {
2656 case Hexagon::L2_loadrub_io:
2657 case Hexagon::L4_loadrub_ur:
2658 case Hexagon::L4_loadrub_ap:
2659 case Hexagon::L2_loadrub_pr:
2660 case Hexagon::L2_loadrub_pbr:
2661 case Hexagon::L2_loadrub_pi:
2662 case Hexagon::L2_loadrub_pci:
2663 case Hexagon::L2_loadrub_pcr:
2664 case Hexagon::L2_loadbzw2_io:
2665 case Hexagon::L4_loadbzw2_ur:
2666 case Hexagon::L4_loadbzw2_ap:
2667 case Hexagon::L2_loadbzw2_pr:
2668 case Hexagon::L2_loadbzw2_pbr:
2669 case Hexagon::L2_loadbzw2_pi:
2670 case Hexagon::L2_loadbzw2_pci:
2671 case Hexagon::L2_loadbzw2_pcr:
2672 case Hexagon::L2_loadbzw4_io:
2673 case Hexagon::L4_loadbzw4_ur:
2674 case Hexagon::L4_loadbzw4_ap:
2675 case Hexagon::L2_loadbzw4_pr:
2676 case Hexagon::L2_loadbzw4_pbr:
2677 case Hexagon::L2_loadbzw4_pi:
2678 case Hexagon::L2_loadbzw4_pci:
2679 case Hexagon::L2_loadbzw4_pcr:
2680 case Hexagon::L4_loadrub_rr:
2681 case Hexagon::L2_ploadrubt_io:
2682 case Hexagon::L2_ploadrubt_pi:
2683 case Hexagon::L2_ploadrubf_io:
2684 case Hexagon::L2_ploadrubf_pi:
2685 case Hexagon::L2_ploadrubtnew_io:
2686 case Hexagon::L2_ploadrubfnew_io:
2687 case Hexagon::L4_ploadrubt_rr:
2688 case Hexagon::L4_ploadrubf_rr:
2689 case Hexagon::L4_ploadrubtnew_rr:
2690 case Hexagon::L4_ploadrubfnew_rr:
2691 case Hexagon::L2_ploadrubtnew_pi:
2692 case Hexagon::L2_ploadrubfnew_pi:
2693 case Hexagon::L4_ploadrubt_abs:
2694 case Hexagon::L4_ploadrubf_abs:
2695 case Hexagon::L4_ploadrubtnew_abs:
2696 case Hexagon::L4_ploadrubfnew_abs:
2697 case Hexagon::L2_loadrubgp:
2699 case Hexagon::L2_loadruh_io:
2700 case Hexagon::L4_loadruh_ur:
2701 case Hexagon::L4_loadruh_ap:
2702 case Hexagon::L2_loadruh_pr:
2703 case Hexagon::L2_loadruh_pbr:
2704 case Hexagon::L2_loadruh_pi:
2705 case Hexagon::L2_loadruh_pci:
2706 case Hexagon::L2_loadruh_pcr:
2707 case Hexagon::L4_loadruh_rr:
2708 case Hexagon::L2_ploadruht_io:
2709 case Hexagon::L2_ploadruht_pi:
2710 case Hexagon::L2_ploadruhf_io:
2711 case Hexagon::L2_ploadruhf_pi:
2712 case Hexagon::L2_ploadruhtnew_io:
2713 case Hexagon::L2_ploadruhfnew_io:
2714 case Hexagon::L4_ploadruht_rr:
2715 case Hexagon::L4_ploadruhf_rr:
2716 case Hexagon::L4_ploadruhtnew_rr:
2717 case Hexagon::L4_ploadruhfnew_rr:
2718 case Hexagon::L2_ploadruhtnew_pi:
2719 case Hexagon::L2_ploadruhfnew_pi:
2720 case Hexagon::L4_ploadruht_abs:
2721 case Hexagon::L4_ploadruhf_abs:
2722 case Hexagon::L4_ploadruhtnew_abs:
2723 case Hexagon::L4_ploadruhfnew_abs:
2724 case Hexagon::L2_loadruhgp:
2731 // Add latency to instruction.
2732 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
2733 const MachineInstr &MI2) const {
2734 if (isHVXVec(MI1) && isHVXVec(MI2))
2735 if (!isVecUsableNextPacket(MI1, MI2))
2740 /// \brief Get the base register and byte offset of a load/store instr.
2741 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt,
2742 unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
2744 unsigned AccessSize = 0;
2746 BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
2748 return BaseReg != 0;
2751 /// \brief Can these instructions execute at the same time in a bundle.
2752 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
2753 const MachineInstr &Second) const {
2754 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2755 const MachineOperand &Op = Second.getOperand(0);
2756 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2759 if (DisableNVSchedule)
2761 if (mayBeNewStore(Second)) {
2762 // Make sure the definition of the first instruction is the value being
2764 const MachineOperand &Stored =
2765 Second.getOperand(Second.getNumOperands() - 1);
2766 if (!Stored.isReg())
2768 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2769 const MachineOperand &Op = First.getOperand(i);
2770 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2777 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
2778 unsigned Opc = CallMI.getOpcode();
2779 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2782 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2789 // Returns true if an instruction can be converted into a non-extended
2790 // equivalent instruction.
2791 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
2793 // Check if the instruction has a register form that uses register in place
2794 // of the extended operand, if so return that as the non-extended form.
2795 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2798 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2799 // Check addressing mode and retrieve non-ext equivalent instruction.
2801 switch (getAddrMode(MI)) {
2802 case HexagonII::Absolute :
2803 // Load/store with absolute addressing mode can be converted into
2804 // base+offset mode.
2805 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
2807 case HexagonII::BaseImmOffset :
2808 // Load/store with base+offset addressing mode can be converted into
2809 // base+register offset addressing mode. However left shift operand should
2811 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
2813 case HexagonII::BaseLongOffset:
2814 NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
2819 if (NonExtOpcode < 0)
2826 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
2827 return Hexagon::getRealHWInstr(MI.getOpcode(),
2828 Hexagon::InstrType_Pseudo) >= 0;
2831 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
2833 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
2842 // Returns true, if a LD insn can be promoted to a cur load.
2843 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
2844 auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
2845 const uint64_t F = MI.getDesc().TSFlags;
2846 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
2850 // Returns true, if a ST insn can be promoted to a new-value store.
2851 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
2852 const uint64_t F = MI.getDesc().TSFlags;
2853 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
2856 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
2857 const MachineInstr &ConsMI) const {
2858 // There is no stall when ProdMI is not a V60 vector.
2859 if (!isHVXVec(ProdMI))
2862 // There is no stall when ProdMI and ConsMI are not dependent.
2863 if (!isDependent(ProdMI, ConsMI))
2866 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2867 // are scheduled in consecutive packets.
2868 if (isVecUsableNextPacket(ProdMI, ConsMI))
2874 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
2875 MachineBasicBlock::const_instr_iterator BII) const {
2876 // There is no stall when I is not a V60 vector.
2880 MachineBasicBlock::const_instr_iterator MII = BII;
2881 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
2883 if (!(*MII).isBundle()) {
2884 const MachineInstr &J = *MII;
2885 return producesStall(J, MI);
2888 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
2889 const MachineInstr &J = *MII;
2890 if (producesStall(J, MI))
2896 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
2897 unsigned PredReg) const {
2898 for (const MachineOperand &MO : MI.operands()) {
2899 // Predicate register must be explicitly defined.
2900 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
2902 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
2906 // Hexagon Programmer's Reference says that decbin, memw_locked, and
2907 // memd_locked cannot be used as .new as well,
2908 // but we don't seem to have these instructions defined.
2909 return MI.getOpcode() != Hexagon::A4_tlbmatch;
2912 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
2913 return Opcode == Hexagon::J2_jumpt ||
2914 Opcode == Hexagon::J2_jumptpt ||
2915 Opcode == Hexagon::J2_jumpf ||
2916 Opcode == Hexagon::J2_jumpfpt ||
2917 Opcode == Hexagon::J2_jumptnew ||
2918 Opcode == Hexagon::J2_jumpfnew ||
2919 Opcode == Hexagon::J2_jumptnewpt ||
2920 Opcode == Hexagon::J2_jumpfnewpt;
2923 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
2924 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
2926 return !isPredicatedTrue(Cond[0].getImm());
2929 short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const {
2930 return Hexagon::getAbsoluteForm(MI.getOpcode());
2933 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
2934 const uint64_t F = MI.getDesc().TSFlags;
2935 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
2938 // Returns the base register in a memory access (load/store). The offset is
2939 // returned in Offset and the access size is returned in AccessSize.
2940 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
2941 int &Offset, unsigned &AccessSize) const {
2942 // Return if it is not a base+offset type instruction or a MemOp.
2943 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
2944 getAddrMode(MI) != HexagonII::BaseLongOffset &&
2945 !isMemOp(MI) && !isPostIncrement(MI))
2948 // Since it is a memory access instruction, getMemAccessSize() should never
2950 assert (getMemAccessSize(MI) &&
2951 "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
2953 // Return Values of getMemAccessSize() are
2954 // 0 - Checked in the assert above.
2955 // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
2956 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
2957 AccessSize = (1U << (getMemAccessSize(MI) - 1));
2959 unsigned basePos = 0, offsetPos = 0;
2960 if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
2963 // Post increment updates its EA after the mem access,
2964 // so we need to treat its offset as zero.
2965 if (isPostIncrement(MI))
2968 Offset = MI.getOperand(offsetPos).getImm();
2971 return MI.getOperand(basePos).getReg();
2974 /// Return the position of the base and offset operands for this instruction.
2975 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
2976 unsigned &BasePos, unsigned &OffsetPos) const {
2977 // Deal with memops first.
2981 } else if (MI.mayStore()) {
2984 } else if (MI.mayLoad()) {
2990 if (isPredicated(MI)) {
2994 if (isPostIncrement(MI)) {
2999 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3005 // Inserts branching instructions in reverse order of their occurrence.
3006 // e.g. jump_t t1 (i1)
3008 // Jumpers = {i2, i1}
3009 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3010 MachineBasicBlock& MBB) const {
3011 SmallVector<MachineInstr*, 2> Jumpers;
3012 // If the block has no terminators, it just falls into the block after it.
3013 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3014 if (I == MBB.instr_begin())
3017 // A basic block may looks like this:
3027 // It has two succs but does not have a terminator
3028 // Don't know how to handle it.
3033 } while (I != MBB.instr_begin());
3035 I = MBB.instr_end();
3038 while (I->isDebugValue()) {
3039 if (I == MBB.instr_begin())
3043 if (!isUnpredicatedTerminator(*I))
3046 // Get the last instruction in the block.
3047 MachineInstr *LastInst = &*I;
3048 Jumpers.push_back(LastInst);
3049 MachineInstr *SecondLastInst = nullptr;
3050 // Find one more terminator if present.
3052 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3053 if (!SecondLastInst) {
3054 SecondLastInst = &*I;
3055 Jumpers.push_back(SecondLastInst);
3056 } else // This is a third branch.
3059 if (I == MBB.instr_begin())
3066 short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
3069 return Hexagon::getBaseWithLongOffset(Opcode);
3072 short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const {
3073 return Hexagon::getBaseWithLongOffset(MI.getOpcode());
3076 short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const {
3077 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
3080 // Returns Operand Index for the constant extended instruction.
3081 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3082 const uint64_t F = MI.getDesc().TSFlags;
3083 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3086 // See if instruction could potentially be a duplex candidate.
3087 // If so, return its group. Zero otherwise.
3088 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3089 const MachineInstr &MI) const {
3090 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3092 switch (MI.getOpcode()) {
3094 return HexagonII::HCG_None;
3097 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3098 // "Rd16=#U6 ; jump #r9:2"
3099 // "Rd16=Rs16 ; jump #r9:2"
3101 case Hexagon::C2_cmpeq:
3102 case Hexagon::C2_cmpgt:
3103 case Hexagon::C2_cmpgtu:
3104 DstReg = MI.getOperand(0).getReg();
3105 Src1Reg = MI.getOperand(1).getReg();
3106 Src2Reg = MI.getOperand(2).getReg();
3107 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3108 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3109 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3110 return HexagonII::HCG_A;
3112 case Hexagon::C2_cmpeqi:
3113 case Hexagon::C2_cmpgti:
3114 case Hexagon::C2_cmpgtui:
3115 // P0 = cmp.eq(Rs,#u2)
3116 DstReg = MI.getOperand(0).getReg();
3117 SrcReg = MI.getOperand(1).getReg();
3118 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3119 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3120 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3121 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3122 (MI.getOperand(2).getImm() == -1)))
3123 return HexagonII::HCG_A;
3125 case Hexagon::A2_tfr:
3127 DstReg = MI.getOperand(0).getReg();
3128 SrcReg = MI.getOperand(1).getReg();
3129 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3130 return HexagonII::HCG_A;
3132 case Hexagon::A2_tfrsi:
3134 // Do not test for #u6 size since the const is getting extended
3135 // regardless and compound could be formed.
3136 DstReg = MI.getOperand(0).getReg();
3137 if (isIntRegForSubInst(DstReg))
3138 return HexagonII::HCG_A;
3140 case Hexagon::S2_tstbit_i:
3141 DstReg = MI.getOperand(0).getReg();
3142 Src1Reg = MI.getOperand(1).getReg();
3143 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3144 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3145 MI.getOperand(2).isImm() &&
3146 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3147 return HexagonII::HCG_A;
3149 // The fact that .new form is used pretty much guarantees
3150 // that predicate register will match. Nevertheless,
3151 // there could be some false positives without additional
3153 case Hexagon::J2_jumptnew:
3154 case Hexagon::J2_jumpfnew:
3155 case Hexagon::J2_jumptnewpt:
3156 case Hexagon::J2_jumpfnewpt:
3157 Src1Reg = MI.getOperand(0).getReg();
3158 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3159 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3160 return HexagonII::HCG_B;
3162 // Transfer and jump:
3163 // Rd=#U6 ; jump #r9:2
3164 // Rd=Rs ; jump #r9:2
3165 // Do not test for jump range here.
3166 case Hexagon::J2_jump:
3167 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3168 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3169 return HexagonII::HCG_C;
3173 return HexagonII::HCG_None;
3176 // Returns -1 when there is no opcode found.
3177 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3178 const MachineInstr &GB) const {
3179 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3180 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3181 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3182 (GB.getOpcode() != Hexagon::J2_jumptnew))
3184 unsigned DestReg = GA.getOperand(0).getReg();
3185 if (!GB.readsRegister(DestReg))
3187 if (DestReg == Hexagon::P0)
3188 return Hexagon::J4_cmpeqi_tp0_jump_nt;
3189 if (DestReg == Hexagon::P1)
3190 return Hexagon::J4_cmpeqi_tp1_jump_nt;
3194 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3195 enum Hexagon::PredSense inPredSense;
3196 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3197 Hexagon::PredSense_true;
3198 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3199 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3202 llvm_unreachable("Unexpected predicable instruction");
3205 // Return the cur value instruction for a given store.
3206 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3207 switch (MI.getOpcode()) {
3208 default: llvm_unreachable("Unknown .cur type");
3209 case Hexagon::V6_vL32b_pi:
3210 return Hexagon::V6_vL32b_cur_pi;
3211 case Hexagon::V6_vL32b_ai:
3212 return Hexagon::V6_vL32b_cur_ai;
3213 case Hexagon::V6_vL32b_nt_pi:
3214 return Hexagon::V6_vL32b_nt_cur_pi;
3215 case Hexagon::V6_vL32b_nt_ai:
3216 return Hexagon::V6_vL32b_nt_cur_ai;
3218 case Hexagon::V6_vL32b_pi_128B:
3219 return Hexagon::V6_vL32b_cur_pi_128B;
3220 case Hexagon::V6_vL32b_ai_128B:
3221 return Hexagon::V6_vL32b_cur_ai_128B;
3222 case Hexagon::V6_vL32b_nt_pi_128B:
3223 return Hexagon::V6_vL32b_nt_cur_pi_128B;
3224 case Hexagon::V6_vL32b_nt_ai_128B:
3225 return Hexagon::V6_vL32b_nt_cur_ai_128B;
3230 // Return the regular version of the .cur instruction.
3231 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3232 switch (MI.getOpcode()) {
3233 default: llvm_unreachable("Unknown .cur type");
3234 case Hexagon::V6_vL32b_cur_pi:
3235 return Hexagon::V6_vL32b_pi;
3236 case Hexagon::V6_vL32b_cur_ai:
3237 return Hexagon::V6_vL32b_ai;
3238 case Hexagon::V6_vL32b_nt_cur_pi:
3239 return Hexagon::V6_vL32b_nt_pi;
3240 case Hexagon::V6_vL32b_nt_cur_ai:
3241 return Hexagon::V6_vL32b_nt_ai;
3243 case Hexagon::V6_vL32b_cur_pi_128B:
3244 return Hexagon::V6_vL32b_pi_128B;
3245 case Hexagon::V6_vL32b_cur_ai_128B:
3246 return Hexagon::V6_vL32b_ai_128B;
3247 case Hexagon::V6_vL32b_nt_cur_pi_128B:
3248 return Hexagon::V6_vL32b_nt_pi_128B;
3249 case Hexagon::V6_vL32b_nt_cur_ai_128B:
3250 return Hexagon::V6_vL32b_nt_ai_128B;
3256 // The diagram below shows the steps involved in the conversion of a predicated
3257 // store instruction to its .new predicated new-value form.
3259 // Note: It doesn't include conditional new-value stores as they can't be
3260 // converted to .new predicate.
3262 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3264 // / \ (not OK. it will cause new-value store to be
3265 // / X conditional on p0.new while R2 producer is
3268 // p.new store p.old NV store
3269 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3275 // [if (p0)memw(R0+#0)=R2]
3277 // The following set of instructions further explains the scenario where
3278 // conditional new-value store becomes invalid when promoted to .new predicate
3281 // { 1) if (p0) r0 = add(r1, r2)
3282 // 2) p0 = cmp.eq(r3, #0) }
3284 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3285 // the first two instructions because in instr 1, r0 is conditional on old value
3286 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3287 // is not valid for new-value stores.
3288 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3289 // from the "Conditional Store" list. Because a predicated new value store
3290 // would NOT be promoted to a double dot new store. See diagram below:
3291 // This function returns yes for those stores that are predicated but not
3292 // yet promoted to predicate dot new instructions.
3294 // +---------------------+
3295 // /-----| if (p0) memw(..)=r0 |---------\~
3296 // || +---------------------+ ||
3297 // promote || /\ /\ || promote
3299 // \||/ demote || \||/
3301 // +-------------------------+ || +-------------------------+
3302 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3303 // +-------------------------+ || +-------------------------+
3306 // promote || \/ NOT possible
3310 // +-----------------------------+
3311 // | if (p0.new) memw(..)=r0.new |
3312 // +-----------------------------+
3313 // Double Dot New Store
3315 // Returns the most basic instruction for the .new predicated instructions and
3316 // new-value stores.
3317 // For example, all of the following instructions will be converted back to the
3318 // same instruction:
3319 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3320 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3321 // 3) if (p0.new) memw(R0+#0) = R1 --->
3323 // To understand the translation of instruction 1 to its original form, consider
3324 // a packet with 3 instructions.
3325 // { p0 = cmp.eq(R0,R1)
3326 // if (p0.new) R2 = add(R3, R4)
3327 // R5 = add (R3, R1)
3329 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3331 // This instruction can be part of the previous packet only if both p0 and R2
3332 // are promoted to .new values. This promotion happens in steps, first
3333 // predicate register is promoted to .new and in the next iteration R2 is
3334 // promoted. Therefore, in case of dependence check failure (due to R5) during
3335 // next iteration, it should be converted back to its most basic form.
3337 // Return the new value instruction for a given store.
3338 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3339 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3340 if (NVOpcode >= 0) // Valid new-value store instruction.
3343 switch (MI.getOpcode()) {
3345 llvm::report_fatal_error(std::string("Unknown .new type: ") +
3346 std::to_string(MI.getOpcode()).c_str());
3347 case Hexagon::S4_storerb_ur:
3348 return Hexagon::S4_storerbnew_ur;
3350 case Hexagon::S2_storerb_pci:
3351 return Hexagon::S2_storerb_pci;
3353 case Hexagon::S2_storeri_pci:
3354 return Hexagon::S2_storeri_pci;
3356 case Hexagon::S2_storerh_pci:
3357 return Hexagon::S2_storerh_pci;
3359 case Hexagon::S2_storerd_pci:
3360 return Hexagon::S2_storerd_pci;
3362 case Hexagon::S2_storerf_pci:
3363 return Hexagon::S2_storerf_pci;
3365 case Hexagon::V6_vS32b_ai:
3366 return Hexagon::V6_vS32b_new_ai;
3368 case Hexagon::V6_vS32b_pi:
3369 return Hexagon::V6_vS32b_new_pi;
3372 case Hexagon::V6_vS32b_ai_128B:
3373 return Hexagon::V6_vS32b_new_ai_128B;
3375 case Hexagon::V6_vS32b_pi_128B:
3376 return Hexagon::V6_vS32b_new_pi_128B;
3381 // Returns the opcode to use when converting MI, which is a conditional jump,
3382 // into a conditional instruction which uses the .new value of the predicate.
3383 // We also use branch probabilities to add a hint to the jump.
3384 // If MBPI is null, all edges will be treated as equally likely for the
3385 // purposes of establishing a predication hint.
3386 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3387 const MachineBranchProbabilityInfo *MBPI) const {
3388 // We assume that block can have at most two successors.
3389 const MachineBasicBlock *Src = MI.getParent();
3390 const MachineOperand &BrTarget = MI.getOperand(1);
3392 const BranchProbability OneHalf(1, 2);
3394 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3395 const MachineBasicBlock *Dst) {
3397 return MBPI->getEdgeProbability(Src, Dst);
3398 return BranchProbability(1, Src->succ_size());
3401 if (BrTarget.isMBB()) {
3402 const MachineBasicBlock *Dst = BrTarget.getMBB();
3403 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3405 // The branch target is not a basic block (most likely a function).
3406 // Since BPI only gives probabilities for targets that are basic blocks,
3407 // try to identify another target of this branch (potentially a fall-
3408 // -through) and check the probability of that target.
3410 // The only handled branch combinations are:
3411 // - one conditional branch,
3412 // - one conditional branch followed by one unconditional branch.
3413 // Otherwise, assume not-taken.
3414 assert(MI.isConditionalBranch());
3415 const MachineBasicBlock &B = *MI.getParent();
3416 bool SawCond = false, Bad = false;
3417 for (const MachineInstr &I : B) {
3420 if (I.isConditionalBranch()) {
3427 if (I.isUnconditionalBranch() && !SawCond) {
3433 MachineBasicBlock::const_instr_iterator It(MI);
3434 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3435 if (NextIt == B.instr_end()) {
3436 // If this branch is the last, look for the fall-through block.
3437 for (const MachineBasicBlock *SB : B.successors()) {
3438 if (!B.isLayoutSuccessor(SB))
3440 Taken = getEdgeProbability(Src, SB) < OneHalf;
3444 assert(NextIt->isUnconditionalBranch());
3445 // Find the first MBB operand and assume it's the target.
3446 const MachineBasicBlock *BT = nullptr;
3447 for (const MachineOperand &Op : NextIt->operands()) {
3453 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3458 // The Taken flag should be set to something reasonable by this point.
3460 switch (MI.getOpcode()) {
3461 case Hexagon::J2_jumpt:
3462 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3463 case Hexagon::J2_jumpf:
3464 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3467 llvm_unreachable("Unexpected jump instruction.");
3471 // Return .new predicate version for an instruction.
3472 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3473 const MachineBranchProbabilityInfo *MBPI) const {
3474 switch (MI.getOpcode()) {
3476 case Hexagon::J2_jumpt:
3477 case Hexagon::J2_jumpf:
3478 return getDotNewPredJumpOp(MI, MBPI);
3481 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3487 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3488 const MachineFunction &MF = *MI.getParent()->getParent();
3489 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
3490 int NewOp = MI.getOpcode();
3491 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3492 NewOp = Hexagon::getPredOldOpcode(NewOp);
3493 // All Hexagon architectures have prediction bits on dot-new branches,
3494 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3495 // to pick the right opcode when converting back to dot-old.
3496 if (!HST.getFeatureBits()[Hexagon::ArchV60]) {
3498 case Hexagon::J2_jumptpt:
3499 NewOp = Hexagon::J2_jumpt;
3501 case Hexagon::J2_jumpfpt:
3502 NewOp = Hexagon::J2_jumpf;
3504 case Hexagon::J2_jumprtpt:
3505 NewOp = Hexagon::J2_jumprt;
3507 case Hexagon::J2_jumprfpt:
3508 NewOp = Hexagon::J2_jumprf;
3512 assert(NewOp >= 0 &&
3513 "Couldn't change predicate new instruction to its old form.");
3516 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3517 NewOp = Hexagon::getNonNVStore(NewOp);
3518 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3521 if (HST.hasV60TOps())
3524 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3526 case Hexagon::J2_jumpfpt:
3527 return Hexagon::J2_jumpf;
3528 case Hexagon::J2_jumptpt:
3529 return Hexagon::J2_jumpt;
3530 case Hexagon::J2_jumprfpt:
3531 return Hexagon::J2_jumprf;
3532 case Hexagon::J2_jumprtpt:
3533 return Hexagon::J2_jumprt;
3538 // See if instruction could potentially be a duplex candidate.
3539 // If so, return its group. Zero otherwise.
3540 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3541 const MachineInstr &MI) const {
3542 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3543 auto &HRI = getRegisterInfo();
3545 switch (MI.getOpcode()) {
3547 return HexagonII::HSIG_None;
3551 // Rd = memw(Rs+#u4:2)
3552 // Rd = memub(Rs+#u4:0)
3553 case Hexagon::L2_loadri_io:
3554 DstReg = MI.getOperand(0).getReg();
3555 SrcReg = MI.getOperand(1).getReg();
3556 // Special case this one from Group L2.
3557 // Rd = memw(r29+#u5:2)
3558 if (isIntRegForSubInst(DstReg)) {
3559 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3560 HRI.getStackRegister() == SrcReg &&
3561 MI.getOperand(2).isImm() &&
3562 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3563 return HexagonII::HSIG_L2;
3564 // Rd = memw(Rs+#u4:2)
3565 if (isIntRegForSubInst(SrcReg) &&
3566 (MI.getOperand(2).isImm() &&
3567 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3568 return HexagonII::HSIG_L1;
3571 case Hexagon::L2_loadrub_io:
3572 // Rd = memub(Rs+#u4:0)
3573 DstReg = MI.getOperand(0).getReg();
3574 SrcReg = MI.getOperand(1).getReg();
3575 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3576 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3577 return HexagonII::HSIG_L1;
3582 // Rd = memh/memuh(Rs+#u3:1)
3583 // Rd = memb(Rs+#u3:0)
3584 // Rd = memw(r29+#u5:2) - Handled above.
3585 // Rdd = memd(r29+#u5:3)
3587 // [if ([!]p0[.new])] dealloc_return
3588 // [if ([!]p0[.new])] jumpr r31
3589 case Hexagon::L2_loadrh_io:
3590 case Hexagon::L2_loadruh_io:
3591 // Rd = memh/memuh(Rs+#u3:1)
3592 DstReg = MI.getOperand(0).getReg();
3593 SrcReg = MI.getOperand(1).getReg();
3594 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3595 MI.getOperand(2).isImm() &&
3596 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3597 return HexagonII::HSIG_L2;
3599 case Hexagon::L2_loadrb_io:
3600 // Rd = memb(Rs+#u3:0)
3601 DstReg = MI.getOperand(0).getReg();
3602 SrcReg = MI.getOperand(1).getReg();
3603 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3604 MI.getOperand(2).isImm() &&
3605 isUInt<3>(MI.getOperand(2).getImm()))
3606 return HexagonII::HSIG_L2;
3608 case Hexagon::L2_loadrd_io:
3609 // Rdd = memd(r29+#u5:3)
3610 DstReg = MI.getOperand(0).getReg();
3611 SrcReg = MI.getOperand(1).getReg();
3612 if (isDblRegForSubInst(DstReg, HRI) &&
3613 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3614 HRI.getStackRegister() == SrcReg &&
3615 MI.getOperand(2).isImm() &&
3616 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3617 return HexagonII::HSIG_L2;
3619 // dealloc_return is not documented in Hexagon Manual, but marked
3620 // with A_SUBINSN attribute in iset_v4classic.py.
3621 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3622 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3623 case Hexagon::L4_return:
3624 case Hexagon::L2_deallocframe:
3625 return HexagonII::HSIG_L2;
3626 case Hexagon::EH_RETURN_JMPR:
3627 case Hexagon::PS_jmpret:
3629 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3630 DstReg = MI.getOperand(0).getReg();
3631 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3632 return HexagonII::HSIG_L2;
3634 case Hexagon::PS_jmprett:
3635 case Hexagon::PS_jmpretf:
3636 case Hexagon::PS_jmprettnewpt:
3637 case Hexagon::PS_jmpretfnewpt:
3638 case Hexagon::PS_jmprettnew:
3639 case Hexagon::PS_jmpretfnew:
3640 DstReg = MI.getOperand(1).getReg();
3641 SrcReg = MI.getOperand(0).getReg();
3642 // [if ([!]p0[.new])] jumpr r31
3643 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3644 (Hexagon::P0 == SrcReg)) &&
3645 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3646 return HexagonII::HSIG_L2;
3648 case Hexagon::L4_return_t :
3649 case Hexagon::L4_return_f :
3650 case Hexagon::L4_return_tnew_pnt :
3651 case Hexagon::L4_return_fnew_pnt :
3652 case Hexagon::L4_return_tnew_pt :
3653 case Hexagon::L4_return_fnew_pt :
3654 // [if ([!]p0[.new])] dealloc_return
3655 SrcReg = MI.getOperand(0).getReg();
3656 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3657 return HexagonII::HSIG_L2;
3662 // memw(Rs+#u4:2) = Rt
3663 // memb(Rs+#u4:0) = Rt
3664 case Hexagon::S2_storeri_io:
3665 // Special case this one from Group S2.
3666 // memw(r29+#u5:2) = Rt
3667 Src1Reg = MI.getOperand(0).getReg();
3668 Src2Reg = MI.getOperand(2).getReg();
3669 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3670 isIntRegForSubInst(Src2Reg) &&
3671 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3672 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3673 return HexagonII::HSIG_S2;
3674 // memw(Rs+#u4:2) = Rt
3675 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3676 MI.getOperand(1).isImm() &&
3677 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3678 return HexagonII::HSIG_S1;
3680 case Hexagon::S2_storerb_io:
3681 // memb(Rs+#u4:0) = Rt
3682 Src1Reg = MI.getOperand(0).getReg();
3683 Src2Reg = MI.getOperand(2).getReg();
3684 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3685 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3686 return HexagonII::HSIG_S1;
3691 // memh(Rs+#u3:1) = Rt
3692 // memw(r29+#u5:2) = Rt
3693 // memd(r29+#s6:3) = Rtt
3694 // memw(Rs+#u4:2) = #U1
3695 // memb(Rs+#u4) = #U1
3696 // allocframe(#u5:3)
3697 case Hexagon::S2_storerh_io:
3698 // memh(Rs+#u3:1) = Rt
3699 Src1Reg = MI.getOperand(0).getReg();
3700 Src2Reg = MI.getOperand(2).getReg();
3701 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3702 MI.getOperand(1).isImm() &&
3703 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3704 return HexagonII::HSIG_S1;
3706 case Hexagon::S2_storerd_io:
3707 // memd(r29+#s6:3) = Rtt
3708 Src1Reg = MI.getOperand(0).getReg();
3709 Src2Reg = MI.getOperand(2).getReg();
3710 if (isDblRegForSubInst(Src2Reg, HRI) &&
3711 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3712 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3713 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3714 return HexagonII::HSIG_S2;
3716 case Hexagon::S4_storeiri_io:
3717 // memw(Rs+#u4:2) = #U1
3718 Src1Reg = MI.getOperand(0).getReg();
3719 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3720 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3721 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3722 return HexagonII::HSIG_S2;
3724 case Hexagon::S4_storeirb_io:
3725 // memb(Rs+#u4) = #U1
3726 Src1Reg = MI.getOperand(0).getReg();
3727 if (isIntRegForSubInst(Src1Reg) &&
3728 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3729 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3730 return HexagonII::HSIG_S2;
3732 case Hexagon::S2_allocframe:
3733 if (MI.getOperand(0).isImm() &&
3734 isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
3735 return HexagonII::HSIG_S1;
3744 // if ([!]P0[.new]) Rd = #0
3745 // Rd = add(r29,#u6:2)
3747 // P0 = cmp.eq(Rs,#u2)
3748 // Rdd = combine(#0,Rs)
3749 // Rdd = combine(Rs,#0)
3750 // Rdd = combine(#u2,#U2)
3753 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3755 case Hexagon::A2_addi:
3756 DstReg = MI.getOperand(0).getReg();
3757 SrcReg = MI.getOperand(1).getReg();
3758 if (isIntRegForSubInst(DstReg)) {
3759 // Rd = add(r29,#u6:2)
3760 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3761 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3762 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3763 return HexagonII::HSIG_A;
3765 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3766 isInt<7>(MI.getOperand(2).getImm()))
3767 return HexagonII::HSIG_A;
3770 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3771 ((MI.getOperand(2).getImm() == 1) ||
3772 (MI.getOperand(2).getImm() == -1)))
3773 return HexagonII::HSIG_A;
3776 case Hexagon::A2_add:
3778 DstReg = MI.getOperand(0).getReg();
3779 Src1Reg = MI.getOperand(1).getReg();
3780 Src2Reg = MI.getOperand(2).getReg();
3781 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3782 isIntRegForSubInst(Src2Reg))
3783 return HexagonII::HSIG_A;
3785 case Hexagon::A2_andir:
3787 // Rd16=and(Rs16,#255)
3788 // Rd16=and(Rs16,#1)
3789 DstReg = MI.getOperand(0).getReg();
3790 SrcReg = MI.getOperand(1).getReg();
3791 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3792 MI.getOperand(2).isImm() &&
3793 ((MI.getOperand(2).getImm() == 1) ||
3794 (MI.getOperand(2).getImm() == 255)))
3795 return HexagonII::HSIG_A;
3797 case Hexagon::A2_tfr:
3799 DstReg = MI.getOperand(0).getReg();
3800 SrcReg = MI.getOperand(1).getReg();
3801 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3802 return HexagonII::HSIG_A;
3804 case Hexagon::A2_tfrsi:
3806 // Do not test for #u6 size since the const is getting extended
3807 // regardless and compound could be formed.
3809 DstReg = MI.getOperand(0).getReg();
3810 if (isIntRegForSubInst(DstReg))
3811 return HexagonII::HSIG_A;
3813 case Hexagon::C2_cmoveit:
3814 case Hexagon::C2_cmovenewit:
3815 case Hexagon::C2_cmoveif:
3816 case Hexagon::C2_cmovenewif:
3817 // if ([!]P0[.new]) Rd = #0
3819 // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3820 DstReg = MI.getOperand(0).getReg();
3821 SrcReg = MI.getOperand(1).getReg();
3822 if (isIntRegForSubInst(DstReg) &&
3823 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3824 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
3825 return HexagonII::HSIG_A;
3827 case Hexagon::C2_cmpeqi:
3828 // P0 = cmp.eq(Rs,#u2)
3829 DstReg = MI.getOperand(0).getReg();
3830 SrcReg = MI.getOperand(1).getReg();
3831 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3832 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3833 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
3834 return HexagonII::HSIG_A;
3836 case Hexagon::A2_combineii:
3837 case Hexagon::A4_combineii:
3838 // Rdd = combine(#u2,#U2)
3839 DstReg = MI.getOperand(0).getReg();
3840 if (isDblRegForSubInst(DstReg, HRI) &&
3841 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
3842 (MI.getOperand(1).isGlobal() &&
3843 isUInt<2>(MI.getOperand(1).getOffset()))) &&
3844 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
3845 (MI.getOperand(2).isGlobal() &&
3846 isUInt<2>(MI.getOperand(2).getOffset()))))
3847 return HexagonII::HSIG_A;
3849 case Hexagon::A4_combineri:
3850 // Rdd = combine(Rs,#0)
3851 DstReg = MI.getOperand(0).getReg();
3852 SrcReg = MI.getOperand(1).getReg();
3853 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3854 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
3855 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
3856 return HexagonII::HSIG_A;
3858 case Hexagon::A4_combineir:
3859 // Rdd = combine(#0,Rs)
3860 DstReg = MI.getOperand(0).getReg();
3861 SrcReg = MI.getOperand(2).getReg();
3862 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3863 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
3864 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
3865 return HexagonII::HSIG_A;
3867 case Hexagon::A2_sxtb:
3868 case Hexagon::A2_sxth:
3869 case Hexagon::A2_zxtb:
3870 case Hexagon::A2_zxth:
3871 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3872 DstReg = MI.getOperand(0).getReg();
3873 SrcReg = MI.getOperand(1).getReg();
3874 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3875 return HexagonII::HSIG_A;
3879 return HexagonII::HSIG_None;
3882 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
3883 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
3886 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
3887 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
3888 // Default to one cycle for no itinerary. However, an "empty" itinerary may
3889 // still have a MinLatency property, which getStageLatency checks.
3891 return getInstrLatency(ItinData, MI);
3893 if (MI.isTransient())
3895 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
3898 /// getOperandLatency - Compute and return the use operand latency of a given
3899 /// pair of def and use.
3900 /// In most cases, the static scheduling itinerary was enough to determine the
3901 /// operand latency. But it may not be possible for instructions with variable
3902 /// number of defs / uses.
3904 /// This is a raw interface to the itinerary that may be directly overriden by
3905 /// a target. Use computeOperandLatency to get the best estimate of latency.
3906 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3907 const MachineInstr &DefMI,
3909 const MachineInstr &UseMI,
3910 unsigned UseIdx) const {
3911 auto &RI = getRegisterInfo();
3912 // Get DefIdx and UseIdx for super registers.
3913 MachineOperand DefMO = DefMI.getOperand(DefIdx);
3915 if (RI.isPhysicalRegister(DefMO.getReg())) {
3916 if (DefMO.isImplicit()) {
3917 for (MCSuperRegIterator SR(DefMO.getReg(), &RI); SR.isValid(); ++SR) {
3918 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &RI);
3926 MachineOperand UseMO = UseMI.getOperand(UseIdx);
3927 if (UseMO.isImplicit()) {
3928 for (MCSuperRegIterator SR(UseMO.getReg(), &RI); SR.isValid(); ++SR) {
3929 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &RI);
3938 return TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
3942 // inverts the predication logic.
3945 bool HexagonInstrInfo::getInvertedPredSense(
3946 SmallVectorImpl<MachineOperand> &Cond) const {
3949 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3950 Cond[0].setImm(Opc);
3954 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3956 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3957 : Hexagon::getTruePredOpcode(Opc);
3958 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
3959 return InvPredOpcode;
3961 llvm_unreachable("Unexpected predicated instruction");
3964 // Returns the max value that doesn't need to be extended.
3965 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
3966 const uint64_t F = MI.getDesc().TSFlags;
3967 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3968 & HexagonII::ExtentSignedMask;
3969 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3970 & HexagonII::ExtentBitsMask;
3972 if (isSigned) // if value is signed
3973 return ~(-1U << (bits - 1));
3975 return ~(-1U << bits);
3978 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
3979 const uint64_t F = MI.getDesc().TSFlags;
3980 return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
3983 // Returns the min value that doesn't need to be extended.
3984 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
3985 const uint64_t F = MI.getDesc().TSFlags;
3986 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3987 & HexagonII::ExtentSignedMask;
3988 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3989 & HexagonII::ExtentBitsMask;
3991 if (isSigned) // if value is signed
3992 return -1U << (bits - 1);
3997 // Returns opcode of the non-extended equivalent instruction.
3998 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
3999 // Check if the instruction has a register form that uses register in place
4000 // of the extended operand, if so return that as the non-extended form.
4001 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4002 if (NonExtOpcode >= 0)
4003 return NonExtOpcode;
4005 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4006 // Check addressing mode and retrieve non-ext equivalent instruction.
4007 switch (getAddrMode(MI)) {
4008 case HexagonII::Absolute :
4009 return Hexagon::getBaseWithImmOffset(MI.getOpcode());
4010 case HexagonII::BaseImmOffset :
4011 return Hexagon::getBaseWithRegOffset(MI.getOpcode());
4012 case HexagonII::BaseLongOffset:
4013 return Hexagon::getRegShlForm(MI.getOpcode());
4022 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4023 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4026 assert(Cond.size() == 2);
4027 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4028 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4031 PredReg = Cond[1].getReg();
4033 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4035 if (Cond[1].isImplicit())
4036 PredRegFlags = RegState::Implicit;
4037 if (Cond[1].isUndef())
4038 PredRegFlags |= RegState::Undef;
4042 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4043 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4046 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4047 return Hexagon::getRegForm(MI.getOpcode());
4050 // Return the number of bytes required to encode the instruction.
4051 // Hexagon instructions are fixed length, 4 bytes, unless they
4052 // use a constant extender, which requires another 4 bytes.
4053 // For debug instructions and prolog labels, return 0.
4054 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4055 if (MI.isDebugValue() || MI.isPosition())
4058 unsigned Size = MI.getDesc().getSize();
4060 // Assume the default insn size in case it cannot be determined
4061 // for whatever reason.
4062 Size = HEXAGON_INSTR_SIZE;
4064 if (isConstExtended(MI) || isExtended(MI))
4065 Size += HEXAGON_INSTR_SIZE;
4067 // Try and compute number of instructions in asm.
4068 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4069 const MachineBasicBlock &MBB = *MI.getParent();
4070 const MachineFunction *MF = MBB.getParent();
4071 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4073 // Count the number of register definitions to find the asm string.
4074 unsigned NumDefs = 0;
4075 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4077 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4079 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4080 // Disassemble the AsmStr and approximate number of instructions.
4081 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4082 Size = getInlineAsmLength(AsmStr, *MAI);
4088 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4089 const uint64_t F = MI.getDesc().TSFlags;
4090 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4093 unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4094 const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
4095 const InstrItineraryData &II = *ST.getInstrItineraryData();
4096 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4098 return IS.getUnits();
4101 // Calculate size of the basic block without debug instructions.
4102 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4103 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4106 unsigned HexagonInstrInfo::nonDbgBundleSize(
4107 MachineBasicBlock::const_iterator BundleHead) const {
4108 assert(BundleHead->isBundle() && "Not a bundle header");
4109 auto MII = BundleHead.getInstrIterator();
4110 // Skip the bundle header.
4111 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4114 /// immediateExtend - Changes the instruction in place to one using an immediate
4116 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4117 assert((isExtendable(MI)||isConstExtended(MI)) &&
4118 "Instruction must be extendable");
4119 // Find which operand is extendable.
4120 short ExtOpNum = getCExtOpNum(MI);
4121 MachineOperand &MO = MI.getOperand(ExtOpNum);
4122 // This needs to be something we understand.
4123 assert((MO.isMBB() || MO.isImm()) &&
4124 "Branch with unknown extendable field type");
4125 // Mark given operand as extended.
4126 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4129 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4130 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4131 DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
4132 << NewTarget->getNumber(); MI.dump(););
4133 assert(MI.isBranch());
4134 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4135 int TargetPos = MI.getNumOperands() - 1;
4136 // In general branch target is the last operand,
4137 // but some implicit defs added at the end might change it.
4138 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4140 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4141 MI.getOperand(TargetPos).setMBB(NewTarget);
4142 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4143 NewOpcode = reversePrediction(NewOpcode);
4145 MI.setDesc(get(NewOpcode));
4149 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4150 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4151 MachineFunction::iterator A = MF.begin();
4152 MachineBasicBlock &B = *A;
4153 MachineBasicBlock::iterator I = B.begin();
4154 DebugLoc DL = I->getDebugLoc();
4155 MachineInstr *NewMI;
4157 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4158 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4159 NewMI = BuildMI(B, I, DL, get(insn));
4160 DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
4161 " Class: " << NewMI->getDesc().getSchedClass());
4162 NewMI->eraseFromParent();
4164 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4167 // inverts the predication logic.
4170 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4171 DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4172 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4176 // Reverse the branch prediction.
4177 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4178 int PredRevOpcode = -1;
4179 if (isPredictedTaken(Opcode))
4180 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4182 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4183 assert(PredRevOpcode > 0);
4184 return PredRevOpcode;
4187 // TODO: Add more rigorous validation.
4188 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4190 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4193 short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const {
4194 return Hexagon::xformRegToImmOffset(MI.getOpcode());