1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
17 #include "MCTargetDesc/HexagonBaseInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/Support/MachineValueType.h"
27 #define GET_INSTRINFO_HEADER
28 #include "HexagonGenInstrInfo.inc"
32 class HexagonSubtarget;
33 class MachineBranchProbabilityInfo;
34 class MachineFunction;
37 class TargetRegisterInfo;
39 class HexagonInstrInfo : public HexagonGenInstrInfo {
40 const HexagonSubtarget &Subtarget;
42 enum BundleAttribute {
43 memShufDisabledMask = 0x4
46 virtual void anchor();
49 explicit HexagonInstrInfo(HexagonSubtarget &ST);
51 /// TargetInstrInfo overrides.
53 /// If the specified machine instruction is a direct
54 /// load from a stack slot, return the virtual or physical register number of
55 /// the destination along with the FrameIndex of the loaded stack slot. If
56 /// not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than loading from the stack slot.
58 unsigned isLoadFromStackSlot(const MachineInstr &MI,
59 int &FrameIndex) const override;
61 /// If the specified machine instruction is a direct
62 /// store to a stack slot, return the virtual or physical register number of
63 /// the source reg along with the FrameIndex of the loaded stack slot. If
64 /// not, return 0. This predicate must return 0 if the instruction has
65 /// any side effects other than storing to the stack slot.
66 unsigned isStoreToStackSlot(const MachineInstr &MI,
67 int &FrameIndex) const override;
69 /// Check if the instruction or the bundle of instructions has
70 /// load from stack slots. Return the frameindex and machine memory operand
72 bool hasLoadFromStackSlot(
73 const MachineInstr &MI,
74 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
76 /// Check if the instruction or the bundle of instructions has
77 /// store to stack slots. Return the frameindex and machine memory operand
79 bool hasStoreToStackSlot(
80 const MachineInstr &MI,
81 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
83 /// Analyze the branching code at the end of MBB, returning
84 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
85 /// implemented for a target). Upon success, this returns false and returns
86 /// with the following information in various cases:
88 /// 1. If this block ends with no branches (it just falls through to its succ)
89 /// just return false, leaving TBB/FBB null.
90 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
91 /// the destination block.
92 /// 3. If this block ends with a conditional branch and it falls through to a
93 /// successor block, it sets TBB to be the branch destination block and a
94 /// list of operands that evaluate the condition. These operands can be
95 /// passed to other TargetInstrInfo methods to create new branches.
96 /// 4. If this block ends with a conditional branch followed by an
97 /// unconditional branch, it returns the 'true' destination in TBB, the
98 /// 'false' destination in FBB, and a list of operands that evaluate the
99 /// condition. These operands can be passed to other TargetInstrInfo
100 /// methods to create new branches.
102 /// Note that removeBranch and insertBranch must be implemented to support
103 /// cases where this method returns success.
105 /// If AllowModify is true, then this routine is allowed to modify the basic
106 /// block (e.g. delete instructions after the unconditional branch).
107 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
108 MachineBasicBlock *&FBB,
109 SmallVectorImpl<MachineOperand> &Cond,
110 bool AllowModify) const override;
112 /// Remove the branching code at the end of the specific MBB.
113 /// This is only invoked in cases where AnalyzeBranch returns success. It
114 /// returns the number of instructions that were removed.
115 unsigned removeBranch(MachineBasicBlock &MBB,
116 int *BytesRemoved = nullptr) const override;
118 /// Insert branch code into the end of the specified MachineBasicBlock.
119 /// The operands to this method are the same as those
120 /// returned by AnalyzeBranch. This is only invoked in cases where
121 /// AnalyzeBranch returns success. It returns the number of instructions
124 /// It is also invoked by tail merging to add unconditional branches in
125 /// cases where AnalyzeBranch doesn't apply because there was no original
126 /// branch to analyze. At least this much must be implemented, else tail
127 /// merging needs to be disabled.
128 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
129 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
131 int *BytesAdded = nullptr) const override;
133 /// Analyze the loop code, return true if it cannot be understood. Upon
134 /// success, this function returns false and returns information about the
135 /// induction variable and compare instruction used at the end.
136 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
137 MachineInstr *&CmpInst) const override;
139 /// Generate code to reduce the loop iteration by one and check if the loop
140 /// is finished. Return the value/register of the new loop count. We need
141 /// this function when peeling off one or more iterations of a loop. This
142 /// function assumes the nth iteration is peeled first.
143 unsigned reduceLoopCount(MachineBasicBlock &MBB,
144 MachineInstr *IndVar, MachineInstr &Cmp,
145 SmallVectorImpl<MachineOperand> &Cond,
146 SmallVectorImpl<MachineInstr *> &PrevInsts,
147 unsigned Iter, unsigned MaxIter) const override;
149 /// Return true if it's profitable to predicate
150 /// instructions with accumulated instruction latency of "NumCycles"
151 /// of the specified basic block, where the probability of the instructions
152 /// being executed is given by Probability, and Confidence is a measure
153 /// of our confidence that it will be properly predicted.
154 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
155 unsigned ExtraPredCycles,
156 BranchProbability Probability) const override;
158 /// Second variant of isProfitableToIfCvt. This one
159 /// checks for the case where two basic blocks from true and false path
160 /// of a if-then-else (diamond) are predicated on mutally exclusive
161 /// predicates, where the probability of the true path being taken is given
162 /// by Probability, and Confidence is a measure of our confidence that it
163 /// will be properly predicted.
164 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
165 unsigned NumTCycles, unsigned ExtraTCycles,
166 MachineBasicBlock &FMBB,
167 unsigned NumFCycles, unsigned ExtraFCycles,
168 BranchProbability Probability) const override;
170 /// Return true if it's profitable for if-converter to duplicate instructions
171 /// of specified accumulated instruction latencies in the specified MBB to
172 /// enable if-conversion.
173 /// The probability of the instructions being executed is given by
174 /// Probability, and Confidence is a measure of our confidence that it
175 /// will be properly predicted.
176 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
177 BranchProbability Probability) const override;
179 /// Emit instructions to copy a pair of physical registers.
181 /// This function should support copies within any legal register class as
182 /// well as any cross-class copies created during instruction selection.
184 /// The source and destination registers may overlap, which may require a
185 /// careful implementation when multiple copy instructions are required for
186 /// large registers. See for example the ARM target.
187 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
188 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
189 bool KillSrc) const override;
191 /// Store the specified register of the given register class to the specified
192 /// stack frame index. The store instruction is to be added to the given
193 /// machine basic block before the specified machine instruction. If isKill
194 /// is true, the register operand is the last use and must be marked kill.
195 void storeRegToStackSlot(MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator MBBI,
197 unsigned SrcReg, bool isKill, int FrameIndex,
198 const TargetRegisterClass *RC,
199 const TargetRegisterInfo *TRI) const override;
201 /// Load the specified register of the given register class from the specified
202 /// stack frame index. The load instruction is to be added to the given
203 /// machine basic block before the specified machine instruction.
204 void loadRegFromStackSlot(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MBBI,
206 unsigned DestReg, int FrameIndex,
207 const TargetRegisterClass *RC,
208 const TargetRegisterInfo *TRI) const override;
210 /// This function is called for all pseudo instructions
211 /// that remain after register allocation. Many pseudo instructions are
212 /// created to help register allocation. This is the place to convert them
213 /// into real instructions. The target can edit MI in place, or it can insert
214 /// new instructions and erase MI. The function should return true if
215 /// anything was changed.
216 bool expandPostRAPseudo(MachineInstr &MI) const override;
218 /// Get the base register and byte offset of a load/store instr.
219 bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
221 const TargetRegisterInfo *TRI) const override;
223 /// Reverses the branch condition of the specified condition list,
224 /// returning false on success and true if it cannot be reversed.
225 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
228 /// Insert a noop into the instruction stream at the specified point.
229 void insertNoop(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator MI) const override;
232 /// Returns true if the instruction is already predicated.
233 bool isPredicated(const MachineInstr &MI) const override;
235 /// Return true for post-incremented instructions.
236 bool isPostIncrement(const MachineInstr &MI) const override;
238 /// Convert the instruction into a predicated instruction.
239 /// It returns true if the operation was successful.
240 bool PredicateInstruction(MachineInstr &MI,
241 ArrayRef<MachineOperand> Cond) const override;
243 /// Returns true if the first specified predicate
244 /// subsumes the second, e.g. GE subsumes GT.
245 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
246 ArrayRef<MachineOperand> Pred2) const override;
248 /// If the specified instruction defines any predicate
249 /// or condition code register(s) used for predication, returns true as well
250 /// as the definition predicate(s) by reference.
251 bool DefinesPredicate(MachineInstr &MI,
252 std::vector<MachineOperand> &Pred) const override;
254 /// Return true if the specified instruction can be predicated.
255 /// By default, this returns true for every instruction with a
256 /// PredicateOperand.
257 bool isPredicable(const MachineInstr &MI) const override;
259 /// Test if the given instruction should be considered a scheduling boundary.
260 /// This primarily includes labels and terminators.
261 bool isSchedulingBoundary(const MachineInstr &MI,
262 const MachineBasicBlock *MBB,
263 const MachineFunction &MF) const override;
265 /// Measure the specified inline asm to determine an approximation of its
267 unsigned getInlineAsmLength(const char *Str,
268 const MCAsmInfo &MAI) const override;
270 /// Allocate and return a hazard recognizer to use for this target when
271 /// scheduling the machine instructions after register allocation.
272 ScheduleHazardRecognizer*
273 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
274 const ScheduleDAG *DAG) const override;
276 /// For a comparison instruction, return the source registers
277 /// in SrcReg and SrcReg2 if having two register operands, and the value it
278 /// compares against in CmpValue. Return true if the comparison instruction
280 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
281 unsigned &SrcReg2, int &Mask, int &Value) const override;
283 /// Compute the instruction latency of a given instruction.
284 /// If the instruction has higher cost when predicated, it's returned via
286 unsigned getInstrLatency(const InstrItineraryData *ItinData,
287 const MachineInstr &MI,
288 unsigned *PredCost = nullptr) const override;
290 /// Create machine specific model for scheduling.
292 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
294 // Sometimes, it is possible for the target
295 // to tell, even without aliasing information, that two MIs access different
296 // memory addresses. This function returns true if two MIs access different
297 // memory addresses and false otherwise.
299 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
300 AliasAnalysis *AA = nullptr) const override;
302 /// For instructions with a base and offset, return the position of the
303 /// base register and offset operands.
304 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
305 unsigned &OffsetPos) const override;
307 /// If the instruction is an increment of a constant value, return the amount.
308 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
310 /// getOperandLatency - Compute and return the use operand latency of a given
311 /// pair of def and use.
312 /// In most cases, the static scheduling itinerary was enough to determine the
313 /// operand latency. But it may not be possible for instructions with variable
314 /// number of defs / uses.
316 /// This is a raw interface to the itinerary that may be directly overriden by
317 /// a target. Use computeOperandLatency to get the best estimate of latency.
318 int getOperandLatency(const InstrItineraryData *ItinData,
319 const MachineInstr &DefMI, unsigned DefIdx,
320 const MachineInstr &UseMI,
321 unsigned UseIdx) const override;
323 /// Decompose the machine operand's target flags into two values - the direct
324 /// target flag value and any of bit flags that are applied.
325 std::pair<unsigned, unsigned>
326 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
328 /// Return an array that contains the direct target flag values and their
331 /// MIR Serialization is able to serialize only the target flags that are
332 /// defined by this method.
333 ArrayRef<std::pair<unsigned, const char *>>
334 getSerializableDirectMachineOperandTargetFlags() const override;
336 /// Return an array that contains the bitmask target flag values and their
339 /// MIR Serialization is able to serialize only the target flags that are
340 /// defined by this method.
341 ArrayRef<std::pair<unsigned, const char *>>
342 getSerializableBitmaskMachineOperandTargetFlags() const override;
344 bool isTailCall(const MachineInstr &MI) const override;
346 /// HexagonInstrInfo specifics.
348 unsigned createVR(MachineFunction *MF, MVT VT) const;
349 MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
350 MachineBasicBlock *TargetBB,
351 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
353 bool isBaseImmOffset(const MachineInstr &MI) const;
354 bool isAbsoluteSet(const MachineInstr &MI) const;
355 bool isAccumulator(const MachineInstr &MI) const;
356 bool isAddrModeWithOffset(const MachineInstr &MI) const;
357 bool isComplex(const MachineInstr &MI) const;
358 bool isCompoundBranchInstr(const MachineInstr &MI) const;
359 bool isConstExtended(const MachineInstr &MI) const;
360 bool isDeallocRet(const MachineInstr &MI) const;
361 bool isDependent(const MachineInstr &ProdMI,
362 const MachineInstr &ConsMI) const;
363 bool isDotCurInst(const MachineInstr &MI) const;
364 bool isDotNewInst(const MachineInstr &MI) const;
365 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
366 bool isEarlySourceInstr(const MachineInstr &MI) const;
367 bool isEndLoopN(unsigned Opcode) const;
368 bool isExpr(unsigned OpType) const;
369 bool isExtendable(const MachineInstr &MI) const;
370 bool isExtended(const MachineInstr &MI) const;
371 bool isFloat(const MachineInstr &MI) const;
372 bool isHVXMemWithAIndirect(const MachineInstr &I,
373 const MachineInstr &J) const;
374 bool isIndirectCall(const MachineInstr &MI) const;
375 bool isIndirectL4Return(const MachineInstr &MI) const;
376 bool isJumpR(const MachineInstr &MI) const;
377 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
378 bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
379 const MachineInstr &ESMI) const;
380 bool isLateResultInstr(const MachineInstr &MI) const;
381 bool isLateSourceInstr(const MachineInstr &MI) const;
382 bool isLoopN(const MachineInstr &MI) const;
383 bool isMemOp(const MachineInstr &MI) const;
384 bool isNewValue(const MachineInstr &MI) const;
385 bool isNewValue(unsigned Opcode) const;
386 bool isNewValueInst(const MachineInstr &MI) const;
387 bool isNewValueJump(const MachineInstr &MI) const;
388 bool isNewValueJump(unsigned Opcode) const;
389 bool isNewValueStore(const MachineInstr &MI) const;
390 bool isNewValueStore(unsigned Opcode) const;
391 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
392 bool isPredicatedNew(const MachineInstr &MI) const;
393 bool isPredicatedNew(unsigned Opcode) const;
394 bool isPredicatedTrue(const MachineInstr &MI) const;
395 bool isPredicatedTrue(unsigned Opcode) const;
396 bool isPredicated(unsigned Opcode) const;
397 bool isPredicateLate(unsigned Opcode) const;
398 bool isPredictedTaken(unsigned Opcode) const;
399 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
400 bool isSignExtendingLoad(const MachineInstr &MI) const;
401 bool isSolo(const MachineInstr &MI) const;
402 bool isSpillPredRegOp(const MachineInstr &MI) const;
403 bool isTC1(const MachineInstr &MI) const;
404 bool isTC2(const MachineInstr &MI) const;
405 bool isTC2Early(const MachineInstr &MI) const;
406 bool isTC4x(const MachineInstr &MI) const;
407 bool isToBeScheduledASAP(const MachineInstr &MI1,
408 const MachineInstr &MI2) const;
409 bool isHVXVec(const MachineInstr &MI) const;
410 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
411 bool isValidOffset(unsigned Opcode, int Offset,
412 const TargetRegisterInfo *TRI, bool Extend = true) const;
413 bool isVecAcc(const MachineInstr &MI) const;
414 bool isVecALU(const MachineInstr &MI) const;
415 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
416 const MachineInstr &ConsMI) const;
417 bool isZeroExtendingLoad(const MachineInstr &MI) const;
419 bool addLatencyToSchedule(const MachineInstr &MI1,
420 const MachineInstr &MI2) const;
421 bool canExecuteInBundle(const MachineInstr &First,
422 const MachineInstr &Second) const;
423 bool doesNotReturn(const MachineInstr &CallMI) const;
424 bool hasEHLabel(const MachineBasicBlock *B) const;
425 bool hasNonExtEquivalent(const MachineInstr &MI) const;
426 bool hasPseudoInstrPair(const MachineInstr &MI) const;
427 bool hasUncondBranch(const MachineBasicBlock *B) const;
428 bool mayBeCurLoad(const MachineInstr &MI) const;
429 bool mayBeNewStore(const MachineInstr &MI) const;
430 bool producesStall(const MachineInstr &ProdMI,
431 const MachineInstr &ConsMI) const;
432 bool producesStall(const MachineInstr &MI,
433 MachineBasicBlock::const_instr_iterator MII) const;
434 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
435 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
436 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
438 unsigned getAddrMode(const MachineInstr &MI) const;
439 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
440 unsigned &AccessSize) const;
441 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
442 unsigned getCExtOpNum(const MachineInstr &MI) const;
443 HexagonII::CompoundGroup
444 getCompoundCandidateGroup(const MachineInstr &MI) const;
445 unsigned getCompoundOpcode(const MachineInstr &GA,
446 const MachineInstr &GB) const;
447 int getCondOpcode(int Opc, bool sense) const;
448 int getDotCurOp(const MachineInstr &MI) const;
449 int getNonDotCurOp(const MachineInstr &MI) const;
450 int getDotNewOp(const MachineInstr &MI) const;
451 int getDotNewPredJumpOp(const MachineInstr &MI,
452 const MachineBranchProbabilityInfo *MBPI) const;
453 int getDotNewPredOp(const MachineInstr &MI,
454 const MachineBranchProbabilityInfo *MBPI) const;
455 int getDotOldOp(const MachineInstr &MI) const;
456 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
458 short getEquivalentHWInstr(const MachineInstr &MI) const;
459 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
460 const MachineInstr &MI) const;
461 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
462 unsigned getInvertedPredicatedOpcode(const int Opc) const;
463 int getMaxValue(const MachineInstr &MI) const;
464 unsigned getMemAccessSize(const MachineInstr &MI) const;
465 int getMinValue(const MachineInstr &MI) const;
466 short getNonExtOpcode(const MachineInstr &MI) const;
467 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
468 unsigned &PredRegPos, unsigned &PredRegFlags) const;
469 short getPseudoInstrPair(const MachineInstr &MI) const;
470 short getRegForm(const MachineInstr &MI) const;
471 unsigned getSize(const MachineInstr &MI) const;
472 uint64_t getType(const MachineInstr &MI) const;
473 unsigned getUnits(const MachineInstr &MI) const;
475 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
477 /// getInstrTimingClassLatency - Compute the instruction latency of a given
478 /// instruction using Timing Class information, if available.
479 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
480 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
482 void immediateExtend(MachineInstr &MI) const;
483 bool invertAndChangeJumpTarget(MachineInstr &MI,
484 MachineBasicBlock *NewTarget) const;
485 void genAllInsnTimingClasses(MachineFunction &MF) const;
486 bool reversePredSense(MachineInstr &MI) const;
487 unsigned reversePrediction(unsigned Opcode) const;
488 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
490 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
491 bool getBundleNoShuf(const MachineInstr &MIB) const;
492 // Addressing mode relations.
493 short changeAddrMode_abs_io(short Opc) const;
494 short changeAddrMode_io_abs(short Opc) const;
495 short changeAddrMode_io_pi(short Opc) const;
496 short changeAddrMode_io_rr(short Opc) const;
497 short changeAddrMode_pi_io(short Opc) const;
498 short changeAddrMode_rr_io(short Opc) const;
499 short changeAddrMode_rr_ur(short Opc) const;
500 short changeAddrMode_ur_rr(short Opc) const;
502 short changeAddrMode_abs_io(const MachineInstr &MI) const {
503 return changeAddrMode_abs_io(MI.getOpcode());
505 short changeAddrMode_io_abs(const MachineInstr &MI) const {
506 return changeAddrMode_io_abs(MI.getOpcode());
508 short changeAddrMode_io_rr(const MachineInstr &MI) const {
509 return changeAddrMode_io_rr(MI.getOpcode());
511 short changeAddrMode_rr_io(const MachineInstr &MI) const {
512 return changeAddrMode_rr_io(MI.getOpcode());
514 short changeAddrMode_rr_ur(const MachineInstr &MI) const {
515 return changeAddrMode_rr_ur(MI.getOpcode());
517 short changeAddrMode_ur_rr(const MachineInstr &MI) const {
518 return changeAddrMode_ur_rr(MI.getOpcode());
522 } // end namespace llvm
524 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H