1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
17 #include "HexagonRegisterInfo.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
20 #include "llvm/Target/TargetFrameLowering.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "HexagonGenInstrInfo.inc"
29 class HexagonSubtarget;
31 class HexagonInstrInfo : public HexagonGenInstrInfo {
32 virtual void anchor();
33 const HexagonRegisterInfo RI;
36 explicit HexagonInstrInfo(HexagonSubtarget &ST);
38 /// TargetInstrInfo overrides.
41 /// If the specified machine instruction is a direct
42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
47 int &FrameIndex) const override;
49 /// If the specified machine instruction is a direct
50 /// store to a stack slot, return the virtual or physical register number of
51 /// the source reg along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than storing to the stack slot.
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
55 int &FrameIndex) const override;
57 /// Analyze the branching code at the end of MBB, returning
58 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
59 /// implemented for a target). Upon success, this returns false and returns
60 /// with the following information in various cases:
62 /// 1. If this block ends with no branches (it just falls through to its succ)
63 /// just return false, leaving TBB/FBB null.
64 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
65 /// the destination block.
66 /// 3. If this block ends with a conditional branch and it falls through to a
67 /// successor block, it sets TBB to be the branch destination block and a
68 /// list of operands that evaluate the condition. These operands can be
69 /// passed to other TargetInstrInfo methods to create new branches.
70 /// 4. If this block ends with a conditional branch followed by an
71 /// unconditional branch, it returns the 'true' destination in TBB, the
72 /// 'false' destination in FBB, and a list of operands that evaluate the
73 /// condition. These operands can be passed to other TargetInstrInfo
74 /// methods to create new branches.
76 /// Note that RemoveBranch and InsertBranch must be implemented to support
77 /// cases where this method returns success.
79 /// If AllowModify is true, then this routine is allowed to modify the basic
80 /// block (e.g. delete instructions after the unconditional branch).
82 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
83 MachineBasicBlock *&FBB,
84 SmallVectorImpl<MachineOperand> &Cond,
85 bool AllowModify) const override;
87 /// Remove the branching code at the end of the specific MBB.
88 /// This is only invoked in cases where AnalyzeBranch returns success. It
89 /// returns the number of instructions that were removed.
90 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
92 /// Insert branch code into the end of the specified MachineBasicBlock.
93 /// The operands to this method are the same as those
94 /// returned by AnalyzeBranch. This is only invoked in cases where
95 /// AnalyzeBranch returns success. It returns the number of instructions
98 /// It is also invoked by tail merging to add unconditional branches in
99 /// cases where AnalyzeBranch doesn't apply because there was no original
100 /// branch to analyze. At least this much must be implemented, else tail
101 /// merging needs to be disabled.
102 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
103 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
104 const DebugLoc &DL) const override;
106 /// Return true if it's profitable to predicate
107 /// instructions with accumulated instruction latency of "NumCycles"
108 /// of the specified basic block, where the probability of the instructions
109 /// being executed is given by Probability, and Confidence is a measure
110 /// of our confidence that it will be properly predicted.
111 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
112 unsigned ExtraPredCycles,
113 BranchProbability Probability) const override;
115 /// Second variant of isProfitableToIfCvt. This one
116 /// checks for the case where two basic blocks from true and false path
117 /// of a if-then-else (diamond) are predicated on mutally exclusive
118 /// predicates, where the probability of the true path being taken is given
119 /// by Probability, and Confidence is a measure of our confidence that it
120 /// will be properly predicted.
121 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
122 unsigned NumTCycles, unsigned ExtraTCycles,
123 MachineBasicBlock &FMBB,
124 unsigned NumFCycles, unsigned ExtraFCycles,
125 BranchProbability Probability) const override;
127 /// Return true if it's profitable for if-converter to duplicate instructions
128 /// of specified accumulated instruction latencies in the specified MBB to
129 /// enable if-conversion.
130 /// The probability of the instructions being executed is given by
131 /// Probability, and Confidence is a measure of our confidence that it
132 /// will be properly predicted.
133 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
134 BranchProbability Probability) const override;
136 /// Emit instructions to copy a pair of physical registers.
138 /// This function should support copies within any legal register class as
139 /// well as any cross-class copies created during instruction selection.
141 /// The source and destination registers may overlap, which may require a
142 /// careful implementation when multiple copy instructions are required for
143 /// large registers. See for example the ARM target.
144 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
145 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
146 bool KillSrc) const override;
148 /// Store the specified register of the given register class to the specified
149 /// stack frame index. The store instruction is to be added to the given
150 /// machine basic block before the specified machine instruction. If isKill
151 /// is true, the register operand is the last use and must be marked kill.
152 void storeRegToStackSlot(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator MBBI,
154 unsigned SrcReg, bool isKill, int FrameIndex,
155 const TargetRegisterClass *RC,
156 const TargetRegisterInfo *TRI) const override;
158 /// Load the specified register of the given register class from the specified
159 /// stack frame index. The load instruction is to be added to the given
160 /// machine basic block before the specified machine instruction.
161 void loadRegFromStackSlot(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator MBBI,
163 unsigned DestReg, int FrameIndex,
164 const TargetRegisterClass *RC,
165 const TargetRegisterInfo *TRI) const override;
167 /// This function is called for all pseudo instructions
168 /// that remain after register allocation. Many pseudo instructions are
169 /// created to help register allocation. This is the place to convert them
170 /// into real instructions. The target can edit MI in place, or it can insert
171 /// new instructions and erase MI. The function should return true if
172 /// anything was changed.
173 bool expandPostRAPseudo(MachineInstr &MI) const override;
175 /// Reverses the branch condition of the specified condition list,
176 /// returning false on success and true if it cannot be reversed.
177 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
180 /// Insert a noop into the instruction stream at the specified point.
181 void insertNoop(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MI) const override;
184 /// Returns true if the instruction is already predicated.
185 bool isPredicated(const MachineInstr &MI) const override;
187 /// Convert the instruction into a predicated instruction.
188 /// It returns true if the operation was successful.
189 bool PredicateInstruction(MachineInstr &MI,
190 ArrayRef<MachineOperand> Cond) const override;
192 /// Returns true if the first specified predicate
193 /// subsumes the second, e.g. GE subsumes GT.
194 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
195 ArrayRef<MachineOperand> Pred2) const override;
197 /// If the specified instruction defines any predicate
198 /// or condition code register(s) used for predication, returns true as well
199 /// as the definition predicate(s) by reference.
200 bool DefinesPredicate(MachineInstr &MI,
201 std::vector<MachineOperand> &Pred) const override;
203 /// Return true if the specified instruction can be predicated.
204 /// By default, this returns true for every instruction with a
205 /// PredicateOperand.
206 bool isPredicable(MachineInstr &MI) const override;
208 /// Test if the given instruction should be considered a scheduling boundary.
209 /// This primarily includes labels and terminators.
210 bool isSchedulingBoundary(const MachineInstr &MI,
211 const MachineBasicBlock *MBB,
212 const MachineFunction &MF) const override;
214 /// Measure the specified inline asm to determine an approximation of its
216 unsigned getInlineAsmLength(const char *Str,
217 const MCAsmInfo &MAI) const override;
219 /// Allocate and return a hazard recognizer to use for this target when
220 /// scheduling the machine instructions after register allocation.
221 ScheduleHazardRecognizer*
222 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
223 const ScheduleDAG *DAG) const override;
225 /// For a comparison instruction, return the source registers
226 /// in SrcReg and SrcReg2 if having two register operands, and the value it
227 /// compares against in CmpValue. Return true if the comparison instruction
229 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
230 unsigned &SrcReg2, int &Mask, int &Value) const override;
232 /// Compute the instruction latency of a given instruction.
233 /// If the instruction has higher cost when predicated, it's returned via
235 unsigned getInstrLatency(const InstrItineraryData *ItinData,
236 const MachineInstr &MI,
237 unsigned *PredCost = 0) const override;
239 /// Create machine specific model for scheduling.
241 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
243 // Sometimes, it is possible for the target
244 // to tell, even without aliasing information, that two MIs access different
245 // memory addresses. This function returns true if two MIs access different
246 // memory addresses and false otherwise.
248 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
249 AliasAnalysis *AA = nullptr) const override;
251 /// HexagonInstrInfo specifics.
254 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
256 unsigned createVR(MachineFunction* MF, MVT VT) const;
258 bool isAbsoluteSet(const MachineInstr* MI) const;
259 bool isAccumulator(const MachineInstr *MI) const;
260 bool isComplex(const MachineInstr *MI) const;
261 bool isCompoundBranchInstr(const MachineInstr *MI) const;
262 bool isCondInst(const MachineInstr *MI) const;
263 bool isConditionalALU32 (const MachineInstr* MI) const;
264 bool isConditionalLoad(const MachineInstr* MI) const;
265 bool isConditionalStore(const MachineInstr* MI) const;
266 bool isConditionalTransfer(const MachineInstr* MI) const;
267 bool isConstExtended(const MachineInstr *MI) const;
268 bool isDeallocRet(const MachineInstr *MI) const;
269 bool isDependent(const MachineInstr *ProdMI,
270 const MachineInstr *ConsMI) const;
271 bool isDotCurInst(const MachineInstr* MI) const;
272 bool isDotNewInst(const MachineInstr* MI) const;
273 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
274 bool isEarlySourceInstr(const MachineInstr *MI) const;
275 bool isEndLoopN(unsigned Opcode) const;
276 bool isExpr(unsigned OpType) const;
277 bool isExtendable(const MachineInstr* MI) const;
278 bool isExtended(const MachineInstr* MI) const;
279 bool isFloat(const MachineInstr *MI) const;
280 bool isHVXMemWithAIndirect(const MachineInstr *I,
281 const MachineInstr *J) const;
282 bool isIndirectCall(const MachineInstr *MI) const;
283 bool isIndirectL4Return(const MachineInstr *MI) const;
284 bool isJumpR(const MachineInstr *MI) const;
285 bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
286 bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
287 const MachineInstr *ESMI) const;
288 bool isLateResultInstr(const MachineInstr *MI) const;
289 bool isLateSourceInstr(const MachineInstr *MI) const;
290 bool isLoopN(const MachineInstr *MI) const;
291 bool isMemOp(const MachineInstr *MI) const;
292 bool isNewValue(const MachineInstr* MI) const;
293 bool isNewValue(unsigned Opcode) const;
294 bool isNewValueInst(const MachineInstr* MI) const;
295 bool isNewValueJump(const MachineInstr* MI) const;
296 bool isNewValueJump(unsigned Opcode) const;
297 bool isNewValueStore(const MachineInstr* MI) const;
298 bool isNewValueStore(unsigned Opcode) const;
299 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
300 bool isPostIncrement(const MachineInstr* MI) const;
301 bool isPredicatedNew(const MachineInstr &MI) const;
302 bool isPredicatedNew(unsigned Opcode) const;
303 bool isPredicatedTrue(const MachineInstr &MI) const;
304 bool isPredicatedTrue(unsigned Opcode) const;
305 bool isPredicated(unsigned Opcode) const;
306 bool isPredicateLate(unsigned Opcode) const;
307 bool isPredictedTaken(unsigned Opcode) const;
308 bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
309 bool isSignExtendingLoad(const MachineInstr &MI) const;
310 bool isSolo(const MachineInstr* MI) const;
311 bool isSpillPredRegOp(const MachineInstr *MI) const;
312 bool isTailCall(const MachineInstr *MI) const;
313 bool isTC1(const MachineInstr *MI) const;
314 bool isTC2(const MachineInstr *MI) const;
315 bool isTC2Early(const MachineInstr *MI) const;
316 bool isTC4x(const MachineInstr *MI) const;
317 bool isToBeScheduledASAP(const MachineInstr *MI1,
318 const MachineInstr *MI2) const;
319 bool isV60VectorInstruction(const MachineInstr *MI) const;
320 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
321 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
322 bool isVecAcc(const MachineInstr *MI) const;
323 bool isVecALU(const MachineInstr *MI) const;
324 bool isVecUsableNextPacket(const MachineInstr *ProdMI,
325 const MachineInstr *ConsMI) const;
326 bool isZeroExtendingLoad(const MachineInstr &MI) const;
328 bool addLatencyToSchedule(const MachineInstr *MI1,
329 const MachineInstr *MI2) const;
330 bool canExecuteInBundle(const MachineInstr *First,
331 const MachineInstr *Second) const;
332 bool hasEHLabel(const MachineBasicBlock *B) const;
333 bool hasNonExtEquivalent(const MachineInstr *MI) const;
334 bool hasPseudoInstrPair(const MachineInstr *MI) const;
335 bool hasUncondBranch(const MachineBasicBlock *B) const;
336 bool mayBeCurLoad(const MachineInstr* MI) const;
337 bool mayBeNewStore(const MachineInstr* MI) const;
338 bool producesStall(const MachineInstr *ProdMI,
339 const MachineInstr *ConsMI) const;
340 bool producesStall(const MachineInstr *MI,
341 MachineBasicBlock::const_instr_iterator MII) const;
342 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
343 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
344 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
347 short getAbsoluteForm(const MachineInstr *MI) const;
348 unsigned getAddrMode(const MachineInstr* MI) const;
349 unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
350 unsigned &AccessSize) const;
351 bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
352 unsigned &OffsetPos) const;
353 short getBaseWithLongOffset(short Opcode) const;
354 short getBaseWithLongOffset(const MachineInstr *MI) const;
355 short getBaseWithRegOffset(const MachineInstr *MI) const;
356 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
357 unsigned getCExtOpNum(const MachineInstr *MI) const;
358 HexagonII::CompoundGroup
359 getCompoundCandidateGroup(const MachineInstr *MI) const;
360 unsigned getCompoundOpcode(const MachineInstr *GA,
361 const MachineInstr *GB) const;
362 int getCondOpcode(int Opc, bool sense) const;
363 int getDotCurOp(const MachineInstr* MI) const;
364 int getDotNewOp(const MachineInstr* MI) const;
365 int getDotNewPredJumpOp(const MachineInstr *MI,
366 const MachineBranchProbabilityInfo *MBPI) const;
367 int getDotNewPredOp(const MachineInstr *MI,
368 const MachineBranchProbabilityInfo *MBPI) const;
369 int getDotOldOp(const int opc) const;
370 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
372 short getEquivalentHWInstr(const MachineInstr *MI) const;
373 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
374 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
375 const MachineInstr *MI) const;
376 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
377 unsigned getInvertedPredicatedOpcode(const int Opc) const;
378 int getMaxValue(const MachineInstr *MI) const;
379 unsigned getMemAccessSize(const MachineInstr* MI) const;
380 int getMinValue(const MachineInstr *MI) const;
381 short getNonExtOpcode(const MachineInstr *MI) const;
382 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
383 unsigned &PredRegPos, unsigned &PredRegFlags) const;
384 short getPseudoInstrPair(const MachineInstr *MI) const;
385 short getRegForm(const MachineInstr *MI) const;
386 unsigned getSize(const MachineInstr *MI) const;
387 uint64_t getType(const MachineInstr* MI) const;
388 unsigned getUnits(const MachineInstr* MI) const;
389 unsigned getValidSubTargets(const unsigned Opcode) const;
392 /// getInstrTimingClassLatency - Compute the instruction latency of a given
393 /// instruction using Timing Class information, if available.
394 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
395 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
398 void immediateExtend(MachineInstr *MI) const;
399 bool invertAndChangeJumpTarget(MachineInstr* MI,
400 MachineBasicBlock* NewTarget) const;
401 void genAllInsnTimingClasses(MachineFunction &MF) const;
402 bool reversePredSense(MachineInstr* MI) const;
403 unsigned reversePrediction(unsigned Opcode) const;
404 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
405 short xformRegToImmOffset(const MachineInstr *MI) const;