1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
17 #include "HexagonRegisterInfo.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
23 #include "llvm/CodeGen/MachineValueType.h"
24 #include "llvm/Target/TargetInstrInfo.h"
28 #define GET_INSTRINFO_HEADER
29 #include "HexagonGenInstrInfo.inc"
34 class HexagonSubtarget;
36 class HexagonInstrInfo : public HexagonGenInstrInfo {
37 const HexagonRegisterInfo RI;
39 virtual void anchor();
42 explicit HexagonInstrInfo(HexagonSubtarget &ST);
44 /// TargetInstrInfo overrides.
47 /// If the specified machine instruction is a direct
48 /// load from a stack slot, return the virtual or physical register number of
49 /// the destination along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than loading from the stack slot.
52 unsigned isLoadFromStackSlot(const MachineInstr &MI,
53 int &FrameIndex) const override;
55 /// If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 unsigned isStoreToStackSlot(const MachineInstr &MI,
61 int &FrameIndex) const override;
63 /// Analyze the branching code at the end of MBB, returning
64 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
65 /// implemented for a target). Upon success, this returns false and returns
66 /// with the following information in various cases:
68 /// 1. If this block ends with no branches (it just falls through to its succ)
69 /// just return false, leaving TBB/FBB null.
70 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
71 /// the destination block.
72 /// 3. If this block ends with a conditional branch and it falls through to a
73 /// successor block, it sets TBB to be the branch destination block and a
74 /// list of operands that evaluate the condition. These operands can be
75 /// passed to other TargetInstrInfo methods to create new branches.
76 /// 4. If this block ends with a conditional branch followed by an
77 /// unconditional branch, it returns the 'true' destination in TBB, the
78 /// 'false' destination in FBB, and a list of operands that evaluate the
79 /// condition. These operands can be passed to other TargetInstrInfo
80 /// methods to create new branches.
82 /// Note that removeBranch and insertBranch must be implemented to support
83 /// cases where this method returns success.
85 /// If AllowModify is true, then this routine is allowed to modify the basic
86 /// block (e.g. delete instructions after the unconditional branch).
88 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
89 MachineBasicBlock *&FBB,
90 SmallVectorImpl<MachineOperand> &Cond,
91 bool AllowModify) const override;
93 /// Remove the branching code at the end of the specific MBB.
94 /// This is only invoked in cases where AnalyzeBranch returns success. It
95 /// returns the number of instructions that were removed.
96 unsigned removeBranch(MachineBasicBlock &MBB,
97 int *BytesRemoved = nullptr) const override;
99 /// Insert branch code into the end of the specified MachineBasicBlock.
100 /// The operands to this method are the same as those
101 /// returned by AnalyzeBranch. This is only invoked in cases where
102 /// AnalyzeBranch returns success. It returns the number of instructions
105 /// It is also invoked by tail merging to add unconditional branches in
106 /// cases where AnalyzeBranch doesn't apply because there was no original
107 /// branch to analyze. At least this much must be implemented, else tail
108 /// merging needs to be disabled.
109 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
110 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
112 int *BytesAdded = nullptr) const override;
114 /// Analyze the loop code, return true if it cannot be understood. Upon
115 /// success, this function returns false and returns information about the
116 /// induction variable and compare instruction used at the end.
117 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
118 MachineInstr *&CmpInst) const override;
120 /// Generate code to reduce the loop iteration by one and check if the loop is
121 /// finished. Return the value/register of the the new loop count. We need
122 /// this function when peeling off one or more iterations of a loop. This
123 /// function assumes the nth iteration is peeled first.
124 unsigned reduceLoopCount(MachineBasicBlock &MBB,
125 MachineInstr *IndVar, MachineInstr &Cmp,
126 SmallVectorImpl<MachineOperand> &Cond,
127 SmallVectorImpl<MachineInstr *> &PrevInsts,
128 unsigned Iter, unsigned MaxIter) const override;
130 /// Return true if it's profitable to predicate
131 /// instructions with accumulated instruction latency of "NumCycles"
132 /// of the specified basic block, where the probability of the instructions
133 /// being executed is given by Probability, and Confidence is a measure
134 /// of our confidence that it will be properly predicted.
135 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
136 unsigned ExtraPredCycles,
137 BranchProbability Probability) const override;
139 /// Second variant of isProfitableToIfCvt. This one
140 /// checks for the case where two basic blocks from true and false path
141 /// of a if-then-else (diamond) are predicated on mutally exclusive
142 /// predicates, where the probability of the true path being taken is given
143 /// by Probability, and Confidence is a measure of our confidence that it
144 /// will be properly predicted.
145 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
146 unsigned NumTCycles, unsigned ExtraTCycles,
147 MachineBasicBlock &FMBB,
148 unsigned NumFCycles, unsigned ExtraFCycles,
149 BranchProbability Probability) const override;
151 /// Return true if it's profitable for if-converter to duplicate instructions
152 /// of specified accumulated instruction latencies in the specified MBB to
153 /// enable if-conversion.
154 /// The probability of the instructions being executed is given by
155 /// Probability, and Confidence is a measure of our confidence that it
156 /// will be properly predicted.
157 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
158 BranchProbability Probability) const override;
160 /// Emit instructions to copy a pair of physical registers.
162 /// This function should support copies within any legal register class as
163 /// well as any cross-class copies created during instruction selection.
165 /// The source and destination registers may overlap, which may require a
166 /// careful implementation when multiple copy instructions are required for
167 /// large registers. See for example the ARM target.
168 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
169 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
170 bool KillSrc) const override;
172 /// Store the specified register of the given register class to the specified
173 /// stack frame index. The store instruction is to be added to the given
174 /// machine basic block before the specified machine instruction. If isKill
175 /// is true, the register operand is the last use and must be marked kill.
176 void storeRegToStackSlot(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator MBBI,
178 unsigned SrcReg, bool isKill, int FrameIndex,
179 const TargetRegisterClass *RC,
180 const TargetRegisterInfo *TRI) const override;
182 /// Load the specified register of the given register class from the specified
183 /// stack frame index. The load instruction is to be added to the given
184 /// machine basic block before the specified machine instruction.
185 void loadRegFromStackSlot(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MBBI,
187 unsigned DestReg, int FrameIndex,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const override;
191 /// This function is called for all pseudo instructions
192 /// that remain after register allocation. Many pseudo instructions are
193 /// created to help register allocation. This is the place to convert them
194 /// into real instructions. The target can edit MI in place, or it can insert
195 /// new instructions and erase MI. The function should return true if
196 /// anything was changed.
197 bool expandPostRAPseudo(MachineInstr &MI) const override;
199 /// \brief Get the base register and byte offset of a load/store instr.
200 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
202 const TargetRegisterInfo *TRI) const override;
204 /// Reverses the branch condition of the specified condition list,
205 /// returning false on success and true if it cannot be reversed.
206 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
209 /// Insert a noop into the instruction stream at the specified point.
210 void insertNoop(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MI) const override;
213 /// Returns true if the instruction is already predicated.
214 bool isPredicated(const MachineInstr &MI) const override;
216 /// Return true for post-incremented instructions.
217 bool isPostIncrement(const MachineInstr &MI) const override;
219 /// Convert the instruction into a predicated instruction.
220 /// It returns true if the operation was successful.
221 bool PredicateInstruction(MachineInstr &MI,
222 ArrayRef<MachineOperand> Cond) const override;
224 /// Returns true if the first specified predicate
225 /// subsumes the second, e.g. GE subsumes GT.
226 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
227 ArrayRef<MachineOperand> Pred2) const override;
229 /// If the specified instruction defines any predicate
230 /// or condition code register(s) used for predication, returns true as well
231 /// as the definition predicate(s) by reference.
232 bool DefinesPredicate(MachineInstr &MI,
233 std::vector<MachineOperand> &Pred) const override;
235 /// Return true if the specified instruction can be predicated.
236 /// By default, this returns true for every instruction with a
237 /// PredicateOperand.
238 bool isPredicable(MachineInstr &MI) const override;
240 /// Test if the given instruction should be considered a scheduling boundary.
241 /// This primarily includes labels and terminators.
242 bool isSchedulingBoundary(const MachineInstr &MI,
243 const MachineBasicBlock *MBB,
244 const MachineFunction &MF) const override;
246 /// Measure the specified inline asm to determine an approximation of its
248 unsigned getInlineAsmLength(const char *Str,
249 const MCAsmInfo &MAI) const override;
251 /// Allocate and return a hazard recognizer to use for this target when
252 /// scheduling the machine instructions after register allocation.
253 ScheduleHazardRecognizer*
254 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
255 const ScheduleDAG *DAG) const override;
257 /// For a comparison instruction, return the source registers
258 /// in SrcReg and SrcReg2 if having two register operands, and the value it
259 /// compares against in CmpValue. Return true if the comparison instruction
261 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
262 unsigned &SrcReg2, int &Mask, int &Value) const override;
264 /// Compute the instruction latency of a given instruction.
265 /// If the instruction has higher cost when predicated, it's returned via
267 unsigned getInstrLatency(const InstrItineraryData *ItinData,
268 const MachineInstr &MI,
269 unsigned *PredCost = nullptr) const override;
271 /// Create machine specific model for scheduling.
273 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
275 // Sometimes, it is possible for the target
276 // to tell, even without aliasing information, that two MIs access different
277 // memory addresses. This function returns true if two MIs access different
278 // memory addresses and false otherwise.
280 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
281 AliasAnalysis *AA = nullptr) const override;
283 /// For instructions with a base and offset, return the position of the
284 /// base register and offset operands.
285 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
286 unsigned &OffsetPos) const override;
288 /// If the instruction is an increment of a constant value, return the amount.
289 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
291 bool isTailCall(const MachineInstr &MI) const override;
293 /// HexagonInstrInfo specifics.
296 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
298 unsigned createVR(MachineFunction* MF, MVT VT) const;
300 bool isAbsoluteSet(const MachineInstr &MI) const;
301 bool isAccumulator(const MachineInstr &MI) const;
302 bool isComplex(const MachineInstr &MI) const;
303 bool isCompoundBranchInstr(const MachineInstr &MI) const;
304 bool isCondInst(const MachineInstr &MI) const;
305 bool isConditionalALU32 (const MachineInstr &MI) const;
306 bool isConditionalLoad(const MachineInstr &MI) const;
307 bool isConditionalStore(const MachineInstr &MI) const;
308 bool isConditionalTransfer(const MachineInstr &MI) const;
309 bool isConstExtended(const MachineInstr &MI) const;
310 bool isDeallocRet(const MachineInstr &MI) const;
311 bool isDependent(const MachineInstr &ProdMI,
312 const MachineInstr &ConsMI) const;
313 bool isDotCurInst(const MachineInstr &MI) const;
314 bool isDotNewInst(const MachineInstr &MI) const;
315 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
316 bool isEarlySourceInstr(const MachineInstr &MI) const;
317 bool isEndLoopN(unsigned Opcode) const;
318 bool isExpr(unsigned OpType) const;
319 bool isExtendable(const MachineInstr &MI) const;
320 bool isExtended(const MachineInstr &MI) const;
321 bool isFloat(const MachineInstr &MI) const;
322 bool isHVXMemWithAIndirect(const MachineInstr &I,
323 const MachineInstr &J) const;
324 bool isIndirectCall(const MachineInstr &MI) const;
325 bool isIndirectL4Return(const MachineInstr &MI) const;
326 bool isJumpR(const MachineInstr &MI) const;
327 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
328 bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
329 const MachineInstr &ESMI) const;
330 bool isLateResultInstr(const MachineInstr &MI) const;
331 bool isLateSourceInstr(const MachineInstr &MI) const;
332 bool isLoopN(const MachineInstr &MI) const;
333 bool isMemOp(const MachineInstr &MI) const;
334 bool isNewValue(const MachineInstr &MI) const;
335 bool isNewValue(unsigned Opcode) const;
336 bool isNewValueInst(const MachineInstr &MI) const;
337 bool isNewValueJump(const MachineInstr &MI) const;
338 bool isNewValueJump(unsigned Opcode) const;
339 bool isNewValueStore(const MachineInstr &MI) const;
340 bool isNewValueStore(unsigned Opcode) const;
341 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
342 bool isPredicatedNew(const MachineInstr &MI) const;
343 bool isPredicatedNew(unsigned Opcode) const;
344 bool isPredicatedTrue(const MachineInstr &MI) const;
345 bool isPredicatedTrue(unsigned Opcode) const;
346 bool isPredicated(unsigned Opcode) const;
347 bool isPredicateLate(unsigned Opcode) const;
348 bool isPredictedTaken(unsigned Opcode) const;
349 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
350 bool isSignExtendingLoad(const MachineInstr &MI) const;
351 bool isSolo(const MachineInstr &MI) const;
352 bool isSpillPredRegOp(const MachineInstr &MI) const;
353 bool isTC1(const MachineInstr &MI) const;
354 bool isTC2(const MachineInstr &MI) const;
355 bool isTC2Early(const MachineInstr &MI) const;
356 bool isTC4x(const MachineInstr &MI) const;
357 bool isToBeScheduledASAP(const MachineInstr &MI1,
358 const MachineInstr &MI2) const;
359 bool isV60VectorInstruction(const MachineInstr &MI) const;
360 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
361 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
362 bool isVecAcc(const MachineInstr &MI) const;
363 bool isVecALU(const MachineInstr &MI) const;
364 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
365 const MachineInstr &ConsMI) const;
366 bool isZeroExtendingLoad(const MachineInstr &MI) const;
368 bool addLatencyToSchedule(const MachineInstr &MI1,
369 const MachineInstr &MI2) const;
370 bool canExecuteInBundle(const MachineInstr &First,
371 const MachineInstr &Second) const;
372 bool doesNotReturn(const MachineInstr &CallMI) const;
373 bool hasEHLabel(const MachineBasicBlock *B) const;
374 bool hasNonExtEquivalent(const MachineInstr &MI) const;
375 bool hasPseudoInstrPair(const MachineInstr &MI) const;
376 bool hasUncondBranch(const MachineBasicBlock *B) const;
377 bool mayBeCurLoad(const MachineInstr &MI) const;
378 bool mayBeNewStore(const MachineInstr &MI) const;
379 bool producesStall(const MachineInstr &ProdMI,
380 const MachineInstr &ConsMI) const;
381 bool producesStall(const MachineInstr &MI,
382 MachineBasicBlock::const_instr_iterator MII) const;
383 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
384 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
385 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
387 short getAbsoluteForm(const MachineInstr &MI) const;
388 unsigned getAddrMode(const MachineInstr &MI) const;
389 unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset,
390 unsigned &AccessSize) const;
391 short getBaseWithLongOffset(short Opcode) const;
392 short getBaseWithLongOffset(const MachineInstr &MI) const;
393 short getBaseWithRegOffset(const MachineInstr &MI) const;
394 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
395 unsigned getCExtOpNum(const MachineInstr &MI) const;
396 HexagonII::CompoundGroup
397 getCompoundCandidateGroup(const MachineInstr &MI) const;
398 unsigned getCompoundOpcode(const MachineInstr &GA,
399 const MachineInstr &GB) const;
400 int getCondOpcode(int Opc, bool sense) const;
401 int getDotCurOp(const MachineInstr &MI) const;
402 int getDotNewOp(const MachineInstr &MI) const;
403 int getDotNewPredJumpOp(const MachineInstr &MI,
404 const MachineBranchProbabilityInfo *MBPI) const;
405 int getDotNewPredOp(const MachineInstr &MI,
406 const MachineBranchProbabilityInfo *MBPI) const;
407 int getDotOldOp(const int opc) const;
408 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
410 short getEquivalentHWInstr(const MachineInstr &MI) const;
411 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
412 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
413 const MachineInstr &MI) const;
414 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
415 unsigned getInvertedPredicatedOpcode(const int Opc) const;
416 int getMaxValue(const MachineInstr &MI) const;
417 unsigned getMemAccessSize(const MachineInstr &MI) const;
418 int getMinValue(const MachineInstr &MI) const;
419 short getNonExtOpcode(const MachineInstr &MI) const;
420 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
421 unsigned &PredRegPos, unsigned &PredRegFlags) const;
422 short getPseudoInstrPair(const MachineInstr &MI) const;
423 short getRegForm(const MachineInstr &MI) const;
424 unsigned getSize(const MachineInstr &MI) const;
425 uint64_t getType(const MachineInstr &MI) const;
426 unsigned getUnits(const MachineInstr &MI) const;
427 unsigned getValidSubTargets(const unsigned Opcode) const;
429 /// getInstrTimingClassLatency - Compute the instruction latency of a given
430 /// instruction using Timing Class information, if available.
431 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
432 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
434 void immediateExtend(MachineInstr &MI) const;
435 bool invertAndChangeJumpTarget(MachineInstr &MI,
436 MachineBasicBlock* NewTarget) const;
437 void genAllInsnTimingClasses(MachineFunction &MF) const;
438 bool reversePredSense(MachineInstr &MI) const;
439 unsigned reversePrediction(unsigned Opcode) const;
440 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
441 short xformRegToImmOffset(const MachineInstr &MI) const;
444 } // end namespace llvm
446 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H