1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
17 #include "MCTargetDesc/HexagonBaseInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/ValueTypes.h"
27 #define GET_INSTRINFO_HEADER
28 #include "HexagonGenInstrInfo.inc"
32 class HexagonSubtarget;
33 class MachineBranchProbabilityInfo;
34 class MachineFunction;
37 class TargetRegisterInfo;
39 class HexagonInstrInfo : public HexagonGenInstrInfo {
40 const HexagonSubtarget &Subtarget;
42 enum BundleAttribute {
43 memShufDisabledMask = 0x4
46 virtual void anchor();
49 explicit HexagonInstrInfo(HexagonSubtarget &ST);
51 /// TargetInstrInfo overrides.
53 /// If the specified machine instruction is a direct
54 /// load from a stack slot, return the virtual or physical register number of
55 /// the destination along with the FrameIndex of the loaded stack slot. If
56 /// not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than loading from the stack slot.
58 unsigned isLoadFromStackSlot(const MachineInstr &MI,
59 int &FrameIndex) const override;
61 /// If the specified machine instruction is a direct
62 /// store to a stack slot, return the virtual or physical register number of
63 /// the source reg along with the FrameIndex of the loaded stack slot. If
64 /// not, return 0. This predicate must return 0 if the instruction has
65 /// any side effects other than storing to the stack slot.
66 unsigned isStoreToStackSlot(const MachineInstr &MI,
67 int &FrameIndex) const override;
69 /// Analyze the branching code at the end of MBB, returning
70 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
71 /// implemented for a target). Upon success, this returns false and returns
72 /// with the following information in various cases:
74 /// 1. If this block ends with no branches (it just falls through to its succ)
75 /// just return false, leaving TBB/FBB null.
76 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
77 /// the destination block.
78 /// 3. If this block ends with a conditional branch and it falls through to a
79 /// successor block, it sets TBB to be the branch destination block and a
80 /// list of operands that evaluate the condition. These operands can be
81 /// passed to other TargetInstrInfo methods to create new branches.
82 /// 4. If this block ends with a conditional branch followed by an
83 /// unconditional branch, it returns the 'true' destination in TBB, the
84 /// 'false' destination in FBB, and a list of operands that evaluate the
85 /// condition. These operands can be passed to other TargetInstrInfo
86 /// methods to create new branches.
88 /// Note that removeBranch and insertBranch must be implemented to support
89 /// cases where this method returns success.
91 /// If AllowModify is true, then this routine is allowed to modify the basic
92 /// block (e.g. delete instructions after the unconditional branch).
93 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
94 MachineBasicBlock *&FBB,
95 SmallVectorImpl<MachineOperand> &Cond,
96 bool AllowModify) const override;
98 /// Remove the branching code at the end of the specific MBB.
99 /// This is only invoked in cases where AnalyzeBranch returns success. It
100 /// returns the number of instructions that were removed.
101 unsigned removeBranch(MachineBasicBlock &MBB,
102 int *BytesRemoved = nullptr) const override;
104 /// Insert branch code into the end of the specified MachineBasicBlock.
105 /// The operands to this method are the same as those
106 /// returned by AnalyzeBranch. This is only invoked in cases where
107 /// AnalyzeBranch returns success. It returns the number of instructions
110 /// It is also invoked by tail merging to add unconditional branches in
111 /// cases where AnalyzeBranch doesn't apply because there was no original
112 /// branch to analyze. At least this much must be implemented, else tail
113 /// merging needs to be disabled.
114 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
115 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
117 int *BytesAdded = nullptr) const override;
119 /// Analyze the loop code, return true if it cannot be understood. Upon
120 /// success, this function returns false and returns information about the
121 /// induction variable and compare instruction used at the end.
122 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
123 MachineInstr *&CmpInst) const override;
125 /// Generate code to reduce the loop iteration by one and check if the loop is
126 /// finished. Return the value/register of the the new loop count. We need
127 /// this function when peeling off one or more iterations of a loop. This
128 /// function assumes the nth iteration is peeled first.
129 unsigned reduceLoopCount(MachineBasicBlock &MBB,
130 MachineInstr *IndVar, MachineInstr &Cmp,
131 SmallVectorImpl<MachineOperand> &Cond,
132 SmallVectorImpl<MachineInstr *> &PrevInsts,
133 unsigned Iter, unsigned MaxIter) const override;
135 /// Return true if it's profitable to predicate
136 /// instructions with accumulated instruction latency of "NumCycles"
137 /// of the specified basic block, where the probability of the instructions
138 /// being executed is given by Probability, and Confidence is a measure
139 /// of our confidence that it will be properly predicted.
140 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
141 unsigned ExtraPredCycles,
142 BranchProbability Probability) const override;
144 /// Second variant of isProfitableToIfCvt. This one
145 /// checks for the case where two basic blocks from true and false path
146 /// of a if-then-else (diamond) are predicated on mutally exclusive
147 /// predicates, where the probability of the true path being taken is given
148 /// by Probability, and Confidence is a measure of our confidence that it
149 /// will be properly predicted.
150 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
151 unsigned NumTCycles, unsigned ExtraTCycles,
152 MachineBasicBlock &FMBB,
153 unsigned NumFCycles, unsigned ExtraFCycles,
154 BranchProbability Probability) const override;
156 /// Return true if it's profitable for if-converter to duplicate instructions
157 /// of specified accumulated instruction latencies in the specified MBB to
158 /// enable if-conversion.
159 /// The probability of the instructions being executed is given by
160 /// Probability, and Confidence is a measure of our confidence that it
161 /// will be properly predicted.
162 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
163 BranchProbability Probability) const override;
165 /// Emit instructions to copy a pair of physical registers.
167 /// This function should support copies within any legal register class as
168 /// well as any cross-class copies created during instruction selection.
170 /// The source and destination registers may overlap, which may require a
171 /// careful implementation when multiple copy instructions are required for
172 /// large registers. See for example the ARM target.
173 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
174 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
175 bool KillSrc) const override;
177 /// Store the specified register of the given register class to the specified
178 /// stack frame index. The store instruction is to be added to the given
179 /// machine basic block before the specified machine instruction. If isKill
180 /// is true, the register operand is the last use and must be marked kill.
181 void storeRegToStackSlot(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MBBI,
183 unsigned SrcReg, bool isKill, int FrameIndex,
184 const TargetRegisterClass *RC,
185 const TargetRegisterInfo *TRI) const override;
187 /// Load the specified register of the given register class from the specified
188 /// stack frame index. The load instruction is to be added to the given
189 /// machine basic block before the specified machine instruction.
190 void loadRegFromStackSlot(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator MBBI,
192 unsigned DestReg, int FrameIndex,
193 const TargetRegisterClass *RC,
194 const TargetRegisterInfo *TRI) const override;
196 /// This function is called for all pseudo instructions
197 /// that remain after register allocation. Many pseudo instructions are
198 /// created to help register allocation. This is the place to convert them
199 /// into real instructions. The target can edit MI in place, or it can insert
200 /// new instructions and erase MI. The function should return true if
201 /// anything was changed.
202 bool expandPostRAPseudo(MachineInstr &MI) const override;
204 /// \brief Get the base register and byte offset of a load/store instr.
205 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
207 const TargetRegisterInfo *TRI) const override;
209 /// Reverses the branch condition of the specified condition list,
210 /// returning false on success and true if it cannot be reversed.
211 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
214 /// Insert a noop into the instruction stream at the specified point.
215 void insertNoop(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator MI) const override;
218 /// Returns true if the instruction is already predicated.
219 bool isPredicated(const MachineInstr &MI) const override;
221 /// Return true for post-incremented instructions.
222 bool isPostIncrement(const MachineInstr &MI) const override;
224 /// Convert the instruction into a predicated instruction.
225 /// It returns true if the operation was successful.
226 bool PredicateInstruction(MachineInstr &MI,
227 ArrayRef<MachineOperand> Cond) const override;
229 /// Returns true if the first specified predicate
230 /// subsumes the second, e.g. GE subsumes GT.
231 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
232 ArrayRef<MachineOperand> Pred2) const override;
234 /// If the specified instruction defines any predicate
235 /// or condition code register(s) used for predication, returns true as well
236 /// as the definition predicate(s) by reference.
237 bool DefinesPredicate(MachineInstr &MI,
238 std::vector<MachineOperand> &Pred) const override;
240 /// Return true if the specified instruction can be predicated.
241 /// By default, this returns true for every instruction with a
242 /// PredicateOperand.
243 bool isPredicable(const MachineInstr &MI) const override;
245 /// Test if the given instruction should be considered a scheduling boundary.
246 /// This primarily includes labels and terminators.
247 bool isSchedulingBoundary(const MachineInstr &MI,
248 const MachineBasicBlock *MBB,
249 const MachineFunction &MF) const override;
251 /// Measure the specified inline asm to determine an approximation of its
253 unsigned getInlineAsmLength(const char *Str,
254 const MCAsmInfo &MAI) const override;
256 /// Allocate and return a hazard recognizer to use for this target when
257 /// scheduling the machine instructions after register allocation.
258 ScheduleHazardRecognizer*
259 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
260 const ScheduleDAG *DAG) const override;
262 /// For a comparison instruction, return the source registers
263 /// in SrcReg and SrcReg2 if having two register operands, and the value it
264 /// compares against in CmpValue. Return true if the comparison instruction
266 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
267 unsigned &SrcReg2, int &Mask, int &Value) const override;
269 /// Compute the instruction latency of a given instruction.
270 /// If the instruction has higher cost when predicated, it's returned via
272 unsigned getInstrLatency(const InstrItineraryData *ItinData,
273 const MachineInstr &MI,
274 unsigned *PredCost = nullptr) const override;
276 /// Create machine specific model for scheduling.
278 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
280 // Sometimes, it is possible for the target
281 // to tell, even without aliasing information, that two MIs access different
282 // memory addresses. This function returns true if two MIs access different
283 // memory addresses and false otherwise.
285 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
286 AliasAnalysis *AA = nullptr) const override;
288 /// For instructions with a base and offset, return the position of the
289 /// base register and offset operands.
290 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
291 unsigned &OffsetPos) const override;
293 /// If the instruction is an increment of a constant value, return the amount.
294 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
296 /// getOperandLatency - Compute and return the use operand latency of a given
297 /// pair of def and use.
298 /// In most cases, the static scheduling itinerary was enough to determine the
299 /// operand latency. But it may not be possible for instructions with variable
300 /// number of defs / uses.
302 /// This is a raw interface to the itinerary that may be directly overriden by
303 /// a target. Use computeOperandLatency to get the best estimate of latency.
304 int getOperandLatency(const InstrItineraryData *ItinData,
305 const MachineInstr &DefMI, unsigned DefIdx,
306 const MachineInstr &UseMI,
307 unsigned UseIdx) const override;
309 /// Decompose the machine operand's target flags into two values - the direct
310 /// target flag value and any of bit flags that are applied.
311 std::pair<unsigned, unsigned>
312 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
314 /// Return an array that contains the direct target flag values and their
317 /// MIR Serialization is able to serialize only the target flags that are
318 /// defined by this method.
319 ArrayRef<std::pair<unsigned, const char *>>
320 getSerializableDirectMachineOperandTargetFlags() const override;
322 /// Return an array that contains the bitmask target flag values and their
325 /// MIR Serialization is able to serialize only the target flags that are
326 /// defined by this method.
327 ArrayRef<std::pair<unsigned, const char *>>
328 getSerializableBitmaskMachineOperandTargetFlags() const override;
330 bool isTailCall(const MachineInstr &MI) const override;
332 /// HexagonInstrInfo specifics.
334 unsigned createVR(MachineFunction *MF, MVT VT) const;
336 bool isAbsoluteSet(const MachineInstr &MI) const;
337 bool isAccumulator(const MachineInstr &MI) const;
338 bool isAddrModeWithOffset(const MachineInstr &MI) const;
339 bool isComplex(const MachineInstr &MI) const;
340 bool isCompoundBranchInstr(const MachineInstr &MI) const;
341 bool isConstExtended(const MachineInstr &MI) const;
342 bool isDeallocRet(const MachineInstr &MI) const;
343 bool isDependent(const MachineInstr &ProdMI,
344 const MachineInstr &ConsMI) const;
345 bool isDotCurInst(const MachineInstr &MI) const;
346 bool isDotNewInst(const MachineInstr &MI) const;
347 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
348 bool isEarlySourceInstr(const MachineInstr &MI) const;
349 bool isEndLoopN(unsigned Opcode) const;
350 bool isExpr(unsigned OpType) const;
351 bool isExtendable(const MachineInstr &MI) const;
352 bool isExtended(const MachineInstr &MI) const;
353 bool isFloat(const MachineInstr &MI) const;
354 bool isHVXMemWithAIndirect(const MachineInstr &I,
355 const MachineInstr &J) const;
356 bool isIndirectCall(const MachineInstr &MI) const;
357 bool isIndirectL4Return(const MachineInstr &MI) const;
358 bool isJumpR(const MachineInstr &MI) const;
359 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
360 bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
361 const MachineInstr &ESMI) const;
362 bool isLateResultInstr(const MachineInstr &MI) const;
363 bool isLateSourceInstr(const MachineInstr &MI) const;
364 bool isLoopN(const MachineInstr &MI) const;
365 bool isMemOp(const MachineInstr &MI) const;
366 bool isNewValue(const MachineInstr &MI) const;
367 bool isNewValue(unsigned Opcode) const;
368 bool isNewValueInst(const MachineInstr &MI) const;
369 bool isNewValueJump(const MachineInstr &MI) const;
370 bool isNewValueJump(unsigned Opcode) const;
371 bool isNewValueStore(const MachineInstr &MI) const;
372 bool isNewValueStore(unsigned Opcode) const;
373 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
374 bool isPredicatedNew(const MachineInstr &MI) const;
375 bool isPredicatedNew(unsigned Opcode) const;
376 bool isPredicatedTrue(const MachineInstr &MI) const;
377 bool isPredicatedTrue(unsigned Opcode) const;
378 bool isPredicated(unsigned Opcode) const;
379 bool isPredicateLate(unsigned Opcode) const;
380 bool isPredictedTaken(unsigned Opcode) const;
381 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
382 bool isSignExtendingLoad(const MachineInstr &MI) const;
383 bool isSolo(const MachineInstr &MI) const;
384 bool isSpillPredRegOp(const MachineInstr &MI) const;
385 bool isTC1(const MachineInstr &MI) const;
386 bool isTC2(const MachineInstr &MI) const;
387 bool isTC2Early(const MachineInstr &MI) const;
388 bool isTC4x(const MachineInstr &MI) const;
389 bool isToBeScheduledASAP(const MachineInstr &MI1,
390 const MachineInstr &MI2) const;
391 bool isHVXVec(const MachineInstr &MI) const;
392 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
393 bool isValidOffset(unsigned Opcode, int Offset,
394 const TargetRegisterInfo *TRI, bool Extend = true) const;
395 bool isVecAcc(const MachineInstr &MI) const;
396 bool isVecALU(const MachineInstr &MI) const;
397 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
398 const MachineInstr &ConsMI) const;
399 bool isZeroExtendingLoad(const MachineInstr &MI) const;
401 bool addLatencyToSchedule(const MachineInstr &MI1,
402 const MachineInstr &MI2) const;
403 bool canExecuteInBundle(const MachineInstr &First,
404 const MachineInstr &Second) const;
405 bool doesNotReturn(const MachineInstr &CallMI) const;
406 bool hasEHLabel(const MachineBasicBlock *B) const;
407 bool hasNonExtEquivalent(const MachineInstr &MI) const;
408 bool hasPseudoInstrPair(const MachineInstr &MI) const;
409 bool hasUncondBranch(const MachineBasicBlock *B) const;
410 bool mayBeCurLoad(const MachineInstr &MI) const;
411 bool mayBeNewStore(const MachineInstr &MI) const;
412 bool producesStall(const MachineInstr &ProdMI,
413 const MachineInstr &ConsMI) const;
414 bool producesStall(const MachineInstr &MI,
415 MachineBasicBlock::const_instr_iterator MII) const;
416 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
417 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
418 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
420 unsigned getAddrMode(const MachineInstr &MI) const;
421 unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset,
422 unsigned &AccessSize) const;
423 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
424 unsigned getCExtOpNum(const MachineInstr &MI) const;
425 HexagonII::CompoundGroup
426 getCompoundCandidateGroup(const MachineInstr &MI) const;
427 unsigned getCompoundOpcode(const MachineInstr &GA,
428 const MachineInstr &GB) const;
429 int getCondOpcode(int Opc, bool sense) const;
430 int getDotCurOp(const MachineInstr &MI) const;
431 int getNonDotCurOp(const MachineInstr &MI) const;
432 int getDotNewOp(const MachineInstr &MI) const;
433 int getDotNewPredJumpOp(const MachineInstr &MI,
434 const MachineBranchProbabilityInfo *MBPI) const;
435 int getDotNewPredOp(const MachineInstr &MI,
436 const MachineBranchProbabilityInfo *MBPI) const;
437 int getDotOldOp(const MachineInstr &MI) const;
438 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
440 short getEquivalentHWInstr(const MachineInstr &MI) const;
441 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
442 const MachineInstr &MI) const;
443 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
444 unsigned getInvertedPredicatedOpcode(const int Opc) const;
445 int getMaxValue(const MachineInstr &MI) const;
446 unsigned getMemAccessSize(const MachineInstr &MI) const;
447 int getMinValue(const MachineInstr &MI) const;
448 short getNonExtOpcode(const MachineInstr &MI) const;
449 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
450 unsigned &PredRegPos, unsigned &PredRegFlags) const;
451 short getPseudoInstrPair(const MachineInstr &MI) const;
452 short getRegForm(const MachineInstr &MI) const;
453 unsigned getSize(const MachineInstr &MI) const;
454 uint64_t getType(const MachineInstr &MI) const;
455 unsigned getUnits(const MachineInstr &MI) const;
457 /// getInstrTimingClassLatency - Compute the instruction latency of a given
458 /// instruction using Timing Class information, if available.
459 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
460 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
462 void immediateExtend(MachineInstr &MI) const;
463 bool invertAndChangeJumpTarget(MachineInstr &MI,
464 MachineBasicBlock *NewTarget) const;
465 void genAllInsnTimingClasses(MachineFunction &MF) const;
466 bool reversePredSense(MachineInstr &MI) const;
467 unsigned reversePrediction(unsigned Opcode) const;
468 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
470 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
471 bool getBundleNoShuf(const MachineInstr &MIB) const;
472 // Addressing mode relations.
473 short changeAddrMode_abs_io(short Opc) const;
474 short changeAddrMode_io_abs(short Opc) const;
475 short changeAddrMode_io_pi(short Opc) const;
476 short changeAddrMode_io_rr(short Opc) const;
477 short changeAddrMode_pi_io(short Opc) const;
478 short changeAddrMode_rr_io(short Opc) const;
479 short changeAddrMode_rr_ur(short Opc) const;
480 short changeAddrMode_ur_rr(short Opc) const;
482 short changeAddrMode_abs_io(const MachineInstr &MI) const {
483 return changeAddrMode_abs_io(MI.getOpcode());
485 short changeAddrMode_io_abs(const MachineInstr &MI) const {
486 return changeAddrMode_io_abs(MI.getOpcode());
488 short changeAddrMode_io_rr(const MachineInstr &MI) const {
489 return changeAddrMode_io_rr(MI.getOpcode());
491 short changeAddrMode_rr_io(const MachineInstr &MI) const {
492 return changeAddrMode_rr_io(MI.getOpcode());
494 short changeAddrMode_rr_ur(const MachineInstr &MI) const {
495 return changeAddrMode_rr_ur(MI.getOpcode());
497 short changeAddrMode_ur_rr(const MachineInstr &MI) const {
498 return changeAddrMode_ur_rr(MI.getOpcode());
502 } // end namespace llvm
504 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H