1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 let isCall = 1, hasSideEffects = 1, isPredicable = 1,
19 isExtended = 0, isExtendable = 1, opExtendable = 0,
20 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
21 class T_Call<bit CSR, string ExtStr>
22 : JInst<(outs), (ins calltarget:$dst),
23 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
24 let BaseOpcode = "call";
27 let Defs = !if (CSR, VolatileV3.Regs, []);
29 let Inst{27-25} = 0b101;
30 let Inst{24-16,13-1} = dst{23-2};
34 let isCall = 1, hasSideEffects = 1, isPredicated = 1,
35 isExtended = 0, isExtendable = 1, opExtendable = 1,
36 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
37 class T_CallPred<bit CSR, bit IfTrue, string ExtStr>
38 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
39 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
40 [], "", J_tc_2early_SLOT23> {
41 let BaseOpcode = "call";
42 let isPredicatedFalse = !if(IfTrue,0,1);
46 let Defs = !if (CSR, VolatileV3.Regs, []);
48 let Inst{27-24} = 0b1101;
49 let Inst{23-22,20-16,13,7-1} = dst{16-2};
50 let Inst{21} = !if(IfTrue,0,1);
55 multiclass T_Calls<bit CSR, string ExtStr> {
56 def NAME : T_Call<CSR, ExtStr>;
57 def t : T_CallPred<CSR, 1, ExtStr>;
58 def f : T_CallPred<CSR, 0, ExtStr>;
61 defm J2_call: T_Calls<1, "">, PredRel;
63 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
64 Defs = VolatileV3.Regs in
65 def PS_call_nr : T_Call<1, "">, PredRel;
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
68 Defs = [PC, R31, R6, R7, P0] in
69 def PS_call_stk : T_Call<0, "">, PredRel;
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
79 // Call subroutine from register.
81 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
82 def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
85 //===----------------------------------------------------------------------===//
87 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
94 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
96 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
97 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
99 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
100 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
102 let hasSideEffects = 0, isAsmParserOnly = 1 in
103 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
104 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", [],
105 "", ALU64_tc_1_SLOT23>;
108 let hasSideEffects = 0 in
109 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
110 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
111 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
112 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
119 let Inst{27-23} = 0b00111;
120 let Inst{22-21} = !if(isMax, 0b10, 0b01);
121 let Inst{20-16} = !if(isMax, Rt, Rs);
122 let Inst{12-8} = !if(isMax, Rs, Rt);
124 let Inst{6} = !if(isMax, 0b0, 0b1);
125 let Inst{5} = isUnsigned;
129 def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
130 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
131 def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
132 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
134 //===----------------------------------------------------------------------===//
136 //===----------------------------------------------------------------------===//
138 //===----------------------------------------------------------------------===//
139 // :raw form of vrcmpys:hi/lo insns
140 //===----------------------------------------------------------------------===//
141 // Vector reduce complex multiply by scalar.
142 let Defs = [USR_OVF], hasSideEffects = 0 in
143 class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
144 MInst<(outs DoubleRegs:$Rdd),
145 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
146 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
153 let Inst{27-24} = 0b1000;
154 let Inst{23-21} = MajOp;
155 let Inst{20-16} = Rss;
156 let Inst{12-8} = Rtt;
157 let Inst{7-5} = 0b100;
161 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
162 def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
164 // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
165 let hasSideEffects = 0, isAsmParserOnly = 1 in
167 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
168 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
170 // Vector reduce complex multiply by scalar with accumulation.
171 let Defs = [USR_OVF], hasSideEffects = 0 in
172 class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
173 MInst <(outs DoubleRegs:$Rxx),
174 (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
175 "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
183 let Inst{27-24} = 0b1010;
184 let Inst{23-21} = MajOp;
185 let Inst{20-16} = Rss;
186 let Inst{12-8} = Rtt;
187 let Inst{7-5} = 0b100;
191 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
192 def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
194 // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
196 let isAsmParserOnly = 1 in
197 def M2_vrcmpys_acc_s1
198 : MInst <(outs DoubleRegs:$dst),
199 (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
200 "$dst += vrcmpys($src1, $src2):<<1:sat", [],
203 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
204 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
206 // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
207 let isAsmParserOnly = 1 in
209 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
210 "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
213 // S2_cabacdecbin: Cabac decode bin.
214 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
215 def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;