1 //=- HexagonInstrInfoV60.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V60 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
13 def alignedload : PatFrag<(ops node:$addr), (load $addr), [{
14 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
17 def unalignedload : PatFrag<(ops node:$addr), (load $addr), [{
18 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
21 def alignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [{
22 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
25 def unalignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [{
26 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
31 let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
33 class VSTInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
34 string cstr = "", InstrItinClass itin = CVI_VM_ST,
35 IType type = TypeCVI_VM_ST>
36 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>, OpcodeHexagon;
41 let Predicates = [HasV60T, UseHVX] in
42 let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
43 class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
44 string cstr = "", InstrItinClass itin = CVI_VM_LD,
45 IType type = TypeCVI_VM_LD>
46 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
48 let Predicates = [HasV60T, UseHVX] in
49 let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
50 class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
51 string cstr = "", InstrItinClass itin = CVI_VM_ST,
52 IType type = TypeCVI_VM_ST>
53 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
55 //===----------------------------------------------------------------------===//
56 // Vector loads with base + immediate offset
57 //===----------------------------------------------------------------------===//
58 let addrMode = BaseImmOffset, accessSize = Vector64Access in
59 class T_vload_ai<string asmStr>
60 : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
63 let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in
64 class T_vload_ai_128B<string asmStr>
65 : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
68 let isCVLoadable = 1, hasNewValue = 1 in {
69 def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">,
71 def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">,
74 def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">,
76 def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">,
77 V6_vL32b_nt_ai_128B_enc;
80 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU, hasNewValue = 1 in {
81 def V6_vL32Ub_ai : T_vload_ai <"$dst = vmemu($src1+#$src2)">,
83 def V6_vL32Ub_ai_128B : T_vload_ai_128B <"$dst = vmemu($src1+#$src2)">,
84 V6_vL32Ub_ai_128B_enc;
87 let Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD, isCVLoad = 1,
89 def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">,
91 def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">,
92 V6_vL32b_nt_cur_ai_enc;
94 def V6_vL32b_cur_ai_128B : T_vload_ai_128B
95 <"$dst.cur = vmem($src1+#$src2)">,
96 V6_vL32b_cur_ai_128B_enc;
97 def V6_vL32b_nt_cur_ai_128B : T_vload_ai_128B
98 <"$dst.cur = vmem($src1+#$src2):nt">,
99 V6_vL32b_nt_cur_ai_128B_enc;
103 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD, hasNewValue = 1 in {
104 def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">,
106 def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">,
107 V6_vL32b_nt_tmp_ai_enc;
109 def V6_vL32b_tmp_ai_128B : T_vload_ai_128B
110 <"$dst.tmp = vmem($src1+#$src2)">,
111 V6_vL32b_tmp_ai_128B_enc;
112 def V6_vL32b_nt_tmp_ai_128B : T_vload_ai_128B
113 <"$dst.tmp = vmem($src1+#$src2)">,
114 V6_vL32b_nt_tmp_ai_128B_enc;
117 //===----------------------------------------------------------------------===//
118 // Vector stores with base + immediate offset - unconditional
119 //===----------------------------------------------------------------------===//
120 let addrMode = BaseImmOffset, accessSize = Vector64Access, isPredicable = 1 in
121 class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
122 RegisterClass RC, bit isNT>
123 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
124 mnemonic#"($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3">, NewValueRel {
125 let BaseOpcode = baseOp;
128 let accessSize = Vector64Access in
129 class T_vstore_ai_64B <string mnemonic, string baseOp, bit isNT = 0>
130 : T_vstore_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isNT>;
132 let isCodeGenOnly = 1, accessSize = Vector128Access in
133 class T_vstore_ai_128B <string mnemonic, string baseOp, bit isNT = 0>
134 : T_vstore_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
136 let isNVStorable = 1 in {
137 def V6_vS32b_ai : T_vstore_ai_64B <"vmem", "vS32b_ai">,
139 def V6_vS32b_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai">,
140 V6_vS32b_ai_128B_enc;
143 let isNVStorable = 1, isNonTemporal = 1 in {
144 def V6_vS32b_nt_ai : T_vstore_ai_64B <"vmem", "vS32b_ai", 1>,
146 def V6_vS32b_nt_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai", 1>,
147 V6_vS32b_nt_ai_128B_enc;
150 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
151 def V6_vS32Ub_ai : T_vstore_ai_64B <"vmemu", "vS32Ub_ai">,
153 def V6_vS32Ub_ai_128B : T_vstore_ai_128B <"vmemu", "vS32Ub_ai">,
154 V6_vS32Ub_ai_128B_enc;
156 //===----------------------------------------------------------------------===//
157 // Vector stores with base + immediate offset - unconditional new
158 //===----------------------------------------------------------------------===//
159 let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1,
160 isPredicable = 1, Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST in
161 class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
162 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
163 "vmem($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3.new">, NewValueRel {
164 let BaseOpcode = baseOp;
167 let accessSize = Vector64Access in
168 class T_vstore_new_ai_64B <string baseOp, bit isNT = 0>
169 : T_vstore_new_ai <baseOp, s4_6Imm, VectorRegs, isNT>;
171 let isCodeGenOnly = 1, accessSize = Vector128Access in
172 class T_vstore_new_ai_128B <string baseOp, bit isNT = 0>
173 : T_vstore_new_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
175 def V6_vS32b_new_ai : T_vstore_new_ai_64B <"vS32b_ai">, V6_vS32b_new_ai_enc;
176 def V6_vS32b_new_ai_128B : T_vstore_new_ai_128B <"vS32b_ai">,
177 V6_vS32b_new_ai_128B_enc;
179 let isNonTemporal = 1 in {
180 def V6_vS32b_nt_new_ai : T_vstore_new_ai_64B<"vS32b_ai", 1>,
181 V6_vS32b_nt_new_ai_enc;
182 def V6_vS32b_nt_new_ai_128B : T_vstore_new_ai_128B<"vS32b_ai", 1>,
183 V6_vS32b_nt_new_ai_128B_enc;
186 //===----------------------------------------------------------------------===//
187 // Vector stores with base + immediate offset - conditional
188 //===----------------------------------------------------------------------===//
189 let addrMode = BaseImmOffset, isPredicated = 1 in
190 class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
191 RegisterClass RC, bit isPredNot = 0, bit isNT = 0>
193 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
194 "if ("#!if(isPredNot, "!", "")#"$src1) "
195 #mnemonic#"($src2+#$src3)"#!if(isNT, ":nt", "")#" = $src4">, NewValueRel {
196 let isPredicatedFalse = isPredNot;
197 let BaseOpcode = baseOp;
200 let accessSize = Vector64Access in
201 class T_vstore_pred_ai_64B <string mnemonic, string baseOp,
202 bit isPredNot = 0, bit isNT = 0>
203 : T_vstore_pred_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
205 let isCodeGenOnly = 1, accessSize = Vector128Access in
206 class T_vstore_pred_ai_128B <string mnemonic, string baseOp,
207 bit isPredNot = 0, bit isNT = 0>
208 : T_vstore_pred_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B,
211 let isNVStorable = 1 in {
212 def V6_vS32b_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai">,
213 V6_vS32b_pred_ai_enc;
214 def V6_vS32b_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1>,
215 V6_vS32b_npred_ai_enc;
217 def V6_vS32b_pred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai">,
218 V6_vS32b_pred_ai_128B_enc;
219 def V6_vS32b_npred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai", 1>,
220 V6_vS32b_npred_ai_128B_enc;
222 let isNVStorable = 1, isNonTemporal = 1 in {
223 def V6_vS32b_nt_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 0, 1>,
224 V6_vS32b_nt_pred_ai_enc;
225 def V6_vS32b_nt_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1, 1>,
226 V6_vS32b_nt_npred_ai_enc;
228 def V6_vS32b_nt_pred_ai_128B : T_vstore_pred_ai_128B
229 <"vmem", "vS32b_ai", 0, 1>,
230 V6_vS32b_nt_pred_ai_128B_enc;
231 def V6_vS32b_nt_npred_ai_128B : T_vstore_pred_ai_128B
232 <"vmem", "vS32b_ai", 1, 1>,
233 V6_vS32b_nt_npred_ai_128B_enc;
236 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
237 def V6_vS32Ub_pred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai">,
238 V6_vS32Ub_pred_ai_enc;
239 def V6_vS32Ub_npred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai", 1>,
240 V6_vS32Ub_npred_ai_enc;
242 def V6_vS32Ub_pred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai">,
243 V6_vS32Ub_pred_ai_128B_enc;
244 def V6_vS32Ub_npred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai", 1>,
245 V6_vS32Ub_npred_ai_128B_enc;
248 //===----------------------------------------------------------------------===//
249 // Vector stores with base + immediate offset - byte-enabled aligned
250 //===----------------------------------------------------------------------===//
251 let addrMode = BaseImmOffset in
252 class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
253 bit isPredNot = 0, bit isNT = 0>
255 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
256 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
257 #!if(isNT, ":nt", "")#" = $src4"> {
258 let isPredicatedFalse = isPredNot;
261 let accessSize = Vector64Access in
262 class T_vstore_qpred_ai_64B <bit isPredNot = 0, bit isNT = 0>
263 : T_vstore_qpred_ai <s4_6Imm, VectorRegs, isPredNot, isNT>;
265 let isCodeGenOnly = 1, accessSize = Vector128Access in
266 class T_vstore_qpred_ai_128B <bit isPredNot = 0, bit isNT = 0>
267 : T_vstore_qpred_ai <s4_7Imm, VectorRegs128B, isPredNot, isNT>;
269 def V6_vS32b_qpred_ai : T_vstore_qpred_ai_64B, V6_vS32b_qpred_ai_enc;
270 def V6_vS32b_nqpred_ai : T_vstore_qpred_ai_64B <1>,
271 V6_vS32b_nqpred_ai_enc;
272 def V6_vS32b_nt_qpred_ai : T_vstore_qpred_ai_64B <0, 1>,
273 V6_vS32b_nt_qpred_ai_enc;
274 def V6_vS32b_nt_nqpred_ai : T_vstore_qpred_ai_64B <1, 1>,
275 V6_vS32b_nt_nqpred_ai_enc;
277 def V6_vS32b_qpred_ai_128B : T_vstore_qpred_ai_128B, V6_vS32b_qpred_ai_128B_enc;
278 def V6_vS32b_nqpred_ai_128B : T_vstore_qpred_ai_128B<1>,
279 V6_vS32b_nqpred_ai_128B_enc;
280 def V6_vS32b_nt_qpred_ai_128B : T_vstore_qpred_ai_128B<0, 1>,
281 V6_vS32b_nt_qpred_ai_128B_enc;
282 def V6_vS32b_nt_nqpred_ai_128B : T_vstore_qpred_ai_128B<1, 1>,
283 V6_vS32b_nt_nqpred_ai_128B_enc;
286 //===----------------------------------------------------------------------===//
287 // Vector stores with base + immediate offset - conditional new
288 //===----------------------------------------------------------------------===//
289 let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3,
290 isNVStore = 1, Type = TypeCVI_VM_NEW_ST, Itinerary = CVI_VM_NEW_ST in
291 class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
292 bit isPredNot, bit isNT>
294 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
295 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
296 #!if(isNT, ":nt", "")#" = $src4.new">, NewValueRel {
297 let isPredicatedFalse = isPredNot;
298 let BaseOpcode = baseOp;
301 let accessSize = Vector64Access in
302 class T_vstore_new_pred_ai_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
303 : T_vstore_new_pred_ai <baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
305 let isCodeGenOnly = 1, accessSize = Vector128Access in
306 class T_vstore_new_pred_ai_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
307 : T_vstore_new_pred_ai <baseOp#"128B", s4_7Imm, VectorRegs128B,
311 def V6_vS32b_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai">,
312 V6_vS32b_new_pred_ai_enc;
313 def V6_vS32b_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1>,
314 V6_vS32b_new_npred_ai_enc;
316 def V6_vS32b_new_pred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai">,
317 V6_vS32b_new_pred_ai_128B_enc;
318 def V6_vS32b_new_npred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai", 1>,
319 V6_vS32b_new_npred_ai_128B_enc;
320 let isNonTemporal = 1 in {
321 def V6_vS32b_nt_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 0, 1>,
322 V6_vS32b_nt_new_pred_ai_enc;
323 def V6_vS32b_nt_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1, 1>,
324 V6_vS32b_nt_new_npred_ai_enc;
326 def V6_vS32b_nt_new_pred_ai_128B : T_vstore_new_pred_ai_128B
328 V6_vS32b_nt_new_pred_ai_128B_enc;
329 def V6_vS32b_nt_new_npred_ai_128B : T_vstore_new_pred_ai_128B
331 V6_vS32b_nt_new_npred_ai_128B_enc;
334 //===----------------------------------------------------------------------===//
335 // Post increment vector loads with immediate offset.
336 //===----------------------------------------------------------------------===//
337 let addrMode = PostInc, hasNewValue = 1 in
338 class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC>
339 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
340 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
343 let accessSize = Vector64Access in
344 class T_vload_pi_64B <string asmStr>
345 : T_vload_pi <asmStr, s3_6Imm, VectorRegs>;
347 let isCodeGenOnly = 1, accessSize = Vector128Access in
348 class T_vload_pi_128B <string asmStr>
349 : T_vload_pi <asmStr, s3_7Imm, VectorRegs128B>;
351 let isCVLoadable = 1 in {
352 def V6_vL32b_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2)">,
354 def V6_vL32b_nt_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2):nt">,
357 def V6_vL32b_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2)">,
358 V6_vL32b_pi_128B_enc;
359 def V6_vL32b_nt_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2):nt">,
360 V6_vL32b_nt_pi_128B_enc;
363 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in {
364 def V6_vL32Ub_pi : T_vload_pi_64B <"$dst = vmemu($src1++#$src2)">,
367 def V6_vL32Ub_pi_128B : T_vload_pi_128B <"$dst = vmemu($src1++#$src2)">,
368 V6_vL32Ub_pi_128B_enc;
371 let isCVLoad = 1, Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD in {
372 def V6_vL32b_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2)">,
374 def V6_vL32b_nt_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2):nt">,
375 V6_vL32b_nt_cur_pi_enc;
377 def V6_vL32b_cur_pi_128B : T_vload_pi_128B
378 <"$dst.cur = vmem($src1++#$src2)">,
379 V6_vL32b_cur_pi_128B_enc;
380 def V6_vL32b_nt_cur_pi_128B : T_vload_pi_128B
381 <"$dst.cur = vmem($src1++#$src2):nt">,
382 V6_vL32b_nt_cur_pi_128B_enc;
385 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
386 def V6_vL32b_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2)">,
388 def V6_vL32b_nt_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2):nt">,
389 V6_vL32b_nt_tmp_pi_enc;
391 def V6_vL32b_tmp_pi_128B : T_vload_pi_128B
392 <"$dst.tmp = vmem($src1++#$src2)">,
393 V6_vL32b_tmp_pi_128B_enc;
394 def V6_vL32b_nt_tmp_pi_128B : T_vload_pi_128B
395 <"$dst.tmp = vmem($src1++#$src2):nt">,
396 V6_vL32b_nt_tmp_pi_128B_enc;
399 //===----------------------------------------------------------------------===//
400 // Post increment vector stores with immediate offset.
401 //===----------------------------------------------------------------------===//
402 let addrMode = PostInc, isPredicable = 1 in
403 class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp,
404 RegisterClass RC, bit isNT>
405 : V6_STInst <(outs IntRegs:$_dst_),
406 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
407 mnemonic#"($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
408 "$src1 = $_dst_">, NewValueRel {
409 let BaseOpcode = baseOp;
412 let accessSize = Vector64Access in
413 class T_vstore_pi_64B <string mnemonic, string baseOp, bit isNT = 0>
414 : T_vstore_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isNT>;
416 let isCodeGenOnly = 1, accessSize = Vector128Access in
417 class T_vstore_pi_128B <string mnemonic, string baseOp, bit isNT = 0>
418 : T_vstore_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>;
420 let isNVStorable = 1 in {
421 def V6_vS32b_pi : T_vstore_pi_64B <"vmem", "vS32b_pi">, V6_vS32b_pi_enc;
422 def V6_vS32b_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi">,
423 V6_vS32b_pi_128B_enc;
426 let isNVStorable = 1 , isNonTemporal = 1 in {
427 def V6_vS32b_nt_pi : T_vstore_pi_64B <"vmem", "vS32b_pi", 1>,
429 def V6_vS32b_nt_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi", 1>,
430 V6_vS32b_nt_pi_128B_enc;
434 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
435 def V6_vS32Ub_pi : T_vstore_pi_64B <"vmemu", "vS32Ub_pi">,
437 def V6_vS32Ub_pi_128B : T_vstore_pi_128B <"vmemu", "vS32Ub_pi">,
438 V6_vS32Ub_pi_128B_enc;
441 //===----------------------------------------------------------------------===//
442 // Post increment unconditional .new vector stores with immediate offset.
443 //===----------------------------------------------------------------------===//
444 let addrMode = PostInc, isNVStore = 1 in
445 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
446 isPredicable = 1, opNewValue = 3, isNVStore = 1 in
447 class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
448 : V6_STInst <(outs IntRegs:$_dst_),
449 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
450 "vmem($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
451 "$src1 = $_dst_">, NewValueRel {
452 let BaseOpcode = baseOp;
455 let accessSize = Vector64Access in
456 class T_vstore_new_pi_64B <string baseOp, bit isNT = 0>
457 : T_vstore_new_pi <baseOp, s3_6Imm, VectorRegs, isNT>;
459 let isCodeGenOnly = 1, accessSize = Vector128Access in
460 class T_vstore_new_pi_128B <string baseOp, bit isNT = 0>
461 : T_vstore_new_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>;
464 def V6_vS32b_new_pi : T_vstore_new_pi_64B <"vS32b_pi">,
466 def V6_vS32b_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi">,
467 V6_vS32b_new_pi_128B_enc;
469 let isNonTemporal = 1 in {
470 def V6_vS32b_nt_new_pi : T_vstore_new_pi_64B <"vS32b_pi", 1>,
471 V6_vS32b_nt_new_pi_enc;
472 def V6_vS32b_nt_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi", 1>,
473 V6_vS32b_nt_new_pi_128B_enc;
476 //===----------------------------------------------------------------------===//
477 // Post increment conditional vector stores with immediate offset
478 //===----------------------------------------------------------------------===//
479 let isPredicated = 1, addrMode = PostInc in
480 class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp,
481 RegisterClass RC, bit isPredNot, bit isNT>
482 : V6_STInst<(outs IntRegs:$_dst_),
483 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
484 "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++#$src3)"
485 #!if(isNT, ":nt", "")#" = $src4", [],
486 "$src2 = $_dst_">, NewValueRel {
487 let isPredicatedFalse = isPredNot;
488 let BaseOpcode = baseOp;
491 let accessSize = Vector64Access in
492 class T_vstore_pred_pi_64B <string mnemonic, string baseOp,
493 bit isPredNot = 0, bit isNT = 0>
494 : T_vstore_pred_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
496 let isCodeGenOnly = 1, accessSize = Vector128Access in
497 class T_vstore_pred_pi_128B <string mnemonic, string baseOp,
498 bit isPredNot = 0, bit isNT = 0>
499 : T_vstore_pred_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B,
502 let isNVStorable = 1 in {
503 def V6_vS32b_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi">,
504 V6_vS32b_pred_pi_enc;
505 def V6_vS32b_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1>,
506 V6_vS32b_npred_pi_enc;
508 def V6_vS32b_pred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi">,
509 V6_vS32b_pred_pi_128B_enc;
510 def V6_vS32b_npred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi", 1>,
511 V6_vS32b_npred_pi_128B_enc;
513 let isNVStorable = 1, isNonTemporal = 1 in {
514 def V6_vS32b_nt_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 0, 1>,
515 V6_vS32b_nt_pred_pi_enc;
516 def V6_vS32b_nt_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1, 1>,
517 V6_vS32b_nt_npred_pi_enc;
519 def V6_vS32b_nt_pred_pi_128B : T_vstore_pred_pi_128B
520 <"vmem", "vS32b_pi", 0, 1>,
521 V6_vS32b_nt_pred_pi_128B_enc;
522 def V6_vS32b_nt_npred_pi_128B : T_vstore_pred_pi_128B
523 <"vmem", "vS32b_pi", 1, 1>,
524 V6_vS32b_nt_npred_pi_128B_enc;
527 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
528 def V6_vS32Ub_pred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi">,
529 V6_vS32Ub_pred_pi_enc;
530 def V6_vS32Ub_npred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi", 1>,
531 V6_vS32Ub_npred_pi_enc;
533 def V6_vS32Ub_pred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi">,
534 V6_vS32Ub_pred_pi_128B_enc;
535 def V6_vS32Ub_npred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi", 1>,
536 V6_vS32Ub_npred_pi_128B_enc;
539 //===----------------------------------------------------------------------===//
540 // Post increment vector stores with immediate offset - byte-enabled aligned
541 //===----------------------------------------------------------------------===//
542 let addrMode = PostInc in
543 class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0,
545 : V6_STInst <(outs IntRegs:$_dst_),
546 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
547 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
548 #!if(isNT, ":nt", "")#" = $src4", [],
551 let accessSize = Vector64Access in
552 class T_vstore_qpred_pi_64B <bit isPredNot = 0, bit isNT = 0>
553 : T_vstore_qpred_pi <s3_6Imm, VectorRegs, isPredNot, isNT>;
555 let isCodeGenOnly = 1, accessSize = Vector128Access in
556 class T_vstore_qpred_pi_128B <bit isPredNot = 0, bit isNT = 0>
557 : T_vstore_qpred_pi <s3_7Imm, VectorRegs128B, isPredNot, isNT>;
559 def V6_vS32b_qpred_pi : T_vstore_qpred_pi_64B, V6_vS32b_qpred_pi_enc;
560 def V6_vS32b_nqpred_pi : T_vstore_qpred_pi_64B <1>, V6_vS32b_nqpred_pi_enc;
562 def V6_vS32b_qpred_pi_128B : T_vstore_qpred_pi_128B,
563 V6_vS32b_qpred_pi_128B_enc;
564 def V6_vS32b_nqpred_pi_128B : T_vstore_qpred_pi_128B<1>,
565 V6_vS32b_nqpred_pi_128B_enc;
567 let isNonTemporal = 1 in {
568 def V6_vS32b_nt_qpred_pi : T_vstore_qpred_pi_64B <0, 1>,
569 V6_vS32b_nt_qpred_pi_enc;
570 def V6_vS32b_nt_nqpred_pi : T_vstore_qpred_pi_64B <1, 1>,
571 V6_vS32b_nt_nqpred_pi_enc;
573 def V6_vS32b_nt_qpred_pi_128B : T_vstore_qpred_pi_128B<0, 1>,
574 V6_vS32b_nt_qpred_pi_128B_enc;
575 def V6_vS32b_nt_nqpred_pi_128B : T_vstore_qpred_pi_128B<1, 1>,
576 V6_vS32b_nt_nqpred_pi_128B_enc;
579 //===----------------------------------------------------------------------===//
580 // Post increment conditional .new vector stores with immediate offset
581 //===----------------------------------------------------------------------===//
582 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
583 isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in
584 class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC,
585 bit isPredNot, bit isNT>
586 : V6_STInst <(outs IntRegs:$_dst_),
587 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
588 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
589 #!if(isNT, ":nt", "")#" = $src4.new", [],
590 "$src2 = $_dst_"> , NewValueRel {
591 let isPredicatedFalse = isPredNot;
592 let BaseOpcode = baseOp;
595 let accessSize = Vector64Access in
596 class T_vstore_new_pred_pi_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
597 : T_vstore_new_pred_pi <baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
599 let isCodeGenOnly = 1, accessSize = Vector128Access in
600 class T_vstore_new_pred_pi_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
601 : T_vstore_new_pred_pi <baseOp#"128B", s3_7Imm, VectorRegs128B,
604 def V6_vS32b_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi">,
605 V6_vS32b_new_pred_pi_enc;
606 def V6_vS32b_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1>,
607 V6_vS32b_new_npred_pi_enc;
609 def V6_vS32b_new_pred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi">,
610 V6_vS32b_new_pred_pi_128B_enc;
611 def V6_vS32b_new_npred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi", 1>,
612 V6_vS32b_new_npred_pi_128B_enc;
613 let isNonTemporal = 1 in {
614 def V6_vS32b_nt_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 0, 1>,
615 V6_vS32b_nt_new_pred_pi_enc;
616 def V6_vS32b_nt_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1, 1>,
617 V6_vS32b_nt_new_npred_pi_enc;
619 def V6_vS32b_nt_new_pred_pi_128B : T_vstore_new_pred_pi_128B
621 V6_vS32b_nt_new_pred_pi_128B_enc;
622 def V6_vS32b_nt_new_npred_pi_128B : T_vstore_new_pred_pi_128B
624 V6_vS32b_nt_new_npred_pi_128B_enc;
627 //===----------------------------------------------------------------------===//
628 // Post increment vector loads with register offset
629 //===----------------------------------------------------------------------===//
630 let hasNewValue = 1 in
631 class T_vload_ppu<string asmStr>
632 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
633 (ins IntRegs:$src1, ModRegs:$src2), asmStr, [],
634 "$src1 = $_dst_">, NewValueRel;
636 let isCVLoadable = 1 in {
637 def V6_vL32b_ppu : T_vload_ppu <"$dst = vmem($src1++$src2)">,
639 def V6_vL32b_nt_ppu : T_vload_ppu <"$dst = vmem($src1++$src2):nt">,
643 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in
644 def V6_vL32Ub_ppu : T_vload_ppu <"$dst = vmemu($src1++$src2)">,
647 let isCVLoad = 1, Itinerary = CVI_VM_CUR_LD, Type = TypeCVI_VM_CUR_LD in {
648 def V6_vL32b_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2)">,
649 V6_vL32b_cur_ppu_enc;
650 def V6_vL32b_nt_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2):nt">,
651 V6_vL32b_nt_cur_ppu_enc;
654 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
655 def V6_vL32b_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2)">,
656 V6_vL32b_tmp_ppu_enc;
657 def V6_vL32b_nt_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2):nt">,
658 V6_vL32b_nt_tmp_ppu_enc;
661 //===----------------------------------------------------------------------===//
662 // Post increment vector stores with register offset
663 //===----------------------------------------------------------------------===//
664 let isPredicable = 1 in
665 class T_vstore_ppu <string mnemonic, bit isNT = 0>
666 : V6_STInst <(outs IntRegs:$_dst_),
667 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
668 mnemonic#"($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
669 "$src1 = $_dst_">, NewValueRel;
671 let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
672 def V6_vS32b_ppu : T_vstore_ppu <"vmem">,
674 let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in
675 def V6_vS32b_nt_ppu : T_vstore_ppu <"vmem", 1>,
679 let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in
680 def V6_vS32Ub_ppu : T_vstore_ppu <"vmemu">, V6_vS32Ub_ppu_enc;
682 //===----------------------------------------------------------------------===//
683 // Post increment .new vector stores with register offset
684 //===----------------------------------------------------------------------===//
685 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
686 isPredicable = 1, opNewValue = 3, isNVStore = 1 in
687 class T_vstore_new_ppu <bit isNT = 0>
688 : V6_STInst <(outs IntRegs:$_dst_),
689 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
690 "vmem($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
691 "$src1 = $_dst_">, NewValueRel;
693 let BaseOpcode = "vS32b_ppu" in
694 def V6_vS32b_new_ppu : T_vstore_new_ppu, V6_vS32b_new_ppu_enc;
696 let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in
697 def V6_vS32b_nt_new_ppu : T_vstore_new_ppu<1>, V6_vS32b_nt_new_ppu_enc;
699 //===----------------------------------------------------------------------===//
700 // Post increment conditional .new vector stores with register offset
701 //===----------------------------------------------------------------------===//
702 let isPredicated = 1 in
703 class T_vstore_pred_ppu <string mnemonic, bit isPredNot = 0, bit isNT = 0>
704 : V6_STInst<(outs IntRegs:$_dst_),
705 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
706 "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++$src3)"
707 #!if(isNT, ":nt", "")#" = $src4", [],
708 "$src2 = $_dst_">, NewValueRel {
709 let isPredicatedFalse = isPredNot;
712 let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
713 def V6_vS32b_pred_ppu : T_vstore_pred_ppu<"vmem">, V6_vS32b_pred_ppu_enc;
714 def V6_vS32b_npred_ppu: T_vstore_pred_ppu<"vmem", 1>, V6_vS32b_npred_ppu_enc;
717 let isNVStorable = 1, BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
718 def V6_vS32b_nt_pred_ppu : T_vstore_pred_ppu <"vmem", 0, 1>,
719 V6_vS32b_nt_pred_ppu_enc;
720 def V6_vS32b_nt_npred_ppu : T_vstore_pred_ppu <"vmem", 1, 1>,
721 V6_vS32b_nt_npred_ppu_enc;
724 let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU,
725 Type = TypeCVI_VM_STU in {
726 def V6_vS32Ub_pred_ppu : T_vstore_pred_ppu <"vmemu">,
727 V6_vS32Ub_pred_ppu_enc;
728 def V6_vS32Ub_npred_ppu : T_vstore_pred_ppu <"vmemu", 1>,
729 V6_vS32Ub_npred_ppu_enc;
732 //===----------------------------------------------------------------------===//
733 // Post increment vector stores with register offset - byte-enabled aligned
734 //===----------------------------------------------------------------------===//
735 class T_vstore_qpred_ppu <bit isPredNot = 0, bit isNT = 0>
736 : V6_STInst <(outs IntRegs:$_dst_),
737 (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
738 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
739 #!if(isNT, ":nt", "")#" = $src4", [],
740 "$src2 = $_dst_">, NewValueRel;
742 def V6_vS32b_qpred_ppu : T_vstore_qpred_ppu, V6_vS32b_qpred_ppu_enc;
743 def V6_vS32b_nqpred_ppu : T_vstore_qpred_ppu<1>, V6_vS32b_nqpred_ppu_enc;
744 def V6_vS32b_nt_qpred_ppu : T_vstore_qpred_ppu<0, 1>,
745 V6_vS32b_nt_qpred_ppu_enc;
746 def V6_vS32b_nt_nqpred_ppu : T_vstore_qpred_ppu<1, 1>,
747 V6_vS32b_nt_nqpred_ppu_enc;
749 //===----------------------------------------------------------------------===//
750 // Post increment conditional .new vector stores with register offset
751 //===----------------------------------------------------------------------===//
752 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
753 isNewValue = 1, opNewValue = 4, isNVStore = 1 in
754 class T_vstore_new_pred_ppu <bit isPredNot = 0, bit isNT = 0>
755 : V6_STInst <(outs IntRegs:$_dst_),
756 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
757 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
758 #!if(isNT, ":nt", "")#" = $src4.new", [],
759 "$src2 = $_dst_">, NewValueRel {
760 let isPredicatedFalse = isPredNot;
763 let BaseOpcode = "vS32b_ppu" in {
764 def V6_vS32b_new_pred_ppu : T_vstore_new_pred_ppu,
765 V6_vS32b_new_pred_ppu_enc;
766 def V6_vS32b_new_npred_ppu : T_vstore_new_pred_ppu<1>,
767 V6_vS32b_new_npred_ppu_enc;
770 let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
771 def V6_vS32b_nt_new_pred_ppu : T_vstore_new_pred_ppu<0, 1>,
772 V6_vS32b_nt_new_pred_ppu_enc;
773 def V6_vS32b_nt_new_npred_ppu : T_vstore_new_pred_ppu<1, 1>,
774 V6_vS32b_nt_new_npred_ppu_enc;
777 let isPseudo = 1, validSubTargets = HasV60SubT in
778 class STrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>:
779 VSTInst<(outs), (ins IntRegs:$addr, ImmOp:$off, RC:$src),
780 #mnemonic#"($addr+#$off) = $src", []>;
782 def STrivv_indexed: STrivv_template<"vvmem", s4_6Imm, VecDblRegs>,
783 Requires<[HasV60T, UseHVXSgl]>;
784 def STrivv_indexed_128B: STrivv_template<"vvmem", s4_7Imm, VecDblRegs128B>,
785 Requires<[HasV60T, UseHVXDbl]>;
787 multiclass STrivv_pats <ValueType VTSgl, ValueType VTDbl> {
788 def : Pat<(store (VTSgl VecDblRegs:$src1), IntRegs:$addr),
789 (STrivv_indexed IntRegs:$addr, #0, (VTSgl VecDblRegs:$src1))>,
790 Requires<[UseHVXSgl]>;
792 def : Pat<(store (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
793 (STrivv_indexed_128B IntRegs:$addr, #0,
794 (VTDbl VecDblRegs128B:$src1))>,
795 Requires<[UseHVXDbl]>;
798 defm : STrivv_pats <v128i8, v256i8>;
799 defm : STrivv_pats <v64i16, v128i16>;
800 defm : STrivv_pats <v32i32, v64i32>;
801 defm : STrivv_pats <v16i64, v32i64>;
804 multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
806 def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
807 (V6_vS32b_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
808 Requires<[UseHVXSgl]>;
809 def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
810 (V6_vS32Ub_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
811 Requires<[UseHVXSgl]>;
813 // 128B Aligned stores
814 def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
815 (V6_vS32b_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
816 Requires<[UseHVXDbl]>;
817 def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
818 (V6_vS32Ub_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
819 Requires<[UseHVXDbl]>;
821 // Fold Add R+IFF into vector store.
822 let AddedComplexity = 10 in {
823 def : Pat<(alignedstore (VTSgl VectorRegs:$src1),
824 (add IntRegs:$src2, s4_6ImmPred:$offset)),
825 (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
826 (VTSgl VectorRegs:$src1))>,
827 Requires<[UseHVXSgl]>;
828 def : Pat<(unalignedstore (VTSgl VectorRegs:$src1),
829 (add IntRegs:$src2, s4_6ImmPred:$offset)),
830 (V6_vS32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset,
831 (VTSgl VectorRegs:$src1))>,
832 Requires<[UseHVXSgl]>;
834 // Fold Add R+IFF into vector store 128B.
835 def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1),
836 (add IntRegs:$src2, s4_7ImmPred:$offset)),
837 (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
838 (VTDbl VectorRegs128B:$src1))>,
839 Requires<[UseHVXDbl]>;
840 def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1),
841 (add IntRegs:$src2, s4_7ImmPred:$offset)),
842 (V6_vS32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
843 (VTDbl VectorRegs128B:$src1))>,
844 Requires<[UseHVXDbl]>;
848 defm : vS32b_ai_pats <v64i8, v128i8>;
849 defm : vS32b_ai_pats <v32i16, v64i16>;
850 defm : vS32b_ai_pats <v16i32, v32i32>;
851 defm : vS32b_ai_pats <v8i64, v16i64>;
853 let isPseudo = 1, validSubTargets = HasV60SubT in
854 class LDrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>
855 : V6_LDInst <(outs RC:$dst), (ins IntRegs:$addr, ImmOp:$off),
856 "$dst="#mnemonic#"($addr+#$off)",
858 Requires<[HasV60T,UseHVXSgl]>;
860 def LDrivv_indexed: LDrivv_template<"vvmem", s4_6Imm, VecDblRegs>;
861 def LDrivv_indexed_128B: LDrivv_template<"vvmem", s4_7Imm, VecDblRegs128B>;
863 multiclass LDrivv_pats <ValueType VTSgl, ValueType VTDbl> {
864 def : Pat < (VTSgl (load IntRegs:$addr)),
865 (LDrivv_indexed IntRegs:$addr, #0) >,
866 Requires<[UseHVXSgl]>;
868 def : Pat < (VTDbl (load IntRegs:$addr)),
869 (LDrivv_indexed_128B IntRegs:$addr, #0) >,
870 Requires<[UseHVXDbl]>;
873 defm : LDrivv_pats <v128i8, v256i8>;
874 defm : LDrivv_pats <v64i16, v128i16>;
875 defm : LDrivv_pats <v32i32, v64i32>;
876 defm : LDrivv_pats <v16i64, v32i64>;
878 multiclass vL32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
880 def : Pat < (VTSgl (alignedload IntRegs:$addr)),
881 (V6_vL32b_ai IntRegs:$addr, #0) >,
882 Requires<[UseHVXSgl]>;
883 def : Pat < (VTSgl (unalignedload IntRegs:$addr)),
884 (V6_vL32Ub_ai IntRegs:$addr, #0) >,
885 Requires<[UseHVXSgl]>;
888 def : Pat < (VTDbl (alignedload IntRegs:$addr)),
889 (V6_vL32b_ai_128B IntRegs:$addr, #0) >,
890 Requires<[UseHVXDbl]>;
891 def : Pat < (VTDbl (unalignedload IntRegs:$addr)),
892 (V6_vL32Ub_ai_128B IntRegs:$addr, #0) >,
893 Requires<[UseHVXDbl]>;
895 // Fold Add R+IFF into vector load.
896 let AddedComplexity = 10 in {
897 def : Pat<(VTDbl (alignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
898 (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
899 Requires<[UseHVXDbl]>;
900 def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
901 (V6_vL32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
902 Requires<[UseHVXDbl]>;
904 def : Pat<(VTSgl (alignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
905 (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
906 Requires<[UseHVXSgl]>;
907 def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
908 (V6_vL32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
909 Requires<[UseHVXSgl]>;
913 defm : vL32b_ai_pats <v64i8, v128i8>;
914 defm : vL32b_ai_pats <v32i16, v64i16>;
915 defm : vL32b_ai_pats <v16i32, v32i32>;
916 defm : vL32b_ai_pats <v8i64, v16i64>;
918 // Store vector predicate pseudo.
919 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
920 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
921 def STriq_pred_V6 : STInst<(outs),
922 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs:$src1),
923 ".error \"should not emit\" ",
925 Requires<[HasV60T,UseHVXSgl]>;
927 def STriq_pred_vec_V6 : STInst<(outs),
928 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
929 ".error \"should not emit\" ",
931 Requires<[HasV60T,UseHVXSgl]>;
933 def STriq_pred_V6_128B : STInst<(outs),
934 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs128B:$src1),
935 ".error \"should not emit\" ",
937 Requires<[HasV60T,UseHVXDbl]>;
939 def STriq_pred_vec_V6_128B : STInst<(outs),
940 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
941 ".error \"should not emit\" ",
943 Requires<[HasV60T,UseHVXDbl]>;
946 // Load vector predicate pseudo.
947 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
948 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
949 def LDriq_pred_V6 : LDInst<(outs VecPredRegs:$dst),
950 (ins IntRegs:$base, s32Imm:$offset),
951 ".error \"should not emit\" ",
953 Requires<[HasV60T,UseHVXSgl]>;
954 def LDriq_pred_vec_V6 : LDInst<(outs VectorRegs:$dst),
955 (ins IntRegs:$base, s32Imm:$offset),
956 ".error \"should not emit\" ",
958 Requires<[HasV60T,UseHVXSgl]>;
959 def LDriq_pred_V6_128B : LDInst<(outs VecPredRegs128B:$dst),
960 (ins IntRegs:$base, s32Imm:$offset),
961 ".error \"should not emit\" ",
963 Requires<[HasV60T,UseHVXDbl]>;
964 def LDriq_pred_vec_V6_128B : LDInst<(outs VectorRegs128B:$dst),
965 (ins IntRegs:$base, s32Imm:$offset),
966 ".error \"should not emit\" ",
968 Requires<[HasV60T,UseHVXDbl]>;
971 // Store vector pseudo.
972 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
973 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
974 def STriv_pseudo_V6 : STInst<(outs),
975 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
976 ".error \"should not emit\" ",
978 Requires<[HasV60T,UseHVXSgl]>;
979 def STriv_pseudo_V6_128B : STInst<(outs),
980 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
981 ".error \"should not emit\" ",
983 Requires<[HasV60T,UseHVXDbl]>;
986 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
987 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
988 def STrivv_pseudo_V6 : STInst<(outs),
989 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs:$src1),
990 ".error \"should not emit\" ",
992 Requires<[HasV60T,UseHVXSgl]>;
993 def STrivv_pseudo_V6_128B : STInst<(outs),
994 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs128B:$src1),
995 ".error \"should not emit\" ",
997 Requires<[HasV60T,UseHVXDbl]>;
1000 // Load vector pseudo.
1001 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1002 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
1003 def LDriv_pseudo_V6 : LDInst<(outs VectorRegs:$dst),
1004 (ins IntRegs:$base, s32Imm:$offset),
1005 ".error \"should not emit\" ",
1007 Requires<[HasV60T,UseHVXSgl]>;
1008 def LDriv_pseudo_V6_128B : LDInst<(outs VectorRegs128B:$dst),
1009 (ins IntRegs:$base, s32Imm:$offset),
1010 ".error \"should not emit\" ",
1012 Requires<[HasV60T,UseHVXDbl]>;
1015 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1016 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
1017 def LDrivv_pseudo_V6 : LDInst<(outs VecDblRegs:$dst),
1018 (ins IntRegs:$base, s32Imm:$offset),
1019 ".error \"should not emit\" ",
1021 Requires<[HasV60T,UseHVXSgl]>;
1022 def LDrivv_pseudo_V6_128B : LDInst<(outs VecDblRegs128B:$dst),
1023 (ins IntRegs:$base, s32Imm:$offset),
1024 ".error \"should not emit\" ",
1026 Requires<[HasV60T,UseHVXDbl]>;
1029 class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
1030 string cstr = "", InstrItinClass itin = CVI_VA_DV,
1031 IType type = TypeCVI_VA_DV>
1032 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
1034 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
1035 def VSelectPseudo_V6 : VSELInst<(outs VectorRegs:$dst),
1036 (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
1037 ".error \"should not emit\" ",
1039 Requires<[HasV60T,UseHVXSgl]>;
1040 def VSelectDblPseudo_V6 : VSELInst<(outs VecDblRegs:$dst),
1041 (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3),
1042 ".error \"should not emit\" ",
1044 Requires<[HasV60T,UseHVXSgl]>;
1047 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs),
1048 (v16i32 VectorRegs:$tval),
1049 (v16i32 VectorRegs:$fval), SETEQ)),
1050 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs),
1051 (i32 IntRegs:$rhs))),
1052 (v16i32 VectorRegs:$tval),
1053 (v16i32 VectorRegs:$fval)))>;
1056 let hasNewValue = 1 in
1057 class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin>
1058 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
1061 multiclass T_vmpy <string asmString, RegisterClass RCout,
1062 RegisterClass RCin> {
1063 def NAME : T_vmpy <asmString, RCout, RCin>;
1064 let isCodeGenOnly = 1 in
1065 def NAME#_128B : T_vmpy <asmString, !cast<RegisterClass>(RCout#"128B"),
1066 !cast<RegisterClass>(RCin#"128B")>;
1069 multiclass T_vmpy_VV <string asmString>:
1070 T_vmpy <asmString, VectorRegs, VectorRegs>;
1072 multiclass T_vmpy_WW <string asmString>:
1073 T_vmpy <asmString, VecDblRegs, VecDblRegs>;
1075 multiclass T_vmpy_VW <string asmString>:
1076 T_vmpy <asmString, VectorRegs, VecDblRegs>;
1078 multiclass T_vmpy_WV <string asmString>:
1079 T_vmpy <asmString, VecDblRegs, VectorRegs>;
1081 defm V6_vtmpyb :T_vmpy_WW<"$dst.h = vtmpy($src1.b,$src2.b)">, V6_vtmpyb_enc;
1082 defm V6_vtmpybus :T_vmpy_WW<"$dst.h = vtmpy($src1.ub,$src2.b)">, V6_vtmpybus_enc;
1083 defm V6_vdsaduh :T_vmpy_WW<"$dst.uw = vdsad($src1.uh,$src2.uh)">, V6_vdsaduh_enc;
1084 defm V6_vmpybus :T_vmpy_WV<"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybus_enc;
1085 defm V6_vmpabus :T_vmpy_WW<"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabus_enc;
1086 defm V6_vmpahb :T_vmpy_WW<"$dst.w = vmpa($src1.h,$src2.b)">, V6_vmpahb_enc;
1087 defm V6_vmpyh :T_vmpy_WV<"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyh_enc;
1088 defm V6_vmpyuh :T_vmpy_WV<"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuh_enc;
1089 defm V6_vmpyiwh :T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_enc;
1090 defm V6_vtmpyhb :T_vmpy_WW<"$dst.w = vtmpy($src1.h,$src2.b)">, V6_vtmpyhb_enc;
1091 defm V6_vmpyub :T_vmpy_WV<"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyub_enc;
1093 let Itinerary = CVI_VX_LONG, Type = TypeCVI_VX in
1094 defm V6_vmpyihb :T_vmpy_VV<"$dst.h = vmpyi($src1.h,$src2.b)">, V6_vmpyihb_enc;
1096 defm V6_vdmpybus_dv :
1097 T_vmpy_WW <"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_dv_enc;
1098 defm V6_vdmpyhsusat :
1099 T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.uh):sat">, V6_vdmpyhsusat_enc;
1100 defm V6_vdmpyhsuisat :
1101 T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.uh,#1):sat">, V6_vdmpyhsuisat_enc;
1103 T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhsat_enc;
1104 defm V6_vdmpyhisat :
1105 T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhisat_enc;
1106 defm V6_vdmpyhb_dv :
1107 T_vmpy_WW <"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_dv_enc;
1109 T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:sat">, V6_vmpyhss_enc;
1111 T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhsrs_enc;
1113 let Itinerary = CVI_VP, Type = TypeCVI_VP in
1114 defm V6_vror : T_vmpy_VV <"$dst = vror($src1,$src2)">, V6_vror_enc;
1116 let Itinerary = CVI_VX, Type = TypeCVI_VX in {
1117 defm V6_vdmpyhb : T_vmpy_VV<"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_enc;
1118 defm V6_vrmpybus : T_vmpy_VV<"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybus_enc;
1119 defm V6_vdmpybus : T_vmpy_VV<"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_enc;
1120 defm V6_vmpyiwb : T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.b)">, V6_vmpyiwb_enc;
1121 defm V6_vrmpyub : T_vmpy_VV<"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyub_enc;
1124 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1125 defm V6_vasrw : T_vmpy_VV <"$dst.w = vasr($src1.w,$src2)">, V6_vasrw_enc;
1126 defm V6_vasrh : T_vmpy_VV <"$dst.h = vasr($src1.h,$src2)">, V6_vasrh_enc;
1127 defm V6_vaslw : T_vmpy_VV <"$dst.w = vasl($src1.w,$src2)">, V6_vaslw_enc;
1128 defm V6_vaslh : T_vmpy_VV <"$dst.h = vasl($src1.h,$src2)">, V6_vaslh_enc;
1129 defm V6_vlsrw : T_vmpy_VV <"$dst.uw = vlsr($src1.uw,$src2)">, V6_vlsrw_enc;
1130 defm V6_vlsrh : T_vmpy_VV <"$dst.uh = vlsr($src1.uh,$src2)">, V6_vlsrh_enc;
1133 let hasNewValue = 1 in
1134 class T_HVX_alu <string asmString, InstrItinClass itin,
1135 RegisterClass RCout, RegisterClass RCin>
1136 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
1138 let Itinerary = itin;
1139 let Type = !cast<IType>("Type"#itin);
1142 multiclass T_HVX_alu <string asmString, RegisterClass RCout,
1143 RegisterClass RCin, InstrItinClass itin> {
1144 def NAME : T_HVX_alu <asmString, itin, RCout, RCin>;
1145 let isCodeGenOnly = 1 in
1146 def NAME#_128B : T_HVX_alu <asmString, itin,
1147 !cast<RegisterClass>(RCout#"128B"),
1148 !cast<RegisterClass>(RCin#"128B")>;
1151 multiclass T_HVX_alu_VV <string asmString>:
1152 T_HVX_alu <asmString, VectorRegs, VectorRegs, CVI_VA>;
1154 multiclass T_HVX_alu_WW <string asmString>:
1155 T_HVX_alu <asmString, VecDblRegs, VecDblRegs, CVI_VA_DV>;
1157 multiclass T_HVX_alu_WV <string asmString>:
1158 T_HVX_alu <asmString, VecDblRegs, VectorRegs, CVI_VX_DV>;
1161 let Itinerary = CVI_VX, Type = TypeCVI_VX in {
1163 T_HVX_alu_VV <"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyubv_enc;
1165 T_HVX_alu_VV <"$dst.w = vrmpy($src1.b,$src2.b)">, V6_vrmpybv_enc;
1167 T_HVX_alu_VV <"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybusv_enc;
1168 defm V6_vabsdiffub :
1169 T_HVX_alu_VV <"$dst.ub = vabsdiff($src1.ub,$src2.ub)">, V6_vabsdiffub_enc;
1171 T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.h,$src2.h)">, V6_vabsdiffh_enc;
1172 defm V6_vabsdiffuh :
1173 T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.uh,$src2.uh)">, V6_vabsdiffuh_enc;
1175 T_HVX_alu_VV <"$dst.uw = vabsdiff($src1.w,$src2.w)">, V6_vabsdiffw_enc;
1178 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1179 defm V6_vdmpyhvsat :
1180 T_HVX_alu_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhvsat_enc;
1182 T_HVX_alu_VV<"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhvsrs_enc;
1184 T_HVX_alu_VV <"$dst.h = vmpyi($src1.h,$src2.h)">, V6_vmpyih_enc;
1188 T_HVX_alu_VV <"$dst = vand($src1,$src2)">, V6_vand_enc;
1190 T_HVX_alu_VV <"$dst = vor($src1,$src2)">, V6_vor_enc;
1192 T_HVX_alu_VV <"$dst = vxor($src1,$src2)">, V6_vxor_enc;
1194 T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_enc;
1196 T_HVX_alu_VV <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_enc;
1198 T_HVX_alu_VV <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_enc;
1200 T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_enc;
1202 T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_enc;
1204 T_HVX_alu_VV <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_enc;
1206 T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_enc;
1208 T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_enc;
1210 T_HVX_alu_VV <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_enc;
1212 T_HVX_alu_VV <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_enc;
1214 T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_enc;
1216 T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_enc;
1218 T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub)">, V6_vavgub_enc;
1220 T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh)">, V6_vavguh_enc;
1222 T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h)">, V6_vavgh_enc;
1224 T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w)">, V6_vavgw_enc;
1226 T_HVX_alu_VV <"$dst.b = vnavg($src1.ub,$src2.ub)">, V6_vnavgub_enc;
1228 T_HVX_alu_VV <"$dst.h = vnavg($src1.h,$src2.h)">, V6_vnavgh_enc;
1230 T_HVX_alu_VV <"$dst.w = vnavg($src1.w,$src2.w)">, V6_vnavgw_enc;
1232 T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub):rnd">, V6_vavgubrnd_enc;
1234 T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh):rnd">, V6_vavguhrnd_enc;
1236 T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h):rnd">, V6_vavghrnd_enc;
1238 T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w):rnd">, V6_vavgwrnd_enc;
1241 T_HVX_alu_WV <"$dst.h = vmpy($src1.b,$src2.b)">, V6_vmpybv_enc;
1243 T_HVX_alu_WV <"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyubv_enc;
1245 T_HVX_alu_WV <"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybusv_enc;
1247 T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyhv_enc;
1249 T_HVX_alu_WV <"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuhv_enc;
1251 T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.uh)">, V6_vmpyhus_enc;
1253 T_HVX_alu_WV <"$dst.h = vadd($src1.ub,$src2.ub)">, V6_vaddubh_enc;
1255 T_HVX_alu_WV <"$dst.w = vadd($src1.uh,$src2.uh)">, V6_vadduhw_enc;
1257 T_HVX_alu_WV <"$dst.w = vadd($src1.h,$src2.h)">, V6_vaddhw_enc;
1259 T_HVX_alu_WV <"$dst.h = vsub($src1.ub,$src2.ub)">, V6_vsububh_enc;
1261 T_HVX_alu_WV <"$dst.w = vsub($src1.uh,$src2.uh)">, V6_vsubuhw_enc;
1263 T_HVX_alu_WV <"$dst.w = vsub($src1.h,$src2.h)">, V6_vsubhw_enc;
1266 T_HVX_alu_WW <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_dv_enc;
1268 T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_dv_enc;
1270 T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_dv_enc;
1271 defm V6_vaddubsat_dv :
1272 T_HVX_alu_WW <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_dv_enc;
1273 defm V6_vadduhsat_dv :
1274 T_HVX_alu_WW <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_dv_enc;
1275 defm V6_vaddhsat_dv :
1276 T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_dv_enc;
1277 defm V6_vaddwsat_dv :
1278 T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_dv_enc;
1280 T_HVX_alu_WW <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_dv_enc;
1282 T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_dv_enc;
1284 T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_dv_enc;
1285 defm V6_vsububsat_dv :
1286 T_HVX_alu_WW <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_dv_enc;
1287 defm V6_vsubuhsat_dv :
1288 T_HVX_alu_WW <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_dv_enc;
1289 defm V6_vsubhsat_dv :
1290 T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_dv_enc;
1291 defm V6_vsubwsat_dv :
1292 T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_dv_enc;
1294 let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV in {
1296 T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabusv_enc;
1298 T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.ub)">, V6_vmpabuuv_enc;
1301 let isAccumulator = 1, hasNewValue = 1 in
1302 class T_HVX_vmpyacc <string asmString, InstrItinClass itin, RegisterClass RCout,
1303 RegisterClass RCin1, RegisterClass RCin2>
1304 : CVI_VA_Resource1 <(outs RCout:$dst),
1305 (ins RCout:$_src_, RCin1:$src1, RCin2:$src2), asmString,
1306 [], "$dst = $_src_" > {
1307 let Itinerary = itin;
1308 let Type = !cast<IType>("Type"#itin);
1311 multiclass T_HVX_vmpyacc_both <string asmString, RegisterClass RCout,
1312 RegisterClass RCin1, RegisterClass RCin2, InstrItinClass itin > {
1313 def NAME : T_HVX_vmpyacc <asmString, itin, RCout, RCin1, RCin2>;
1314 let isCodeGenOnly = 1 in
1315 def NAME#_128B : T_HVX_vmpyacc <asmString, itin,
1316 !cast<RegisterClass>(RCout#"128B"),
1317 !cast<RegisterClass>(RCin1#"128B"),
1318 !cast<RegisterClass>(RCin2#
1319 !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>;
1322 multiclass T_HVX_vmpyacc_VVR <string asmString>:
1323 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>;
1325 multiclass T_HVX_vmpyacc_VWR <string asmString>:
1326 T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1328 multiclass T_HVX_vmpyacc_WVR <string asmString>:
1329 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>;
1331 multiclass T_HVX_vmpyacc_WWR <string asmString>:
1332 T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1334 multiclass T_HVX_vmpyacc_VVV <string asmString>:
1335 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
1337 multiclass T_HVX_vmpyacc_WVV <string asmString>:
1338 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
1341 defm V6_vtmpyb_acc :
1342 T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.b,$src2.b)">,
1344 defm V6_vtmpybus_acc :
1345 T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.ub,$src2.b)">,
1346 V6_vtmpybus_acc_enc;
1347 defm V6_vtmpyhb_acc :
1348 T_HVX_vmpyacc_WWR <"$dst.w += vtmpy($src1.h,$src2.b)">,
1350 defm V6_vdmpyhb_acc :
1351 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.b)">,
1353 defm V6_vrmpyub_acc :
1354 T_HVX_vmpyacc_VVR <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
1356 defm V6_vrmpybus_acc :
1357 T_HVX_vmpyacc_VVR <"$dst.w += vrmpy($src1.ub,$src2.b)">,
1358 V6_vrmpybus_acc_enc;
1359 defm V6_vdmpybus_acc :
1360 T_HVX_vmpyacc_VVR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
1361 V6_vdmpybus_acc_enc;
1362 defm V6_vdmpybus_dv_acc :
1363 T_HVX_vmpyacc_WWR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
1364 V6_vdmpybus_dv_acc_enc;
1365 defm V6_vdmpyhsuisat_acc :
1366 T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.uh,#1):sat">,
1367 V6_vdmpyhsuisat_acc_enc;
1368 defm V6_vdmpyhisat_acc :
1369 T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1370 V6_vdmpyhisat_acc_enc;
1371 defm V6_vdmpyhb_dv_acc :
1372 T_HVX_vmpyacc_WWR <"$dst.w += vdmpy($src1.h,$src2.b)">,
1373 V6_vdmpyhb_dv_acc_enc;
1374 defm V6_vmpybus_acc :
1375 T_HVX_vmpyacc_WVR <"$dst.h += vmpy($src1.ub,$src2.b)">,
1377 defm V6_vmpabus_acc :
1378 T_HVX_vmpyacc_WWR <"$dst.h += vmpa($src1.ub,$src2.b)">,
1380 defm V6_vmpahb_acc :
1381 T_HVX_vmpyacc_WWR <"$dst.w += vmpa($src1.h,$src2.b)">,
1383 defm V6_vmpyhsat_acc :
1384 T_HVX_vmpyacc_WVR <"$dst.w += vmpy($src1.h,$src2.h):sat">,
1385 V6_vmpyhsat_acc_enc;
1386 defm V6_vmpyuh_acc :
1387 T_HVX_vmpyacc_WVR <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
1389 defm V6_vmpyiwb_acc :
1390 T_HVX_vmpyacc_VVR <"$dst.w += vmpyi($src1.w,$src2.b)">,
1392 defm V6_vdsaduh_acc :
1393 T_HVX_vmpyacc_WWR <"$dst.uw += vdsad($src1.uh,$src2.uh)">,
1395 defm V6_vmpyihb_acc :
1396 T_HVX_vmpyacc_VVR <"$dst.h += vmpyi($src1.h,$src2.b)">,
1398 defm V6_vmpyub_acc :
1399 T_HVX_vmpyacc_WVR <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
1402 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1403 defm V6_vdmpyhsusat_acc :
1404 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.uh):sat">,
1405 V6_vdmpyhsusat_acc_enc;
1406 defm V6_vdmpyhsat_acc :
1407 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1408 V6_vdmpyhsat_acc_enc;
1409 defm V6_vmpyiwh_acc : T_HVX_vmpyacc_VVR
1410 <"$dst.w += vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_acc_enc;
1413 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1415 T_HVX_vmpyacc_VVR <"$dst.w += vasl($src1.w,$src2)">, V6_vaslw_acc_enc;
1417 T_HVX_vmpyacc_VVR <"$dst.w += vasr($src1.w,$src2)">, V6_vasrw_acc_enc;
1420 defm V6_vdmpyhvsat_acc :
1421 T_HVX_vmpyacc_VVV <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1422 V6_vdmpyhvsat_acc_enc;
1423 defm V6_vmpybusv_acc :
1424 T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.ub,$src2.b)">,
1425 V6_vmpybusv_acc_enc;
1426 defm V6_vmpybv_acc :
1427 T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.b,$src2.b)">, V6_vmpybv_acc_enc;
1428 defm V6_vmpyhus_acc :
1429 T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.uh)">, V6_vmpyhus_acc_enc;
1430 defm V6_vmpyhv_acc :
1431 T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.h)">, V6_vmpyhv_acc_enc;
1432 defm V6_vmpyiewh_acc :
1433 T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.h)">,
1434 V6_vmpyiewh_acc_enc;
1435 defm V6_vmpyiewuh_acc :
1436 T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.uh)">,
1437 V6_vmpyiewuh_acc_enc;
1438 defm V6_vmpyih_acc :
1439 T_HVX_vmpyacc_VVV <"$dst.h += vmpyi($src1.h,$src2.h)">, V6_vmpyih_acc_enc;
1440 defm V6_vmpyowh_rnd_sacc :
1441 T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:rnd:sat:shift">,
1442 V6_vmpyowh_rnd_sacc_enc;
1443 defm V6_vmpyowh_sacc :
1444 T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:sat:shift">,
1445 V6_vmpyowh_sacc_enc;
1446 defm V6_vmpyubv_acc :
1447 T_HVX_vmpyacc_WVV <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
1449 defm V6_vmpyuhv_acc :
1450 T_HVX_vmpyacc_WVV <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
1452 defm V6_vrmpybusv_acc :
1453 T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.ub,$src2.b)">,
1454 V6_vrmpybusv_acc_enc;
1455 defm V6_vrmpybv_acc :
1456 T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.b,$src2.b)">, V6_vrmpybv_acc_enc;
1457 defm V6_vrmpyubv_acc :
1458 T_HVX_vmpyacc_VVV <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
1459 V6_vrmpyubv_acc_enc;
1462 class T_HVX_vcmp <string asmString, RegisterClass RCout, RegisterClass RCin>
1463 : CVI_VA_Resource1 <(outs RCout:$dst),
1464 (ins RCout:$_src_, RCin:$src1, RCin:$src2), asmString,
1465 [], "$dst = $_src_" > {
1466 let Itinerary = CVI_VA;
1467 let Type = TypeCVI_VA;
1470 multiclass T_HVX_vcmp <string asmString> {
1471 def NAME : T_HVX_vcmp <asmString, VecPredRegs, VectorRegs>;
1472 let isCodeGenOnly = 1 in
1473 def NAME#_128B : T_HVX_vcmp <asmString, VecPredRegs128B, VectorRegs128B>;
1477 T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc;
1479 T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc;
1481 T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc;
1483 T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc;
1485 T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc;
1487 T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc;
1489 T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc;
1491 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc;
1493 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc;
1495 T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc;
1497 T_HVX_vcmp <"$dst |= vcmp.eq($src1.h,$src2.h)">, V6_veqh_or_enc;
1499 T_HVX_vcmp <"$dst |= vcmp.eq($src1.w,$src2.w)">, V6_veqw_or_enc;
1501 T_HVX_vcmp <"$dst |= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_or_enc;
1503 T_HVX_vcmp <"$dst |= vcmp.gt($src1.h,$src2.h)">, V6_vgth_or_enc;
1505 T_HVX_vcmp <"$dst |= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_or_enc;
1507 T_HVX_vcmp <"$dst |= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_or_enc;
1509 T_HVX_vcmp <"$dst |= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_or_enc;
1511 T_HVX_vcmp <"$dst |= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_or_enc;
1513 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.b,$src2.b)">, V6_veqb_xor_enc;
1515 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.h,$src2.h)">, V6_veqh_xor_enc;
1517 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.w,$src2.w)">, V6_veqw_xor_enc;
1519 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_xor_enc;
1521 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.h,$src2.h)">, V6_vgth_xor_enc;
1523 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_xor_enc;
1525 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_xor_enc;
1527 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_xor_enc;
1529 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_xor_enc;
1532 T_HVX_alu_VV <"$dst.ub = vmin($src1.ub,$src2.ub)">, V6_vminub_enc;
1534 T_HVX_alu_VV <"$dst.uh = vmin($src1.uh,$src2.uh)">, V6_vminuh_enc;
1536 T_HVX_alu_VV <"$dst.h = vmin($src1.h,$src2.h)">, V6_vminh_enc;
1538 T_HVX_alu_VV <"$dst.w = vmin($src1.w,$src2.w)">, V6_vminw_enc;
1540 T_HVX_alu_VV <"$dst.ub = vmax($src1.ub,$src2.ub)">, V6_vmaxub_enc;
1542 T_HVX_alu_VV <"$dst.uh = vmax($src1.uh,$src2.uh)">, V6_vmaxuh_enc;
1544 T_HVX_alu_VV <"$dst.h = vmax($src1.h,$src2.h)">, V6_vmaxh_enc;
1546 T_HVX_alu_VV <"$dst.w = vmax($src1.w,$src2.w)">, V6_vmaxw_enc;
1548 T_HVX_alu_VV <"$dst.b = vshuffe($src1.b,$src2.b)">, V6_vshuffeb_enc;
1550 T_HVX_alu_VV <"$dst.b = vshuffo($src1.b,$src2.b)">, V6_vshuffob_enc;
1552 T_HVX_alu_VV <"$dst.h = vshuffe($src1.h,$src2.h)">, V6_vshufeh_enc;
1554 T_HVX_alu_VV <"$dst.h = vshuffo($src1.h,$src2.h)">, V6_vshufoh_enc;
1556 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1557 defm V6_vmpyowh_rnd :
1558 T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:rnd:sat">,
1561 T_HVX_alu_VV <"$dst.w = vmpyie($src1.w,$src2.uh)">, V6_vmpyiewuh_enc;
1563 T_HVX_alu_VV <"$dst.w = vmpye($src1.w,$src2.uh)">, V6_vmpyewuh_enc;
1565 T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:sat">, V6_vmpyowh_enc;
1567 T_HVX_alu_VV <"$dst.w = vmpyio($src1.w,$src2.h)">, V6_vmpyiowh_enc;
1569 let Itinerary = CVI_VX, Type = TypeCVI_VX in
1571 T_HVX_alu_VV <"$dst.w = vmpyieo($src1.h,$src2.h)">, V6_vmpyieoh_enc;
1573 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in {
1575 T_HVX_alu_WV <"$dst.h = vshuffoe($src1.h,$src2.h)">, V6_vshufoeh_enc;
1577 T_HVX_alu_WV <"$dst.b = vshuffoe($src1.b,$src2.b)">, V6_vshufoeb_enc;
1580 let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
1582 T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc;
1584 def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
1585 SDTCisSubVecOfVec<1, 0>]>;
1587 def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
1589 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1590 (v16i32 VectorRegs:$Vt))),
1591 (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>,
1592 Requires<[UseHVXSgl]>;
1593 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
1594 (v32i32 VecDblRegs:$Vt))),
1595 (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>,
1596 Requires<[UseHVXDbl]>;
1598 let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in {
1600 T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc;
1602 T_HVX_alu_VV <"$dst.h = vsat($src1.w,$src2.w)">, V6_vsatwh_enc;
1605 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1607 T_HVX_alu_VV <"$dst.h = vround($src1.w,$src2.w):sat">, V6_vroundwh_enc;
1609 T_HVX_alu_VV <"$dst.uh = vround($src1.w,$src2.w):sat">, V6_vroundwuh_enc;
1611 T_HVX_alu_VV <"$dst.b = vround($src1.h,$src2.h):sat">, V6_vroundhb_enc;
1613 T_HVX_alu_VV <"$dst.ub = vround($src1.h,$src2.h):sat">, V6_vroundhub_enc;
1615 T_HVX_alu_VV <"$dst.w = vasr($src1.w,$src2.w)">, V6_vasrwv_enc;
1617 T_HVX_alu_VV <"$dst.w = vlsr($src1.w,$src2.w)">, V6_vlsrwv_enc;
1619 T_HVX_alu_VV <"$dst.h = vlsr($src1.h,$src2.h)">, V6_vlsrhv_enc;
1621 T_HVX_alu_VV <"$dst.h = vasr($src1.h,$src2.h)">, V6_vasrhv_enc;
1623 T_HVX_alu_VV <"$dst.w = vasl($src1.w,$src2.w)">, V6_vaslwv_enc;
1625 T_HVX_alu_VV <"$dst.h = vasl($src1.h,$src2.h)">, V6_vaslhv_enc;
1629 T_HVX_alu_VV <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_enc;
1631 T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_enc;
1633 let Itinerary = CVI_VP, Type = TypeCVI_VP in {
1635 T_HVX_alu_VV <"$dst = vdelta($src1,$src2)">, V6_vdelta_enc;
1637 T_HVX_alu_VV <"$dst = vrdelta($src1,$src2)">, V6_vrdelta_enc;
1639 T_HVX_alu_VV <"$dst.b = vdeale($src1.b,$src2.b)">, V6_vdealb4w_enc;
1641 T_HVX_alu_VV <"$dst.b = vpacke($src1.h,$src2.h)">, V6_vpackeb_enc;
1643 T_HVX_alu_VV <"$dst.h = vpacke($src1.w,$src2.w)">, V6_vpackeh_enc;
1644 defm V6_vpackhub_sat :
1645 T_HVX_alu_VV <"$dst.ub = vpack($src1.h,$src2.h):sat">, V6_vpackhub_sat_enc;
1646 defm V6_vpackhb_sat :
1647 T_HVX_alu_VV <"$dst.b = vpack($src1.h,$src2.h):sat">, V6_vpackhb_sat_enc;
1648 defm V6_vpackwuh_sat :
1649 T_HVX_alu_VV <"$dst.uh = vpack($src1.w,$src2.w):sat">, V6_vpackwuh_sat_enc;
1650 defm V6_vpackwh_sat :
1651 T_HVX_alu_VV <"$dst.h = vpack($src1.w,$src2.w):sat">, V6_vpackwh_sat_enc;
1653 T_HVX_alu_VV <"$dst.b = vpacko($src1.h,$src2.h)">, V6_vpackob_enc;
1655 T_HVX_alu_VV <"$dst.h = vpacko($src1.w,$src2.w)">, V6_vpackoh_enc;
1658 let hasNewValue = 1, hasSideEffects = 0 in
1659 class T_HVX_condALU <string asmString, RegisterClass RC1, RegisterClass RC2>
1660 : CVI_VA_Resource1 <(outs RC2:$dst),
1661 (ins RC1:$src1, RC2:$_src_, RC2:$src2), asmString,
1662 [], "$dst = $_src_" > {
1663 let Itinerary = CVI_VA;
1664 let Type = TypeCVI_VA;
1667 multiclass T_HVX_condALU <string asmString> {
1668 def NAME : T_HVX_condALU <asmString, VecPredRegs, VectorRegs>;
1669 let isCodeGenOnly = 1 in
1670 def NAME#_128B : T_HVX_condALU <asmString, VecPredRegs128B, VectorRegs128B>;
1673 defm V6_vaddbq : T_HVX_condALU <"if ($src1) $dst.b += $src2.b">,
1675 defm V6_vaddhq : T_HVX_condALU <"if ($src1) $dst.h += $src2.h">,
1677 defm V6_vaddwq : T_HVX_condALU <"if ($src1) $dst.w += $src2.w">,
1679 defm V6_vsubbq : T_HVX_condALU <"if ($src1) $dst.b -= $src2.b">,
1681 defm V6_vsubhq : T_HVX_condALU <"if ($src1) $dst.h -= $src2.h">,
1683 defm V6_vsubwq : T_HVX_condALU <"if ($src1) $dst.w -= $src2.w">,
1685 defm V6_vaddbnq : T_HVX_condALU <"if (!$src1) $dst.b += $src2.b">,
1687 defm V6_vaddhnq : T_HVX_condALU <"if (!$src1) $dst.h += $src2.h">,
1689 defm V6_vaddwnq : T_HVX_condALU <"if (!$src1) $dst.w += $src2.w">,
1691 defm V6_vsubbnq : T_HVX_condALU <"if (!$src1) $dst.b -= $src2.b">,
1693 defm V6_vsubhnq : T_HVX_condALU <"if (!$src1) $dst.h -= $src2.h">,
1695 defm V6_vsubwnq : T_HVX_condALU <"if (!$src1) $dst.w -= $src2.w">,
1698 let hasNewValue = 1 in
1699 class T_HVX_alu_2op <string asmString, InstrItinClass itin,
1700 RegisterClass RCout, RegisterClass RCin>
1701 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1),
1703 let Itinerary = itin;
1704 let Type = !cast<IType>("Type"#itin);
1707 multiclass T_HVX_alu_2op <string asmString, RegisterClass RCout,
1708 RegisterClass RCin, InstrItinClass itin> {
1709 def NAME : T_HVX_alu_2op <asmString, itin, RCout, RCin>;
1710 let isCodeGenOnly = 1 in
1711 def NAME#_128B : T_HVX_alu_2op <asmString, itin,
1712 !cast<RegisterClass>(RCout#"128B"),
1713 !cast<RegisterClass>(RCin#"128B")>;
1716 let hasNewValue = 1 in
1717 multiclass T_HVX_alu_2op_VV <string asmString>:
1718 T_HVX_alu_2op <asmString, VectorRegs, VectorRegs, CVI_VA>;
1720 multiclass T_HVX_alu_2op_WV <string asmString>:
1721 T_HVX_alu_2op <asmString, VecDblRegs, VectorRegs, CVI_VA_DV>;
1724 defm V6_vabsh : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h)">,
1726 defm V6_vabsw : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w)">,
1728 defm V6_vabsh_sat : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h):sat">,
1730 defm V6_vabsw_sat : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w):sat">,
1732 defm V6_vnot : T_HVX_alu_2op_VV <"$dst = vnot($src1)">,
1734 defm V6_vassign : T_HVX_alu_2op_VV <"$dst = $src1">,
1737 defm V6_vzb : T_HVX_alu_2op_WV <"$dst.uh = vzxt($src1.ub)">,
1739 defm V6_vzh : T_HVX_alu_2op_WV <"$dst.uw = vzxt($src1.uh)">,
1741 defm V6_vsb : T_HVX_alu_2op_WV <"$dst.h = vsxt($src1.b)">,
1743 defm V6_vsh : T_HVX_alu_2op_WV <"$dst.w = vsxt($src1.h)">,
1746 let Itinerary = CVI_VP, Type = TypeCVI_VP in {
1747 defm V6_vdealh : T_HVX_alu_2op_VV <"$dst.h = vdeal($src1.h)">,
1749 defm V6_vdealb : T_HVX_alu_2op_VV <"$dst.b = vdeal($src1.b)">,
1751 defm V6_vshuffh : T_HVX_alu_2op_VV <"$dst.h = vshuff($src1.h)">,
1753 defm V6_vshuffb : T_HVX_alu_2op_VV <"$dst.b = vshuff($src1.b)">,
1757 let Itinerary = CVI_VP_VS, Type = TypeCVI_VP_VS in {
1758 defm V6_vunpackub : T_HVX_alu_2op_WV <"$dst.uh = vunpack($src1.ub)">,
1760 defm V6_vunpackuh : T_HVX_alu_2op_WV <"$dst.uw = vunpack($src1.uh)">,
1762 defm V6_vunpackb : T_HVX_alu_2op_WV <"$dst.h = vunpack($src1.b)">,
1764 defm V6_vunpackh : T_HVX_alu_2op_WV <"$dst.w = vunpack($src1.h)">,
1768 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1769 defm V6_vcl0w : T_HVX_alu_2op_VV <"$dst.uw = vcl0($src1.uw)">,
1771 defm V6_vcl0h : T_HVX_alu_2op_VV <"$dst.uh = vcl0($src1.uh)">,
1773 defm V6_vnormamtw : T_HVX_alu_2op_VV <"$dst.w = vnormamt($src1.w)">,
1775 defm V6_vnormamth : T_HVX_alu_2op_VV <"$dst.h = vnormamt($src1.h)">,
1777 defm V6_vpopcounth : T_HVX_alu_2op_VV <"$dst.h = vpopcount($src1.h)">,
1781 let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG,
1782 Type = TypeCVI_VX_DV in
1783 class T_HVX_vmpyacc2 <string asmString, RegisterClass RC>
1784 : CVI_VA_Resource1 <(outs RC:$dst),
1785 (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1Imm:$src3),
1786 asmString, [], "$dst = $_src_" > ;
1789 multiclass T_HVX_vmpyacc2 <string asmString> {
1790 def NAME : T_HVX_vmpyacc2 <asmString, VecDblRegs>;
1792 let isCodeGenOnly = 1 in
1793 def NAME#_128B : T_HVX_vmpyacc2 <asmString, VecDblRegs128B>;
1796 defm V6_vrmpybusi_acc :
1797 T_HVX_vmpyacc2<"$dst.w += vrmpy($src1.ub,$src2.b,#$src3)">,
1798 V6_vrmpybusi_acc_enc;
1799 defm V6_vrsadubi_acc :
1800 T_HVX_vmpyacc2<"$dst.uw += vrsad($src1.ub,$src2.ub,#$src3)">,
1801 V6_vrsadubi_acc_enc;
1802 defm V6_vrmpyubi_acc :
1803 T_HVX_vmpyacc2<"$dst.uw += vrmpy($src1.ub,$src2.ub,#$src3)">,
1804 V6_vrmpyubi_acc_enc;
1807 let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in
1808 class T_HVX_vmpy2 <string asmString, RegisterClass RC>
1809 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1Imm:$src3),
1813 multiclass T_HVX_vmpy2 <string asmString> {
1814 def NAME : T_HVX_vmpy2 <asmString, VecDblRegs>;
1816 let isCodeGenOnly = 1 in
1817 def NAME#_128B : T_HVX_vmpy2 <asmString, VecDblRegs128B>;
1821 T_HVX_vmpy2 <"$dst.w = vrmpy($src1.ub,$src2.b,#$src3)">, V6_vrmpybusi_enc;
1823 T_HVX_vmpy2 <"$dst.uw = vrsad($src1.ub,$src2.ub,#$src3)">, V6_vrsadubi_enc;
1825 T_HVX_vmpy2 <"$dst.uw = vrmpy($src1.ub,$src2.ub,#$src3)">, V6_vrmpyubi_enc;
1828 let Itinerary = CVI_VP_VS_LONG_EARLY, Type = TypeCVI_VP_VS,
1829 hasSideEffects = 0, hasNewValue2 = 1, opNewValue2 = 1 in
1830 class T_HVX_perm <string asmString, RegisterClass RC>
1831 : CVI_VA_Resource1 <(outs RC:$_dst1_, RC:$_dst2_),
1832 (ins RC:$src1, RC:$src2, IntRegs:$src3),
1833 asmString, [], "$_dst1_ = $src1, $_dst2_ = $src2" >;
1835 multiclass T_HVX_perm <string asmString> {
1836 def NAME : T_HVX_perm <asmString, VectorRegs>;
1838 let isCodeGenOnly = 1 in
1839 def NAME#_128B : T_HVX_perm <asmString, VectorRegs128B>;
1842 let hasNewValue = 1, opNewValue = 0, hasNewValue2 = 1, opNewValue2 = 1 in {
1843 defm V6_vshuff : T_HVX_perm <"vshuff($src1,$src2,$src3)">, V6_vshuff_enc;
1844 defm V6_vdeal : T_HVX_perm <"vdeal($src1,$src2,$src3)">, V6_vdeal_enc;
1847 // Conditional vector move.
1848 let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1849 class T_HVX_cmov <bit isPredNot, RegisterClass RC>
1850 : CVI_VA_Resource1 <(outs RC:$dst), (ins PredRegs:$src1, RC:$src2),
1851 "if ("#!if(isPredNot, "!", "")#"$src1) $dst = $src2"> {
1852 let isPredicatedFalse = isPredNot;
1855 multiclass T_HVX_cmov <bit isPredNot = 0> {
1856 def NAME : T_HVX_cmov <isPredNot, VectorRegs>;
1858 let isCodeGenOnly = 1 in
1859 def NAME#_128B : T_HVX_cmov <isPredNot, VectorRegs128B>;
1862 defm V6_vcmov : T_HVX_cmov, V6_vcmov_enc;
1863 defm V6_vncmov : T_HVX_cmov<1>, V6_vncmov_enc;
1865 // Conditional vector combine.
1866 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, isPredicated = 1,
1867 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1868 class T_HVX_ccombine <bit isPredNot, RegisterClass RCout, RegisterClass RCin>
1869 : CVI_VA_Resource1 < (outs RCout:$dst),
1870 (ins PredRegs:$src1, RCin:$src2, RCin:$src3),
1871 "if ("#!if(isPredNot, "!", "")#"$src1) $dst = vcombine($src2,$src3)"> {
1872 let isPredicatedFalse = isPredNot;
1875 multiclass T_HVX_ccombine <bit isPredNot = 0> {
1876 def NAME : T_HVX_ccombine <isPredNot, VecDblRegs, VectorRegs>;
1878 let isCodeGenOnly = 1 in
1879 def NAME#_128B : T_HVX_ccombine <isPredNot, VecDblRegs128B, VectorRegs128B>;
1882 defm V6_vccombine : T_HVX_ccombine, V6_vccombine_enc;
1883 defm V6_vnccombine : T_HVX_ccombine<1>, V6_vnccombine_enc;
1885 let hasNewValue = 1 in
1886 class T_HVX_shift <string asmString, RegisterClass RCout, RegisterClass RCin>
1887 : CVI_VX_DV_Resource1<(outs RCout:$dst),
1888 (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
1891 multiclass T_HVX_shift <string asmString, RegisterClass RCout,
1892 RegisterClass RCin> {
1893 def NAME : T_HVX_shift <asmString, RCout, RCin>;
1894 let isCodeGenOnly = 1 in
1895 def NAME#_128B : T_HVX_shift <asmString, !cast<RegisterClass>(RCout#"128B"),
1896 !cast<RegisterClass>(RCin#"128B")>;
1899 multiclass T_HVX_shift_VV <string asmString>:
1900 T_HVX_shift <asmString, VectorRegs, VectorRegs>;
1902 multiclass T_HVX_shift_WV <string asmString>:
1903 T_HVX_shift <asmString, VecDblRegs, VectorRegs>;
1905 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in {
1907 T_HVX_shift_VV <"$dst = valign($src1,$src2,$src3)">, V6_valignb_enc;
1909 T_HVX_shift_VV <"$dst = vlalign($src1,$src2,$src3)">, V6_vlalignb_enc;
1912 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1914 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3)">, V6_vasrwh_enc;
1916 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):sat">,
1918 defm V6_vasrwhrndsat :
1919 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):rnd:sat">,
1920 V6_vasrwhrndsat_enc;
1921 defm V6_vasrwuhsat :
1922 T_HVX_shift_VV <"$dst.uh = vasr($src1.w,$src2.w,$src3):sat">,
1924 defm V6_vasrhubsat :
1925 T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):sat">,
1927 defm V6_vasrhubrndsat :
1928 T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):rnd:sat">,
1929 V6_vasrhubrndsat_enc;
1930 defm V6_vasrhbrndsat :
1931 T_HVX_shift_VV <"$dst.b = vasr($src1.h,$src2.h,$src3):rnd:sat">,
1932 V6_vasrhbrndsat_enc;
1935 // Assembler mapped -- alias?
1936 //defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc;
1937 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in {
1939 T_HVX_shift_WV <"$dst = vshuff($src1,$src2,$src3)">, V6_vshuffvdd_enc;
1941 T_HVX_shift_WV <"$dst = vdeal($src1,$src2,$src3)">, V6_vdealvdd_enc;
1944 let hasNewValue = 1, Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in
1945 class T_HVX_unpack <string asmString, RegisterClass RCout, RegisterClass RCin>
1946 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCout:$_src_, RCin:$src1),
1947 asmString, [], "$dst = $_src_">;
1949 multiclass T_HVX_unpack <string asmString> {
1950 def NAME : T_HVX_unpack <asmString, VecDblRegs, VectorRegs>;
1951 let isCodeGenOnly = 1 in
1952 def NAME#_128B : T_HVX_unpack <asmString, VecDblRegs128B, VectorRegs128B>;
1955 defm V6_vunpackob : T_HVX_unpack <"$dst.h |= vunpacko($src1.b)">, V6_vunpackob_enc;
1956 defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_enc;
1958 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1,
1959 hasSideEffects = 0 in
1960 class T_HVX_valign <string asmString, RegisterClass RC>
1961 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3Imm:$src3),
1964 multiclass T_HVX_valign <string asmString> {
1965 def NAME : T_HVX_valign <asmString, VectorRegs>;
1967 let isCodeGenOnly = 1 in
1968 def NAME#_128B : T_HVX_valign <asmString, VectorRegs128B>;
1972 T_HVX_valign <"$dst = valign($src1,$src2,#$src3)">, V6_valignbi_enc;
1974 T_HVX_valign <"$dst = vlalign($src1,$src2,#$src3)">, V6_vlalignbi_enc;
1976 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
1977 class T_HVX_predAlu <string asmString, RegisterClass RC>
1978 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2),
1981 multiclass T_HVX_predAlu <string asmString> {
1982 def NAME : T_HVX_predAlu <asmString, VecPredRegs>;
1984 let isCodeGenOnly = 1 in
1985 def NAME#_128B : T_HVX_predAlu <asmString, VecPredRegs128B>;
1988 defm V6_pred_and : T_HVX_predAlu <"$dst = and($src1,$src2)">, V6_pred_and_enc;
1989 defm V6_pred_or : T_HVX_predAlu <"$dst = or($src1,$src2)">, V6_pred_or_enc;
1990 defm V6_pred_xor : T_HVX_predAlu <"$dst = xor($src1,$src2)">, V6_pred_xor_enc;
1991 defm V6_pred_or_n : T_HVX_predAlu <"$dst = or($src1,!$src2)">, V6_pred_or_n_enc;
1992 defm V6_pred_and_n :
1993 T_HVX_predAlu <"$dst = and($src1,!$src2)">, V6_pred_and_n_enc;
1995 let Itinerary = CVI_VA, Type = TypeCVI_VA in
1996 class T_HVX_prednot <RegisterClass RC>
1997 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1),
1998 "$dst = not($src1)">, V6_pred_not_enc;
2000 def V6_pred_not : T_HVX_prednot <VecPredRegs>;
2001 let isCodeGenOnly = 1 in
2002 def V6_pred_not_128B : T_HVX_prednot <VecPredRegs128B>;
2004 let Itinerary = CVI_VA, Type = TypeCVI_VA in
2005 class T_HVX_vcmp2 <string asmString, RegisterClass RCout, RegisterClass RCin>
2006 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
2009 multiclass T_HVX_vcmp2 <string asmString> {
2010 def NAME : T_HVX_vcmp2 <asmString, VecPredRegs, VectorRegs>;
2011 let isCodeGenOnly = 1 in
2012 def NAME#_128B : T_HVX_vcmp2 <asmString, VecPredRegs128B, VectorRegs128B>;
2015 defm V6_veqb : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.b,$src2.b)">, V6_veqb_enc;
2016 defm V6_veqh : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.h,$src2.h)">, V6_veqh_enc;
2017 defm V6_veqw : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.w,$src2.w)">, V6_veqw_enc;
2018 defm V6_vgtb : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.b,$src2.b)">, V6_vgtb_enc;
2019 defm V6_vgth : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.h,$src2.h)">, V6_vgth_enc;
2020 defm V6_vgtw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.w,$src2.w)">, V6_vgtw_enc;
2021 defm V6_vgtub : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_enc;
2022 defm V6_vgtuh : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_enc;
2023 defm V6_vgtuw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_enc;
2025 let isAccumulator = 1, hasNewValue = 1, hasSideEffects = 0 in
2026 class T_V6_vandqrt_acc <RegisterClass RCout, RegisterClass RCin>
2027 : CVI_VX_Resource_late<(outs RCout:$dst),
2028 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
2029 "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandqrt_acc_enc;
2031 def V6_vandqrt_acc : T_V6_vandqrt_acc <VectorRegs, VecPredRegs>;
2032 let isCodeGenOnly = 1 in
2033 def V6_vandqrt_acc_128B : T_V6_vandqrt_acc <VectorRegs128B, VecPredRegs128B>;
2035 let isAccumulator = 1 in
2036 class T_V6_vandvrt_acc <RegisterClass RCout, RegisterClass RCin>
2037 : CVI_VX_Resource_late<(outs RCout:$dst),
2038 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
2039 "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandvrt_acc_enc;
2041 def V6_vandvrt_acc : T_V6_vandvrt_acc <VecPredRegs, VectorRegs>;
2042 let isCodeGenOnly = 1 in
2043 def V6_vandvrt_acc_128B : T_V6_vandvrt_acc <VecPredRegs128B, VectorRegs128B>;
2045 let hasNewValue = 1, hasSideEffects = 0 in
2046 class T_V6_vandqrt <RegisterClass RCout, RegisterClass RCin>
2047 : CVI_VX_Resource_late<(outs RCout:$dst),
2048 (ins RCin:$src1, IntRegs:$src2),
2049 "$dst = vand($src1,$src2)" >, V6_vandqrt_enc;
2051 def V6_vandqrt : T_V6_vandqrt <VectorRegs, VecPredRegs>;
2052 let isCodeGenOnly = 1 in
2053 def V6_vandqrt_128B : T_V6_vandqrt <VectorRegs128B, VecPredRegs128B>;
2055 let hasNewValue = 1, hasSideEffects = 0 in
2056 class T_V6_lvsplatw <RegisterClass RC>
2057 : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1),
2058 "$dst = vsplat($src1)" >, V6_lvsplatw_enc;
2060 def V6_lvsplatw : T_V6_lvsplatw <VectorRegs>;
2061 let isCodeGenOnly = 1 in
2062 def V6_lvsplatw_128B : T_V6_lvsplatw <VectorRegs128B>;
2065 let hasNewValue = 1 in
2066 class T_V6_vinsertwr <RegisterClass RC>
2067 : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1),
2068 "$dst.w = vinsert($src1)", [], "$dst = $_src_">,
2071 def V6_vinsertwr : T_V6_vinsertwr <VectorRegs>;
2072 let isCodeGenOnly = 1 in
2073 def V6_vinsertwr_128B : T_V6_vinsertwr <VectorRegs128B>;
2076 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in
2077 class T_V6_pred_scalar2 <RegisterClass RC>
2078 : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1),
2079 "$dst = vsetq($src1)">, V6_pred_scalar2_enc;
2081 def V6_pred_scalar2 : T_V6_pred_scalar2 <VecPredRegs>;
2082 let isCodeGenOnly = 1 in
2083 def V6_pred_scalar2_128B : T_V6_pred_scalar2 <VecPredRegs128B>;
2085 class T_V6_vandvrt <RegisterClass RCout, RegisterClass RCin>
2086 : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
2087 "$dst = vand($src1,$src2)">, V6_vandvrt_enc;
2089 def V6_vandvrt : T_V6_vandvrt <VecPredRegs, VectorRegs>;
2090 let isCodeGenOnly = 1 in
2091 def V6_vandvrt_128B : T_V6_vandvrt <VecPredRegs128B, VectorRegs128B>;
2093 let validSubTargets = HasV60SubT in
2094 class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp >
2095 : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>;
2097 class T_HVX_rol_R <string asmString>
2098 : T_HVX_rol <asmString, IntRegs, u5Imm>;
2099 class T_HVX_rol_P <string asmString>
2100 : T_HVX_rol <asmString, DoubleRegs, u6Imm>;
2102 def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc;
2103 let hasNewValue = 1, opNewValue = 0 in
2104 def S6_rol_i_r : T_HVX_rol_R <"$dst = rol($src1,#$src2)">, S6_rol_i_r_enc;
2106 let validSubTargets = HasV60SubT in
2107 class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp>
2108 : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2),
2109 asmString, [], "$dst = $_src_" >;
2111 class T_HVX_rol_acc_P <string asmString>
2112 : T_HVX_rol_acc <asmString, DoubleRegs, u6Imm>;
2114 class T_HVX_rol_acc_R <string asmString>
2115 : T_HVX_rol_acc <asmString, IntRegs, u5Imm>;
2117 def S6_rol_i_p_nac :
2118 T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc;
2119 def S6_rol_i_p_acc :
2120 T_HVX_rol_acc_P <"$dst += rol($src1,#$src2)">, S6_rol_i_p_acc_enc;
2121 def S6_rol_i_p_and :
2122 T_HVX_rol_acc_P <"$dst &= rol($src1,#$src2)">, S6_rol_i_p_and_enc;
2124 T_HVX_rol_acc_P <"$dst |= rol($src1,#$src2)">, S6_rol_i_p_or_enc;
2125 def S6_rol_i_p_xacc :
2126 T_HVX_rol_acc_P<"$dst ^= rol($src1,#$src2)">, S6_rol_i_p_xacc_enc;
2128 let hasNewValue = 1, opNewValue = 0 in {
2129 def S6_rol_i_r_nac :
2130 T_HVX_rol_acc_R <"$dst -= rol($src1,#$src2)">, S6_rol_i_r_nac_enc;
2131 def S6_rol_i_r_acc :
2132 T_HVX_rol_acc_R <"$dst += rol($src1,#$src2)">, S6_rol_i_r_acc_enc;
2133 def S6_rol_i_r_and :
2134 T_HVX_rol_acc_R <"$dst &= rol($src1,#$src2)">, S6_rol_i_r_and_enc;
2136 T_HVX_rol_acc_R <"$dst |= rol($src1,#$src2)">, S6_rol_i_r_or_enc;
2137 def S6_rol_i_r_xacc :
2138 T_HVX_rol_acc_R <"$dst ^= rol($src1,#$src2)">, S6_rol_i_r_xacc_enc;
2141 let isSolo = 1, Itinerary = LD_tc_ld_SLOT0, Type = TypeLD in
2142 class T_V6_extractw <RegisterClass RC>
2143 : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2),
2144 "$dst = vextract($src1,$src2)">, V6_extractw_enc;
2146 def V6_extractw : T_V6_extractw <VectorRegs>;
2147 let isCodeGenOnly = 1 in
2148 def V6_extractw_128B : T_V6_extractw <VectorRegs128B>;
2150 let Itinerary = ST_tc_st_SLOT0, validSubTargets = HasV55SubT in
2151 class T_sys0op <string asmString>
2152 : ST1Inst <(outs), (ins), asmString>;
2154 let isSolo = 1, validSubTargets = HasV55SubT in {
2155 def Y5_l2gunlock : T_sys0op <"l2gunlock">, Y5_l2gunlock_enc;
2156 def Y5_l2gclean : T_sys0op <"l2gclean">, Y5_l2gclean_enc;
2157 def Y5_l2gcleaninv : T_sys0op <"l2gcleaninv">, Y5_l2gcleaninv_enc;
2160 class T_sys1op <string asmString, RegisterClass RC>
2161 : ST1Inst <(outs), (ins RC:$src1), asmString>;
2163 class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>;
2164 class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>;
2166 let isSoloAX = 1, validSubTargets = HasV55SubT in
2167 def Y5_l2unlocka : T_sys1op_R <"l2unlocka($src1)">, Y5_l2unlocka_enc;
2169 let isSolo = 1, validSubTargets = HasV60SubT in {
2170 def Y6_l2gcleanpa : T_sys1op_P <"l2gclean($src1)">, Y6_l2gcleanpa_enc;
2171 def Y6_l2gcleaninvpa : T_sys1op_P <"l2gcleaninv($src1)">, Y6_l2gcleaninvpa_enc;
2174 let Itinerary = ST_tc_3stall_SLOT0, isPredicateLate = 1, isSoloAX = 1,
2175 validSubTargets = HasV55SubT in
2176 def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1),
2177 "$dst = l2locka($src1)">, Y5_l2locka_enc;
2179 // not defined on etc side. why?
2180 // defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc;
2182 let Defs = [USR_OVF], Itinerary = M_tc_3stall_SLOT23, isPredicateLate = 1,
2184 validSubTargets = HasV55SubT in
2185 def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2),
2186 (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2),
2187 "$dst1,$dst2 = vacsh($src1,$src2)", [],
2188 "$dst1 = $_src_" >, Requires<[HasV55T]>, A5_ACS_enc;
2190 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, hasNewValue = 1,
2191 hasSideEffects = 0 in
2192 class T_HVX_alu2 <string asmString, RegisterClass RCout, RegisterClass RCin1,
2193 RegisterClass RCin2>
2194 : CVI_VA_Resource1<(outs RCout:$dst),
2195 (ins RCin1:$src1, RCin2:$src2, RCin2:$src3), asmString>;
2197 multiclass T_HVX_alu2 <string asmString, RegisterClass RC > {
2198 def NAME : T_HVX_alu2 <asmString, RC, VecPredRegs, VectorRegs>;
2199 let isCodeGenOnly = 1 in
2200 def NAME#_128B : T_HVX_alu2 <asmString, !cast<RegisterClass>(RC#"128B"),
2201 VecPredRegs128B, VectorRegs128B>;
2204 multiclass T_HVX_alu2_V <string asmString> :
2205 T_HVX_alu2 <asmString, VectorRegs>;
2207 multiclass T_HVX_alu2_W <string asmString> :
2208 T_HVX_alu2 <asmString, VecDblRegs>;
2210 defm V6_vswap : T_HVX_alu2_W <"$dst = vswap($src1,$src2,$src3)">, V6_vswap_enc;
2212 let Itinerary = CVI_VA, Type = TypeCVI_VA, hasNewValue = 1,
2213 hasSideEffects = 0 in
2214 defm V6_vmux : T_HVX_alu2_V <"$dst = vmux($src1,$src2,$src3)">, V6_vmux_enc;
2216 class T_HVX_vlutb <string asmString, RegisterClass RCout, RegisterClass RCin>
2217 : CVI_VA_Resource1<(outs RCout:$dst),
2218 (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), asmString>;
2220 multiclass T_HVX_vlutb <string asmString, RegisterClass RCout,
2221 RegisterClass RCin> {
2222 def NAME : T_HVX_vlutb <asmString, RCout, RCin>;
2223 let isCodeGenOnly = 1 in
2224 def NAME#_128B : T_HVX_vlutb <asmString, !cast<RegisterClass>(RCout#"128B"),
2225 !cast<RegisterClass>(RCin#"128B")>;
2228 multiclass T_HVX_vlutb_V <string asmString> :
2229 T_HVX_vlutb <asmString, VectorRegs, VectorRegs>;
2231 multiclass T_HVX_vlutb_W <string asmString> :
2232 T_HVX_vlutb <asmString, VecDblRegs, VectorRegs>;
2234 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, isAccumulator = 1 in
2235 class T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
2237 : CVI_VA_Resource1<(outs RCout:$dst),
2238 (ins RCout:$_src_, RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
2239 asmString, [], "$dst = $_src_">;
2241 multiclass T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
2242 RegisterClass RCin> {
2243 def NAME : T_HVX_vlutb_acc <asmString, RCout, RCin>;
2244 let isCodeGenOnly = 1 in
2245 def NAME#_128B : T_HVX_vlutb_acc<asmString,
2246 !cast<RegisterClass>(RCout#"128B"),
2247 !cast<RegisterClass>(RCin#"128B")>;
2250 multiclass T_HVX_vlutb_acc_V <string asmString> :
2251 T_HVX_vlutb_acc <asmString, VectorRegs, VectorRegs>;
2253 multiclass T_HVX_vlutb_acc_W <string asmString> :
2254 T_HVX_vlutb_acc <asmString, VecDblRegs, VectorRegs>;
2257 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1 in
2259 T_HVX_vlutb_V <"$dst.b = vlut32($src1.b,$src2.b,$src3)">, V6_vlutvvb_enc;
2261 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, hasNewValue = 1 in
2263 T_HVX_vlutb_W <"$dst.h = vlut16($src1.b,$src2.h,$src3)">, V6_vlutvwh_enc;
2265 let hasNewValue = 1 in {
2266 defm V6_vlutvvb_oracc:
2267 T_HVX_vlutb_acc_V <"$dst.b |= vlut32($src1.b,$src2.b,$src3)">,
2268 V6_vlutvvb_oracc_enc;
2269 defm V6_vlutvwh_oracc:
2270 T_HVX_vlutb_acc_W <"$dst.h |= vlut16($src1.b,$src2.h,$src3)">,
2271 V6_vlutvwh_oracc_enc;
2274 // It's a fake instruction and should not be defined?
2276 : SInst2<(outs DoubleRegs:$dst),
2277 (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),
2278 "$dst = encbin($src1,$src2,$src3)">, S2_cabacencbin_enc;
2280 // Vhist instructions
2282 : CVI_HIST_Resource1 <(outs), (ins VecPredRegs:$src1),
2283 "vhist($src1)">, V6_vhistq_enc;
2286 : CVI_HIST_Resource1 <(outs), (ins),
2287 "vhist" >, V6_vhist_enc;