1 //===- HexagonInstrInfoVector.td - Hexagon Vector Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon Vector instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Vector shift support. Vector shifting in Hexagon is rather different
15 // from internal representation of LLVM.
16 // LLVM assumes all shifts (in vector case) will have the form
17 // <VT> = SHL/SRA/SRL <VT> by <VT>
18 // while Hexagon has the following format:
19 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>
20 // As a result, special care is needed to guarantee correctness and
22 class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
23 : S_2OpInstImm<Str, MajOp, MinOp, u4_0Imm, []> {
25 let Inst{11-8} = src2;
28 class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
29 : S_2OpInstImm<Str, MajOp, MinOp, u5_0Imm, []> {
31 let Inst{12-8} = src2;
34 def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
35 def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>;
36 def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>;
38 def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>;
39 def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>;
40 def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
42 // Vector shift words by register
43 def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>;
44 def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>;
45 def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>;
46 def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>;
48 // Vector shift halfwords by register
49 def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>;
50 def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>;
51 def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>;
52 def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>;
55 // Hexagon doesn't have a vector multiply with C semantics.
56 // Instead, generate a pseudo instruction that gets expaneded into two
57 // scalar MPYI instructions.
58 // This is expanded by ExpandPostRAPseudos.
60 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
61 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
64 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
65 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],