contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // These intrinsic patterns are not auto-generated.
  11
  12 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  13   : Pat <(IntID I32:$Rs),
  14          (MI I32:$Rs)>;
  15
  16 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID I32:$Rs, I32:$Rt),
  18          (MI I32:$Rs, I32:$Rt)>;
  19
  20 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs, I64:$Rt),
  22          (MI I32:$Rs, I64:$Rt)>;
  23
  24 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
  25          (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
  26 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, imm:$s16),
  27          (A2_addi IntRegs:$Rs, imm:$s16)>;
  28 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
  29          (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  30
  31 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
  32          (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
  33 def: Pat<(int_hexagon_A2_subri imm:$s10, IntRegs:$Rs),
  34          (A2_subri imm:$s10, IntRegs:$Rs)>;
  35 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
  36          (A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  37
  38 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
  39          (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
  40 def: Pat<(int_hexagon_M2_mpyui IntRegs:$Rs, IntRegs:$Rt), // Same as M2_mpyi
  41          (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
  42 def: Pat<(int_hexagon_M2_mpysmi IntRegs:$Rs, imm:$s9),
  43          (M2_mpysmi IntRegs:$Rs, imm:$s9)>;
  44 def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt),
  45          (M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt)>;
  46 def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt),
  47          (M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt)>;
  48
  49 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, imm:$u5),
  50          (S2_asl_i_r IntRegs:$Rs, imm:$u5)>;
  51 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, imm:$u5),
  52          (S2_lsr_i_r IntRegs:$Rs, imm:$u5)>;
  53 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, imm:$u5),
  54          (S2_asr_i_r IntRegs:$Rs, imm:$u5)>;
  55 def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$Rs, imm:$u6),
  56          (S2_asl_i_p DoubleRegs:$Rs, imm:$u6)>;
  57 def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$Rs, imm:$u6),
  58          (S2_lsr_i_p DoubleRegs:$Rs, imm:$u6)>;
  59 def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$Rs, imm:$u6),
  60          (S2_asr_i_p DoubleRegs:$Rs, imm:$u6)>;
  61
  62 def: Pat<(int_hexagon_A2_and IntRegs:$Rs, IntRegs:$Rt),
  63          (A2_and IntRegs:$Rs, IntRegs:$Rt)>;
  64 def: Pat<(int_hexagon_A2_andir IntRegs:$Rs, imm:$s10),
  65          (A2_andir IntRegs:$Rs, imm:$s10)>;
  66 def: Pat<(int_hexagon_A2_or IntRegs:$Rs, IntRegs:$Rt),
  67          (A2_or IntRegs:$Rs, IntRegs:$Rt)>;
  68 def: Pat<(int_hexagon_A2_orir IntRegs:$Rs, imm:$s10),
  69          (A2_orir IntRegs:$Rs, imm:$s10)>;
  70 def: Pat<(int_hexagon_A2_xor IntRegs:$Rs, IntRegs:$Rt),
  71          (A2_xor IntRegs:$Rs, IntRegs:$Rt)>;
  72
  73 def: Pat<(int_hexagon_A2_sxtb IntRegs:$Rs),
  74          (A2_sxtb IntRegs:$Rs)>;
  75 def: Pat<(int_hexagon_A2_sxth IntRegs:$Rs),
  76          (A2_sxth IntRegs:$Rs)>;
  77 def: Pat<(int_hexagon_A2_zxtb IntRegs:$Rs),
  78          (A2_zxtb IntRegs:$Rs)>;
  79 def: Pat<(int_hexagon_A2_zxth IntRegs:$Rs),
  80          (A2_zxth IntRegs:$Rs)>;
  81
  82 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
  83 def : Pat <(int_hexagon_A2_not I32:$Rs),
  84            (A2_subri -1, I32:$Rs)>;
  85
  86 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
  87 def : Pat <(int_hexagon_A2_neg I32:$Rs),
  88            (A2_subri 0, I32:$Rs)>;
  89
  90 // Make sure the patterns with zero immediate value has higher complexity
  91 // otherwise, we need to updated the predicates for immediates to exclude zero
  92 let AddedComplexity = 200 in {
  93 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
  94            (A2_tfr I32:$Rs)>;
  95 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
  96            (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
  97 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
  98            (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
  99 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
 100            (S2_vsathub I64:$Rs)>;
 101 }
 102
 103 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm),
 104            (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
 105 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm),
 106            (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
 107 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
 108            (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
 109 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
 110            (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
 111
 112 def ImmExt64: SDNodeXForm<imm, [{
 113   int64_t V = N->getSExtValue();
 114   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64);
 115 }]>;
 116
 117 // A2_tfrpi has an operand of type i64. This is necessary, since it is
 118 // generated from "(set I64:$Rd, imm)". That pattern would not appear
 119 // in the DAG, if the immediate was not a 64-bit value.
 120 // The builtin for A2_tfrpi, on the other hand, takes a 32-bit value,
 121 // which makes it impossible to simply replace it with the instruction.
 122 // To connect the builtin with the instruction, the builtin's operand
 123 // needs to be extended to the right type.
 124
 125 def : Pat<(int_hexagon_A2_tfrpi imm:$Is),
 126           (A2_tfrpi (ImmExt64 $Is))>;
 127
 128 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2),
 129            (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
 130
 131 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred:$src2),
 132            (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
 133
 134 def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0),
 135            (C2_tfrpr (C2_cmpeq I32:$src, I32:$src))>;
 136 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
 137            (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
 138 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
 139            (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
 140
 141 //===----------------------------------------------------------------------===//
 142 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
 143 //===----------------------------------------------------------------------===//
 144 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
 145                          SDNodeXForm XformImm>
 146   : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred:$src3, u5_0ImmPred:$src4),
 147          (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
 148                      (XformImm u5_0ImmPred:$src4))>;
 149
 150 def SDEC2 : SDNodeXForm<imm, [{
 151   int32_t V = N->getSExtValue();
 152   return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
 153 }]>;
 154
 155 def SDEC3 : SDNodeXForm<imm, [{
 156   int32_t V = N->getSExtValue();
 157   return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
 158 }]>;
 159
 160 // Table Index : Extract and insert bits.
 161 // Map to the real hardware instructions after subtracting appropriate
 162 // values from the 4th input operand. Please note that subtraction is not
 163 // needed for int_hexagon_S2_tableidxb_goodsyntax.
 164
 165 def : S2op_tableidx_pat <int_hexagon_S2_tableidxb_goodsyntax, S2_tableidxb,
 166                          IdImm>;
 167 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
 168                          SDEC1>;
 169 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
 170                          SDEC2>;
 171 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
 172                          SDEC3>;
 173
 174 // Load/store locked.
 175 def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>;
 176 def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>;
 177
 178 def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt),
 179           (C2_tfrpr (S2_storew_locked I32:$Rs, I32:$Rt))>;
 180 def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt),
 181           (C2_tfrpr (S4_stored_locked I32:$Rs, I64:$Rt))>;
 182
 183 //*******************************************************************
 184 //           ST
 185 //*******************************************************************
 186
 187 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
 188   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
 189         (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
 190
 191 def : T_stb_pat <S2_storerh_pbr, int_hexagon_S2_storerh_pbr, I32>;
 192 def : T_stb_pat <S2_storerb_pbr, int_hexagon_S2_storerb_pbr, I32>;
 193 def : T_stb_pat <S2_storeri_pbr, int_hexagon_S2_storeri_pbr, I32>;
 194 def : T_stb_pat <S2_storerf_pbr, int_hexagon_S2_storerf_pbr, I32>;
 195 def : T_stb_pat <S2_storerd_pbr, int_hexagon_S2_storerd_pbr, I64>;
 196
 197 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
 198   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
 199         (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;
 200
 201 def: T_stc_pat<S2_storerb_pci, int_hexagon_circ_stb,   s4_0ImmPred, I32>;
 202 def: T_stc_pat<S2_storerh_pci, int_hexagon_circ_sth,   s4_1ImmPred, I32>;
 203 def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw,   s4_2ImmPred, I32>;
 204 def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std,   s4_3ImmPred, I64>;
 205 def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
 206
 207 multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
 208   def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
 209             (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
 210         Requires<[UseHVX]>;
 211
 212   def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
 213                                              HvxVR:$src3),
 214             (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
 215         Requires<[UseHVX]>;
 216 }
 217
 218 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>;
 219 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>;
 220 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
 221 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
 222
 223 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>;
 224 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>;
 225 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>;
 226 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>;
 227
 228 //*******************************************************************
 229 //           SYSTEM
 230 //*******************************************************************
 231
 232 def: T_R_pat<Y2_dccleana,    int_hexagon_Y2_dccleana>;
 233 def: T_R_pat<Y2_dccleaninva, int_hexagon_Y2_dccleaninva>;
 234 def: T_R_pat<Y2_dcinva,      int_hexagon_Y2_dcinva>;
 235 def: T_R_pat<Y2_dczeroa,     int_hexagon_Y2_dczeroa>;
 236
 237 def: T_RR_pat<Y4_l2fetch,    int_hexagon_Y4_l2fetch>;
 238 def: T_RP_pat<Y5_l2fetch,    int_hexagon_Y5_l2fetch>;
 239
 240 //
 241 // Patterns for optimizing code generations for HVX.
 242
 243 def u3_64_ImmPred  : PatLeaf<(i32 imm), [{
 244   int64_t v = (int64_t)(64 - N->getSExtValue());
 245   return isUInt<3>(v);
 246 }]>;
 247
 248 def u3_128_ImmPred  : PatLeaf<(i32 imm), [{
 249   int64_t v = (int64_t)(128 - N->getSExtValue());
 250   return isUInt<3>(v);
 251 }]>;
 252
 253 def SUB_64_VAL : SDNodeXForm<imm, [{
 254    int32_t Imm = N->getSExtValue();
 255    return CurDAG->getTargetConstant(64 - Imm, SDLoc(N), MVT::i32);
 256 }]>;
 257
 258 def SUB_128_VAL : SDNodeXForm<imm, [{
 259    int32_t Imm = N->getSExtValue();
 260    return CurDAG->getTargetConstant(128 - Imm, SDLoc(N), MVT::i32);
 261 }]>;
 262
 263 let AddedComplexity = 100 in {
 264 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
 265            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
 266            Requires<[UseHVX]>;
 267
 268 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
 269            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
 270            Requires<[UseHVX]>;
 271
 272 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
 273            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
 274            Requires<[UseHVX]>;
 275
 276 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
 277            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
 278            Requires<[UseHVX]>;
 279 }
 280
 281 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
 282            (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 283            Requires<[UseHVX]>;
 284
 285 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
 286            (v512i1 (V6_vandvrt (v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 287            Requires<[UseHVX]>;
 288
 289 def : Pat <(v512i1 (bitconvert (v64i8  HvxVR:$src1))),
 290            (v512i1 (V6_vandvrt (v64i8  HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 291            Requires<[UseHVX]>;
 292
 293 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
 294            (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 295            Requires<[UseHVX]>;
 296
 297 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
 298            (v32i16 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 299            Requires<[UseHVX]>;
 300
 301 def : Pat <(v64i8  (bitconvert (v512i1 HvxQR:$src1))),
 302            (v64i8  (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 303            Requires<[UseHVX]>;
 304
 305 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
 306            (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 307            Requires<[UseHVX]>;
 308
 309 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
 310            (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 311            Requires<[UseHVX]>;
 312
 313 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
 314            (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
 315            Requires<[UseHVX]>;
 316
 317 def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
 318            (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 319            Requires<[UseHVX]>;
 320
 321 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
 322            (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 323            Requires<[UseHVX]>;
 324
 325 def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))),
 326            (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
 327            Requires<[UseHVX]>;
 328
 329 let AddedComplexity = 140 in {
 330 def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)),
 331            (V6_vS32b_ai IntRegs:$addr, 0,
 332            (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>,
 333            Requires<[UseHVX]>;
 334
 335 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
 336            (v512i1 (V6_vandvrt
 337            (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
 338            Requires<[UseHVX]>;
 339
 340 def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)),
 341            (V6_vS32b_ai IntRegs:$addr, 0,
 342            (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>,
 343            Requires<[UseHVX]>;
 344
 345 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
 346            (v1024i1 (V6_vandvrt
 347            (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
 348            Requires<[UseHVX]>;
 349 }
 350
 351 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
 352          (v64i16 (V6_vpackwh_sat
 353                  (v32i32 (V6_hi HvxWR:$Vdd)),
 354                  (v32i32 (V6_lo HvxWR:$Vdd))))>,
 355      Requires<[UseHVX]>;
 356
 357 def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, IntRegs:$src2),
 358          (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV55]>;
 359
 360 multiclass T_VI_pat <InstHexagon MI, Intrinsic IntID> {
 361   def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
 362            (MI    HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
 363        Requires<[UseHVX]>;
 364
 365   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_0ImmPred:$src2),
 366            (MI                 HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
 367        Requires<[UseHVX]>;
 368 }
 369
 370 multiclass T_VI_inv_pat <InstHexagon MI, Intrinsic IntID> {
 371   def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
 372            (MI    HvxVR:$src1, HvxVR:$src1,
 373                   (SUB_64_VAL u3_64_ImmPred:$src2))>,
 374        Requires<[UseHVX]>;
 375
 376   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_128_ImmPred:$src2),
 377            (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>,
 378        Requires<[UseHVX]>;
 379 }
 380
 381 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
 382   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
 383            (MI    HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
 384        Requires<[UseHVX]>;
 385
 386   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
 387                                             u3_0ImmPred:$src3),
 388            (MI                              HvxVR:$src1, HvxVR:$src2,
 389                                             u3_0ImmPred:$src3)>,
 390        Requires<[UseHVX]>;
 391 }
 392
 393 multiclass T_VVI_inv_pat <InstHexagon MI, Intrinsic IntID> {
 394   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_64_ImmPred:$src3),
 395            (MI    HvxVR:$src1, HvxVR:$src2,
 396                                     (SUB_64_VAL u3_64_ImmPred:$src3))>,
 397        Requires<[UseHVX]>;
 398
 399   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
 400                                             u3_128_ImmPred:$src3),
 401            (MI                              HvxVR:$src1, HvxVR:$src2,
 402                                           (SUB_128_VAL u3_128_ImmPred:$src3))>,
 403        Requires<[UseHVX]>;
 404 }
 405
 406 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
 407   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
 408            (MI    HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>,
 409        Requires<[UseHVX]>;
 410
 411   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
 412                                             IntRegs:$src3),
 413            (MI                              HvxVR:$src1, HvxVR:$src2,
 414                                             IntRegs:$src3)>,
 415        Requires<[UseHVX]>;
 416 }
 417
 418 defm : T_VI_pat <V6_valignbi, int_hexagon_V6_vror>;
 419 defm : T_VI_inv_pat <V6_vlalignbi, int_hexagon_V6_vror>;
 420
 421 defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignb>;
 422 defm : T_VVI_inv_pat <V6_vlalignbi, int_hexagon_V6_valignbi>;
 423 defm : T_VVI_inv_pat <V6_vlalignbi, int_hexagon_V6_valignb>;
 424 defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignbi>;
 425 defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignb>;
 426 defm : T_VVI_inv_pat <V6_valignbi, int_hexagon_V6_vlalignbi>;
 427 defm : T_VVI_inv_pat <V6_valignbi, int_hexagon_V6_vlalignb>;
 428 defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignbi>;
 429
 430 def: Pat<(int_hexagon_V6_vd0),
 431          (V6_vd0)>, Requires<[HasV60, UseHVX64B]>;
 432 def: Pat<(int_hexagon_V6_vd0_128B ),
 433          (V6_vd0)>, Requires<[HasV60, UseHVX128B]>;
 434
 435 def: Pat<(int_hexagon_V6_vdd0),
 436          (V6_vdd0)>, Requires<[HasV65, UseHVX64B]>;
 437 def: Pat<(int_hexagon_V6_vdd0_128B),
 438          (V6_vdd0)>, Requires<[HasV65, UseHVX128B]>;
 439
 440 def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 441          (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 442 def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 443          (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 444 def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 445          (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 446 def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 447          (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 448 def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),
 449          (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 450 def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),
 451          (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 452 def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
 453          (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 454 def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
 455          (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 456 def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5),
 457          (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 458 def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 459          (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 460 def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 461          (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 462 def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 463          (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 464 def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
 465          (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 466 def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),
 467          (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 468 def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),
 469          (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 470 def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
 471          (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 472 def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
 473          (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>;
 474 def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5),
 475          (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>;
 476
 477 include "HexagonDepMapAsm2Intrin.td"