contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs),
  26          (MI I64:$Rs)>;
  27
  28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  29   : Pat<(IntID Imm1:$Is, Imm2:$It),
  30         (MI Imm1:$Is, Imm2:$It)>;
  31
  32 class T_RI_pat <InstHexagon MI, Intrinsic IntID,
  33                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  34   : Pat<(IntID I32:$Rs, ImmPred:$It),
  35         (MI I32:$Rs, ImmPred:$It)>;
  36
  37 class T_IR_pat <InstHexagon MI, Intrinsic IntID,
  38                 PatFrag ImmPred = PatLeaf<(i32 imm)>>
  39   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  40         (MI ImmPred:$Is, I32:$Rt)>;
  41
  42 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
  43   : Pat<(IntID I64:$Rs, imm:$It),
  44         (MI I64:$Rs, imm:$It)>;
  45
  46 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  47   : Pat<(IntID I32:$Rs, I64:$Rt),
  48         (MI I32:$Rs, I64:$Rt)>;
  49
  50 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  51   : Pat <(IntID I32:$Rs, I32:$Rt),
  52          (MI I32:$Rs, I32:$Rt)>;
  53
  54 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  55   : Pat <(IntID I64:$Rs, I64:$Rt),
  56          (MI I64:$Rs, I64:$Rt)>;
  57
  58 class T_QQ_pat <InstHexagon MI, Intrinsic IntID>
  59   : Pat <(IntID I32:$Rs, I32:$Rt),
  60          (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>;
  61
  62 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  63   : Pat <(IntID I32:$Rp, Imm1:$Is, Imm2:$It),
  64          (MI (C2_tfrrp I32:$Rp), Imm1:$Is, Imm2:$It)>;
  65
  66 class T_QRR_pat <InstHexagon MI, Intrinsic IntID>
  67   : Pat <(IntID I32:$Rp, I32:$Rs, I32:$Rt),
  68          (MI (C2_tfrrp I32:$Rp), I32:$Rs, I32:$Rt)>;
  69
  70 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  71   : Pat <(IntID I32:$Rp, I32:$Rs, ImmPred:$Is),
  72          (MI (C2_tfrrp I32:$Rp), I32:$Rs, ImmPred:$Is)>;
  73
  74 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  75   : Pat <(IntID I32:$Rp, ImmPred:$Is, I32:$Rs),
  76          (MI (C2_tfrrp I32:$Rp), ImmPred:$Is, I32:$Rs)>;
  77
  78 class T_QPP_pat <InstHexagon MI, Intrinsic IntID>
  79   : Pat <(IntID I32:$Rp, I64:$Rs, I64:$Rt),
  80          (MI (C2_tfrrp I32:$Rp), I64:$Rs, I64:$Rt)>;
  81
  82 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  83   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  84          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  85
  86 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
  87   : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
  88          (MI I32:$Rs, imm:$It, imm:$Iu)>;
  89
  90 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
  91   : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
  92          (MI imm:$It, I32:$Rs, imm:$Iu)>;
  93
  94 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
  95   : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
  96          (MI imm:$Is, I32:$Rs, I32:$Rt)>;
  97
  98 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
  99   : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
 100          (MI I32:$Rs, imm:$Is, I32:$Rt)>;
 101
 102 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
 103   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
 104          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
 105
 106 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
 107   : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
 108          (MI I64:$Rs, I64:$Rt, imm:$Iu)>;
 109
 110 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
 111   : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
 112          (MI I64:$Rs, imm:$It, imm:$Iu)>;
 113
 114 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
 115   : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
 116          (MI I64:$Rs, I64:$Rt, I64:$Ru)>;
 117
 118 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
 119   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
 120          (MI I64:$Rs, I64:$Rt, I32:$Ru)>;
 121
 122 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
 123   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
 124          (MI I64:$Rs, I32:$Rt, I32:$Ru)>;
 125
 126 class T_PPQ_pat <InstHexagon MI, Intrinsic IntID>
 127   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Rp),
 128          (MI I64:$Rs, I64:$Rt, (C2_tfrrp I32:$Rp))>;
 129
 130 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
 131   : Pat <(IntID I64:$Rs, I32:$Rt),
 132          (MI I64:$Rs, I32:$Rt)>;
 133
 134 class T_D_pat <InstHexagon MI, Intrinsic IntID>
 135   : Pat<(IntID (F64:$Rs)),
 136         (MI (F64:$Rs))>;
 137
 138 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
 139                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 140   : Pat<(IntID F64:$Rs, ImmPred:$It),
 141         (MI F64:$Rs, ImmPred:$It)>;
 142
 143 class T_F_pat <InstHexagon MI, Intrinsic IntID>
 144   : Pat<(IntID F32:$Rs),
 145         (MI F32:$Rs)>;
 146
 147 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
 148                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 149   : Pat<(IntID F32:$Rs, ImmPred:$It),
 150         (MI F32:$Rs, ImmPred:$It)>;
 151
 152 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
 153   : Pat<(IntID F32:$Rs, F32:$Rt),
 154         (MI F32:$Rs, F32:$Rt)>;
 155
 156 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
 157   : Pat<(IntID F64:$Rs, F64:$Rt),
 158         (MI F64:$Rs, F64:$Rt)>;
 159
 160 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
 161   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
 162         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 163
 164 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
 165   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, I32:$Rp),
 166          (MI F32:$Rs, F32:$Rt, F32:$Ru, (C2_tfrrp I32:$Rp))>;
 167
 168 class T_Q_RI_pat <InstHexagon MI, Intrinsic IntID,
 169                   PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 170   : Pat<(IntID I32:$Rs, ImmPred:$It),
 171         (C2_tfrpr (MI I32:$Rs, ImmPred:$It))>;
 172
 173 class T_Q_RR_pat <InstHexagon MI, Intrinsic IntID>
 174   : Pat <(IntID I32:$Rs, I32:$Rt),
 175          (C2_tfrpr (MI I32:$Rs, I32:$Rt))>;
 176
 177 class T_Q_RP_pat <InstHexagon MI, Intrinsic IntID>
 178   : Pat <(IntID I32:$Rs, I64:$Rt),
 179          (C2_tfrpr (MI I32:$Rs, I64:$Rt))>;
 180
 181 class T_Q_PR_pat <InstHexagon MI, Intrinsic IntID>
 182   : Pat <(IntID I64:$Rs, I32:$Rt),
 183          (C2_tfrpr (MI I64:$Rs, I32:$Rt))>;
 184
 185 class T_Q_PI_pat <InstHexagon MI, Intrinsic IntID>
 186   : Pat<(IntID I64:$Rs, imm:$It),
 187         (C2_tfrpr (MI I64:$Rs, imm:$It))>;
 188
 189 class T_Q_PP_pat <InstHexagon MI, Intrinsic IntID>
 190   : Pat <(IntID I64:$Rs, I64:$Rt),
 191          (C2_tfrpr (MI I64:$Rs, I64:$Rt))>;
 192
 193 class T_Q_Q_pat <InstHexagon MI, Intrinsic IntID>
 194   : Pat <(IntID I32:$Rp),
 195          (C2_tfrpr (MI (C2_tfrrp I32:$Rp)))>;
 196
 197 class T_Q_QQ_pat <InstHexagon MI, Intrinsic IntID>
 198   : Pat <(IntID I32:$Rp, I32:$Rq),
 199          (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq)))>;
 200
 201 class T_Q_FF_pat <InstHexagon MI, Intrinsic IntID>
 202   : Pat<(IntID F32:$Rs, F32:$Rt),
 203         (C2_tfrpr (MI F32:$Rs, F32:$Rt))>;
 204
 205 class T_Q_DD_pat <InstHexagon MI, Intrinsic IntID>
 206   : Pat<(IntID F64:$Rs, F64:$Rt),
 207         (C2_tfrpr (MI F64:$Rs, F64:$Rt))>;
 208
 209 class T_Q_FI_pat <InstHexagon MI, Intrinsic IntID>
 210   : Pat<(IntID F32:$Rs, imm:$It),
 211         (C2_tfrpr (MI F32:$Rs, imm:$It))>;
 212
 213 class T_Q_DI_pat <InstHexagon MI, Intrinsic IntID>
 214   : Pat<(IntID F64:$Rs, imm:$It),
 215         (C2_tfrpr (MI F64:$Rs, imm:$It))>;
 216
 217 class T_Q_QQQ_pat <InstHexagon MI, Intrinsic IntID>
 218   : Pat <(IntID I32:$Rp, I32:$Rq, I32:$Rs),
 219          (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq),
 220                        (C2_tfrrp I32:$Rs)))>;
 221
 222 //===----------------------------------------------------------------------===//
 223 // MPYS / Multipy signed/unsigned halfwords
 224 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
 225 //===----------------------------------------------------------------------===//
 226
 227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
 228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
 229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
 230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
 231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
 232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
 233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
 234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
 235
 236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
 237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
 238 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
 239 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
 240 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
 241 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
 242 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
 243 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
 244
 245 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
 246 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
 247 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
 248 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
 249 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
 250 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
 251 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
 252 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
 253
 254 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 255 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 256 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 257 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 258 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 259 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 260 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 261 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 262
 263 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 264 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 265 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 266 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 267 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 268 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 269 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 270 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 275 // result from the accumulator.
 276 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 277 //===----------------------------------------------------------------------===//
 278
 279 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 280 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 281 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 282 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 283 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 284 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 285 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 286 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 287
 288 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 289 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 290 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 291 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 292 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 293 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 294 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 295 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 296
 297 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 298 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 299 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 300 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 301 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 302 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 303 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 304 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 305
 306 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 307 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 308 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 309 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 310 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 311 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 312 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 313 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 314
 315 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 316 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 317 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 318 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 319 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 320 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 321 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 322 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 323
 324 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 325 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 326 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 327 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 328 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 329 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 330 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 331 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 332
 333
 334 //===----------------------------------------------------------------------===//
 335 // Multiply signed/unsigned halfwords with and without saturation and rounding
 336 // into a 64-bits destination register.
 337 //===----------------------------------------------------------------------===//
 338
 339 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 340 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 341 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 342 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 343 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 344 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 345 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 346 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 347
 348 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 349 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 350 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 351 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 352 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 353 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 354 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 355 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 356
 357 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 358 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 359 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 360 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 361 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 362 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 363 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 364 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 365
 366 //===----------------------------------------------------------------------===//
 367 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 368 // result from the 64-bit destination register.
 369 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 370 //===----------------------------------------------------------------------===//
 371
 372 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 373 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 374 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 375 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 376
 377 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 378 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 379 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 380 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 381
 382 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 383 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 384 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 385 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 386
 387 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 388 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 389 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 390 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 391
 392 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 393 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 394 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 395 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 396
 397 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 398 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 399 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 400 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 401
 402 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 403 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 404 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 405 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 406
 407 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 408 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 409 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 410 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 411
 412 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
 413 def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>;
 414 def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>;
 415
 416 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
 417 def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>;
 418 def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>;
 419
 420 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
 421 def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>;
 422 def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>;
 423
 424 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
 425 def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>;
 426 def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>;
 427
 428 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
 429 def : T_PP_pat <M2_mmpyh_s0,  int_hexagon_M2_mmpyh_s0>;
 430 def : T_PP_pat <M2_mmpyh_s1,  int_hexagon_M2_mmpyh_s1>;
 431 def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>;
 432 def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>;
 433
 434 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
 435 def : T_PP_pat <M2_mmpyl_s0,  int_hexagon_M2_mmpyl_s0>;
 436 def : T_PP_pat <M2_mmpyl_s1,  int_hexagon_M2_mmpyl_s1>;
 437 def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>;
 438 def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>;
 439
 440 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
 441 def : T_PP_pat <M2_mmpyuh_s0,  int_hexagon_M2_mmpyuh_s0>;
 442 def : T_PP_pat <M2_mmpyuh_s1,  int_hexagon_M2_mmpyuh_s1>;
 443 def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>;
 444 def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>;
 445
 446 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
 447 def : T_PP_pat <M2_mmpyul_s0,  int_hexagon_M2_mmpyul_s0>;
 448 def : T_PP_pat <M2_mmpyul_s1,  int_hexagon_M2_mmpyul_s1>;
 449 def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>;
 450 def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>;
 451
 452 // Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32)
 453 def : T_PP_pat  <A2_vraddub,     int_hexagon_A2_vraddub>;
 454 def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>;
 455
 456 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
 457 def : T_PP_pat  <A2_vrsadub,     int_hexagon_A2_vrsadub>;
 458 def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>;
 459
 460 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
 461 def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>;
 462
 463 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
 464 def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>;
 465
 466 // Vector reduce complex multiply real or imaginary:
 467 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
 468 def : T_PP_pat  <M2_vrcmpyi_s0,  int_hexagon_M2_vrcmpyi_s0>;
 469 def : T_PP_pat  <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>;
 470 def : T_PPP_pat <M2_vrcmaci_s0,  int_hexagon_M2_vrcmaci_s0>;
 471 def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>;
 472
 473 def : T_PP_pat  <M2_vrcmpyr_s0,  int_hexagon_M2_vrcmpyr_s0>;
 474 def : T_PP_pat  <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>;
 475 def : T_PPP_pat <M2_vrcmacr_s0,  int_hexagon_M2_vrcmacr_s0>;
 476 def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>;
 477
 478 // Vector reduce halfwords
 479 // Rdd[+]=vrmpyh(Rss,Rtt)
 480 def : T_PP_pat  <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>;
 481 def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>;
 482
 483 //===----------------------------------------------------------------------===//
 484 // Vector Multipy with accumulation
 485 //===----------------------------------------------------------------------===//
 486
 487 // Vector multiply word by signed half with accumulation
 488 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
 489 def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>;
 490 def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>;
 491 def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>;
 492 def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>;
 493 def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>;
 494 def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>;
 495 def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>;
 496 def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>;
 497
 498 // Vector multiply word by unsigned half with accumulation
 499 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
 500 def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>;
 501 def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>;
 502 def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>;
 503 def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>;
 504 def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>;
 505 def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>;
 506 def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>;
 507 def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>;
 508
 509 // Vector multiply even halfwords with accumulation
 510 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
 511 def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>;
 512 def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>;
 513 def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>;
 514
 515 // Vector dual multiply with accumulation
 516 // Rxx+=vdmpy(Rss,Rtt)[:sat]
 517 def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>;
 518 def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>;
 519
 520 // Vector complex multiply real or imaginary with accumulation
 521 // Rxx+=vcmpy[ir](Rss,Rtt):sat
 522 def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>;
 523 def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>;
 524
 525 //===----------------------------------------------------------------------===//
 526 // Add/Subtract halfword
 527 // Rd=add(Rt.L,Rs.[HL])[:sat]
 528 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 529 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 530 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 531 //===----------------------------------------------------------------------===//
 532
 533 //Rd=add(Rt.L,Rs.[LH])
 534 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 535 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 536
 537 //Rd=add(Rt.L,Rs.[LH]):sat
 538 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 539 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 540
 541 //Rd=sub(Rt.L,Rs.[LH])
 542 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 543 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 544
 545 //Rd=sub(Rt.L,Rs.[LH]):sat
 546 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 547 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 548
 549 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 550 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 551 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 552 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 553 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 554
 555 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 556 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 557 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 558 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 559 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 560
 561 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 562 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 563 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 564 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 565 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 566
 567 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 568 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 569 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 570 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 571 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 572
 573 // ALU64 / ALU / min max
 574 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 575 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 576 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 577 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 578
 579 // Shift and accumulate
 580 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 581 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 582 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 583 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 584 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 585 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 586
 587 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 588 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 589 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 590 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 591 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 592 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 593 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 594 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 595
 596 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 597 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 598 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 599 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 600 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 601 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 602
 603 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 604 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 605 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 606 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 607 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 608 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 609 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 610 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 611
 612 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 613 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 614 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 615 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 616 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 617 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 618 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 619 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 620
 621 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 622 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 623 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 624 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 625 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 626 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 627 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 628 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 629
 630 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 631 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 632 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 633 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 634 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 635 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 636 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 637 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 638
 639 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 640 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 641 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 642 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 643 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 644 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 645 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 646 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 647
 648 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 649 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 650 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 651 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 652 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 653 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 654
 655 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 656 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 657 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 658 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 659 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 660 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 661 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 662 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 663
 664 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 665 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 666 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 667 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 668 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 669 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 670
 671 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 672 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 673 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 674 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 675 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 676 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 677 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 678 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 679
 680 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 681 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 682 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 683 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 684 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 685 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 686 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 687 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 688
 689 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 690 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 691 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 692 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 693 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 694 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 695 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 696 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 697
 698 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 699 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 700 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 701 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 702 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 703 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 704 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 705 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 706
 707 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 708 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 709 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 710 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 711 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 712 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 713 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 714 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 715
 716 //*******************************************************************
 717 //           ALU32/ALU
 718 //*******************************************************************
 719 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 720 def : T_RI_pat<A2_addi,     int_hexagon_A2_addi>;
 721 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 722 def : T_IR_pat<A2_subri,    int_hexagon_A2_subri>;
 723 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 724 def : T_RI_pat<A2_andir,    int_hexagon_A2_andir>;
 725 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 726 def : T_RI_pat<A2_orir,     int_hexagon_A2_orir>;
 727 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 728 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 729
 730 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 731 def : Pat <(int_hexagon_A2_not I32:$Rs),
 732            (A2_subri -1, I32:$Rs)>;
 733
 734 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 735 def : Pat <(int_hexagon_A2_neg I32:$Rs),
 736            (A2_subri 0, I32:$Rs)>;
 737
 738 // Transfer immediate
 739 def  : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is),
 740             (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>;
 741 def  : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is),
 742             (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>;
 743
 744 //  Transfer Register/immediate.
 745 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 746 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 747
 748 def ImmExt64: SDNodeXForm<imm, [{
 749   int64_t V = N->getSExtValue();
 750   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64);
 751 }]>;
 752
 753 // A2_tfrpi has an operand of type i64. This is necessary, since it is
 754 // generated from "(set I64:$Rd, imm)". That pattern would not appear
 755 // in the DAG, if the immediate was not a 64-bit value.
 756 // The builtin for A2_tfrpi, on the other hand, takes a 32-bit value,
 757 // which makes it impossible to simply replace it with the instruction.
 758 // To connect the builtin with the instruction, the builtin's operand
 759 // needs to be extended to the right type.
 760
 761 def : Pat<(int_hexagon_A2_tfrpi imm:$Is),
 762           (A2_tfrpi (ImmExt64 $Is))>;
 763
 764 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 765 def : Pat<(int_hexagon_A2_tfrp I64:$src),
 766           (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
 767
 768 //*******************************************************************
 769 //           ALU32/PERM
 770 //*******************************************************************
 771 // Combine
 772 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 773 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 774 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 775 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 776
 777 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32_0ImmPred, s8_0ImmPred>;
 778
 779 // Mux
 780 def : T_QRR_pat<C2_mux,   int_hexagon_C2_mux>;
 781 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32_0ImmPred>;
 782 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32_0ImmPred>;
 783 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>;
 784
 785 // Shift halfword
 786 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 787 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 788 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 789
 790 // Sign/zero extend
 791 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 792 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 793 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 794 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 795
 796 //*******************************************************************
 797 //           ALU32/PRED
 798 //*******************************************************************
 799 // Compare
 800 def : T_Q_RR_pat<C2_cmpeq,  int_hexagon_C2_cmpeq>;
 801 def : T_Q_RR_pat<C2_cmpgt,  int_hexagon_C2_cmpgt>;
 802 def : T_Q_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
 803
 804 def : T_Q_RI_pat<C2_cmpeqi,  int_hexagon_C2_cmpeqi, s32_0ImmPred>;
 805 def : T_Q_RI_pat<C2_cmpgti,  int_hexagon_C2_cmpgti, s32_0ImmPred>;
 806 def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32_0ImmPred>;
 807
 808 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2),
 809            (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
 810
 811 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred:$src2),
 812            (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
 813
 814 def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0),
 815            (C2_tfrpr (C2_cmpeq I32:$src, I32:$src))>;
 816 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
 817            (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
 818 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
 819            (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
 820
 821 //*******************************************************************
 822 //           ALU32/VH
 823 //*******************************************************************
 824 // Vector add, subtract, average halfwords
 825 def: T_RR_pat<A2_svaddh,   int_hexagon_A2_svaddh>;
 826 def: T_RR_pat<A2_svaddhs,  int_hexagon_A2_svaddhs>;
 827 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
 828
 829 def: T_RR_pat<A2_svsubh,   int_hexagon_A2_svsubh>;
 830 def: T_RR_pat<A2_svsubhs,  int_hexagon_A2_svsubhs>;
 831 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
 832
 833 def: T_RR_pat<A2_svavgh,   int_hexagon_A2_svavgh>;
 834 def: T_RR_pat<A2_svavghs,  int_hexagon_A2_svavghs>;
 835 def: T_RR_pat<A2_svnavgh,  int_hexagon_A2_svnavgh>;
 836
 837 //*******************************************************************
 838 //           ALU64/ALU
 839 //*******************************************************************
 840 def: T_RR_pat<A2_addsat,     int_hexagon_A2_addsat>;
 841 def: T_RR_pat<A2_subsat,     int_hexagon_A2_subsat>;
 842 def: T_PP_pat<A2_addp,       int_hexagon_A2_addp>;
 843 def: T_PP_pat<A2_subp,       int_hexagon_A2_subp>;
 844
 845 def: T_PP_pat<A2_andp,       int_hexagon_A2_andp>;
 846 def: T_PP_pat<A2_orp,        int_hexagon_A2_orp>;
 847 def: T_PP_pat<A2_xorp,       int_hexagon_A2_xorp>;
 848
 849 def: T_Q_PP_pat<C2_cmpeqp,   int_hexagon_C2_cmpeqp>;
 850 def: T_Q_PP_pat<C2_cmpgtp,   int_hexagon_C2_cmpgtp>;
 851 def: T_Q_PP_pat<C2_cmpgtup,  int_hexagon_C2_cmpgtup>;
 852
 853 def: T_PP_pat<S2_parityp,    int_hexagon_S2_parityp>;
 854 def: T_RR_pat<S2_packhl,     int_hexagon_S2_packhl>;
 855
 856 //*******************************************************************
 857 //           ALU64/VB
 858 //*******************************************************************
 859 // ALU64 - Vector add
 860 def : T_PP_pat <A2_vaddub,   int_hexagon_A2_vaddub>;
 861 def : T_PP_pat <A2_vaddubs,  int_hexagon_A2_vaddubs>;
 862 def : T_PP_pat <A2_vaddh,    int_hexagon_A2_vaddh>;
 863 def : T_PP_pat <A2_vaddhs,   int_hexagon_A2_vaddhs>;
 864 def : T_PP_pat <A2_vadduhs,  int_hexagon_A2_vadduhs>;
 865 def : T_PP_pat <A2_vaddw,    int_hexagon_A2_vaddw>;
 866 def : T_PP_pat <A2_vaddws,   int_hexagon_A2_vaddws>;
 867
 868 // ALU64 - Vector average
 869 def : T_PP_pat <A2_vavgub,   int_hexagon_A2_vavgub>;
 870 def : T_PP_pat <A2_vavgubr,  int_hexagon_A2_vavgubr>;
 871 def : T_PP_pat <A2_vavgh,    int_hexagon_A2_vavgh>;
 872 def : T_PP_pat <A2_vavghr,   int_hexagon_A2_vavghr>;
 873 def : T_PP_pat <A2_vavghcr,  int_hexagon_A2_vavghcr>;
 874 def : T_PP_pat <A2_vavguh,   int_hexagon_A2_vavguh>;
 875 def : T_PP_pat <A2_vavguhr,  int_hexagon_A2_vavguhr>;
 876
 877 def : T_PP_pat <A2_vavgw,    int_hexagon_A2_vavgw>;
 878 def : T_PP_pat <A2_vavgwr,   int_hexagon_A2_vavgwr>;
 879 def : T_PP_pat <A2_vavgwcr,  int_hexagon_A2_vavgwcr>;
 880 def : T_PP_pat <A2_vavguw,   int_hexagon_A2_vavguw>;
 881 def : T_PP_pat <A2_vavguwr,  int_hexagon_A2_vavguwr>;
 882
 883 // ALU64 - Vector negative average
 884 def : T_PP_pat <A2_vnavgh,   int_hexagon_A2_vnavgh>;
 885 def : T_PP_pat <A2_vnavghr,  int_hexagon_A2_vnavghr>;
 886 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
 887 def : T_PP_pat <A2_vnavgw,   int_hexagon_A2_vnavgw>;
 888 def : T_PP_pat <A2_vnavgwr,  int_hexagon_A2_vnavgwr>;
 889 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
 890
 891 // ALU64 - Vector max
 892 def : T_PP_pat <A2_vmaxh,    int_hexagon_A2_vmaxh>;
 893 def : T_PP_pat <A2_vmaxw,    int_hexagon_A2_vmaxw>;
 894 def : T_PP_pat <A2_vmaxub,   int_hexagon_A2_vmaxub>;
 895 def : T_PP_pat <A2_vmaxuh,   int_hexagon_A2_vmaxuh>;
 896 def : T_PP_pat <A2_vmaxuw,   int_hexagon_A2_vmaxuw>;
 897
 898 // ALU64 - Vector min
 899 def : T_PP_pat <A2_vminh,    int_hexagon_A2_vminh>;
 900 def : T_PP_pat <A2_vminw,    int_hexagon_A2_vminw>;
 901 def : T_PP_pat <A2_vminub,   int_hexagon_A2_vminub>;
 902 def : T_PP_pat <A2_vminuh,   int_hexagon_A2_vminuh>;
 903 def : T_PP_pat <A2_vminuw,   int_hexagon_A2_vminuw>;
 904
 905 // ALU64 - Vector sub
 906 def : T_PP_pat <A2_vsubub,   int_hexagon_A2_vsubub>;
 907 def : T_PP_pat <A2_vsububs,  int_hexagon_A2_vsububs>;
 908 def : T_PP_pat <A2_vsubh,    int_hexagon_A2_vsubh>;
 909 def : T_PP_pat <A2_vsubhs,   int_hexagon_A2_vsubhs>;
 910 def : T_PP_pat <A2_vsubuhs,  int_hexagon_A2_vsubuhs>;
 911 def : T_PP_pat <A2_vsubw,    int_hexagon_A2_vsubw>;
 912 def : T_PP_pat <A2_vsubws,   int_hexagon_A2_vsubws>;
 913
 914 // ALU64 - Vector compare bytes
 915 def : T_Q_PP_pat <A2_vcmpbeq,  int_hexagon_A2_vcmpbeq>;
 916 def : T_Q_PP_pat <A4_vcmpbgt,  int_hexagon_A4_vcmpbgt>;
 917 def : T_Q_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
 918
 919 // ALU64 - Vector compare halfwords
 920 def : T_Q_PP_pat <A2_vcmpheq,  int_hexagon_A2_vcmpheq>;
 921 def : T_Q_PP_pat <A2_vcmphgt,  int_hexagon_A2_vcmphgt>;
 922 def : T_Q_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
 923
 924 // ALU64 - Vector compare words
 925 def : T_Q_PP_pat <A2_vcmpweq,  int_hexagon_A2_vcmpweq>;
 926 def : T_Q_PP_pat <A2_vcmpwgt,  int_hexagon_A2_vcmpwgt>;
 927 def : T_Q_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
 928
 929 // ALU64 / VB / Vector mux.
 930 def : T_QPP_pat <C2_vmux,      int_hexagon_C2_vmux>;
 931
 932 // MPY - Multiply and use full result
 933 // Rdd = mpy[u](Rs, Rt)
 934 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
 935 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
 936
 937 // Complex multiply real or imaginary
 938 def : T_RR_pat <M2_cmpyi_s0,   int_hexagon_M2_cmpyi_s0>;
 939 def : T_RR_pat <M2_cmpyr_s0,   int_hexagon_M2_cmpyr_s0>;
 940
 941 // Complex multiply
 942 def : T_RR_pat <M2_cmpys_s0,   int_hexagon_M2_cmpys_s0>;
 943 def : T_RR_pat <M2_cmpysc_s0,  int_hexagon_M2_cmpysc_s0>;
 944 def : T_RR_pat <M2_cmpys_s1,   int_hexagon_M2_cmpys_s1>;
 945 def : T_RR_pat <M2_cmpysc_s1,  int_hexagon_M2_cmpysc_s1>;
 946
 947 // Vector multiply halfwords
 948 // Rdd=vmpyh(Rs,Rt)[:<<1]:sat
 949 def : T_RR_pat <M2_vmpy2s_s0,  int_hexagon_M2_vmpy2s_s0>;
 950 def : T_RR_pat <M2_vmpy2s_s1,  int_hexagon_M2_vmpy2s_s1>;
 951
 952 // Rxx[+-]= mpy[u](Rs,Rt)
 953 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
 954 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
 955 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
 956 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
 957
 958 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
 959 def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>;
 960 def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>;
 961 def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>;
 962 def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>;
 963
 964 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
 965 def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>;
 966 def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>;
 967 def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>;
 968 def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>;
 969
 970 // Rxx+=cmpy[ir](Rs,Rt)
 971 def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>;
 972 def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>;
 973
 974 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
 975 def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>;
 976 def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>;
 977 def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>;
 978
 979 //*******************************************************************
 980 //           CR
 981 //*******************************************************************
 982 def: T_Q_Q_pat<C2_not,       int_hexagon_C2_not>;
 983 def: T_Q_Q_pat<C2_all8,      int_hexagon_C2_all8>;
 984 def: T_Q_Q_pat<C2_any8,      int_hexagon_C2_any8>;
 985 def: T_Q_Q_pat<C2_pxfer_map, int_hexagon_C2_pxfer_map>;
 986
 987 def: T_Q_QQ_pat<C2_and,      int_hexagon_C2_and>;
 988 def: T_Q_QQ_pat<C2_andn,     int_hexagon_C2_andn>;
 989 def: T_Q_QQ_pat<C2_or,       int_hexagon_C2_or>;
 990 def: T_Q_QQ_pat<C2_orn,      int_hexagon_C2_orn>;
 991 def: T_Q_QQ_pat<C2_xor,      int_hexagon_C2_xor>;
 992
 993 // Multiply 32x32 and use lower result
 994 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 995 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 996 def : T_RRR_pat <M2_maci,   int_hexagon_M2_maci>;
 997
 998 // Subtract and accumulate
 999 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
1000
1001 // Add and accumulate
1002 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
1003 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
1004 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
1005 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
1006
1007 // XOR and XOR with destination
1008 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
1009
1010 // Vector dual multiply with round and pack
1011 def : T_PP_pat <M2_vdmpyrs_s0, int_hexagon_M2_vdmpyrs_s0>;
1012 def : T_PP_pat <M2_vdmpyrs_s1, int_hexagon_M2_vdmpyrs_s1>;
1013
1014 // Vector multiply halfwords with round and pack
1015 def : T_RR_pat <M2_vmpy2s_s0pack, int_hexagon_M2_vmpy2s_s0pack>;
1016 def : T_RR_pat <M2_vmpy2s_s1pack, int_hexagon_M2_vmpy2s_s1pack>;
1017
1018 // Multiply and use lower result
1019 def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyi>;
1020 def : T_RI_pat <M2_mpysmi, int_hexagon_M2_mpysmi>;
1021
1022 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
1023 def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyui>;
1024
1025 // Multiply and use upper result
1026 def : T_RR_pat <M2_mpy_up, int_hexagon_M2_mpy_up>;
1027 def : T_RR_pat <M2_mpyu_up, int_hexagon_M2_mpyu_up>;
1028 def : T_RR_pat <M2_hmmpyh_rs1, int_hexagon_M2_hmmpyh_rs1>;
1029 def : T_RR_pat <M2_hmmpyl_rs1, int_hexagon_M2_hmmpyl_rs1>;
1030 def : T_RR_pat <M2_dpmpyss_rnd_s0, int_hexagon_M2_dpmpyss_rnd_s0>;
1031
1032 // Complex multiply with round and pack
1033 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
1034 def : T_RR_pat <M2_cmpyrs_s0, int_hexagon_M2_cmpyrs_s0>;
1035 def : T_RR_pat <M2_cmpyrs_s1, int_hexagon_M2_cmpyrs_s1>;
1036 def : T_RR_pat <M2_cmpyrsc_s0, int_hexagon_M2_cmpyrsc_s0>;
1037 def : T_RR_pat <M2_cmpyrsc_s1, int_hexagon_M2_cmpyrsc_s1>;
1038
1039 //*******************************************************************
1040 //           STYPE/ALU
1041 //*******************************************************************
1042 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
1043 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
1044 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
1045
1046 //*******************************************************************
1047 //           STYPE/BIT
1048 //*******************************************************************
1049
1050 // Count leading/trailing
1051 def: T_R_pat<S2_cl0,     int_hexagon_S2_cl0>;
1052 def: T_P_pat<S2_cl0p,    int_hexagon_S2_cl0p>;
1053 def: T_R_pat<S2_cl1,     int_hexagon_S2_cl1>;
1054 def: T_P_pat<S2_cl1p,    int_hexagon_S2_cl1p>;
1055 def: T_R_pat<S2_clb,     int_hexagon_S2_clb>;
1056 def: T_P_pat<S2_clbp,    int_hexagon_S2_clbp>;
1057 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
1058 def: T_R_pat<S2_ct0,     int_hexagon_S2_ct0>;
1059 def: T_R_pat<S2_ct1,     int_hexagon_S2_ct1>;
1060
1061 // Compare bit mask
1062 def: T_RR_pat<C2_bitsclr,  int_hexagon_C2_bitsclr>;
1063 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
1064 def: T_RR_pat<C2_bitsset,  int_hexagon_C2_bitsset>;
1065
1066 // Vector shuffle
1067 def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>;
1068 def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>;
1069 def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>;
1070 def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>;
1071
1072 // Vector truncate
1073 def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>;
1074 def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>;
1075
1076 // Linear feedback-shift Iteration.
1077 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
1078
1079 // Vector align
1080 // Need custom lowering
1081 def : T_PPQ_pat <S2_valignrb, int_hexagon_S2_valignrb>;
1082 def : T_PPI_pat <S2_valignib, int_hexagon_S2_valignib>;
1083
1084 // Vector splice
1085 def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>;
1086 def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>;
1087
1088 // Shift by immediate and add
1089 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
1090
1091 // Extract bitfield
1092 def : T_PII_pat<S2_extractup,    int_hexagon_S2_extractup>;
1093 def : T_RII_pat<S2_extractu,     int_hexagon_S2_extractu>;
1094 def : T_RP_pat <S2_extractu_rp,  int_hexagon_S2_extractu_rp>;
1095 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
1096
1097 // Insert bitfield
1098 def : Pat <(int_hexagon_S2_insert_rp I32:$src1, I32:$src2, I64:$src3),
1099            (S2_insert_rp I32:$src1, I32:$src2, I64:$src3)>;
1100
1101 def : Pat<(i64 (int_hexagon_S2_insertp_rp I64:$src1, I64:$src2, I64:$src3)),
1102           (i64 (S2_insertp_rp I64:$src1, I64:$src2, I64:$src3))>;
1103
1104 def : Pat<(int_hexagon_S2_insert I32:$src1, I32:$src2,
1105                                  u5_0ImmPred:$src3, u5_0ImmPred:$src4),
1106           (S2_insert I32:$src1, I32:$src2,
1107                      u5_0ImmPred:$src3, u5_0ImmPred:$src4)>;
1108
1109 def : Pat<(i64 (int_hexagon_S2_insertp I64:$src1, I64:$src2,
1110                                        u6_0ImmPred:$src3, u6_0ImmPred:$src4)),
1111           (i64 (S2_insertp I64:$src1, I64:$src2,
1112                            u6_0ImmPred:$src3, u6_0ImmPred:$src4))>;
1113
1114 // Innterleave/deinterleave
1115 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
1116 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
1117
1118 // Set/Clear/Toggle Bit
1119 def: T_RI_pat<S2_setbit_i,    int_hexagon_S2_setbit_i>;
1120 def: T_RI_pat<S2_clrbit_i,    int_hexagon_S2_clrbit_i>;
1121 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
1122
1123 def: T_RR_pat<S2_setbit_r,    int_hexagon_S2_setbit_r>;
1124 def: T_RR_pat<S2_clrbit_r,    int_hexagon_S2_clrbit_r>;
1125 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
1126
1127 // Test Bit
1128 def: T_Q_RI_pat<S2_tstbit_i,  int_hexagon_S2_tstbit_i>;
1129 def: T_Q_RR_pat<S2_tstbit_r,  int_hexagon_S2_tstbit_r>;
1130
1131 //*******************************************************************
1132 //           STYPE/COMPLEX
1133 //*******************************************************************
1134 // Vector Complex conjugate
1135 def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>;
1136
1137 // Vector Complex rotate
1138 def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>;
1139
1140 //*******************************************************************
1141 //           STYPE/PERM
1142 //*******************************************************************
1143
1144 // Vector saturate without pack
1145 def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>;
1146 def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>;
1147 def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>;
1148 def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
1149
1150 //*******************************************************************
1151 //           STYPE/PRED
1152 //*******************************************************************
1153
1154 // Predicate transfer
1155 def: Pat<(i32 (int_hexagon_C2_tfrpr I32:$Rs)),
1156          (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>;
1157 def: Pat<(i32 (int_hexagon_C2_tfrrp I32:$Rs)),
1158          (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>;
1159
1160 // Mask generate from predicate
1161 def: Pat<(i64 (int_hexagon_C2_mask I32:$Rs)),
1162          (i64 (C2_mask (C2_tfrrp I32:$Rs)))>;
1163
1164 // Viterbi pack even and odd predicate bits
1165 def: T_QQ_pat<C2_vitpack, int_hexagon_C2_vitpack>;
1166
1167 //*******************************************************************
1168 //           STYPE/SHIFT
1169 //*******************************************************************
1170
1171 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
1172 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
1173 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
1174
1175 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
1176 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
1177 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
1178 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
1179
1180 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
1181 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
1182 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
1183 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
1184
1185 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
1186 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
1187
1188 def : T_R_pat <S2_vsxtbh,   int_hexagon_S2_vsxtbh>;
1189 def : T_R_pat <S2_vzxtbh,   int_hexagon_S2_vzxtbh>;
1190 def : T_R_pat <S2_vsxthw,   int_hexagon_S2_vsxthw>;
1191 def : T_R_pat <S2_vzxthw,   int_hexagon_S2_vzxthw>;
1192 def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>;
1193 def : T_R_pat <A2_sxtw,     int_hexagon_A2_sxtw>;
1194
1195 // Vector saturate and pack
1196 def : T_R_pat <S2_svsathb,  int_hexagon_S2_svsathb>;
1197 def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>;
1198 def : T_P_pat <S2_vsathub,  int_hexagon_S2_vsathub>;
1199 def : T_P_pat <S2_vsatwh,   int_hexagon_S2_vsatwh>;
1200 def : T_P_pat <S2_vsatwuh,  int_hexagon_S2_vsatwuh>;
1201 def : T_P_pat <S2_vsathb,   int_hexagon_S2_vsathb>;
1202
1203 def : T_P_pat <S2_vtrunohb,    int_hexagon_S2_vtrunohb>;
1204 def : T_P_pat <S2_vtrunehb,    int_hexagon_S2_vtrunehb>;
1205 def : T_P_pat <S2_vrndpackwh,  int_hexagon_S2_vrndpackwh>;
1206 def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>;
1207 def : T_R_pat <S2_brev,        int_hexagon_S2_brev>;
1208 def : T_R_pat <S2_vsplatrb,    int_hexagon_S2_vsplatrb>;
1209
1210 def : T_R_pat <A2_abs,    int_hexagon_A2_abs>;
1211 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
1212 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
1213
1214 def : T_R_pat <A2_swiz,   int_hexagon_A2_swiz>;
1215
1216 def : T_P_pat <A2_sat,    int_hexagon_A2_sat>;
1217 def : T_R_pat <A2_sath,   int_hexagon_A2_sath>;
1218 def : T_R_pat <A2_satuh,  int_hexagon_A2_satuh>;
1219 def : T_R_pat <A2_satub,  int_hexagon_A2_satub>;
1220 def : T_R_pat <A2_satb,   int_hexagon_A2_satb>;
1221
1222 // Vector arithmetic shift right by immediate with truncate and pack.
1223 def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>;
1224
1225 def : T_RI_pat <S2_asr_i_r,     int_hexagon_S2_asr_i_r>;
1226 def : T_RI_pat <S2_lsr_i_r,     int_hexagon_S2_lsr_i_r>;
1227 def : T_RI_pat <S2_asl_i_r,     int_hexagon_S2_asl_i_r>;
1228 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
1229 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
1230                 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
1231
1232 // Shift left by immediate with saturation.
1233 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
1234
1235 //===----------------------------------------------------------------------===//
1236 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
1237 //===----------------------------------------------------------------------===//
1238 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
1239                          SDNodeXForm XformImm>
1240   : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred:$src3, u5_0ImmPred:$src4),
1241          (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
1242                      (XformImm u5_0ImmPred:$src4))>;
1243
1244 def SDEC2 : SDNodeXForm<imm, [{
1245   int32_t V = N->getSExtValue();
1246   return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
1247 }]>;
1248
1249 def SDEC3 : SDNodeXForm<imm, [{
1250   int32_t V = N->getSExtValue();
1251   return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
1252 }]>;
1253
1254 // Table Index : Extract and insert bits.
1255 // Map to the real hardware instructions after subtracting appropriate
1256 // values from the 4th input operand. Please note that subtraction is not
1257 // needed for int_hexagon_S2_tableidxb_goodsyntax.
1258
1259 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax I32:$src1, I32:$src2,
1260                                               u4_0ImmPred:$src3, u5_0ImmPred:$src4),
1261            (S2_tableidxb I32:$src1, I32:$src2,
1262                          u4_0ImmPred:$src3, u5_0ImmPred:$src4)>;
1263
1264 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
1265                          SDEC1>;
1266 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
1267                          SDEC2>;
1268 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
1269                          SDEC3>;
1270
1271 //*******************************************************************
1272 //           STYPE/VH
1273 //*******************************************************************
1274
1275 // Vector absolute value halfwords with and without saturation
1276 // Rdd64=vabsh(Rss64)[:sat]
1277 def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>;
1278 def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>;
1279
1280 // Vector shift halfwords by immediate
1281 // Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4)
1282 def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>;
1283 def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>;
1284 def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>;
1285
1286 // Vector shift halfwords by register
1287 // Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32)
1288 def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>;
1289 def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>;
1290 def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>;
1291 def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>;
1292
1293 //*******************************************************************
1294 //           STYPE/VW
1295 //*******************************************************************
1296
1297 // Vector absolute value words with and without saturation
1298 def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>;
1299 def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>;
1300
1301 // Vector shift words by immediate.
1302 // Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5)
1303 def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>;
1304 def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>;
1305 def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>;
1306
1307 // Vector shift words by register.
1308 // Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32)
1309 def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>;
1310 def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>;
1311 def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>;
1312 def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>;
1313
1314 // Vector shift words with truncate and pack
1315 def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>;
1316
1317 // Load/store locked.
1318 def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>;
1319 def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>;
1320
1321 def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt),
1322           (C2_tfrpr (S2_storew_locked I32:$Rs, I32:$Rt))>;
1323 def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt),
1324           (C2_tfrpr (S4_stored_locked I32:$Rs, I64:$Rt))>;
1325
1326 //*******************************************************************
1327 //           ST
1328 //*******************************************************************
1329
1330 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
1331   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
1332         (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
1333
1334 def : T_stb_pat <S2_storerh_pbr, int_hexagon_brev_sth,   I32>;
1335 def : T_stb_pat <S2_storerb_pbr, int_hexagon_brev_stb,   I32>;
1336 def : T_stb_pat <S2_storeri_pbr, int_hexagon_brev_stw,   I32>;
1337 def : T_stb_pat <S2_storerf_pbr, int_hexagon_brev_sthhi, I32>;
1338 def : T_stb_pat <S2_storerd_pbr, int_hexagon_brev_std,   I64>;
1339
1340 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
1341   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
1342         (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;
1343
1344 def: T_stc_pat<S2_storerb_pci, int_hexagon_circ_stb,   s4_0ImmPred, I32>;
1345 def: T_stc_pat<S2_storerh_pci, int_hexagon_circ_sth,   s4_1ImmPred, I32>;
1346 def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw,   s4_2ImmPred, I32>;
1347 def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std,   s4_3ImmPred, I64>;
1348 def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
1349
1350 include "HexagonIntrinsicsV3.td"
1351 include "HexagonIntrinsicsV4.td"
1352 include "HexagonIntrinsicsV5.td"
1353 include "HexagonIntrinsicsV60.td"