1 //=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
12 //===----------------------------------------------------------------------===//
15 let AddedComplexity = 100 in {
16 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
17 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
19 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
20 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
22 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
23 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
25 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
26 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
29 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
30 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
32 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
33 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
35 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
36 (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
38 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
39 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
41 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
42 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
44 def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))),
45 (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
47 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
48 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
50 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
51 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
53 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
54 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
56 def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
57 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
59 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
60 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
62 def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))),
63 (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
65 let AddedComplexity = 140 in {
66 def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)),
67 (V6_vS32b_ai IntRegs:$addr, 0,
68 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1),
69 (A2_tfrsi 0x01010101))))>;
71 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
73 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
75 def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)),
76 (V6_vS32b_ai IntRegs:$addr, 0,
77 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1),
78 (A2_tfrsi 0x01010101))))>;
80 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
82 (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
85 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
86 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
87 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
91 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
92 def: Pat<(IntID HvxVR:$src1),
95 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
99 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
100 def: Pat<(IntID HvxWR:$src1),
103 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
107 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
108 def: Pat<(IntID HvxQR:$src1),
111 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1),
115 multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
116 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
117 (MI HvxWR:$src1, IntRegs:$src2)>;
119 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
120 (MI HvxWR:$src1, IntRegs:$src2)>;
123 multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
124 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
125 (MI HvxVR:$src1, IntRegs:$src2)>;
127 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
128 (MI HvxVR:$src1, IntRegs:$src2)>;
131 multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
132 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
133 (MI HvxWR:$src1, HvxVR:$src2)>;
135 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
136 (MI HvxWR:$src1, HvxVR:$src2)>;
139 multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
140 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
141 (MI HvxWR:$src1, HvxWR:$src2)>;
143 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
144 (MI HvxWR:$src1, HvxWR:$src2)>;
147 multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
148 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
149 (MI HvxVR:$src1, HvxVR:$src2)>;
151 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
152 (MI HvxVR:$src1, HvxVR:$src2)>;
155 multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
156 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
157 (MI HvxQR:$src1, IntRegs:$src2)>;
159 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
160 (MI HvxQR:$src1, IntRegs:$src2)>;
163 multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
164 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
165 (MI HvxQR:$src1, HvxQR:$src2)>;
167 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
168 (MI HvxQR:$src1, HvxQR:$src2)>;
171 multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
172 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
173 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
177 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
181 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
182 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
186 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
190 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
191 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
193 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
195 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
198 multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
199 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
200 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
202 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
204 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
207 multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
208 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
209 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
211 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
213 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
216 multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
217 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
218 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
220 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
222 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
225 multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
226 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
227 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
229 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
231 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
234 multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
235 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
236 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
238 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
240 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
244 multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
245 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
246 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
248 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
250 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
253 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
254 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
255 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
257 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1,
258 HvxVR:$src2, imm:$src3),
259 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
262 multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
263 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
264 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
266 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1,
267 IntRegs:$src2, imm:$src3),
268 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
271 multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
272 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
273 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
276 IntRegs:$src3, imm:$src4),
277 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
281 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
282 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
285 HvxVR:$src3, IntRegs:$src4),
286 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
290 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
291 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
293 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
294 HvxVR:$src3, IntRegs:$src4),
295 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
298 defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
299 defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
300 defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
301 defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
302 defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>;
303 defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>;
304 defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>;
305 defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>;
306 defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>;
307 defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>;
308 defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>;
309 defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>;
310 defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>;
311 defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>;
312 defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>;
313 defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>;
314 defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>;
315 defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>;
316 defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>;
317 defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>;
318 defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>;
319 defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>;
320 defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>;
321 defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>;
322 defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>;
323 defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>;
324 defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>;
325 defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>;
326 defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>;
327 defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>;
328 defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>;
329 defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>;
331 defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>;
332 defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>;
333 defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>;
334 defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>;
335 defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>;
336 defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>;
337 defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>;
338 defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>;
339 defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>;
340 defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>;
341 defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>;
342 defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>;
343 defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>;
344 defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>;
345 defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>;
346 defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>;
347 defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>;
348 defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>;
349 defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>;
350 defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>;
351 defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>;
352 defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>;
353 defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>;
354 defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>;
355 defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>;
356 defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>;
357 defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>;
358 defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>;
359 defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>;
360 defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>;
361 defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>;
362 defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>;
363 defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>;
364 defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>;
365 defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>;
366 defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>;
367 defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>;
368 defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>;
369 defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>;
370 defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>;
371 defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>;
372 defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>;
373 defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>;
374 defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>;
375 defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>;
376 defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>;
377 defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>;
378 defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>;
379 defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>;
380 defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>;
381 defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>;
382 defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>;
383 defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>;
384 defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>;
385 defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>;
386 defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>;
387 defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>;
388 defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>;
389 defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>;
390 defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>;
391 defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>;
392 defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>;
393 defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>;
394 defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>;
396 defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>;
397 defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>;
398 defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>;
399 defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>;
400 defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>;
401 defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>;
402 defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>;
403 defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>;
404 defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>;
405 defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>;
406 defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>;
408 defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>;
409 defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>;
411 defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>;
412 defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>;
413 defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>;
414 defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>;
416 defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>;
417 defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>;
418 defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>;
419 defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>;
420 defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>;
421 defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>;
422 defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>;
423 defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>;
425 defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>;
426 defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>;
427 defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>;
428 defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>;
429 defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>;
430 defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>;
431 defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>;
432 defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>;
433 defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>;
434 defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>;
435 defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>;
436 defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>;
437 defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>;
438 defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>;
439 defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>;
441 // Compare instructions
442 defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>;
443 defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>;
444 defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>;
445 defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>;
446 defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>;
447 defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>;
448 defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>;
449 defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>;
450 defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>;
451 defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>;
452 defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>;
453 defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>;
454 defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>;
455 defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>;
456 defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>;
457 defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>;
458 defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>;
459 defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>;
460 defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>;
461 defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>;
462 defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>;
463 defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>;
464 defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>;
465 defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>;
466 defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>;
467 defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>;
468 defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>;
470 defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>;
471 defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>;
472 defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>;
473 defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>;
474 defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>;
475 defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>;
476 defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>;
477 defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>;
478 defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>;
479 defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>;
480 defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>;
481 defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>;
482 defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>;
483 defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>;
484 defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>;
485 defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>;
486 defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>;
487 defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>;
488 defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>;
489 defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>;
490 defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>;
491 defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>;
492 defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>;
493 defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>;
494 defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>;
495 defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>;
496 defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>;
497 defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>;
498 defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>;
499 defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>;
500 defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>;
501 defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>;
502 defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>;
503 defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>;
504 defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>;
505 defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>;
506 defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>;
507 defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>;
508 defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>;
509 defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>;
510 defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>;
511 defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>;
512 defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>;
513 defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>;
514 defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>;
515 defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>;
517 defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>;
518 defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>;
519 defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>;
520 defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>;
521 defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>;
522 defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>;
523 defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>;
524 defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>;
525 defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>;
526 defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>;
527 defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>;
528 defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>;
530 defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>;
531 defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>;
532 defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>;
533 defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>;
534 defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>;
535 defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>;
536 defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>;
537 defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>;
538 defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>;
539 defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>;
540 defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>;
541 defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>;
542 defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>;
543 defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>;
544 defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>;
545 defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>;
546 defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>;
547 defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>;
548 defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>;
549 defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>;
550 defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>;
551 defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
552 defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
554 defm : T_W_pat <V6_lo, int_hexagon_V6_lo>;
555 defm : T_W_pat <V6_hi, int_hexagon_V6_hi>;
556 defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>;
558 defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
559 defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
560 defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
562 defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>;
563 defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>;
564 defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>;
567 //defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>;
568 // not present earlier.. need to add intrinsic
569 defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>;
570 defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>;
571 defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>;
572 defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>;
573 defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>;
574 defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>;
575 defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>;
576 defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>;
577 defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>;
579 defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>;
580 defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>;
582 defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>;
583 defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>;
584 defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>;
585 defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>;
587 defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>;
588 defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>;
589 defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>;
590 defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>;
591 defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>;
592 defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>;
593 defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>;
594 defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>;
595 defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>;
596 defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>;
597 defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>;
598 defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>;
599 defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>;
600 defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>;
601 defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>;
602 defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>;
603 defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>;
605 defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>;
606 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
607 defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>;
608 defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>;
609 defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>;
610 defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>;
612 defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>;
613 defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>;
614 defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>;
615 defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>;
617 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
618 def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>;
619 def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>;
620 def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>;
621 def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>;
622 def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>;
623 def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>;
624 def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>;
625 def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>;
626 def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>;
627 def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>;
628 def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>;
629 def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>;
631 defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
632 defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
634 //def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
636 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
637 (v64i16 (V6_vpackwh_sat
638 (v32i32 (V6_hi HvxWR:$Vdd)),
639 (v32i32 (V6_lo HvxWR:$Vdd))))>;
641 def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>;
642 def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>;