1 //===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
11 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
12 (MI VectorRegs:$src1, IntRegs:$src2)>,
13 Requires<[UseHVXSgl]>;
14 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2),
15 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>,
16 Requires<[UseHVXDbl]>;
19 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
20 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3),
21 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>,
22 Requires<[UseHVXSgl]>;
23 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3),
24 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>,
25 Requires<[UseHVXDbl]>;
28 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
29 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
30 (MI VectorRegs:$src1, VectorRegs:$src2)>,
31 Requires<[UseHVXSgl]>;
32 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2),
33 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>,
34 Requires<[UseHVXDbl]>;
37 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
38 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
39 (MI VecDblRegs:$src1, VecDblRegs:$src2)>,
40 Requires<[UseHVXSgl]>;
41 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2),
42 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>,
43 Requires<[UseHVXDbl]>;
46 multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
47 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
48 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
49 Requires<[UseHVXSgl]>;
50 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
51 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>,
52 Requires<[UseHVXDbl]>;
55 multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
56 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
57 (MI VecDblRegs:$src1, IntRegs:$src2)>,
58 Requires<[UseHVXSgl]>;
59 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2),
60 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>,
61 Requires<[UseHVXDbl]>;
64 multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
65 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
66 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
67 Requires<[UseHVXSgl]>;
68 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3),
69 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>,
70 Requires<[UseHVXDbl]>;
73 multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
74 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
75 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
76 Requires<[UseHVXSgl]>;
77 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3),
78 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>,
79 Requires<[UseHVXDbl]>;
82 multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
83 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
84 (MI VecPredRegs:$src1, IntRegs:$src2)>,
85 Requires<[UseHVXSgl]>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2),
87 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>,
88 Requires<[UseHVXDbl]>;
91 multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
92 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
93 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
94 Requires<[UseHVXSgl]>;
95 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3),
96 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>,
97 Requires<[UseHVXDbl]>;
100 multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
101 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2),
102 (MI VecPredRegs:$src1, VectorRegs:$src2)>,
103 Requires<[UseHVXSgl]>;
104 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2),
105 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>,
106 Requires<[UseHVXDbl]>;
109 multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
110 def: Pat<(IntID IntRegs:$src1),
112 Requires<[UseHVXSgl]>;
113 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
114 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
115 Requires<[UseHVXDbl]>;
118 multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
119 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
120 (MI VecPredRegs:$src1, VecPredRegs:$src2)>,
121 Requires<[UseHVXSgl]>;
122 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2),
123 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>,
124 Requires<[UseHVXDbl]>;
127 multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
128 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
129 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
130 Requires<[UseHVXSgl]>;
131 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3),
132 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>,
133 Requires<[UseHVXDbl]>;
136 multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
137 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
138 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
139 Requires<[UseHVXSgl]>;
140 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
141 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
142 Requires<[UseHVXDbl]>;
145 multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
146 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
147 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
148 Requires<[UseHVXSgl]>;
149 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
150 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
151 Requires<[UseHVXDbl]>;
154 def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
155 def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>;
156 def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>;
157 def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>;
158 def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>;
160 defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>;
161 defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>;
162 defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>;
163 defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>;
164 defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>;
165 defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>;
166 defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>;
167 defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>;
168 defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>;
169 defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>;
170 defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>;
171 defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>;
172 defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>;
173 defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>;
174 defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>;
175 defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>;
176 defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>;
177 defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>;
178 defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>;
179 defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>;
180 defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>;
181 defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>;
182 defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>;
183 defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>;
184 defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>;
185 defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>;
186 defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>;
187 defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>;
188 defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>;
189 defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>;
190 defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>;
191 defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>;
192 defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>;
193 defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>;
194 defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>;
195 defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>;
196 defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>;
197 defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>;
198 defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>;
199 defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>;
200 defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>;
201 defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>;
202 defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>;
203 defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>;
204 defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>;