1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new value jump
22 //===----------------------------------------------------------------------===//
25 #include "HexagonInstrInfo.h"
26 #include "HexagonRegisterInfo.h"
27 #include "HexagonSubtarget.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/TargetOpcodes.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/DebugLoc.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/BranchProbability.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
55 #define DEBUG_TYPE "hexagon-nvj"
57 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
59 static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
60 cl::desc("Maximum number of predicated jumps to be converted to "
63 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
64 cl::ZeroOrMore, cl::init(false),
65 cl::desc("Disable New Value Jumps"));
69 FunctionPass *createHexagonNewValueJump();
70 void initializeHexagonNewValueJumpPass(PassRegistry&);
72 } // end namespace llvm
76 struct HexagonNewValueJump : public MachineFunctionPass {
79 HexagonNewValueJump() : MachineFunctionPass(ID) {}
81 void getAnalysisUsage(AnalysisUsage &AU) const override {
82 AU.addRequired<MachineBranchProbabilityInfo>();
83 MachineFunctionPass::getAnalysisUsage(AU);
86 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
88 bool runOnMachineFunction(MachineFunction &Fn) override;
90 MachineFunctionProperties getRequiredProperties() const override {
91 return MachineFunctionProperties().set(
92 MachineFunctionProperties::Property::NoVRegs);
96 const HexagonInstrInfo *QII;
97 const HexagonRegisterInfo *QRI;
99 /// A handle to the branch probability pass.
100 const MachineBranchProbabilityInfo *MBPI;
102 bool isNewValueJumpCandidate(const MachineInstr &MI) const;
105 } // end anonymous namespace
107 char HexagonNewValueJump::ID = 0;
109 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
110 "Hexagon NewValueJump", false, false)
111 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
112 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
113 "Hexagon NewValueJump", false, false)
115 // We have identified this II could be feeder to NVJ,
116 // verify that it can be.
117 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
118 const TargetRegisterInfo *TRI,
119 MachineBasicBlock::iterator II,
120 MachineBasicBlock::iterator end,
121 MachineBasicBlock::iterator skip,
122 MachineFunction &MF) {
123 // Predicated instruction can not be feeder to NVJ.
124 if (QII->isPredicated(*II))
127 // Bail out if feederReg is a paired register (double regs in
128 // our case). One would think that we can check to see if a given
129 // register cmpReg1 or cmpReg2 is a sub register of feederReg
130 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
131 // before the callsite of this function
132 // But we can not as it comes in the following fashion.
133 // %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
134 // %r0 = KILL %r0, implicit killed %d0
135 // %p0 = CMPEQri killed %r0, 0
136 // Hence, we need to check if it's a KILL instruction.
137 if (II->getOpcode() == TargetOpcode::KILL)
140 if (II->isImplicitDef())
143 if (QII->isSolo(*II))
146 if (QII->isFloat(*II))
149 // Make sure that the (unique) def operand is a register from IntRegs.
151 for (const MachineOperand &Op : II->operands()) {
152 if (!Op.isReg() || !Op.isDef())
157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
162 // Make sure there is no 'def' or 'use' of any of the uses of
163 // feeder insn between its definition, this MI and jump, jmpInst
164 // skipping compare, cmpInst.
165 // Here's the example.
166 // r21=memub(r22+r24<<#0)
167 // p0 = cmp.eq(r21, #0)
168 // r4=memub(r3+r21<<#0)
169 // if (p0.new) jump:t .LBB29_45
170 // Without this check, it will be converted into
171 // r4=memub(r3+r21<<#0)
172 // r21=memub(r22+r24<<#0)
173 // p0 = cmp.eq(r21, #0)
174 // if (p0.new) jump:t .LBB29_45
175 // and result WAR hazards if converted to New Value Jump.
176 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
177 if (II->getOperand(i).isReg() &&
178 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
179 MachineBasicBlock::iterator localII = II;
181 unsigned Reg = II->getOperand(i).getReg();
182 for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
184 if (localBegin == skip)
186 // Check for Subregisters too.
187 if (localBegin->modifiesRegister(Reg, TRI) ||
188 localBegin->readsRegister(Reg, TRI))
196 // These are the common checks that need to performed
198 // 1. compare instruction can be moved before jump.
199 // 2. feeder to the compare instruction can be moved before jump.
200 static bool commonChecksToProhibitNewValueJump(bool afterRA,
201 MachineBasicBlock::iterator MII) {
202 // If store in path, bail out.
206 // if call in path, bail out.
210 // if NVJ is running prior to RA, do the following checks.
212 // The following Target Opcode instructions are spurious
213 // to new value jump. If they are in the path, bail out.
214 // KILL sets kill flag on the opcode. It also sets up a
215 // single register, out of pair.
216 // %d0 = S2_lsr_r_p killed %d0, killed %r2
217 // %r0 = KILL %r0, implicit killed %d0
218 // %p0 = C2_cmpeqi killed %r0, 0
219 // PHI can be anything after RA.
220 // COPY can remateriaze things in between feeder, compare and nvj.
221 if (MII->getOpcode() == TargetOpcode::KILL ||
222 MII->getOpcode() == TargetOpcode::PHI ||
223 MII->getOpcode() == TargetOpcode::COPY)
226 // The following pseudo Hexagon instructions sets "use" and "def"
227 // of registers by individual passes in the backend. At this time,
228 // we don't know the scope of usage and definitions of these
230 if (MII->getOpcode() == Hexagon::LDriw_pred ||
231 MII->getOpcode() == Hexagon::STriw_pred)
238 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
239 const TargetRegisterInfo *TRI,
240 MachineBasicBlock::iterator II,
244 MachineBasicBlock::iterator end,
245 MachineFunction &MF) {
246 MachineInstr &MI = *II;
248 // If the second operand of the compare is an imm, make sure it's in the
249 // range specified by the arch.
251 const MachineOperand &Op2 = MI.getOperand(2);
255 int64_t v = Op2.getImm();
258 switch (MI.getOpcode()) {
259 case Hexagon::C2_cmpeqi:
260 case Hexagon::C4_cmpneqi:
261 case Hexagon::C2_cmpgti:
262 case Hexagon::C4_cmpltei:
263 Valid = (isUInt<5>(v) || v == -1);
265 case Hexagon::C2_cmpgtui:
266 case Hexagon::C4_cmplteui:
267 Valid = isUInt<5>(v);
269 case Hexagon::S2_tstbit_i:
270 case Hexagon::S4_ntstbit_i:
279 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
280 cmpReg1 = MI.getOperand(1).getReg();
283 cmpOp2 = MI.getOperand(2).getReg();
285 // If the same register appears as both operands, we cannot generate a new
286 // value compare. Only one operand may use the .new suffix.
287 if (cmpReg1 == cmpOp2)
290 // Make sure that the second register is not from COPY
291 // at machine code level, we don't need this, but if we decide
292 // to move new value jump prior to RA, we would be needing this.
293 MachineRegisterInfo &MRI = MF.getRegInfo();
294 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
295 MachineInstr *def = MRI.getVRegDef(cmpOp2);
296 if (def->getOpcode() == TargetOpcode::COPY)
301 // Walk the instructions after the compare (predicate def) to the jump,
302 // and satisfy the following conditions.
304 for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
305 if (localII->isDebugInstr())
309 // If "common" checks fail, bail out.
310 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
314 // If there is a def or use of predicate (result of compare), bail out.
315 if (localII->modifiesRegister(pReg, TRI) ||
316 localII->readsRegister(pReg, TRI))
320 // If there is a def of any of the use of the compare (operands of compare),
323 // p0 = cmp.eq(r2, r0)
325 // if (p0.new) jump:t .LBB28_3
326 if (localII->modifiesRegister(cmpReg1, TRI) ||
327 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
333 // Given a compare operator, return a matching New Value Jump compare operator.
334 // Make sure that MI here is included in isNewValueJumpCandidate.
335 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
336 bool secondRegNewified,
337 MachineBasicBlock *jmpTarget,
338 const MachineBranchProbabilityInfo
341 MachineBasicBlock *Src = MI->getParent();
342 const BranchProbability Prediction =
343 MBPI->getEdgeProbability(Src, jmpTarget);
345 if (Prediction >= BranchProbability(1,2))
348 switch (MI->getOpcode()) {
349 case Hexagon::C2_cmpeq:
350 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
351 : Hexagon::J4_cmpeq_t_jumpnv_nt;
353 case Hexagon::C2_cmpeqi:
355 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
356 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
357 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
358 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
360 case Hexagon::C4_cmpneqi:
362 return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
363 : Hexagon::J4_cmpeqi_f_jumpnv_nt;
364 return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
365 Hexagon::J4_cmpeqn1_f_jumpnv_nt;
367 case Hexagon::C2_cmpgt:
368 if (secondRegNewified)
369 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
370 : Hexagon::J4_cmplt_t_jumpnv_nt;
371 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
372 : Hexagon::J4_cmpgt_t_jumpnv_nt;
374 case Hexagon::C2_cmpgti:
376 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
377 : Hexagon::J4_cmpgti_t_jumpnv_nt;
378 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
379 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
381 case Hexagon::C2_cmpgtu:
382 if (secondRegNewified)
383 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
384 : Hexagon::J4_cmpltu_t_jumpnv_nt;
385 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
386 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
388 case Hexagon::C2_cmpgtui:
389 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
390 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
392 case Hexagon::C4_cmpneq:
393 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
394 : Hexagon::J4_cmpeq_f_jumpnv_nt;
396 case Hexagon::C4_cmplte:
397 if (secondRegNewified)
398 return taken ? Hexagon::J4_cmplt_f_jumpnv_t
399 : Hexagon::J4_cmplt_f_jumpnv_nt;
400 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
401 : Hexagon::J4_cmpgt_f_jumpnv_nt;
403 case Hexagon::C4_cmplteu:
404 if (secondRegNewified)
405 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
406 : Hexagon::J4_cmpltu_f_jumpnv_nt;
407 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
408 : Hexagon::J4_cmpgtu_f_jumpnv_nt;
410 case Hexagon::C4_cmpltei:
412 return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
413 : Hexagon::J4_cmpgti_f_jumpnv_nt;
414 return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
415 : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
417 case Hexagon::C4_cmplteui:
418 return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
419 : Hexagon::J4_cmpgtui_f_jumpnv_nt;
422 llvm_unreachable("Could not find matching New Value Jump instruction.");
424 // return *some value* to avoid compiler warning
428 bool HexagonNewValueJump::isNewValueJumpCandidate(
429 const MachineInstr &MI) const {
430 switch (MI.getOpcode()) {
431 case Hexagon::C2_cmpeq:
432 case Hexagon::C2_cmpeqi:
433 case Hexagon::C2_cmpgt:
434 case Hexagon::C2_cmpgti:
435 case Hexagon::C2_cmpgtu:
436 case Hexagon::C2_cmpgtui:
437 case Hexagon::C4_cmpneq:
438 case Hexagon::C4_cmpneqi:
439 case Hexagon::C4_cmplte:
440 case Hexagon::C4_cmplteu:
441 case Hexagon::C4_cmpltei:
442 case Hexagon::C4_cmplteui:
450 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
451 LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
452 << "********** Function: " << MF.getName() << "\n");
454 if (skipFunction(MF.getFunction()))
457 // If we move NewValueJump before register allocation we'll need live variable
458 // analysis here too.
460 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
461 QRI = static_cast<const HexagonRegisterInfo *>(
462 MF.getSubtarget().getRegisterInfo());
463 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
465 if (DisableNewValueJumps ||
466 !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
469 int nvjCount = DbgNVJCount;
470 int nvjGenerated = 0;
472 // Loop through all the bb's of the function
473 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
474 MBBb != MBBe; ++MBBb) {
475 MachineBasicBlock *MBB = &*MBBb;
477 LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
478 LLVM_DEBUG(MBB->dump());
479 LLVM_DEBUG(dbgs() << "\n"
480 << "********** dumping instr bottom up **********\n");
481 bool foundJump = false;
482 bool foundCompare = false;
483 bool invertPredicate = false;
484 unsigned predReg = 0; // predicate reg of the jump.
485 unsigned cmpReg1 = 0;
487 MachineBasicBlock::iterator jmpPos;
488 MachineBasicBlock::iterator cmpPos;
489 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
490 MachineBasicBlock *jmpTarget = nullptr;
491 bool afterRA = false;
492 bool isSecondOpReg = false;
493 bool isSecondOpNewified = false;
494 // Traverse the basic block - bottom up
495 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
497 MachineInstr &MI = *--MII;
498 if (MI.isDebugInstr()) {
502 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
505 LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
507 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
508 MI.getOpcode() == Hexagon::J2_jumptpt ||
509 MI.getOpcode() == Hexagon::J2_jumpf ||
510 MI.getOpcode() == Hexagon::J2_jumpfpt ||
511 MI.getOpcode() == Hexagon::J2_jumptnewpt ||
512 MI.getOpcode() == Hexagon::J2_jumptnew ||
513 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
514 MI.getOpcode() == Hexagon::J2_jumpfnew)) {
515 // This is where you would insert your compare and
516 // instr that feeds compare
519 predReg = MI.getOperand(0).getReg();
520 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
522 // If ifconverter had not messed up with the kill flags of the
523 // operands, the following check on the kill flag would suffice.
524 // if(!jmpInstr->getOperand(0).isKill()) break;
526 // This predicate register is live out of BB
527 // this would only work if we can actually use Live
528 // variable analysis on phy regs - but LLVM does not
529 // provide LV analysis on phys regs.
530 //if(LVs.isLiveOut(predReg, *MBB)) break;
532 // Get all the successors of this block - which will always
533 // be 2. Check if the predicate register is live-in in those
534 // successor. If yes, we can not delete the predicate -
535 // I am doing this only because LLVM does not provide LiveOut
537 bool predLive = false;
538 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
539 SIE = MBB->succ_end();
541 MachineBasicBlock *succMBB = *SI;
542 if (succMBB->isLiveIn(predReg))
548 if (!MI.getOperand(1).isMBB())
550 jmpTarget = MI.getOperand(1).getMBB();
552 if (MI.getOpcode() == Hexagon::J2_jumpf ||
553 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
554 MI.getOpcode() == Hexagon::J2_jumpfnew) {
555 invertPredicate = true;
560 // No new value jump if there is a barrier. A barrier has to be in its
561 // own packet. A barrier has zero operands. We conservatively bail out
562 // here if we see any instruction with zero operands.
563 if (foundJump && MI.getNumOperands() == 0)
566 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
567 MI.getOperand(0).getReg() == predReg) {
568 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
569 if (isNewValueJumpCandidate(MI)) {
571 (MI.getDesc().isCompare()) &&
572 "Only compare instruction can be collapsed into New Value Jump");
573 isSecondOpReg = MI.getOperand(2).isReg();
575 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
576 afterRA, jmpPos, MF))
583 // We need cmpReg1 and cmpOp2(imm or reg) while building
584 // new value jump instruction.
585 cmpReg1 = MI.getOperand(1).getReg();
588 cmpOp2 = MI.getOperand(2).getReg();
590 cmpOp2 = MI.getOperand(2).getImm();
595 if (foundCompare && foundJump) {
596 // If "common" checks fail, bail out on this BB.
597 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
600 bool foundFeeder = false;
601 MachineBasicBlock::iterator feederPos = MII;
602 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
603 (MI.getOperand(0).getReg() == cmpReg1 ||
605 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
607 unsigned feederReg = MI.getOperand(0).getReg();
609 // First try to see if we can get the feeder from the first operand
610 // of the compare. If we can not, and if secondOpReg is true
611 // (second operand of the compare is also register), try that one.
612 // TODO: Try to come up with some heuristic to figure out which
613 // feeder would benefit.
615 if (feederReg == cmpReg1) {
616 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
625 if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
626 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
630 // In case of CMPLT, or CMPLTU, or EQ with the second register
631 // to newify, swap the operands.
632 unsigned COp = cmpInstr->getOpcode();
633 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
634 (feederReg == (unsigned)cmpOp2)) {
635 unsigned tmp = cmpReg1;
640 // Now we have swapped the operands, all we need to check is,
641 // if the second operand (after swap) is the feeder.
642 // And if it is, make a note.
643 if (feederReg == (unsigned)cmpOp2)
644 isSecondOpNewified = true;
647 // Now that we are moving feeder close the jump,
648 // make sure we are respecting the kill values of
649 // the operands of the feeder.
651 auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
652 for (MachineOperand &MO : MI.operands()) {
653 if (!MO.isReg() || !MO.isUse())
655 unsigned UseR = MO.getReg();
656 for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
659 for (MachineOperand &Op : I->operands()) {
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
662 if (Op.getReg() != UseR)
664 // We found that there is kill of a use register
665 // Set up a kill flag on the register
674 TransferKills(*feederPos);
675 TransferKills(*cmpPos);
676 bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
677 bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
679 MBB->splice(jmpPos, MI.getParent(), MI);
680 MBB->splice(jmpPos, MI.getParent(), cmpInstr);
681 DebugLoc dl = MI.getDebugLoc();
684 assert((isNewValueJumpCandidate(*cmpInstr)) &&
685 "This compare is not a New Value Jump candidate.");
686 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
690 opc = QII->getInvertedPredicatedOpcode(opc);
693 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
694 .addReg(cmpReg1, getKillRegState(MO1IsKill))
695 .addReg(cmpOp2, getKillRegState(MO2IsKill))
699 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
700 .addReg(cmpReg1, getKillRegState(MO1IsKill))
704 assert(NewMI && "New Value Jump Instruction Not created!");
706 if (cmpInstr->getOperand(0).isReg() &&
707 cmpInstr->getOperand(0).isKill())
708 cmpInstr->getOperand(0).setIsKill(false);
709 if (cmpInstr->getOperand(1).isReg() &&
710 cmpInstr->getOperand(1).isKill())
711 cmpInstr->getOperand(1).setIsKill(false);
712 cmpInstr->eraseFromParent();
713 jmpInstr->eraseFromParent();
725 FunctionPass *llvm::createHexagonNewValueJump() {
726 return new HexagonNewValueJump();