1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
25 #include "HexagonInstrInfo.h"
26 #include "HexagonMachineFunctionInfo.h"
27 #include "HexagonRegisterInfo.h"
28 #include "HexagonSubtarget.h"
29 #include "HexagonTargetMachine.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/LiveVariables.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/PassSupport.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
47 #define DEBUG_TYPE "hexagon-nvj"
49 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
52 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
53 "Maximum number of predicated jumps to be converted to New Value Jump"));
55 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
56 cl::ZeroOrMore, cl::init(false),
57 cl::desc("Disable New Value Jumps"));
60 FunctionPass *createHexagonNewValueJump();
61 void initializeHexagonNewValueJumpPass(PassRegistry&);
66 struct HexagonNewValueJump : public MachineFunctionPass {
67 const HexagonInstrInfo *QII;
68 const HexagonRegisterInfo *QRI;
73 HexagonNewValueJump() : MachineFunctionPass(ID) {
74 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
77 void getAnalysisUsage(AnalysisUsage &AU) const override {
78 AU.addRequired<MachineBranchProbabilityInfo>();
79 MachineFunctionPass::getAnalysisUsage(AU);
82 const char *getPassName() const override {
83 return "Hexagon NewValueJump";
86 bool runOnMachineFunction(MachineFunction &Fn) override;
87 MachineFunctionProperties getRequiredProperties() const override {
88 return MachineFunctionProperties().set(
89 MachineFunctionProperties::Property::AllVRegsAllocated);
93 /// \brief A handle to the branch probability pass.
94 const MachineBranchProbabilityInfo *MBPI;
96 bool isNewValueJumpCandidate(const MachineInstr &MI) const;
99 } // end of anonymous namespace
101 char HexagonNewValueJump::ID = 0;
103 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
104 "Hexagon NewValueJump", false, false)
105 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
106 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
107 "Hexagon NewValueJump", false, false)
110 // We have identified this II could be feeder to NVJ,
111 // verify that it can be.
112 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
113 const TargetRegisterInfo *TRI,
114 MachineBasicBlock::iterator II,
115 MachineBasicBlock::iterator end,
116 MachineBasicBlock::iterator skip,
117 MachineFunction &MF) {
119 // Predicated instruction can not be feeder to NVJ.
120 if (QII->isPredicated(*II))
123 // Bail out if feederReg is a paired register (double regs in
124 // our case). One would think that we can check to see if a given
125 // register cmpReg1 or cmpReg2 is a sub register of feederReg
126 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
127 // before the callsite of this function
128 // But we can not as it comes in the following fashion.
129 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
130 // %R0<def> = KILL %R0, %D0<imp-use,kill>
131 // %P0<def> = CMPEQri %R0<kill>, 0
132 // Hence, we need to check if it's a KILL instruction.
133 if (II->getOpcode() == TargetOpcode::KILL)
137 // Make sure there there is no 'def' or 'use' of any of the uses of
138 // feeder insn between it's definition, this MI and jump, jmpInst
139 // skipping compare, cmpInst.
140 // Here's the example.
141 // r21=memub(r22+r24<<#0)
142 // p0 = cmp.eq(r21, #0)
143 // r4=memub(r3+r21<<#0)
144 // if (p0.new) jump:t .LBB29_45
145 // Without this check, it will be converted into
146 // r4=memub(r3+r21<<#0)
147 // r21=memub(r22+r24<<#0)
148 // p0 = cmp.eq(r21, #0)
149 // if (p0.new) jump:t .LBB29_45
150 // and result WAR hazards if converted to New Value Jump.
152 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
153 if (II->getOperand(i).isReg() &&
154 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
155 MachineBasicBlock::iterator localII = II;
157 unsigned Reg = II->getOperand(i).getReg();
158 for (MachineBasicBlock::iterator localBegin = localII;
159 localBegin != end; ++localBegin) {
160 if (localBegin == skip ) continue;
161 // Check for Subregisters too.
162 if (localBegin->modifiesRegister(Reg, TRI) ||
163 localBegin->readsRegister(Reg, TRI))
171 // These are the common checks that need to performed
173 // 1. compare instruction can be moved before jump.
174 // 2. feeder to the compare instruction can be moved before jump.
175 static bool commonChecksToProhibitNewValueJump(bool afterRA,
176 MachineBasicBlock::iterator MII) {
178 // If store in path, bail out.
179 if (MII->getDesc().mayStore())
182 // if call in path, bail out.
183 if (MII->getOpcode() == Hexagon::J2_call)
186 // if NVJ is running prior to RA, do the following checks.
188 // The following Target Opcode instructions are spurious
189 // to new value jump. If they are in the path, bail out.
190 // KILL sets kill flag on the opcode. It also sets up a
191 // single register, out of pair.
192 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
193 // %R0<def> = KILL %R0, %D0<imp-use,kill>
194 // %P0<def> = CMPEQri %R0<kill>, 0
195 // PHI can be anything after RA.
196 // COPY can remateriaze things in between feeder, compare and nvj.
197 if (MII->getOpcode() == TargetOpcode::KILL ||
198 MII->getOpcode() == TargetOpcode::PHI ||
199 MII->getOpcode() == TargetOpcode::COPY)
202 // The following pseudo Hexagon instructions sets "use" and "def"
203 // of registers by individual passes in the backend. At this time,
204 // we don't know the scope of usage and definitions of these
206 if (MII->getOpcode() == Hexagon::LDriw_pred ||
207 MII->getOpcode() == Hexagon::STriw_pred)
214 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
215 const TargetRegisterInfo *TRI,
216 MachineBasicBlock::iterator II,
220 MachineBasicBlock::iterator end,
221 MachineFunction &MF) {
223 MachineInstr &MI = *II;
225 // If the second operand of the compare is an imm, make sure it's in the
226 // range specified by the arch.
228 int64_t v = MI.getOperand(2).getImm();
230 if (!(isUInt<5>(v) || ((MI.getOpcode() == Hexagon::C2_cmpeqi ||
231 MI.getOpcode() == Hexagon::C2_cmpgti) &&
236 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
237 cmpReg1 = MI.getOperand(1).getReg();
240 cmpOp2 = MI.getOperand(2).getReg();
242 // Make sure that that second register is not from COPY
243 // At machine code level, we don't need this, but if we decide
244 // to move new value jump prior to RA, we would be needing this.
245 MachineRegisterInfo &MRI = MF.getRegInfo();
246 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
247 MachineInstr *def = MRI.getVRegDef(cmpOp2);
248 if (def->getOpcode() == TargetOpcode::COPY)
253 // Walk the instructions after the compare (predicate def) to the jump,
254 // and satisfy the following conditions.
256 for (MachineBasicBlock::iterator localII = II; localII != end;
260 // If "common" checks fail, bail out.
261 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
265 // If there is a def or use of predicate (result of compare), bail out.
266 if (localII->modifiesRegister(pReg, TRI) ||
267 localII->readsRegister(pReg, TRI))
271 // If there is a def of any of the use of the compare (operands of compare),
274 // p0 = cmp.eq(r2, r0)
276 // if (p0.new) jump:t .LBB28_3
277 if (localII->modifiesRegister(cmpReg1, TRI) ||
278 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
285 // Given a compare operator, return a matching New Value Jump compare operator.
286 // Make sure that MI here is included in isNewValueJumpCandidate.
287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
288 bool secondRegNewified,
289 MachineBasicBlock *jmpTarget,
290 const MachineBranchProbabilityInfo
293 MachineBasicBlock *Src = MI->getParent();
294 const BranchProbability Prediction =
295 MBPI->getEdgeProbability(Src, jmpTarget);
297 if (Prediction >= BranchProbability(1,2))
300 switch (MI->getOpcode()) {
301 case Hexagon::C2_cmpeq:
302 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
303 : Hexagon::J4_cmpeq_t_jumpnv_nt;
305 case Hexagon::C2_cmpeqi: {
307 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
308 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
310 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
311 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
314 case Hexagon::C2_cmpgt: {
315 if (secondRegNewified)
316 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
317 : Hexagon::J4_cmplt_t_jumpnv_nt;
319 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
320 : Hexagon::J4_cmpgt_t_jumpnv_nt;
323 case Hexagon::C2_cmpgti: {
325 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
326 : Hexagon::J4_cmpgti_t_jumpnv_nt;
328 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
329 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
332 case Hexagon::C2_cmpgtu: {
333 if (secondRegNewified)
334 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
335 : Hexagon::J4_cmpltu_t_jumpnv_nt;
337 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
338 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
341 case Hexagon::C2_cmpgtui:
342 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
343 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
345 case Hexagon::C4_cmpneq:
346 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
347 : Hexagon::J4_cmpeq_f_jumpnv_nt;
349 case Hexagon::C4_cmplte:
350 if (secondRegNewified)
351 return taken ? Hexagon::J4_cmplt_f_jumpnv_t
352 : Hexagon::J4_cmplt_f_jumpnv_nt;
353 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
354 : Hexagon::J4_cmpgt_f_jumpnv_nt;
356 case Hexagon::C4_cmplteu:
357 if (secondRegNewified)
358 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
359 : Hexagon::J4_cmpltu_f_jumpnv_nt;
360 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
361 : Hexagon::J4_cmpgtu_f_jumpnv_nt;
364 llvm_unreachable("Could not find matching New Value Jump instruction.");
366 // return *some value* to avoid compiler warning
370 bool HexagonNewValueJump::isNewValueJumpCandidate(
371 const MachineInstr &MI) const {
372 switch (MI.getOpcode()) {
373 case Hexagon::C2_cmpeq:
374 case Hexagon::C2_cmpeqi:
375 case Hexagon::C2_cmpgt:
376 case Hexagon::C2_cmpgti:
377 case Hexagon::C2_cmpgtu:
378 case Hexagon::C2_cmpgtui:
379 case Hexagon::C4_cmpneq:
380 case Hexagon::C4_cmplte:
381 case Hexagon::C4_cmplteu:
390 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
392 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
393 << "********** Function: "
394 << MF.getName() << "\n");
396 if (skipFunction(*MF.getFunction()))
399 // If we move NewValueJump before register allocation we'll need live variable
400 // analysis here too.
402 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
403 QRI = static_cast<const HexagonRegisterInfo *>(
404 MF.getSubtarget().getRegisterInfo());
405 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
407 if (DisableNewValueJumps) {
411 int nvjCount = DbgNVJCount;
412 int nvjGenerated = 0;
414 // Loop through all the bb's of the function
415 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
416 MBBb != MBBe; ++MBBb) {
417 MachineBasicBlock *MBB = &*MBBb;
419 DEBUG(dbgs() << "** dumping bb ** "
420 << MBB->getNumber() << "\n");
422 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
423 bool foundJump = false;
424 bool foundCompare = false;
425 bool invertPredicate = false;
426 unsigned predReg = 0; // predicate reg of the jump.
427 unsigned cmpReg1 = 0;
429 bool MO1IsKill = false;
430 bool MO2IsKill = false;
431 MachineBasicBlock::iterator jmpPos;
432 MachineBasicBlock::iterator cmpPos;
433 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
434 MachineBasicBlock *jmpTarget = nullptr;
435 bool afterRA = false;
436 bool isSecondOpReg = false;
437 bool isSecondOpNewified = false;
438 // Traverse the basic block - bottom up
439 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
441 MachineInstr &MI = *--MII;
442 if (MI.isDebugValue()) {
446 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
449 DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
451 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
452 MI.getOpcode() == Hexagon::J2_jumpf ||
453 MI.getOpcode() == Hexagon::J2_jumptnewpt ||
454 MI.getOpcode() == Hexagon::J2_jumptnew ||
455 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
456 MI.getOpcode() == Hexagon::J2_jumpfnew)) {
457 // This is where you would insert your compare and
458 // instr that feeds compare
461 predReg = MI.getOperand(0).getReg();
462 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
464 // If ifconverter had not messed up with the kill flags of the
465 // operands, the following check on the kill flag would suffice.
466 // if(!jmpInstr->getOperand(0).isKill()) break;
468 // This predicate register is live out out of BB
469 // this would only work if we can actually use Live
470 // variable analysis on phy regs - but LLVM does not
471 // provide LV analysis on phys regs.
472 //if(LVs.isLiveOut(predReg, *MBB)) break;
474 // Get all the successors of this block - which will always
475 // be 2. Check if the predicate register is live in in those
476 // successor. If yes, we can not delete the predicate -
477 // I am doing this only because LLVM does not provide LiveOut
479 bool predLive = false;
480 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
481 SIE = MBB->succ_end(); SI != SIE; ++SI) {
482 MachineBasicBlock* succMBB = *SI;
483 if (succMBB->isLiveIn(predReg)) {
490 if (!MI.getOperand(1).isMBB())
492 jmpTarget = MI.getOperand(1).getMBB();
494 if (MI.getOpcode() == Hexagon::J2_jumpf ||
495 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
496 MI.getOpcode() == Hexagon::J2_jumpfnew) {
497 invertPredicate = true;
502 // No new value jump if there is a barrier. A barrier has to be in its
503 // own packet. A barrier has zero operands. We conservatively bail out
504 // here if we see any instruction with zero operands.
505 if (foundJump && MI.getNumOperands() == 0)
508 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
509 MI.getOperand(0).getReg() == predReg) {
511 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
512 if (isNewValueJumpCandidate(MI)) {
515 (MI.getDesc().isCompare()) &&
516 "Only compare instruction can be collapsed into New Value Jump");
517 isSecondOpReg = MI.getOperand(2).isReg();
519 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
520 afterRA, jmpPos, MF))
527 // We need cmpReg1 and cmpOp2(imm or reg) while building
528 // new value jump instruction.
529 cmpReg1 = MI.getOperand(1).getReg();
530 if (MI.getOperand(1).isKill())
534 cmpOp2 = MI.getOperand(2).getReg();
535 if (MI.getOperand(2).isKill())
538 cmpOp2 = MI.getOperand(2).getImm();
543 if (foundCompare && foundJump) {
545 // If "common" checks fail, bail out on this BB.
546 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
549 bool foundFeeder = false;
550 MachineBasicBlock::iterator feederPos = MII;
551 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
552 (MI.getOperand(0).getReg() == cmpReg1 ||
554 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
556 unsigned feederReg = MI.getOperand(0).getReg();
558 // First try to see if we can get the feeder from the first operand
559 // of the compare. If we can not, and if secondOpReg is true
560 // (second operand of the compare is also register), try that one.
561 // TODO: Try to come up with some heuristic to figure out which
562 // feeder would benefit.
564 if (feederReg == cmpReg1) {
565 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
576 feederReg == (unsigned) cmpOp2)
577 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
581 // In case of CMPLT, or CMPLTU, or EQ with the second register
582 // to newify, swap the operands.
583 if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
584 feederReg == (unsigned) cmpOp2) {
585 unsigned tmp = cmpReg1;
586 bool tmpIsKill = MO1IsKill;
588 MO1IsKill = MO2IsKill;
590 MO2IsKill = tmpIsKill;
593 // Now we have swapped the operands, all we need to check is,
594 // if the second operand (after swap) is the feeder.
595 // And if it is, make a note.
596 if (feederReg == (unsigned)cmpOp2)
597 isSecondOpNewified = true;
600 // Now that we are moving feeder close the jump,
601 // make sure we are respecting the kill values of
602 // the operands of the feeder.
604 bool updatedIsKill = false;
605 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
606 MachineOperand &MO = MI.getOperand(i);
607 if (MO.isReg() && MO.isUse()) {
608 unsigned feederReg = MO.getReg();
609 for (MachineBasicBlock::iterator localII = feederPos,
610 end = jmpPos; localII != end; localII++) {
611 MachineInstr &localMI = *localII;
612 for (unsigned j = 0; j < localMI.getNumOperands(); j++) {
613 MachineOperand &localMO = localMI.getOperand(j);
614 if (localMO.isReg() && localMO.isUse() &&
615 localMO.isKill() && feederReg == localMO.getReg()) {
616 // We found that there is kill of a use register
617 // Set up a kill flag on the register
618 localMO.setIsKill(false);
620 updatedIsKill = true;
624 if (updatedIsKill) break;
627 if (updatedIsKill) break;
630 MBB->splice(jmpPos, MI.getParent(), MI);
631 MBB->splice(jmpPos, MI.getParent(), cmpInstr);
632 DebugLoc dl = MI.getDebugLoc();
635 assert((isNewValueJumpCandidate(*cmpInstr)) &&
636 "This compare is not a New Value Jump candidate.");
637 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
641 opc = QII->getInvertedPredicatedOpcode(opc);
644 NewMI = BuildMI(*MBB, jmpPos, dl,
646 .addReg(cmpReg1, getKillRegState(MO1IsKill))
647 .addReg(cmpOp2, getKillRegState(MO2IsKill))
650 else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi ||
651 cmpInstr->getOpcode() == Hexagon::C2_cmpgti) &&
653 // Corresponding new-value compare jump instructions don't have the
654 // operand for -1 immediate value.
655 NewMI = BuildMI(*MBB, jmpPos, dl,
657 .addReg(cmpReg1, getKillRegState(MO1IsKill))
661 NewMI = BuildMI(*MBB, jmpPos, dl,
663 .addReg(cmpReg1, getKillRegState(MO1IsKill))
667 assert(NewMI && "New Value Jump Instruction Not created!");
669 if (cmpInstr->getOperand(0).isReg() &&
670 cmpInstr->getOperand(0).isKill())
671 cmpInstr->getOperand(0).setIsKill(false);
672 if (cmpInstr->getOperand(1).isReg() &&
673 cmpInstr->getOperand(1).isKill())
674 cmpInstr->getOperand(1).setIsKill(false);
675 cmpInstr->eraseFromParent();
676 jmpInstr->eraseFromParent();
689 FunctionPass *llvm::createHexagonNewValueJump() {
690 return new HexagonNewValueJump();