1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
25 #include "HexagonInstrInfo.h"
26 #include "HexagonMachineFunctionInfo.h"
27 #include "HexagonRegisterInfo.h"
28 #include "HexagonSubtarget.h"
29 #include "HexagonTargetMachine.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/LiveVariables.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
37 #include "llvm/PassSupport.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
46 #define DEBUG_TYPE "hexagon-nvj"
48 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
51 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
52 "Maximum number of predicated jumps to be converted to New Value Jump"));
54 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
55 cl::ZeroOrMore, cl::init(false),
56 cl::desc("Disable New Value Jumps"));
59 FunctionPass *createHexagonNewValueJump();
60 void initializeHexagonNewValueJumpPass(PassRegistry&);
65 struct HexagonNewValueJump : public MachineFunctionPass {
66 const HexagonInstrInfo *QII;
67 const HexagonRegisterInfo *QRI;
72 HexagonNewValueJump() : MachineFunctionPass(ID) {
73 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
76 void getAnalysisUsage(AnalysisUsage &AU) const override {
77 AU.addRequired<MachineBranchProbabilityInfo>();
78 MachineFunctionPass::getAnalysisUsage(AU);
81 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
83 bool runOnMachineFunction(MachineFunction &Fn) override;
84 MachineFunctionProperties getRequiredProperties() const override {
85 return MachineFunctionProperties().set(
86 MachineFunctionProperties::Property::NoVRegs);
90 /// \brief A handle to the branch probability pass.
91 const MachineBranchProbabilityInfo *MBPI;
93 bool isNewValueJumpCandidate(const MachineInstr &MI) const;
96 } // end of anonymous namespace
98 char HexagonNewValueJump::ID = 0;
100 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
101 "Hexagon NewValueJump", false, false)
102 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
103 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
104 "Hexagon NewValueJump", false, false)
107 // We have identified this II could be feeder to NVJ,
108 // verify that it can be.
109 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
110 const TargetRegisterInfo *TRI,
111 MachineBasicBlock::iterator II,
112 MachineBasicBlock::iterator end,
113 MachineBasicBlock::iterator skip,
114 MachineFunction &MF) {
116 // Predicated instruction can not be feeder to NVJ.
117 if (QII->isPredicated(*II))
120 // Bail out if feederReg is a paired register (double regs in
121 // our case). One would think that we can check to see if a given
122 // register cmpReg1 or cmpReg2 is a sub register of feederReg
123 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
124 // before the callsite of this function
125 // But we can not as it comes in the following fashion.
126 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
127 // %R0<def> = KILL %R0, %D0<imp-use,kill>
128 // %P0<def> = CMPEQri %R0<kill>, 0
129 // Hence, we need to check if it's a KILL instruction.
130 if (II->getOpcode() == TargetOpcode::KILL)
133 if (II->isImplicitDef())
136 // Make sure there there is no 'def' or 'use' of any of the uses of
137 // feeder insn between it's definition, this MI and jump, jmpInst
138 // skipping compare, cmpInst.
139 // Here's the example.
140 // r21=memub(r22+r24<<#0)
141 // p0 = cmp.eq(r21, #0)
142 // r4=memub(r3+r21<<#0)
143 // if (p0.new) jump:t .LBB29_45
144 // Without this check, it will be converted into
145 // r4=memub(r3+r21<<#0)
146 // r21=memub(r22+r24<<#0)
147 // p0 = cmp.eq(r21, #0)
148 // if (p0.new) jump:t .LBB29_45
149 // and result WAR hazards if converted to New Value Jump.
151 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
152 if (II->getOperand(i).isReg() &&
153 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
154 MachineBasicBlock::iterator localII = II;
156 unsigned Reg = II->getOperand(i).getReg();
157 for (MachineBasicBlock::iterator localBegin = localII;
158 localBegin != end; ++localBegin) {
159 if (localBegin == skip ) continue;
160 // Check for Subregisters too.
161 if (localBegin->modifiesRegister(Reg, TRI) ||
162 localBegin->readsRegister(Reg, TRI))
170 // These are the common checks that need to performed
172 // 1. compare instruction can be moved before jump.
173 // 2. feeder to the compare instruction can be moved before jump.
174 static bool commonChecksToProhibitNewValueJump(bool afterRA,
175 MachineBasicBlock::iterator MII) {
177 // If store in path, bail out.
178 if (MII->getDesc().mayStore())
181 // if call in path, bail out.
185 // if NVJ is running prior to RA, do the following checks.
187 // The following Target Opcode instructions are spurious
188 // to new value jump. If they are in the path, bail out.
189 // KILL sets kill flag on the opcode. It also sets up a
190 // single register, out of pair.
191 // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill>
192 // %R0<def> = KILL %R0, %D0<imp-use,kill>
193 // %P0<def> = C2_cmpeqi %R0<kill>, 0
194 // PHI can be anything after RA.
195 // COPY can remateriaze things in between feeder, compare and nvj.
196 if (MII->getOpcode() == TargetOpcode::KILL ||
197 MII->getOpcode() == TargetOpcode::PHI ||
198 MII->getOpcode() == TargetOpcode::COPY)
201 // The following pseudo Hexagon instructions sets "use" and "def"
202 // of registers by individual passes in the backend. At this time,
203 // we don't know the scope of usage and definitions of these
205 if (MII->getOpcode() == Hexagon::LDriw_pred ||
206 MII->getOpcode() == Hexagon::STriw_pred)
213 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
214 const TargetRegisterInfo *TRI,
215 MachineBasicBlock::iterator II,
219 MachineBasicBlock::iterator end,
220 MachineFunction &MF) {
222 MachineInstr &MI = *II;
224 // If the second operand of the compare is an imm, make sure it's in the
225 // range specified by the arch.
227 int64_t v = MI.getOperand(2).getImm();
230 switch (MI.getOpcode()) {
231 case Hexagon::C2_cmpeqi:
232 case Hexagon::C2_cmpgti:
233 Valid = (isUInt<5>(v) || v == -1);
235 case Hexagon::C2_cmpgtui:
236 Valid = isUInt<5>(v);
238 case Hexagon::S2_tstbit_i:
239 case Hexagon::S4_ntstbit_i:
248 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
249 cmpReg1 = MI.getOperand(1).getReg();
252 cmpOp2 = MI.getOperand(2).getReg();
254 // If the same register appears as both operands, we cannot generate a new
255 // value compare. Only one operand may use the .new suffix.
256 if (cmpReg1 == cmpOp2)
259 // Make sure that that second register is not from COPY
260 // At machine code level, we don't need this, but if we decide
261 // to move new value jump prior to RA, we would be needing this.
262 MachineRegisterInfo &MRI = MF.getRegInfo();
263 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
264 MachineInstr *def = MRI.getVRegDef(cmpOp2);
265 if (def->getOpcode() == TargetOpcode::COPY)
270 // Walk the instructions after the compare (predicate def) to the jump,
271 // and satisfy the following conditions.
273 for (MachineBasicBlock::iterator localII = II; localII != end;
275 if (localII->isDebugValue())
279 // If "common" checks fail, bail out.
280 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
284 // If there is a def or use of predicate (result of compare), bail out.
285 if (localII->modifiesRegister(pReg, TRI) ||
286 localII->readsRegister(pReg, TRI))
290 // If there is a def of any of the use of the compare (operands of compare),
293 // p0 = cmp.eq(r2, r0)
295 // if (p0.new) jump:t .LBB28_3
296 if (localII->modifiesRegister(cmpReg1, TRI) ||
297 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
304 // Given a compare operator, return a matching New Value Jump compare operator.
305 // Make sure that MI here is included in isNewValueJumpCandidate.
306 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
307 bool secondRegNewified,
308 MachineBasicBlock *jmpTarget,
309 const MachineBranchProbabilityInfo
312 MachineBasicBlock *Src = MI->getParent();
313 const BranchProbability Prediction =
314 MBPI->getEdgeProbability(Src, jmpTarget);
316 if (Prediction >= BranchProbability(1,2))
319 switch (MI->getOpcode()) {
320 case Hexagon::C2_cmpeq:
321 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
322 : Hexagon::J4_cmpeq_t_jumpnv_nt;
324 case Hexagon::C2_cmpeqi: {
326 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
327 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
329 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
330 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
333 case Hexagon::C2_cmpgt: {
334 if (secondRegNewified)
335 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
336 : Hexagon::J4_cmplt_t_jumpnv_nt;
338 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
339 : Hexagon::J4_cmpgt_t_jumpnv_nt;
342 case Hexagon::C2_cmpgti: {
344 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
345 : Hexagon::J4_cmpgti_t_jumpnv_nt;
347 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
348 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
351 case Hexagon::C2_cmpgtu: {
352 if (secondRegNewified)
353 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
354 : Hexagon::J4_cmpltu_t_jumpnv_nt;
356 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
357 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
360 case Hexagon::C2_cmpgtui:
361 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
362 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
364 case Hexagon::C4_cmpneq:
365 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
366 : Hexagon::J4_cmpeq_f_jumpnv_nt;
368 case Hexagon::C4_cmplte:
369 if (secondRegNewified)
370 return taken ? Hexagon::J4_cmplt_f_jumpnv_t
371 : Hexagon::J4_cmplt_f_jumpnv_nt;
372 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
373 : Hexagon::J4_cmpgt_f_jumpnv_nt;
375 case Hexagon::C4_cmplteu:
376 if (secondRegNewified)
377 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
378 : Hexagon::J4_cmpltu_f_jumpnv_nt;
379 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
380 : Hexagon::J4_cmpgtu_f_jumpnv_nt;
383 llvm_unreachable("Could not find matching New Value Jump instruction.");
385 // return *some value* to avoid compiler warning
389 bool HexagonNewValueJump::isNewValueJumpCandidate(
390 const MachineInstr &MI) const {
391 switch (MI.getOpcode()) {
392 case Hexagon::C2_cmpeq:
393 case Hexagon::C2_cmpeqi:
394 case Hexagon::C2_cmpgt:
395 case Hexagon::C2_cmpgti:
396 case Hexagon::C2_cmpgtu:
397 case Hexagon::C2_cmpgtui:
398 case Hexagon::C4_cmpneq:
399 case Hexagon::C4_cmplte:
400 case Hexagon::C4_cmplteu:
409 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
411 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
412 << "********** Function: "
413 << MF.getName() << "\n");
415 if (skipFunction(*MF.getFunction()))
418 // If we move NewValueJump before register allocation we'll need live variable
419 // analysis here too.
421 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
422 QRI = static_cast<const HexagonRegisterInfo *>(
423 MF.getSubtarget().getRegisterInfo());
424 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
426 if (DisableNewValueJumps) {
430 int nvjCount = DbgNVJCount;
431 int nvjGenerated = 0;
433 // Loop through all the bb's of the function
434 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
435 MBBb != MBBe; ++MBBb) {
436 MachineBasicBlock *MBB = &*MBBb;
438 DEBUG(dbgs() << "** dumping bb ** "
439 << MBB->getNumber() << "\n");
441 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
442 bool foundJump = false;
443 bool foundCompare = false;
444 bool invertPredicate = false;
445 unsigned predReg = 0; // predicate reg of the jump.
446 unsigned cmpReg1 = 0;
448 bool MO1IsKill = false;
449 bool MO2IsKill = false;
450 MachineBasicBlock::iterator jmpPos;
451 MachineBasicBlock::iterator cmpPos;
452 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
453 MachineBasicBlock *jmpTarget = nullptr;
454 bool afterRA = false;
455 bool isSecondOpReg = false;
456 bool isSecondOpNewified = false;
457 // Traverse the basic block - bottom up
458 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
460 MachineInstr &MI = *--MII;
461 if (MI.isDebugValue()) {
465 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
468 DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
470 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
471 MI.getOpcode() == Hexagon::J2_jumptpt ||
472 MI.getOpcode() == Hexagon::J2_jumpf ||
473 MI.getOpcode() == Hexagon::J2_jumpfpt ||
474 MI.getOpcode() == Hexagon::J2_jumptnewpt ||
475 MI.getOpcode() == Hexagon::J2_jumptnew ||
476 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
477 MI.getOpcode() == Hexagon::J2_jumpfnew)) {
478 // This is where you would insert your compare and
479 // instr that feeds compare
482 predReg = MI.getOperand(0).getReg();
483 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
485 // If ifconverter had not messed up with the kill flags of the
486 // operands, the following check on the kill flag would suffice.
487 // if(!jmpInstr->getOperand(0).isKill()) break;
489 // This predicate register is live out out of BB
490 // this would only work if we can actually use Live
491 // variable analysis on phy regs - but LLVM does not
492 // provide LV analysis on phys regs.
493 //if(LVs.isLiveOut(predReg, *MBB)) break;
495 // Get all the successors of this block - which will always
496 // be 2. Check if the predicate register is live-in in those
497 // successor. If yes, we can not delete the predicate -
498 // I am doing this only because LLVM does not provide LiveOut
500 bool predLive = false;
501 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
502 SIE = MBB->succ_end(); SI != SIE; ++SI) {
503 MachineBasicBlock* succMBB = *SI;
504 if (succMBB->isLiveIn(predReg)) {
511 if (!MI.getOperand(1).isMBB())
513 jmpTarget = MI.getOperand(1).getMBB();
515 if (MI.getOpcode() == Hexagon::J2_jumpf ||
516 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
517 MI.getOpcode() == Hexagon::J2_jumpfnew) {
518 invertPredicate = true;
523 // No new value jump if there is a barrier. A barrier has to be in its
524 // own packet. A barrier has zero operands. We conservatively bail out
525 // here if we see any instruction with zero operands.
526 if (foundJump && MI.getNumOperands() == 0)
529 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
530 MI.getOperand(0).getReg() == predReg) {
532 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
533 if (isNewValueJumpCandidate(MI)) {
536 (MI.getDesc().isCompare()) &&
537 "Only compare instruction can be collapsed into New Value Jump");
538 isSecondOpReg = MI.getOperand(2).isReg();
540 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
541 afterRA, jmpPos, MF))
548 // We need cmpReg1 and cmpOp2(imm or reg) while building
549 // new value jump instruction.
550 cmpReg1 = MI.getOperand(1).getReg();
551 if (MI.getOperand(1).isKill())
555 cmpOp2 = MI.getOperand(2).getReg();
556 if (MI.getOperand(2).isKill())
559 cmpOp2 = MI.getOperand(2).getImm();
564 if (foundCompare && foundJump) {
566 // If "common" checks fail, bail out on this BB.
567 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
570 bool foundFeeder = false;
571 MachineBasicBlock::iterator feederPos = MII;
572 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
573 (MI.getOperand(0).getReg() == cmpReg1 ||
575 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
577 unsigned feederReg = MI.getOperand(0).getReg();
579 // First try to see if we can get the feeder from the first operand
580 // of the compare. If we can not, and if secondOpReg is true
581 // (second operand of the compare is also register), try that one.
582 // TODO: Try to come up with some heuristic to figure out which
583 // feeder would benefit.
585 if (feederReg == cmpReg1) {
586 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
597 feederReg == (unsigned) cmpOp2)
598 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
602 // In case of CMPLT, or CMPLTU, or EQ with the second register
603 // to newify, swap the operands.
604 unsigned COp = cmpInstr->getOpcode();
605 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
606 (feederReg == (unsigned) cmpOp2)) {
607 unsigned tmp = cmpReg1;
608 bool tmpIsKill = MO1IsKill;
610 MO1IsKill = MO2IsKill;
612 MO2IsKill = tmpIsKill;
615 // Now we have swapped the operands, all we need to check is,
616 // if the second operand (after swap) is the feeder.
617 // And if it is, make a note.
618 if (feederReg == (unsigned)cmpOp2)
619 isSecondOpNewified = true;
622 // Now that we are moving feeder close the jump,
623 // make sure we are respecting the kill values of
624 // the operands of the feeder.
626 bool updatedIsKill = false;
627 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
628 MachineOperand &MO = MI.getOperand(i);
629 if (MO.isReg() && MO.isUse()) {
630 unsigned feederReg = MO.getReg();
631 for (MachineBasicBlock::iterator localII = feederPos,
632 end = jmpPos; localII != end; localII++) {
633 MachineInstr &localMI = *localII;
634 for (unsigned j = 0; j < localMI.getNumOperands(); j++) {
635 MachineOperand &localMO = localMI.getOperand(j);
636 if (localMO.isReg() && localMO.isUse() &&
637 localMO.isKill() && feederReg == localMO.getReg()) {
638 // We found that there is kill of a use register
639 // Set up a kill flag on the register
640 localMO.setIsKill(false);
642 updatedIsKill = true;
646 if (updatedIsKill) break;
649 if (updatedIsKill) break;
652 MBB->splice(jmpPos, MI.getParent(), MI);
653 MBB->splice(jmpPos, MI.getParent(), cmpInstr);
654 DebugLoc dl = MI.getDebugLoc();
657 assert((isNewValueJumpCandidate(*cmpInstr)) &&
658 "This compare is not a New Value Jump candidate.");
659 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
663 opc = QII->getInvertedPredicatedOpcode(opc);
666 NewMI = BuildMI(*MBB, jmpPos, dl,
668 .addReg(cmpReg1, getKillRegState(MO1IsKill))
669 .addReg(cmpOp2, getKillRegState(MO2IsKill))
673 NewMI = BuildMI(*MBB, jmpPos, dl,
675 .addReg(cmpReg1, getKillRegState(MO1IsKill))
679 assert(NewMI && "New Value Jump Instruction Not created!");
681 if (cmpInstr->getOperand(0).isReg() &&
682 cmpInstr->getOperand(0).isKill())
683 cmpInstr->getOperand(0).setIsKill(false);
684 if (cmpInstr->getOperand(1).isReg() &&
685 cmpInstr->getOperand(1).isKill())
686 cmpInstr->getOperand(1).setIsKill(false);
687 cmpInstr->eraseFromParent();
688 jmpInstr->eraseFromParent();
701 FunctionPass *llvm::createHexagonNewValueJump() {
702 return new HexagonNewValueJump();