1 //===--- HexagonOptAddrMode.cpp -------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This implements a Hexagon-specific pass to optimize addressing mode for
10 // load/store instructions.
11 //===----------------------------------------------------------------------===//
13 #include "HexagonInstrInfo.h"
14 #include "HexagonSubtarget.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
17 #include "RDFLiveness.h"
18 #include "llvm/ADT/DenseSet.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineDominanceFrontier.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Pass.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
37 #define DEBUG_TYPE "opt-addr-mode"
39 static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
40 cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
47 FunctionPass *createHexagonOptAddrMode();
48 void initializeHexagonOptAddrModePass(PassRegistry&);
49 } // end namespace llvm
53 class HexagonOptAddrMode : public MachineFunctionPass {
58 : MachineFunctionPass(ID), HII(nullptr), MDT(nullptr), DFG(nullptr),
61 StringRef getPassName() const override {
62 return "Optimize addressing mode of load/store";
65 void getAnalysisUsage(AnalysisUsage &AU) const override {
66 MachineFunctionPass::getAnalysisUsage(AU);
67 AU.addRequired<MachineDominatorTree>();
68 AU.addRequired<MachineDominanceFrontier>();
72 bool runOnMachineFunction(MachineFunction &MF) override;
75 typedef DenseSet<MachineInstr *> MISetType;
76 typedef DenseMap<MachineInstr *, bool> InstrEvalMap;
77 const HexagonInstrInfo *HII;
78 MachineDominatorTree *MDT;
80 DataFlowGraph::DefStackMap DefM;
84 bool processBlock(NodeAddr<BlockNode *> BA);
85 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
86 NodeAddr<UseNode *> UseN, unsigned UseMOnum);
87 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
88 InstrEvalMap &InstrEvalResult, short &SizeInc);
89 bool hasRepForm(MachineInstr &MI, unsigned TfrDefR);
90 bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr &MI,
91 const NodeList &UNodeList);
92 void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
93 bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
94 short getBaseWithLongOffset(const MachineInstr &MI) const;
95 bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
97 bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
98 bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI,
99 const MachineOperand &ImmOp, unsigned ImmOpNum);
102 } // end anonymous namespace
104 char HexagonOptAddrMode::ID = 0;
106 INITIALIZE_PASS_BEGIN(HexagonOptAddrMode, "amode-opt",
107 "Optimize addressing mode", false, false)
108 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
109 INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
110 INITIALIZE_PASS_END(HexagonOptAddrMode, "amode-opt", "Optimize addressing mode",
113 bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
114 const MCInstrDesc &MID = MI.getDesc();
116 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
119 if (MID.mayStore()) {
120 MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
121 if (StOp.isReg() && StOp.getReg() == TfrDefR)
125 if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
126 // Tranform to Absolute plus register offset.
127 return (HII->getBaseWithLongOffset(MI) >= 0);
128 else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
129 // Tranform to absolute addressing mode.
130 return (HII->getAbsoluteForm(MI) >= 0);
135 // Check if addasl instruction can be removed. This is possible only
136 // if it's feeding to only load/store instructions with base + register
137 // offset as these instruction can be tranformed to use 'absolute plus
138 // shifted register offset'.
141 // Rx = addasl(Rs, Rt, #2)
142 // Rd = memw(Rx + #28)
143 // Above three instructions can be replaced with Rd = memw(Rt<<#2 + ##foo+28)
145 bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
147 const NodeList &UNodeList) {
148 // check offset size in addasl. if 'offset > 3' return false
149 const MachineOperand &OffsetOp = MI.getOperand(3);
150 if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
153 unsigned OffsetReg = MI.getOperand(2).getReg();
154 RegisterRef OffsetRR;
155 NodeId OffsetRegRD = 0;
156 for (NodeAddr<UseNode *> UA : AddAslSN.Addr->members_if(DFG->IsUse, *DFG)) {
157 RegisterRef RR = UA.Addr->getRegRef(*DFG);
158 if (OffsetReg == RR.Reg) {
160 OffsetRegRD = UA.Addr->getReachingDef();
164 for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
165 NodeAddr<UseNode *> UA = *I;
166 NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
167 if (UA.Addr->getFlags() & NodeAttrs::PhiRef)
169 NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(OffsetRR, IA);
170 if ((DFG->IsDef(AA) && AA.Id != OffsetRegRD) ||
171 AA.Addr->getReachingDef() != OffsetRegRD)
174 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
175 NodeAddr<DefNode *> OffsetRegDN = DFG->addr<DefNode *>(OffsetRegRD);
176 // Reaching Def to an offset register can't be a phi.
177 if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
178 MI.getParent() != UseMI.getParent())
181 const MCInstrDesc &UseMID = UseMI.getDesc();
182 if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
183 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
184 getBaseWithLongOffset(UseMI) < 0)
187 // Addasl output can't be a store value.
188 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
189 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
192 for (auto &Mo : UseMI.operands())
199 bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA,
200 NodeList &UNodeList) {
201 for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
202 NodeAddr<UseNode *> UN = *I;
203 RegisterRef UR = UN.Addr->getRegRef(*DFG);
204 NodeSet Visited, Defs;
205 const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
208 dbgs() << "*** Unable to collect all reaching defs for use ***\n"
209 << PrintNode<UseNode*>(UN, *DFG) << '\n'
210 << "The program's complexity may exceed the limits.\n";
214 const auto &ReachingDefs = P.first;
215 if (ReachingDefs.size() > 1) {
217 dbgs() << "*** Multiple Reaching Defs found!!! ***\n";
218 for (auto DI : ReachingDefs) {
219 NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI);
220 NodeAddr<StmtNode *> TempIA = DA.Addr->getOwner(*DFG);
221 dbgs() << "\t\t[Reaching Def]: "
222 << Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
231 void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
232 NodeList &UNodeList) {
233 for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) {
234 DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG)
236 RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG));
238 auto UseSet = LV->getAllReachedUses(DR, DA);
240 for (auto UI : UseSet) {
241 NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI);
243 NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG);
244 dbgs() << "\t\t\t[Reached Use]: "
245 << Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
248 if (UA.Addr->getFlags() & NodeAttrs::PhiRef) {
249 NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG);
251 const Liveness::RefMap &phiUse = LV->getRealUses(id);
252 DEBUG(dbgs() << "\t\t\t\tphi real Uses"
253 << Print<Liveness::RefMap>(phiUse, *DFG) << "\n");
254 if (!phiUse.empty()) {
255 for (auto I : phiUse) {
256 if (!DFG->getPRI().alias(RegisterRef(I.first), DR))
258 auto phiUseSet = I.second;
259 for (auto phiUI : phiUseSet) {
260 NodeAddr<UseNode *> phiUA = DFG->addr<UseNode *>(phiUI.first);
261 UNodeList.push_back(phiUA);
266 UNodeList.push_back(UA);
271 bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR,
272 const NodeList &UNodeList,
273 InstrEvalMap &InstrEvalResult,
275 bool KeepTfr = false;
276 bool HasRepInstr = false;
277 InstrEvalResult.clear();
279 for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
280 bool CanBeReplaced = false;
281 NodeAddr<UseNode *> UN = *I;
282 NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
283 MachineInstr &MI = *SN.Addr->getCode();
284 const MCInstrDesc &MID = MI.getDesc();
285 if ((MID.mayLoad() || MID.mayStore())) {
286 if (!hasRepForm(MI, tfrDefR)) {
291 CanBeReplaced = true;
292 } else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) {
293 NodeList AddaslUseList;
295 DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n");
296 getAllRealUses(SN, AddaslUseList);
297 // Process phi nodes.
298 if (allValidCandidates(SN, AddaslUseList) &&
299 canRemoveAddasl(SN, MI, AddaslUseList)) {
300 SizeInc += AddaslUseList.size();
301 SizeInc -= 1; // Reduce size by 1 as addasl itself can be removed.
302 CanBeReplaced = true;
306 // Currently, only load/store and addasl are handled.
307 // Some other instructions to consider -
309 // M4_mpyrr_addr -> M4_mpyrr_addi
312 InstrEvalResult[&MI] = CanBeReplaced;
313 HasRepInstr |= CanBeReplaced;
316 // Reduce total size by 2 if original tfr can be deleted.
323 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
325 bool Changed = false;
326 MachineBasicBlock *BB = OldMI->getParent();
327 auto UsePos = MachineBasicBlock::iterator(OldMI);
328 MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
331 unsigned OpEnd = OldMI->getNumOperands();
332 MachineInstrBuilder MIB;
335 if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
336 short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
337 assert(NewOpCode >= 0 && "Invalid New opcode\n");
338 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
339 MIB.add(OldMI->getOperand(0));
340 MIB.add(OldMI->getOperand(2));
341 MIB.add(OldMI->getOperand(3));
345 } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
346 short NewOpCode = HII->getAbsoluteForm(*OldMI);
347 assert(NewOpCode >= 0 && "Invalid New opcode\n");
348 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
349 .add(OldMI->getOperand(0));
350 const GlobalValue *GV = ImmOp.getGlobal();
351 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
353 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
359 DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
360 DEBUG(dbgs() << "[TO]: " << MIB << "\n");
361 } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
362 short NewOpCode = HII->xformRegToImmOffset(*OldMI);
363 assert(NewOpCode >= 0 && "Invalid New opcode\n");
364 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
365 MIB.add(OldMI->getOperand(0));
366 MIB.add(OldMI->getOperand(1));
370 DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
371 DEBUG(dbgs() << "[TO]: " << MIB << "\n");
375 for (unsigned i = OpStart; i < OpEnd; ++i)
376 MIB.add(OldMI->getOperand(i));
381 bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
383 bool Changed = false;
385 unsigned OpEnd = OldMI->getNumOperands();
386 MachineBasicBlock *BB = OldMI->getParent();
387 auto UsePos = MachineBasicBlock::iterator(OldMI);
388 MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
390 MachineInstrBuilder MIB;
392 if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
393 short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
394 assert(NewOpCode >= 0 && "Invalid New opcode\n");
395 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
396 MIB.add(OldMI->getOperand(1));
397 MIB.add(OldMI->getOperand(2));
399 MIB.add(OldMI->getOperand(3));
401 } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
402 short NewOpCode = HII->getAbsoluteForm(*OldMI);
403 assert(NewOpCode >= 0 && "Invalid New opcode\n");
404 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
405 const GlobalValue *GV = ImmOp.getGlobal();
406 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm();
407 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
408 MIB.add(OldMI->getOperand(2));
412 DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
413 DEBUG(dbgs() << "[TO]: " << MIB << "\n");
414 } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
415 short NewOpCode = HII->xformRegToImmOffset(*OldMI);
416 assert(NewOpCode >= 0 && "Invalid New opcode\n");
417 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
418 MIB.add(OldMI->getOperand(0));
420 MIB.add(OldMI->getOperand(1));
423 DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
424 DEBUG(dbgs() << "[TO]: " << MIB << "\n");
427 for (unsigned i = OpStart; i < OpEnd; ++i)
428 MIB.add(OldMI->getOperand(i));
433 short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr &MI) const {
434 if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
435 short TempOpCode = HII->getBaseWithRegOffset(MI);
436 return HII->getBaseWithLongOffset(TempOpCode);
438 return HII->getBaseWithLongOffset(MI);
441 bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
442 MachineInstr *AddAslMI,
443 const MachineOperand &ImmOp,
445 NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG);
447 DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n");
450 getAllRealUses(SA, UNodeList);
452 for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
453 NodeAddr<UseNode *> UseUN = *I;
454 assert(!(UseUN.Addr->getFlags() & NodeAttrs::PhiRef) &&
455 "Can't transform this 'AddAsl' instruction!");
457 NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG);
458 DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
460 MachineInstr *UseMI = UseIA.Addr->getCode();
461 DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
462 << ">]: " << *UseMI << "\n");
463 const MCInstrDesc &UseMID = UseMI->getDesc();
464 assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
466 auto UsePos = MachineBasicBlock::iterator(UseMI);
467 MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
468 short NewOpCode = getBaseWithLongOffset(*UseMI);
469 assert(NewOpCode >= 0 && "Invalid New opcode\n");
472 unsigned OpEnd = UseMI->getNumOperands();
474 MachineBasicBlock *BB = UseMI->getParent();
475 MachineInstrBuilder MIB =
476 BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
477 // change mem(Rs + # ) -> mem(Rt << # + ##)
478 if (UseMID.mayLoad()) {
479 MIB.add(UseMI->getOperand(0));
480 MIB.add(AddAslMI->getOperand(2));
481 MIB.add(AddAslMI->getOperand(3));
482 const GlobalValue *GV = ImmOp.getGlobal();
483 MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm()+ImmOp.getOffset(),
484 ImmOp.getTargetFlags());
486 } else if (UseMID.mayStore()) {
487 MIB.add(AddAslMI->getOperand(2));
488 MIB.add(AddAslMI->getOperand(3));
489 const GlobalValue *GV = ImmOp.getGlobal();
490 MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm()+ImmOp.getOffset(),
491 ImmOp.getTargetFlags());
492 MIB.add(UseMI->getOperand(2));
495 llvm_unreachable("Unhandled instruction");
497 for (unsigned i = OpStart; i < OpEnd; ++i)
498 MIB.add(UseMI->getOperand(i));
500 Deleted.insert(UseMI);
506 bool HexagonOptAddrMode::xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
507 NodeAddr<UseNode *> UseN,
509 const MachineOperand ImmOp = TfrMI->getOperand(1);
510 const MCInstrDesc &MID = UseMI->getDesc();
511 unsigned Changed = false;
513 Changed = changeLoad(UseMI, ImmOp, UseMOnum);
514 else if (MID.mayStore())
515 Changed = changeStore(UseMI, ImmOp, UseMOnum);
516 else if (UseMI->getOpcode() == Hexagon::S2_addasl_rrri)
517 Changed = changeAddAsl(UseN, UseMI, ImmOp, UseMOnum);
520 Deleted.insert(UseMI);
525 bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
526 bool Changed = false;
528 for (auto IA : BA.Addr->members(*DFG)) {
529 if (!DFG->IsCode<NodeAttrs::Stmt>(IA))
532 NodeAddr<StmtNode *> SA = IA;
533 MachineInstr *MI = SA.Addr->getCode();
534 if (MI->getOpcode() != Hexagon::A2_tfrsi ||
535 !MI->getOperand(1).isGlobal())
538 DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: "
539 << *MI << "\n\t[InstrNode]: "
540 << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n');
543 getAllRealUses(SA, UNodeList);
545 if (!allValidCandidates(SA, UNodeList))
549 unsigned DefR = MI->getOperand(0).getReg();
550 InstrEvalMap InstrEvalResult;
552 // Analyze all uses and calculate increase in size. Perform the optimization
553 // only if there is no increase in size.
554 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
556 if (SizeInc > CodeGrowthLimit)
559 bool KeepTfr = false;
561 DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n");
562 DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n");
563 for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
564 NodeAddr<UseNode *> UseN = *I;
565 assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
566 "Found a PhiRef node as a real reached use!!");
568 NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
569 MachineInstr *UseMI = OwnerN.Addr->getCode();
570 DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
571 << ">]: " << *UseMI << "\n");
574 unsigned NumOperands = UseMI->getNumOperands();
575 for (unsigned j = 0; j < NumOperands - 1; ++j) {
576 const MachineOperand &op = UseMI->getOperand(j);
577 if (op.isReg() && op.isUse() && DefR == op.getReg())
580 assert(UseMOnum >= 0 && "Invalid reached use!");
582 if (InstrEvalResult[UseMI])
583 // Change UseMI if replacement is possible.
584 Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum);
594 bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
595 if (skipFunction(*MF.getFunction()))
598 bool Changed = false;
599 auto &HST = MF.getSubtarget<HexagonSubtarget>();
600 auto &MRI = MF.getRegInfo();
601 HII = HST.getInstrInfo();
602 const auto &MDF = getAnalysis<MachineDominanceFrontier>();
603 MDT = &getAnalysis<MachineDominatorTree>();
604 const auto &TRI = *MF.getSubtarget().getRegisterInfo();
605 const TargetOperandInfo TOI(*HII);
607 DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, TOI);
608 // Need to keep dead phis because we can propagate uses of registers into
609 // nodes dominated by those would-be phis.
610 G.build(BuildOptions::KeepDeadPhis);
613 Liveness L(MRI, *DFG);
618 NodeAddr<FuncNode *> FA = DFG->getFunc();
619 DEBUG(dbgs() << "==== [RefMap#]=====:\n "
620 << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n");
622 for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
623 Changed |= processBlock(BA);
625 for (auto MI : Deleted)
626 MI->eraseFromParent();
638 //===----------------------------------------------------------------------===//
639 // Public Constructor Functions
640 //===----------------------------------------------------------------------===//
642 FunctionPass *llvm::createHexagonOptAddrMode() {
643 return new HexagonOptAddrMode();