1 //==- HexagonPatterns.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 // (3) Extend/truncate
20 // (9) Arithmetic/bitwise
30 // Guidelines (in no particular order):
31 // 1. Avoid relying on pattern ordering to give preference to one pattern
32 // over another, prefer using AddedComplexity instead. The reason for
33 // this is to avoid unintended conseqeuences (caused by altering the
34 // order) when making changes. The current order of patterns in this
35 // file obviously does play some role, but none of the ordering was
36 // deliberately chosen (other than to create a logical structure of
37 // this file). When making changes, adding AddedComplexity to existing
38 // patterns may be needed.
39 // 2. Maintain the logical structure of the file, try to put new patterns
40 // in designated sections.
41 // 3. Do not use A2_combinew instruction directly, use Combinew fragment
42 // instead. It uses REG_SEQUENCE, which is more amenable to optimizations.
43 // 4. Most selection macros are based on PatFrags. For DAGs that involve
44 // SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags
45 // whenever possible (see the Definitions section). When adding new
46 // macro, try to make is general to enable reuse across sections.
47 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
48 // that the nested operation has only one use. Having it separated in case
49 // of multiple uses avoids duplication of (processor) work.
50 // 6. The v4 vector instructions (64-bit) are treated as core instructions,
51 // for example, A2_vaddh is in the "arithmetic" section with A2_add.
52 // 7. When adding a pattern for an instruction with a constant-extendable
53 // operand, allow all possible kinds of inputs for the immediate value
54 // (see AnyImm/anyimm and their variants in the Definitions section).
57 // --(0) Definitions -----------------------------------------------------
60 // This complex pattern exists only to create a machine instruction operand
61 // of type "frame index". There doesn't seem to be a way to do that directly
63 def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
65 // These complex patterns are not strictly necessary, since global address
66 // folding will happen during DAG combining. For distinguishing between GA
67 // and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
68 def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
69 def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
70 def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>;
71 def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>;
73 // Global address or a constant being a multiple of 2^n.
74 def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>;
75 def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>;
76 def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>;
77 def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>;
81 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
82 def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
83 def V8I1: PatLeaf<(v8i1 PredRegs:$R)>;
84 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
85 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
87 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
88 def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
89 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
91 def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>;
92 def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>;
93 def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>;
95 def HVI8: PatLeaf<(VecI8 HvxVR:$R)>;
96 def HVI16: PatLeaf<(VecI16 HvxVR:$R)>;
97 def HVI32: PatLeaf<(VecI32 HvxVR:$R)>;
99 def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>;
100 def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>;
101 def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>;
103 // Pattern fragments to extract the low and high subregisters from a
105 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
106 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
108 def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
109 return isOrEquivalentToAdd(N);
112 def IsVecOff : PatLeaf<(i32 imm), [{
113 int32_t V = N->getSExtValue();
114 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
115 assert(isPowerOf2_32(VecSize));
116 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
118 int32_t L = Log2_32(VecSize);
119 return isInt<4>(V >> L);
122 def IsPow2_32: PatLeaf<(i32 imm), [{
123 uint32_t V = N->getZExtValue();
124 return isPowerOf2_32(V);
127 def IsPow2_64: PatLeaf<(i64 imm), [{
128 uint64_t V = N->getZExtValue();
129 return isPowerOf2_64(V);
132 def IsNPow2_32: PatLeaf<(i32 imm), [{
133 uint32_t NV = ~N->getZExtValue();
134 return isPowerOf2_32(NV);
137 def IsPow2_64L: PatLeaf<(i64 imm), [{
138 uint64_t V = N->getZExtValue();
139 return isPowerOf2_64(V) && Log2_64(V) < 32;
142 def IsPow2_64H: PatLeaf<(i64 imm), [{
143 uint64_t V = N->getZExtValue();
144 return isPowerOf2_64(V) && Log2_64(V) >= 32;
147 def IsNPow2_64L: PatLeaf<(i64 imm), [{
148 uint64_t NV = ~N->getZExtValue();
149 return isPowerOf2_64(NV) && Log2_64(NV) < 32;
152 def IsNPow2_64H: PatLeaf<(i64 imm), [{
153 uint64_t NV = ~N->getZExtValue();
154 return isPowerOf2_64(NV) && Log2_64(NV) >= 32;
157 class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm),
158 "uint64_t V = N->getZExtValue();" #
159 "return isUInt<" # Width # ">(V) && V > " # Arg # ";"
162 def SDEC1: SDNodeXForm<imm, [{
163 int32_t V = N->getSExtValue();
164 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
167 def UDEC1: SDNodeXForm<imm, [{
168 uint32_t V = N->getZExtValue();
170 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
173 def UDEC32: SDNodeXForm<imm, [{
174 uint32_t V = N->getZExtValue();
176 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32);
179 def Log2_32: SDNodeXForm<imm, [{
180 uint32_t V = N->getZExtValue();
181 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
184 def Log2_64: SDNodeXForm<imm, [{
185 uint64_t V = N->getZExtValue();
186 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
189 def LogN2_32: SDNodeXForm<imm, [{
190 uint32_t NV = ~N->getZExtValue();
191 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
194 def LogN2_64: SDNodeXForm<imm, [{
195 uint64_t NV = ~N->getZExtValue();
196 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
199 def NegImm8: SDNodeXForm<imm, [{
200 int8_t NV = -N->getSExtValue();
201 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
204 def NegImm16: SDNodeXForm<imm, [{
205 int16_t NV = -N->getSExtValue();
206 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
209 def NegImm32: SDNodeXForm<imm, [{
210 int32_t NV = -N->getSExtValue();
211 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
215 // Helpers for type promotions/contractions.
216 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
217 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_tfrrp (i32 $Rs)))>;
218 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
219 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
221 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
222 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
224 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
225 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
226 def anyimm: PatLeaf<(i32 AnyImm:$Imm)>;
227 def anyint: PatLeaf<(i32 AnyInt:$Imm)>;
229 // Global address or an aligned constant.
230 def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>;
231 def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>;
232 def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>;
233 def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>;
235 def f32ImmPred : PatLeaf<(f32 fpimm:$F)>;
236 def f64ImmPred : PatLeaf<(f64 fpimm:$F)>;
238 // This complex pattern is really only to detect various forms of
239 // sign-extension i32->i64. The selected value will be of type i64
240 // whose low word is the value being extended. The high word is
242 def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>;
244 def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
245 def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
246 def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
248 def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
249 (PS_fi (i32 AddrFI:$Rs), imm:$off)>;
252 def alignedload: PatFrag<(ops node:$a), (load $a), [{
253 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
256 def unalignedload: PatFrag<(ops node:$a), (load $a), [{
257 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
260 def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
261 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
264 def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
265 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
269 // Converters from unary/binary SDNode to PatFrag.
270 class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>;
271 class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>;
273 class Not2<PatFrag P>
274 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>;
277 : PatFrag<Op.Operands, Op.Fragment, [{ return hasOneUse(N); }],
278 Op.OperandTransform>;
280 // Main selection macros.
282 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
283 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
285 class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
286 PatFrag RegPred, PatFrag ImmPred>
287 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
288 (MI RegPred:$Rs, imm:$I)>;
290 class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
291 PatFrag RsPred, PatFrag RtPred = RsPred>
292 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
293 (MI RsPred:$Rs, RtPred:$Rt)>;
295 class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
296 PatFrag RegPred, PatFrag ImmPred>
297 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
298 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
300 class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
301 PatFrag RsPred, PatFrag RtPred>
302 : Pat<(AccOp RsPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
303 (MI RsPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
305 multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
306 InstHexagon InstA, InstHexagon InstB> {
307 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
308 (InstA Val:$A, Val:$B)>;
309 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
310 (InstB Val:$A, Val:$B)>;
314 // Frags for commonly used SDNodes.
315 def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
316 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
317 def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>;
320 // --(1) Immediate -------------------------------------------------------
323 def SDTHexagonCONST32
324 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>;
326 def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
327 def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
328 def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
329 def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
331 def TruncI64ToI32: SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
335 def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
336 def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
338 def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>;
339 def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>;
340 def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>;
341 def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>;
342 def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>;
343 def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>;
344 def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>;
345 // The HVX load patterns also match CP directly. Make sure that if
346 // the selection of this opcode changes, it's updated in all places.
348 def: Pat<(i1 0), (PS_false)>;
349 def: Pat<(i1 1), (PS_true)>;
350 def: Pat<(i64 imm:$v), (CONST64 imm:$v)>;
352 def ftoi : SDNodeXForm<fpimm, [{
353 APInt I = N->getValueAPF().bitcastToAPInt();
354 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N),
355 MVT::getIntegerVT(I.getBitWidth()));
358 def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>;
359 def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>;
361 def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>;
363 // --(2) Type cast -------------------------------------------------------
366 let Predicates = [HasV5T] in {
367 def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>;
368 def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>;
370 def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>;
371 def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>;
372 def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>;
373 def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>;
375 def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>;
376 def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>;
377 def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>;
378 def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>;
380 def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>;
381 def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>;
382 def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>;
383 def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>;
385 def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>;
386 def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>;
387 def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>;
388 def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>;
391 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
392 let Predicates = [HasV5T] in {
393 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
394 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
395 def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
396 def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
399 multiclass Cast_pat<ValueType Ta, ValueType Tb, RegisterClass RC> {
400 def: Pat<(Tb (bitconvert (Ta RC:$Rs))), (Tb RC:$Rs)>;
401 def: Pat<(Ta (bitconvert (Tb RC:$Rs))), (Ta RC:$Rs)>;
404 // Bit convert vector types to integers.
405 defm: Cast_pat<v4i8, i32, IntRegs>;
406 defm: Cast_pat<v2i16, i32, IntRegs>;
407 defm: Cast_pat<v8i8, i64, DoubleRegs>;
408 defm: Cast_pat<v4i16, i64, DoubleRegs>;
409 defm: Cast_pat<v2i32, i64, DoubleRegs>;
412 // --(3) Extend/truncate -------------------------------------------------
415 def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>;
416 def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>;
417 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
418 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
419 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
421 def: Pat<(i64 (sext I1:$Pu)),
422 (Combinew (C2_muxii PredRegs:$Pu, -1, 0),
423 (C2_muxii PredRegs:$Pu, -1, 0))>;
425 def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>;
426 def: Pat<(i32 (zext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>;
427 def: Pat<(i64 (zext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>;
429 def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>;
430 def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>;
431 def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>;
433 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
434 def: Pat<(i1 (trunc I64:$Rs)), (C2_tfrrp (LoReg $Rs))>;
436 let AddedComplexity = 20 in {
437 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>;
438 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>;
441 def: Pat<(i32 (anyext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>;
442 def: Pat<(i64 (anyext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>;
444 def: Pat<(v4i16 (zext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
445 def: Pat<(v2i32 (zext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
446 def: Pat<(v4i16 (anyext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
447 def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
448 def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>;
449 def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
451 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
452 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
454 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
455 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
457 // Truncate: from vector B copy all 'E'ven 'B'yte elements:
458 // A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6];
459 def: Pat<(v4i8 (trunc V4I16:$Rs)),
460 (S2_vtrunehb V4I16:$Rs)>;
462 // Truncate: from vector B copy all 'O'dd 'B'yte elements:
463 // A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7];
466 // Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
467 // A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2];
470 def: Pat<(v2i16 (trunc V2I32:$Rs)),
471 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
474 // --(4) Logical ---------------------------------------------------------
477 def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>;
478 def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>;
480 def: OpR_RR_pat<C2_and, And, i1, I1>;
481 def: OpR_RR_pat<C2_or, Or, i1, I1>;
482 def: OpR_RR_pat<C2_xor, Xor, i1, I1>;
483 def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>;
484 def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>;
486 // op(Ps, op(Pt, Pu))
487 def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1>;
488 def: AccRRR_pat<C4_and_or, And, Su<Or>, I1, I1>;
489 def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1>;
490 def: AccRRR_pat<C4_or_or, Or, Su<Or>, I1, I1>;
492 // op(Ps, op(Pt, ~Pu))
493 def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1>;
494 def: AccRRR_pat<C4_and_orn, And, Su<Not2<Or>>, I1, I1>;
495 def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1>;
496 def: AccRRR_pat<C4_or_orn, Or, Su<Not2<Or>>, I1, I1>;
499 // --(5) Compare ---------------------------------------------------------
502 // Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)".
503 // These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt).
505 def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>;
506 def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>;
507 def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>;
509 def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
510 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>;
511 def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)),
512 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>;
514 def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)),
515 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>;
516 def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)),
517 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>;
519 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
520 // that reverse the order of the operands.
521 class RevCmp<PatFrag F>
522 : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment, F.PredicateCode,
525 def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>;
526 def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>;
527 def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>;
528 def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>;
529 def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>;
530 def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>;
531 def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>;
532 def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>;
533 def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>;
534 def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>;
535 def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>;
536 def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>;
537 def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>;
538 def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>;
539 def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>;
540 def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>;
541 def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>;
542 def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>;
543 def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>;
544 def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>;
545 def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>;
546 def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>;
547 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>;
548 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>;
549 def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>;
550 def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>;
551 def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>;
552 def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>;
553 def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>;
554 def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>;
555 def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>;
556 def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>;
557 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>;
558 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>;
559 def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>;
560 def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
561 def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>;
562 def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>;
563 def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>;
564 def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>;
566 let Predicates = [HasV5T] in {
567 def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>;
568 def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
569 def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>;
570 def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>;
571 def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>;
572 def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>;
573 def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>;
574 def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>;
575 def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>;
576 def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>;
577 def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>;
579 def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>;
580 def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>;
581 def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>;
582 def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>;
583 def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>;
584 def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>;
585 def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>;
586 def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>;
587 def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>;
588 def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>;
589 def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>;
592 // Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds.
594 def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)),
595 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>;
596 def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)),
597 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>;
598 def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)),
599 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>;
601 def: Pat<(i1 (setne I32:$Rs, I32:$Rt)),
602 (C2_not (C2_cmpeq I32:$Rs, I32:$Rt))>;
603 def: Pat<(i1 (setle I32:$Rs, I32:$Rt)),
604 (C2_not (C2_cmpgt I32:$Rs, I32:$Rt))>;
605 def: Pat<(i1 (setule I32:$Rs, I32:$Rt)),
606 (C2_not (C2_cmpgtu I32:$Rs, I32:$Rt))>;
607 def: Pat<(i1 (setge I32:$Rs, I32:$Rt)),
608 (C2_not (C2_cmpgt I32:$Rt, I32:$Rs))>;
609 def: Pat<(i1 (setuge I32:$Rs, I32:$Rt)),
610 (C2_not (C2_cmpgtu I32:$Rt, I32:$Rs))>;
612 def: Pat<(i1 (setle I64:$Rs, I64:$Rt)),
613 (C2_not (C2_cmpgtp I64:$Rs, I64:$Rt))>;
614 def: Pat<(i1 (setne I64:$Rs, I64:$Rt)),
615 (C2_not (C2_cmpeqp I64:$Rs, I64:$Rt))>;
616 def: Pat<(i1 (setge I64:$Rs, I64:$Rt)),
617 (C2_not (C2_cmpgtp I64:$Rt, I64:$Rs))>;
618 def: Pat<(i1 (setuge I64:$Rs, I64:$Rt)),
619 (C2_not (C2_cmpgtup I64:$Rt, I64:$Rs))>;
620 def: Pat<(i1 (setule I64:$Rs, I64:$Rt)),
621 (C2_not (C2_cmpgtup I64:$Rs, I64:$Rt))>;
623 let AddedComplexity = 100 in {
624 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)),
625 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
626 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)),
627 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
628 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
629 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
630 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
631 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
634 // PatFrag for AsserZext which takes the original type as a parameter.
635 def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>;
636 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
637 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
639 multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
640 PatLeaf ImmPred, int Mask> {
641 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
642 (MI I32:$Rs, imm:$I)>;
643 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
644 (MI I32:$Rs, imm:$I)>;
647 multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
648 PatLeaf ImmPred, int Mask> {
649 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
650 (C2_not (MI I32:$Rs, imm:$I))>;
651 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
652 (C2_not (MI I32:$Rs, imm:$I))>;
655 multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
656 PatLeaf ImmPred, int Mask> {
657 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
658 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
659 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
660 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
663 let AddedComplexity = 200 in {
664 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
665 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
666 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
667 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
668 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
669 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
670 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
671 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
674 def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))),
675 (A4_rcmpeq I32:$Rs, I32:$Rt)>;
676 def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))),
677 (A4_rcmpneq I32:$Rs, I32:$Rt)>;
678 def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
679 (A4_rcmpeqi I32:$Rs, imm:$s8)>;
680 def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
681 (A4_rcmpneqi I32:$Rs, imm:$s8)>;
683 def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
684 (C2_xor I1:$Ps, I1:$Pt)>;
686 def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
687 (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;
688 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
689 (A4_vcmpbgt (ToZext64 $Rs), (ToZext64 $Rt))>;
690 def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)),
691 (A2_vcmpbgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
693 def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)),
694 (A2_vcmpheq (ToZext64 $Rs), (ToZext64 $Rt))>;
695 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
696 (A2_vcmphgt (ToZext64 $Rs), (ToZext64 $Rt))>;
697 def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)),
698 (A2_vcmphgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
700 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
701 (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
703 // Floating-point comparisons with checks for ordered/unordered status.
705 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
706 : OutPatFrag<(ops node:$Rs, node:$Rt),
707 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
709 class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType,
710 PatFrag RsPred, PatFrag RtPred = RsPred>
711 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
712 (Output RsPred:$Rs, RtPred:$Rt)>;
714 class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>;
715 class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>;
717 class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>;
718 class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>;
720 let Predicates = [HasV5T] in {
721 def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>;
722 def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>;
723 def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>;
724 def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>;
725 def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>;
726 def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>;
728 def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>;
729 def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>;
730 def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>;
731 def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>;
732 def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>;
733 def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>;
736 class Outn<InstHexagon MI>
737 : OutPatFrag<(ops node:$Rs, node:$Rt),
738 (C2_not (MI $Rs, $Rt))>;
740 let Predicates = [HasV5T] in {
741 def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>;
742 def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>;
744 def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>;
745 def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>;
747 def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>;
748 def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>;
752 // --(6) Select ----------------------------------------------------------
755 def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
756 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>;
757 def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs),
758 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
759 def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8),
760 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
761 def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8),
762 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
764 def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt),
765 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>;
766 def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8),
767 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
768 def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs),
769 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
770 def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8),
771 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
773 // Map from a 64-bit select to an emulated 64-bit mux.
774 // Hexagon does not support 64-bit MUXes; so emulate with combines.
775 def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt),
776 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
777 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
779 let Predicates = [HasV5T] in {
780 def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I),
781 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
782 def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt),
783 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
784 def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt),
785 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>;
786 def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt),
787 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
788 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
790 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
791 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
792 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
793 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
795 def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs),
796 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
797 def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I),
798 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
801 def: Pat<(select I1:$Pu, V4I8:$Rs, V4I8:$Rt),
802 (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
803 def: Pat<(select I1:$Pu, V2I16:$Rs, V2I16:$Rt),
804 (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
805 def: Pat<(select I1:$Pu, V2I32:$Rs, V2I32:$Rt),
806 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
807 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
809 def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt),
810 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
811 def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt),
812 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>;
813 def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt),
814 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>;
817 class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
818 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
819 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
821 let Predicates = [HasV60T,UseHVX] in {
822 def: HvxSel_pat<PS_vselect, HVI8>;
823 def: HvxSel_pat<PS_vselect, HVI16>;
824 def: HvxSel_pat<PS_vselect, HVI32>;
825 def: HvxSel_pat<PS_wselect, HWI8>;
826 def: HvxSel_pat<PS_wselect, HWI16>;
827 def: HvxSel_pat<PS_wselect, HWI32>;
830 // From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw).
831 def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw),
832 (C2_or (C2_and I1:$Pu, I1:$Pv),
833 (C2_andn I1:$Pw, I1:$Pu))>;
836 def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
837 return isPositiveHalfWord(N);
840 multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA,
842 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
843 IsPosHalf:$Rs, IsPosHalf:$Rt), i16),
844 (InstA IntRegs:$Rs, IntRegs:$Rt)>;
845 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
846 IsPosHalf:$Rt, IsPosHalf:$Rs), i16),
847 (InstB IntRegs:$Rs, IntRegs:$Rt)>;
850 let AddedComplexity = 200 in {
851 defm: SelMinMax16_pats<setge, A2_max, A2_min>;
852 defm: SelMinMax16_pats<setgt, A2_max, A2_min>;
853 defm: SelMinMax16_pats<setle, A2_min, A2_max>;
854 defm: SelMinMax16_pats<setlt, A2_min, A2_max>;
855 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>;
856 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>;
857 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>;
858 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
861 let AddedComplexity = 200 in {
862 defm: SelMinMax_pats<setge, I32, A2_max, A2_min>;
863 defm: SelMinMax_pats<setgt, I32, A2_max, A2_min>;
864 defm: SelMinMax_pats<setle, I32, A2_min, A2_max>;
865 defm: SelMinMax_pats<setlt, I32, A2_min, A2_max>;
866 defm: SelMinMax_pats<setuge, I32, A2_maxu, A2_minu>;
867 defm: SelMinMax_pats<setugt, I32, A2_maxu, A2_minu>;
868 defm: SelMinMax_pats<setule, I32, A2_minu, A2_maxu>;
869 defm: SelMinMax_pats<setult, I32, A2_minu, A2_maxu>;
871 defm: SelMinMax_pats<setge, I64, A2_maxp, A2_minp>;
872 defm: SelMinMax_pats<setgt, I64, A2_maxp, A2_minp>;
873 defm: SelMinMax_pats<setle, I64, A2_minp, A2_maxp>;
874 defm: SelMinMax_pats<setlt, I64, A2_minp, A2_maxp>;
875 defm: SelMinMax_pats<setuge, I64, A2_maxup, A2_minup>;
876 defm: SelMinMax_pats<setugt, I64, A2_maxup, A2_minup>;
877 defm: SelMinMax_pats<setule, I64, A2_minup, A2_maxup>;
878 defm: SelMinMax_pats<setult, I64, A2_minup, A2_maxup>;
881 let AddedComplexity = 100, Predicates = [HasV5T] in {
882 defm: SelMinMax_pats<setolt, F32, F2_sfmin, F2_sfmax>;
883 defm: SelMinMax_pats<setole, F32, F2_sfmin, F2_sfmax>;
884 defm: SelMinMax_pats<setogt, F32, F2_sfmax, F2_sfmin>;
885 defm: SelMinMax_pats<setoge, F32, F2_sfmax, F2_sfmin>;
889 // --(7) Insert/extract --------------------------------------------------
892 def SDTHexagonINSERT:
893 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
894 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
895 def SDTHexagonINSERTRP:
896 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
897 SDTCisInt<0>, SDTCisVT<3, i64>]>;
899 def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>;
900 def HexagonINSERTRP: SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
902 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
903 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>;
904 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
905 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>;
906 def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
907 (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
908 def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
909 (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
911 def SDTHexagonEXTRACTU
912 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
913 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
914 def SDTHexagonEXTRACTURP
915 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
918 def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>;
919 def HexagonEXTRACTURP: SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
921 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5),
922 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>;
923 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6),
924 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>;
925 def: Pat<(HexagonEXTRACTURP I32:$Rs, I64:$Rt),
926 (S2_extractu_rp I32:$Rs, I64:$Rt)>;
927 def: Pat<(HexagonEXTRACTURP I64:$Rs, I64:$Rt),
928 (S2_extractup_rp I64:$Rs, I64:$Rt)>;
930 def SDTHexagonVSPLAT:
931 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
933 def HexagonVSPLAT: SDNode<"HexagonISD::VSPLAT", SDTHexagonVSPLAT>;
935 def: Pat<(v4i8 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
936 def: Pat<(v4i16 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
937 def: Pat<(v2i32 (HexagonVSPLAT s8_0ImmPred:$s8)),
938 (A2_combineii imm:$s8, imm:$s8)>;
939 def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>;
942 // --(8) Shift/permute ---------------------------------------------------
945 def SDTHexagonI64I32I32: SDTypeProfile<1, 2,
946 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
947 def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
948 SDTCisSubVecOfVec<1, 0>]>;
949 def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>;
951 def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
952 def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
953 def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>;
954 def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>;
956 def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>;
958 // The complexity of the combines involving immediates should be greater
959 // than the complexity of the combine with two registers.
960 let AddedComplexity = 50 in {
961 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8),
962 (A4_combineri IntRegs:$Rs, imm:$s8)>;
963 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs),
964 (A4_combineir imm:$s8, IntRegs:$Rs)>;
967 // The complexity of the combine with two immediates should be greater than
968 // the complexity of a combine involving a register.
969 let AddedComplexity = 75 in {
970 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6),
971 (A4_combineii imm:$s8, imm:$u6)>;
972 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8),
973 (A2_combineii imm:$s8, imm:$S8)>;
976 def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>;
977 def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)),
978 (A2_swiz (HiReg $Rss)))>;
980 def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>;
981 def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>;
982 def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>;
984 def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>;
985 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
986 def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>;
987 def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>;
988 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
989 def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>;
990 def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>;
991 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
992 def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>;
993 def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>;
994 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
995 def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>;
997 def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>;
998 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
999 def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>;
1000 def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>;
1001 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1002 def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>;
1005 def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)),
1006 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>;
1007 def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)),
1008 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5T]>;
1010 // Prefer S2_addasl_rrri over S2_asl_i_r_acc.
1011 let AddedComplexity = 120 in
1012 def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)),
1013 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>;
1015 let AddedComplexity = 100 in {
1016 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>;
1017 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>;
1018 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>;
1019 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>;
1021 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>;
1022 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>;
1023 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>;
1024 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>;
1026 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>;
1027 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>;
1028 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>;
1029 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>;
1030 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>;
1032 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>;
1033 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>;
1034 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>;
1035 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>;
1036 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>;
1038 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>;
1039 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>;
1040 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>;
1041 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>;
1042 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>;
1044 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>;
1045 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>;
1046 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>;
1047 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>;
1048 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>;
1051 let AddedComplexity = 100 in {
1052 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32>;
1053 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32>;
1054 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32>;
1055 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32>;
1057 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I32>;
1058 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I32>;
1059 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I32>;
1060 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I32>;
1061 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I32>;
1063 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32>;
1064 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32>;
1065 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32>;
1066 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32>;
1068 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I32>;
1069 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I32>;
1070 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I32>;
1071 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I32>;
1072 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I32>;
1074 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32>;
1075 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32>;
1076 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32>;
1077 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32>;
1079 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I32>;
1080 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I32>;
1081 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I32>;
1082 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I32>;
1083 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I32>;
1087 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1088 PatFrag RegPred, PatFrag ImmPred>
1089 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
1090 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>;
1092 let AddedComplexity = 200 in {
1093 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>;
1094 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>;
1095 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>;
1096 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>;
1097 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>;
1098 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>;
1099 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>;
1100 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>;
1103 // Prefer this pattern to S2_asl_i_p_or for the special case of joining
1104 // two 32-bit words into a 64-bit word.
1105 let AddedComplexity = 200 in
1106 def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)),
1107 (Combinew I32:$a, I32:$b)>;
1109 def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)),
1110 (Zext64 (and I32:$a, (i32 65535)))),
1111 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))),
1112 (shl (Aext64 I32:$d), (i32 48))),
1113 (Combinew (A2_combine_ll I32:$d, I32:$c),
1114 (A2_combine_ll I32:$b, I32:$a))>;
1116 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add I32:$b, 3))),
1118 (i32 (zextloadi8 (add I32:$b, 2)))),
1120 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
1121 (zextloadi8 I32:$b)),
1122 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
1124 let AddedComplexity = 200 in {
1125 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))),
1126 (A2_combine_ll I32:$Rt, I32:$Rs)>;
1127 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))),
1128 (A2_combine_lh I32:$Rt, I32:$Rs)>;
1129 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))),
1130 (A2_combine_hl I32:$Rt, I32:$Rs)>;
1131 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))),
1132 (A2_combine_hh I32:$Rt, I32:$Rs)>;
1135 def SDTHexagonVShift
1136 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>;
1138 def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>;
1139 def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>;
1140 def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>;
1142 def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>;
1143 def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>;
1144 def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>;
1145 def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>;
1146 def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>;
1147 def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>;
1149 def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>;
1150 def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>;
1151 def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>;
1152 def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>;
1153 def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>;
1154 def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>;
1156 def: Pat<(sra V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
1157 (S2_asr_i_vw V2I32:$b, imm:$c)>;
1158 def: Pat<(srl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
1159 (S2_lsr_i_vw V2I32:$b, imm:$c)>;
1160 def: Pat<(shl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
1161 (S2_asl_i_vw V2I32:$b, imm:$c)>;
1162 def: Pat<(sra V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
1163 (S2_asr_i_vh V4I16:$b, imm:$c)>;
1164 def: Pat<(srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
1165 (S2_lsr_i_vh V4I16:$b, imm:$c)>;
1166 def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
1167 (S2_asl_i_vh V4I16:$b, imm:$c)>;
1170 // --(9) Arithmetic/bitwise ----------------------------------------------
1173 def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>;
1174 def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
1175 def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>;
1177 let Predicates = [HasV5T] in {
1178 def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>;
1179 def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>;
1181 def: Pat<(fabs F64:$Rs),
1182 (Combinew (S2_clrbit_i (HiReg $Rs), 31),
1183 (i32 (LoReg $Rs)))>;
1184 def: Pat<(fneg F64:$Rs),
1185 (Combinew (S2_togglebit_i (HiReg $Rs), 31),
1186 (i32 (LoReg $Rs)))>;
1189 let AddedComplexity = 50 in
1190 def: Pat<(xor (add (sra I32:$Rs, (i32 31)),
1192 (sra I32:$Rs, (i32 31))),
1196 def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>;
1197 def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>;
1198 def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>;
1199 def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>;
1201 def: OpR_RR_pat<A2_add, Add, i32, I32>;
1202 def: OpR_RR_pat<A2_sub, Sub, i32, I32>;
1203 def: OpR_RR_pat<A2_and, And, i32, I32>;
1204 def: OpR_RR_pat<A2_or, Or, i32, I32>;
1205 def: OpR_RR_pat<A2_xor, Xor, i32, I32>;
1206 def: OpR_RR_pat<A2_addp, Add, i64, I64>;
1207 def: OpR_RR_pat<A2_subp, Sub, i64, I64>;
1208 def: OpR_RR_pat<A2_andp, And, i64, I64>;
1209 def: OpR_RR_pat<A2_orp, Or, i64, I64>;
1210 def: OpR_RR_pat<A2_xorp, Xor, i64, I64>;
1211 def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>;
1212 def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>;
1214 def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>;
1215 def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>;
1217 def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>;
1218 def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>;
1219 def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>;
1220 def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>;
1221 def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>;
1222 def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>;
1224 def: OpR_RR_pat<A2_and, And, v2i16, V2I16>;
1225 def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>;
1226 def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>;
1228 def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>;
1229 def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>;
1230 def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>;
1231 def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>;
1232 def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>;
1233 def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>;
1234 def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>;
1235 def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>;
1236 def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>;
1238 def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>;
1239 def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>;
1240 def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>;
1241 def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>;
1242 def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>;
1244 // Arithmetic on predicates.
1245 def: OpR_RR_pat<C2_xor, Add, i1, I1>;
1246 def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>;
1247 def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>;
1248 def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>;
1249 def: OpR_RR_pat<C2_xor, Sub, i1, I1>;
1250 def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>;
1251 def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>;
1252 def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>;
1253 def: OpR_RR_pat<C2_and, Mul, i1, I1>;
1254 def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>;
1255 def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>;
1256 def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>;
1258 let Predicates = [HasV5T] in {
1259 def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>;
1260 def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>;
1261 def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>;
1262 def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>;
1263 def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>;
1266 // In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add,
1267 // over add-add with individual multiplies as inputs.
1268 let AddedComplexity = 10 in {
1269 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>;
1270 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>;
1271 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32>;
1274 def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>;
1275 def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>;
1276 def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32>;
1279 def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)),
1280 (M2_mpysin IntRegs:$Rs, imm:$u8)>;
1282 def n8_0ImmPred: PatLeaf<(i32 imm), [{
1283 int64_t V = N->getSExtValue();
1284 return -255 <= V && V <= 0;
1287 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
1288 def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8),
1289 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>;
1291 def: Pat<(add Sext64:$Rs, I64:$Rt),
1292 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>;
1294 def: AccRRR_pat<M4_and_and, And, Su<And>, I32, I32>;
1295 def: AccRRR_pat<M4_and_or, And, Su<Or>, I32, I32>;
1296 def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32>;
1297 def: AccRRR_pat<M4_or_and, Or, Su<And>, I32, I32>;
1298 def: AccRRR_pat<M4_or_or, Or, Su<Or>, I32, I32>;
1299 def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32>;
1300 def: AccRRR_pat<M4_xor_and, Xor, Su<And>, I32, I32>;
1301 def: AccRRR_pat<M4_xor_or, Xor, Su<Or>, I32, I32>;
1302 def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32>;
1303 def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64>;
1305 // For dags like (or (and (not _), _), (shl _, _)) where the "or" with
1306 // one argument matches the patterns below, and with the other argument
1307 // matches S2_asl_r_r_or, etc, prefer the patterns below.
1308 let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor.
1309 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32>;
1310 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32>;
1311 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32>;
1314 // S4_addaddi and S4_subaddi don't have tied operands, so give them
1315 // a bit of preference.
1316 let AddedComplexity = 30 in {
1317 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)),
1318 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
1319 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)),
1320 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
1321 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)),
1322 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1323 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru),
1324 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1325 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6),
1326 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1329 def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)),
1330 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>;
1331 def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)),
1332 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
1333 def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)),
1334 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
1337 def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
1338 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1339 def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
1340 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1342 def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)),
1343 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
1344 def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
1345 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
1346 def: Pat<(mul Sext64:$Rs, Sext64:$Rt),
1347 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1349 def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
1350 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1351 def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
1352 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1353 def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
1354 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1355 def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
1356 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1357 def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
1358 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1359 def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
1360 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1363 def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16),
1364 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>;
1365 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
1366 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
1367 def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)),
1368 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>;
1370 // Subtract halfword.
1371 def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16),
1372 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>;
1373 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
1374 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
1375 def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)),
1376 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>;
1378 def: Pat<(mul I64:$Rss, I64:$Rtt),
1380 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))),
1385 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>;
1387 def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt),
1393 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32),
1396 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))),
1400 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>;
1402 // Multiply 64-bit unsigned and use upper result.
1403 def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>;
1405 // Multiply 64-bit signed and use upper result.
1407 // For two signed 64-bit integers A and B, let A' and B' denote A and B
1408 // with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the
1409 // sign bit of A (and identically for B). With this notation, the signed
1410 // product A*B can be written as:
1411 // AB = (-2^63 s(A) + A') * (-2^63 s(B) + B')
1412 // = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B'
1413 // = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A']
1414 // = (unsigned product AB) - 2^64 [s(A)B'+s(B)A']
1416 // Clear the sign bit in a 64-bit register.
1417 def ClearSign : OutPatFrag<(ops node:$Rss),
1418 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>;
1420 def : Pat <(mulhs I64:$Rss, I64:$Rtt),
1424 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)),
1425 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>;
1427 // Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions
1428 // will put the immediate addend into a register, while these instructions will
1429 // use it directly. Such a construct does not appear in the middle of a gep,
1430 // where M2_macsip would be preferable.
1431 let AddedComplexity = 20 in {
1432 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6),
1433 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
1434 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6),
1435 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
1438 // Keep these instructions less preferable to M2_macsip/M2_macsin.
1439 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
1440 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
1441 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
1442 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>;
1443 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
1444 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
1447 let Predicates = [HasV5T] in {
1448 def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx),
1449 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>;
1450 def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx),
1451 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
1452 def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx),
1453 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
1457 def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
1458 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>;
1459 def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
1460 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>;
1462 // Add/subtract two v4i8: Hexagon does not have an insn for this one, so
1463 // we use the double add v8i8, and use only the low part of the result.
1464 def: Pat<(add V4I8:$Rs, V4I8:$Rt),
1465 (LoReg (A2_vaddub (ToZext64 $Rs), (ToZext64 $Rt)))>;
1466 def: Pat<(sub V4I8:$Rs, V4I8:$Rt),
1467 (LoReg (A2_vsubub (ToZext64 $Rs), (ToZext64 $Rt)))>;
1469 // Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two
1470 // half-words, and saturates the result to a 32-bit value, except the
1471 // saturation never happens (it can only occur with scaling).
1472 def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
1473 (LoReg (S2_vtrunewh (A2_combineii 0, 0),
1474 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>;
1475 def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
1476 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
1477 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>;
1479 // Multiplies two v4i8 vectors.
1480 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
1481 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>,
1484 // Multiplies two v8i8 vectors.
1485 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
1486 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))),
1487 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>,
1491 // --(10) Bit ------------------------------------------------------------
1494 // Count leading zeros.
1495 def: Pat<(ctlz I32:$Rs), (S2_cl0 I32:$Rs)>;
1496 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
1498 // Count trailing zeros.
1499 def: Pat<(cttz I32:$Rs), (S2_ct0 I32:$Rs)>;
1500 def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>;
1502 // Count leading ones.
1503 def: Pat<(ctlz (not I32:$Rs)), (S2_cl1 I32:$Rs)>;
1504 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
1506 // Count trailing ones.
1507 def: Pat<(cttz (not I32:$Rs)), (S2_ct1 I32:$Rs)>;
1508 def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
1510 // Define leading/trailing patterns that require zero-extensions to 64 bits.
1511 def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>;
1512 def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>;
1513 def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>;
1514 def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>;
1516 def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>;
1517 def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>;
1519 def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>;
1520 def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>;
1523 let AddedComplexity = 20 in { // Complexity greater than and/or/xor
1524 def: Pat<(and I32:$Rs, IsNPow2_32:$V),
1525 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
1526 def: Pat<(or I32:$Rs, IsPow2_32:$V),
1527 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
1528 def: Pat<(xor I32:$Rs, IsPow2_32:$V),
1529 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
1531 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))),
1532 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1533 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)),
1534 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1535 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)),
1536 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
1539 // Clr/set/toggle bit for 64-bit values with immediate bit index.
1540 let AddedComplexity = 20 in { // Complexity greater than and/or/xor
1541 def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
1542 (Combinew (i32 (HiReg $Rss)),
1543 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>;
1544 def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
1545 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
1546 (i32 (LoReg $Rss)))>;
1548 def: Pat<(or I64:$Rss, IsPow2_64L:$V),
1549 (Combinew (i32 (HiReg $Rss)),
1550 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>;
1551 def: Pat<(or I64:$Rss, IsPow2_64H:$V),
1552 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
1553 (i32 (LoReg $Rss)))>;
1555 def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
1556 (Combinew (i32 (HiReg $Rss)),
1557 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>;
1558 def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
1559 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
1560 (i32 (LoReg $Rss)))>;
1563 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
1564 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
1565 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>;
1566 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)),
1567 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1568 def: Pat<(i1 (trunc I32:$Rs)),
1569 (S2_tstbit_i IntRegs:$Rs, 0)>;
1570 def: Pat<(i1 (trunc I64:$Rs)),
1571 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
1574 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
1575 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)),
1576 (C2_bitsclri IntRegs:$Rs, imm:$u6)>;
1577 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)),
1578 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
1581 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
1582 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)),
1583 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
1585 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
1586 def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
1587 (S4_ntstbit_i I32:$Rs, imm:$u5)>;
1588 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)),
1589 (S4_ntstbit_r I32:$Rs, I32:$Rt)>;
1592 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
1593 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
1594 // if ([!]tstbit(...)) jump ...
1595 let AddedComplexity = 100 in
1596 def: Pat<(i1 (setne (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
1597 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
1599 let AddedComplexity = 100 in
1600 def: Pat<(i1 (seteq (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
1601 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
1603 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
1604 // represented as a compare against "value & 0xFF", which is an exact match
1605 // for cmpb (same for cmph). The patterns below do not contain any additional
1606 // complexity that would make them preferable, and if they were actually used
1607 // instead of cmpb/cmph, they would result in a compare against register that
1608 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
1609 def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)),
1610 (C4_nbitsclri I32:$Rs, imm:$u6)>;
1611 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
1612 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
1613 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
1614 (C4_nbitsset I32:$Rs, I32:$Rt)>;
1616 // Special patterns to address certain cases where the "top-down" matching
1617 // algorithm would cause suboptimal selection.
1619 let AddedComplexity = 100 in {
1620 // Avoid A4_rcmp[n]eqi in these cases:
1621 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
1622 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
1623 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
1624 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
1627 // --(11) PIC ------------------------------------------------------------
1630 def SDT_HexagonAtGot
1631 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>;
1632 def SDT_HexagonAtPcrel
1633 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1635 // AT_GOT address-of-GOT, address-of-global, offset-in-global
1636 def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>;
1637 // AT_PCREL address-of-global
1638 def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>;
1640 def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)),
1641 (L2_loadri_io I32:$got, imm:$addr)>;
1642 def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off),
1643 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>;
1644 def: Pat<(HexagonAtPcrel I32:$addr),
1645 (C4_addipc imm:$addr)>;
1647 // The HVX load patterns also match AT_PCREL directly. Make sure that
1648 // if the selection of this opcode changes, it's updated in all places.
1651 // --(12) Load -----------------------------------------------------------
1654 def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{
1655 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
1657 def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{
1658 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
1661 def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
1662 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
1664 def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
1665 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
1668 def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
1669 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
1671 def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
1672 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
1675 // Patterns to select load-indexed: Rs + Off.
1676 // - frameindex [+ imm],
1677 multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1679 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
1680 (VT (MI AddrFI:$fi, imm:$Off))>;
1681 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
1682 (VT (MI AddrFI:$fi, imm:$Off))>;
1683 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1686 // Patterns to select load-indexed: Rs + Off.
1687 // - base reg [+ imm]
1688 multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1690 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
1691 (VT (MI IntRegs:$Rs, imm:$Off))>;
1692 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
1693 (VT (MI IntRegs:$Rs, imm:$Off))>;
1694 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>;
1697 // Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
1698 multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1700 defm: Loadxfi_pat<Load, VT, ImmPred, MI>;
1701 defm: Loadxgi_pat<Load, VT, ImmPred, MI>;
1704 // Patterns to select load reg indexed: Rs + Off with a value modifier.
1705 // - frameindex [+ imm]
1706 multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
1707 PatLeaf ImmPred, InstHexagon MI> {
1708 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
1709 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
1710 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
1711 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
1712 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>;
1715 // Patterns to select load reg indexed: Rs + Off with a value modifier.
1716 // - base reg [+ imm]
1717 multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
1718 PatLeaf ImmPred, InstHexagon MI> {
1719 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
1720 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
1721 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
1722 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
1723 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
1726 // Patterns to select load reg indexed: Rs + Off with a value modifier.
1727 // Combines Loadxfim + Loadxgim.
1728 multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
1729 PatLeaf ImmPred, InstHexagon MI> {
1730 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>;
1731 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>;
1734 // Pattern to select load reg reg-indexed: Rs + Rt<<u2.
1735 class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI>
1736 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
1737 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
1739 // Pattern to select load reg reg-indexed: Rs + Rt<<0.
1740 class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI>
1741 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
1742 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
1744 // Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier.
1745 class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
1747 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
1748 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>;
1750 // Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier.
1751 class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
1753 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
1754 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>;
1756 // Pattern to select load long-offset reg-indexed: Addr + Rt<<u2.
1757 // Don't match for u2==0, instead use reg+imm for those cases.
1758 class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI>
1759 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))),
1760 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>;
1762 class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod,
1764 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))),
1765 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>;
1767 // Pattern to select load absolute.
1768 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
1769 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
1771 // Pattern to select load absolute with value modifier.
1772 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
1774 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
1777 let AddedComplexity = 20 in {
1778 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>;
1779 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>;
1780 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>;
1781 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>;
1782 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>;
1783 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>;
1784 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>;
1785 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>;
1786 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>;
1787 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>;
1788 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>;
1789 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>;
1790 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>;
1791 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>;
1792 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>;
1793 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>;
1794 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>;
1795 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>;
1798 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>;
1799 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>;
1800 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>;
1801 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>;
1804 let AddedComplexity = 30 in {
1805 defm: Loadxim_pat<extloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>;
1806 defm: Loadxim_pat<extloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>;
1807 defm: Loadxim_pat<extloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>;
1808 defm: Loadxim_pat<extloadi32, i64, ToZext64, anyimm2, L2_loadri_io>;
1809 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>;
1810 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>;
1811 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>;
1812 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>;
1813 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>;
1814 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>;
1815 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>;
1818 let AddedComplexity = 60 in {
1819 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>;
1820 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>;
1821 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>;
1822 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
1823 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>;
1824 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>;
1825 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>;
1826 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
1827 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>;
1828 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>;
1829 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>;
1830 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
1831 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>;
1832 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>;
1833 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>;
1834 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>;
1836 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>;
1837 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>;
1838 def: Loadxum_pat<extloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>;
1839 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>;
1840 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>;
1841 def: Loadxum_pat<extloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>;
1842 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>;
1843 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>;
1844 def: Loadxum_pat<extloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>;
1847 let AddedComplexity = 40 in {
1848 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>;
1849 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>;
1850 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>;
1851 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>;
1852 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>;
1853 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>;
1854 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>;
1855 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>;
1856 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>;
1857 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>;
1860 let AddedComplexity = 20 in {
1861 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>;
1862 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>;
1863 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>;
1864 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>;
1865 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>;
1866 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>;
1867 def: Loadxr_add_pat<load, i32, L4_loadri_rr>;
1868 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>;
1869 def: Loadxr_add_pat<load, f32, L4_loadri_rr>;
1870 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>;
1873 let AddedComplexity = 40 in {
1874 def: Loadxrm_shl_pat<extloadi8, i64, ToZext64, L4_loadrub_rr>;
1875 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>;
1876 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>;
1877 def: Loadxrm_shl_pat<extloadi16, i64, ToZext64, L4_loadruh_rr>;
1878 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>;
1879 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>;
1880 def: Loadxrm_shl_pat<extloadi32, i64, ToZext64, L4_loadri_rr>;
1881 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>;
1882 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>;
1885 let AddedComplexity = 20 in {
1886 def: Loadxrm_add_pat<extloadi8, i64, ToZext64, L4_loadrub_rr>;
1887 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>;
1888 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>;
1889 def: Loadxrm_add_pat<extloadi16, i64, ToZext64, L4_loadruh_rr>;
1890 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>;
1891 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>;
1892 def: Loadxrm_add_pat<extloadi32, i64, ToZext64, L4_loadri_rr>;
1893 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>;
1894 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>;
1899 let AddedComplexity = 60 in {
1900 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>;
1901 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>;
1902 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>;
1903 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>;
1904 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>;
1905 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>;
1906 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>;
1907 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>;
1908 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>;
1909 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>;
1910 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>;
1912 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>;
1913 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>;
1914 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>;
1915 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>;
1918 let AddedComplexity = 30 in {
1919 def: Loadam_pat<extloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>;
1920 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>;
1921 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>;
1922 def: Loadam_pat<extloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>;
1923 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>;
1924 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>;
1925 def: Loadam_pat<extloadi32, i64, anyimm2, ToZext64, PS_loadriabs>;
1926 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>;
1927 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>;
1929 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>;
1930 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>;
1933 // GP-relative address
1935 let AddedComplexity = 100 in {
1936 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>;
1937 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>;
1938 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>;
1939 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>;
1940 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>;
1941 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>;
1942 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>;
1943 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>;
1944 def: Loada_pat<load, i32, addrgp, L2_loadrigp>;
1945 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>;
1946 def: Loada_pat<load, f32, addrgp, L2_loadrigp>;
1947 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>;
1949 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
1950 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
1951 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
1952 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
1955 let AddedComplexity = 70 in {
1956 def: Loadam_pat<extloadi8, i64, addrgp, ToZext64, L2_loadrubgp>;
1957 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>;
1958 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>;
1959 def: Loadam_pat<extloadi16, i64, addrgp, ToZext64, L2_loadruhgp>;
1960 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>;
1961 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>;
1962 def: Loadam_pat<extloadi32, i64, addrgp, ToZext64, L2_loadrigp>;
1963 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>;
1964 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>;
1966 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
1967 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>;
1971 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1972 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1974 let AddedComplexity = 20 in
1975 def: Pat<(i32 (sextloadi1 I32:$Rs)),
1976 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1978 // Patterns for loads of i1:
1979 def: Pat<(i1 (load AddrFI:$fi)),
1980 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
1981 def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))),
1982 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
1983 def: Pat<(i1 (load I32:$Rs)),
1984 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
1988 multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType VT,
1990 def: Pat<(VT (Load I32:$Rt)), (MI I32:$Rt, 0)>;
1991 def: Pat<(VT (Load (add I32:$Rt, ImmPred:$s))), (MI I32:$Rt, imm:$s)>;
1992 // The HVX selection code for shuffles can generate vector constants.
1993 // Calling "Select" on the resulting loads from CP fails without these
1995 def: Pat<(VT (Load (HexagonCP tconstpool:$A))), (MI (A2_tfrsi imm:$A), 0)>;
1996 def: Pat<(VT (Load (HexagonAtPcrel tconstpool:$A))),
1997 (MI (C4_addipc imm:$A), 0)>;
2001 let Predicates = [UseHVX] in {
2002 multiclass HvxLdVs_pat<InstHexagon MI, PatFrag Load> {
2003 defm: HvxLd_pat<MI, Load, VecI8, IsVecOff>;
2004 defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>;
2005 defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>;
2007 defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>;
2008 defm: HvxLdVs_pat<V6_vL32b_ai, alignedload>;
2009 defm: HvxLdVs_pat<V6_vL32Ub_ai, unalignedload>;
2011 multiclass HvxLdWs_pat<InstHexagon MI, PatFrag Load> {
2012 defm: HvxLd_pat<MI, Load, VecPI8, IsVecOff>;
2013 defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>;
2014 defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>;
2016 defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>;
2017 defm: HvxLdWs_pat<PS_vloadrw_ai, alignedload>;
2018 defm: HvxLdWs_pat<PS_vloadrwu_ai, unalignedload>;
2022 // --(13) Store ----------------------------------------------------------
2026 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI>
2027 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4),
2028 (MI I32:$Rx, imm:$s4, Value:$Rt)>;
2030 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>;
2031 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
2032 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>;
2033 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
2035 // Patterns for generating stores, where the address takes different forms:
2037 // - frameindex + offset,
2039 // - simple (base address without offset).
2040 // These would usually be used together (via Storexi_pat defined below), but
2041 // in some cases one may want to apply different properties (such as
2042 // AddedComplexity) to the individual patterns.
2043 class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2044 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2046 multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2048 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
2049 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2050 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
2051 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2054 multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2056 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
2057 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2058 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
2059 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2062 class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2063 : Pat<(Store Value:$Rt, I32:$Rs),
2064 (MI IntRegs:$Rs, 0, Value:$Rt)>;
2066 // Patterns for generating stores, where the address takes different forms,
2067 // and where the value being stored is transformed through the value modifier
2068 // ValueMod. The address forms are same as above.
2069 class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
2071 : Pat<(Store Value:$Rs, AddrFI:$fi),
2072 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
2074 multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2075 PatFrag ValueMod, InstHexagon MI> {
2076 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
2077 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2078 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
2079 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2082 multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2083 PatFrag ValueMod, InstHexagon MI> {
2084 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
2085 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2086 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
2087 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2090 class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
2092 : Pat<(Store Value:$Rt, I32:$Rs),
2093 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
2095 multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
2097 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>;
2098 def: Storexi_fi_pat <Store, Value, MI>;
2099 defm: Storexi_add_pat <Store, Value, ImmPred, MI>;
2102 multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
2103 PatFrag ValueMod, InstHexagon MI> {
2104 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
2105 def: Storexim_fi_pat <Store, Value, ValueMod, MI>;
2106 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>;
2110 class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI>
2111 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)),
2112 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>;
2115 class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2116 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))),
2117 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
2120 class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2121 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)),
2122 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>;
2124 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
2125 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
2127 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
2129 : Pat<(Store Value:$val, Addr:$addr),
2130 (MI Addr:$addr, (ValueMod Value:$val))>;
2132 // Regular stores in the DAG have two operands: value and address.
2133 // Atomic stores also have two, but they are reversed: address, value.
2134 // To use atomic stores with the patterns, they need to have their operands
2135 // swapped. This relies on the knowledge that the F.Fragment uses names
2137 class AtomSt<PatFrag F>
2138 : PatFrag<(ops node:$val, node:$ptr), F.Fragment, F.PredicateCode,
2139 F.OperandTransform> {
2140 let IsAtomic = F.IsAtomic;
2141 let MemoryVT = F.MemoryVT;
2145 def IMM_BYTE : SDNodeXForm<imm, [{
2146 // -1 can be represented as 255, etc.
2147 // assigning to a byte restores our desired signed value.
2148 int8_t imm = N->getSExtValue();
2149 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2152 def IMM_HALF : SDNodeXForm<imm, [{
2153 // -1 can be represented as 65535, etc.
2154 // assigning to a short restores our desired signed value.
2155 int16_t imm = N->getSExtValue();
2156 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2159 def IMM_WORD : SDNodeXForm<imm, [{
2160 // -1 can be represented as 4294967295, etc.
2161 // Currently, it's not doing this. But some optimization
2162 // might convert -1 to a large +ve number.
2163 // assigning to a word restores our desired signed value.
2164 int32_t imm = N->getSExtValue();
2165 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2168 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
2169 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
2170 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
2172 // Even though the offset is not extendable in the store-immediate, we
2173 // can still generate the fi# in the base address. If the final offset
2174 // is not valid for the instruction, we will replace it with a scratch
2176 class SmallStackStore<PatFrag Store>
2177 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{
2178 return isSmallStackStore(cast<StoreSDNode>(N));
2181 // This is the complement of SmallStackStore.
2182 class LargeStackStore<PatFrag Store>
2183 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{
2184 return !isSmallStackStore(cast<StoreSDNode>(N));
2187 // Preferred addressing modes for various combinations of stored value
2188 // and address computation.
2189 // For stores where the address and value are both immediates, prefer
2190 // store-immediate. The reason is that the constant-extender optimization
2191 // can replace store-immediate with a store-register, but there is nothing
2192 // to generate a store-immediate out of a store-register.
2194 // C R F F+C R+C R+R R<<S+C R<<S+R
2195 // --+-------+-----+-----+------+-----+-----+--------+--------
2196 // C | imm | imm | imm | imm | imm | rr | ur | rr
2197 // R | abs* | io | io | io | io | rr | ur | rr
2199 // (*) Absolute or GP-relative.
2201 // Note that any expression can be matched by Reg. In particular, an immediate
2202 // can always be placed in a register, so patterns checking for Imm should
2203 // have a higher priority than the ones involving Reg that could also match.
2204 // For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the
2205 // preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before
2208 // The order in which the different combinations are tried:
2210 // C F R F+C R+C R+R R<<S+C R<<S+R
2211 // --+-------+-----+-----+------+-----+-----+--------+--------
2212 // C | 1 | 6 | - | 5 | 9 | - | - | -
2213 // R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4
2216 // First, match the unusual case of doubleword store into Reg+Imm4, i.e.
2217 // a store where the offset Imm4 is a multiple of 4, but not of 8. This
2218 // implies that Reg is also a proper multiple of 4. To still generate a
2219 // doubleword store, add 4 to Reg, and subtract 4 from the offset.
2221 def s30_2ProperPred : PatLeaf<(i32 imm), [{
2222 int64_t v = (int64_t)N->getSExtValue();
2223 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
2225 def RoundTo8 : SDNodeXForm<imm, [{
2226 int32_t Imm = N->getSExtValue();
2227 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
2230 let AddedComplexity = 150 in
2231 def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)),
2232 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>;
2234 class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2235 : Pat<(Store Value:$val, anyimm:$addr),
2236 (MI (ToI32 $addr), 0, Value:$val)>;
2237 class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
2239 : Pat<(Store Value:$val, anyimm:$addr),
2240 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>;
2242 let AddedComplexity = 140 in {
2243 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>;
2244 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>;
2245 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>;
2247 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>;
2248 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>;
2249 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>;
2252 // GP-relative address
2253 let AddedComplexity = 120 in {
2254 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
2255 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
2256 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
2257 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
2258 def: Storea_pat<store, F32, addrgp, S2_storerigp>;
2259 def: Storea_pat<store, F64, addrgp, S2_storerdgp>;
2260 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
2261 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
2262 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
2263 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
2265 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>;
2266 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>;
2267 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>;
2268 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
2272 let AddedComplexity = 110 in {
2273 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>;
2274 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>;
2275 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>;
2276 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>;
2277 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>;
2278 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>;
2279 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>;
2280 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>;
2281 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>;
2282 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>;
2284 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>;
2285 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>;
2286 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>;
2287 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>;
2291 let AddedComplexity = 100 in {
2292 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>;
2293 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>;
2294 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>;
2295 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>;
2296 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>;
2297 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>;
2299 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)),
2300 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>;
2304 let AddedComplexity = 90 in {
2305 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>;
2306 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>;
2307 def: Storexr_shl_pat<store, I32, S4_storeri_rr>;
2308 def: Storexr_shl_pat<store, I64, S4_storerd_rr>;
2309 def: Storexr_shl_pat<store, F32, S4_storeri_rr>;
2310 def: Storexr_shl_pat<store, F64, S4_storerd_rr>;
2312 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)),
2313 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>;
2316 class SS_<PatFrag F> : SmallStackStore<F>;
2317 class LS_<PatFrag F> : LargeStackStore<F>;
2319 multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
2320 defm: Storexim_fi_add_pat<S, V, O, M, I>;
2322 multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
2323 defm: Storexi_fi_add_pat<S, V, O, I>;
2326 // Fi+Imm, store-immediate
2327 let AddedComplexity = 80 in {
2328 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>;
2329 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>;
2330 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>;
2332 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>;
2333 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>;
2334 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>;
2336 // For large-stack stores, generate store-register (prefer explicit Fi
2338 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>;
2339 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>;
2340 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>;
2343 // Fi, store-immediate
2344 let AddedComplexity = 70 in {
2345 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>;
2346 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>;
2347 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>;
2349 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>;
2350 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>;
2351 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>;
2353 // For large-stack stores, generate store-register (prefer explicit Fi
2355 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>;
2356 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>;
2357 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>;
2360 // Fi+Imm, Fi, store-register
2361 let AddedComplexity = 60 in {
2362 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>;
2363 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>;
2364 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>;
2365 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>;
2366 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>;
2367 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>;
2368 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>;
2370 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>;
2371 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>;
2372 def: Storexi_fi_pat<store, I32, S2_storeri_io>;
2373 def: Storexi_fi_pat<store, I64, S2_storerd_io>;
2374 def: Storexi_fi_pat<store, F32, S2_storeri_io>;
2375 def: Storexi_fi_pat<store, F64, S2_storerd_io>;
2376 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>;
2380 multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
2381 defm: Storexim_add_pat<S, V, O, M, I>;
2383 multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
2384 defm: Storexi_add_pat<S, V, O, I>;
2387 // Reg+Imm, store-immediate
2388 let AddedComplexity = 50 in {
2389 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>;
2390 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>;
2391 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>;
2393 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>;
2394 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>;
2395 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>;
2398 // Reg+Imm, store-register
2399 let AddedComplexity = 40 in {
2400 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>;
2401 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>;
2402 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>;
2403 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>;
2404 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>;
2405 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>;
2407 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>;
2408 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>;
2409 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>;
2410 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>;
2412 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>;
2413 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>;
2414 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>;
2415 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>;
2419 let AddedComplexity = 30 in {
2420 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>;
2421 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>;
2422 def: Storexr_add_pat<store, I32, S4_storeri_rr>;
2423 def: Storexr_add_pat<store, I64, S4_storerd_rr>;
2424 def: Storexr_add_pat<store, F32, S4_storeri_rr>;
2425 def: Storexr_add_pat<store, F64, S4_storerd_rr>;
2427 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)),
2428 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>;
2431 // Reg, store-immediate
2432 let AddedComplexity = 20 in {
2433 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>;
2434 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>;
2435 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>;
2437 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>;
2438 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>;
2439 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>;
2442 // Reg, store-register
2443 let AddedComplexity = 10 in {
2444 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>;
2445 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>;
2446 def: Storexi_base_pat<store, I32, S2_storeri_io>;
2447 def: Storexi_base_pat<store, I64, S2_storerd_io>;
2448 def: Storexi_base_pat<store, F32, S2_storeri_io>;
2449 def: Storexi_base_pat<store, F64, S2_storerd_io>;
2451 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
2452 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
2453 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
2454 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>;
2456 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>;
2457 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>;
2458 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>;
2459 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>;
2464 multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
2466 def: Pat<(Store Value:$Vs, I32:$Rt),
2467 (MI I32:$Rt, 0, Value:$Vs)>;
2468 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
2469 (MI I32:$Rt, imm:$s, Value:$Vs)>;
2472 let Predicates = [UseHVX] in {
2473 multiclass HvxStVs_pat<InstHexagon MI, PatFrag Store> {
2474 defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>;
2475 defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>;
2476 defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>;
2478 defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>;
2479 defm: HvxStVs_pat<V6_vS32b_ai, alignedstore>;
2480 defm: HvxStVs_pat<V6_vS32Ub_ai, unalignedstore>;
2482 multiclass HvxStWs_pat<InstHexagon MI, PatFrag Store> {
2483 defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>;
2484 defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>;
2485 defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>;
2487 defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>;
2488 defm: HvxStWs_pat<PS_vstorerw_ai, alignedstore>;
2489 defm: HvxStWs_pat<PS_vstorerwu_ai, unalignedstore>;
2493 // --(14) Memop ----------------------------------------------------------
2496 def m5_0Imm8Pred : PatLeaf<(i32 imm), [{
2497 int8_t V = N->getSExtValue();
2498 return -32 < V && V <= -1;
2501 def m5_0Imm16Pred : PatLeaf<(i32 imm), [{
2502 int16_t V = N->getSExtValue();
2503 return -32 < V && V <= -1;
2506 def m5_0ImmPred : PatLeaf<(i32 imm), [{
2507 int64_t V = N->getSExtValue();
2508 return -31 <= V && V <= -1;
2511 def IsNPow2_8 : PatLeaf<(i32 imm), [{
2512 uint8_t NV = ~N->getZExtValue();
2513 return isPowerOf2_32(NV);
2516 def IsNPow2_16 : PatLeaf<(i32 imm), [{
2517 uint16_t NV = ~N->getZExtValue();
2518 return isPowerOf2_32(NV);
2521 def Log2_8 : SDNodeXForm<imm, [{
2522 uint8_t V = N->getZExtValue();
2523 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
2526 def Log2_16 : SDNodeXForm<imm, [{
2527 uint16_t V = N->getZExtValue();
2528 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
2531 def LogN2_8 : SDNodeXForm<imm, [{
2532 uint8_t NV = ~N->getZExtValue();
2533 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
2536 def LogN2_16 : SDNodeXForm<imm, [{
2537 uint16_t NV = ~N->getZExtValue();
2538 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
2541 def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>;
2543 multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper,
2546 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs),
2547 (MI I32:$Rs, 0, I32:$A)>;
2549 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs),
2550 (MI AddrFI:$Rs, 0, I32:$A)>;
2553 multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
2554 SDNode Oper, InstHexagon MI> {
2556 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A),
2557 (add I32:$Rs, ImmPred:$Off)),
2558 (MI I32:$Rs, imm:$Off, I32:$A)>;
2559 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A),
2560 (IsOrAdd I32:$Rs, ImmPred:$Off)),
2561 (MI I32:$Rs, imm:$Off, I32:$A)>;
2563 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A),
2564 (add AddrFI:$Rs, ImmPred:$Off)),
2565 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
2566 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A),
2567 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)),
2568 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
2571 multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
2572 SDNode Oper, InstHexagon MI> {
2573 defm: Memopxr_base_pat <Load, Store, Oper, MI>;
2574 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>;
2577 let AddedComplexity = 200 in {
2579 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add,
2580 /*anyext*/ L4_add_memopb_io>;
2581 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add,
2582 /*sext*/ L4_add_memopb_io>;
2583 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add,
2584 /*zext*/ L4_add_memopb_io>;
2585 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add,
2586 /*anyext*/ L4_add_memoph_io>;
2587 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add,
2588 /*sext*/ L4_add_memoph_io>;
2589 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add,
2590 /*zext*/ L4_add_memoph_io>;
2591 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>;
2594 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub,
2595 /*anyext*/ L4_sub_memopb_io>;
2596 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub,
2597 /*sext*/ L4_sub_memopb_io>;
2598 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub,
2599 /*zext*/ L4_sub_memopb_io>;
2600 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub,
2601 /*anyext*/ L4_sub_memoph_io>;
2602 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub,
2603 /*sext*/ L4_sub_memoph_io>;
2604 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub,
2605 /*zext*/ L4_sub_memoph_io>;
2606 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>;
2609 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and,
2610 /*anyext*/ L4_and_memopb_io>;
2611 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and,
2612 /*sext*/ L4_and_memopb_io>;
2613 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and,
2614 /*zext*/ L4_and_memopb_io>;
2615 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and,
2616 /*anyext*/ L4_and_memoph_io>;
2617 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and,
2618 /*sext*/ L4_and_memoph_io>;
2619 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and,
2620 /*zext*/ L4_and_memoph_io>;
2621 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>;
2624 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or,
2625 /*anyext*/ L4_or_memopb_io>;
2626 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or,
2627 /*sext*/ L4_or_memopb_io>;
2628 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or,
2629 /*zext*/ L4_or_memopb_io>;
2630 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or,
2631 /*anyext*/ L4_or_memoph_io>;
2632 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or,
2633 /*sext*/ L4_or_memoph_io>;
2634 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or,
2635 /*zext*/ L4_or_memoph_io>;
2636 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>;
2640 multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper,
2641 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> {
2643 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs),
2644 (MI I32:$Rs, 0, (ArgMod Arg:$A))>;
2646 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs),
2647 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>;
2650 multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
2651 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
2654 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A),
2655 (add I32:$Rs, ImmPred:$Off)),
2656 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
2657 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A),
2658 (IsOrAdd I32:$Rs, ImmPred:$Off)),
2659 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
2661 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
2662 (add AddrFI:$Rs, ImmPred:$Off)),
2663 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
2664 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
2665 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)),
2666 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
2669 multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
2670 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
2672 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>;
2673 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>;
2676 let AddedComplexity = 220 in {
2678 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
2679 /*anyext*/ IdImm, L4_iadd_memopb_io>;
2680 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
2681 /*sext*/ IdImm, L4_iadd_memopb_io>;
2682 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
2683 /*zext*/ IdImm, L4_iadd_memopb_io>;
2684 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
2685 /*anyext*/ IdImm, L4_iadd_memoph_io>;
2686 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
2687 /*sext*/ IdImm, L4_iadd_memoph_io>;
2688 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
2689 /*zext*/ IdImm, L4_iadd_memoph_io>;
2690 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm,
2692 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
2693 /*anyext*/ NegImm8, L4_iadd_memopb_io>;
2694 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
2695 /*sext*/ NegImm8, L4_iadd_memopb_io>;
2696 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
2697 /*zext*/ NegImm8, L4_iadd_memopb_io>;
2698 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
2699 /*anyext*/ NegImm16, L4_iadd_memoph_io>;
2700 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
2701 /*sext*/ NegImm16, L4_iadd_memoph_io>;
2702 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
2703 /*zext*/ NegImm16, L4_iadd_memoph_io>;
2704 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32,
2708 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
2709 /*anyext*/ IdImm, L4_isub_memopb_io>;
2710 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
2711 /*sext*/ IdImm, L4_isub_memopb_io>;
2712 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
2713 /*zext*/ IdImm, L4_isub_memopb_io>;
2714 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
2715 /*anyext*/ IdImm, L4_isub_memoph_io>;
2716 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
2717 /*sext*/ IdImm, L4_isub_memoph_io>;
2718 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
2719 /*zext*/ IdImm, L4_isub_memoph_io>;
2720 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm,
2722 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
2723 /*anyext*/ NegImm8, L4_isub_memopb_io>;
2724 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
2725 /*sext*/ NegImm8, L4_isub_memopb_io>;
2726 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
2727 /*zext*/ NegImm8, L4_isub_memopb_io>;
2728 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
2729 /*anyext*/ NegImm16, L4_isub_memoph_io>;
2730 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
2731 /*sext*/ NegImm16, L4_isub_memoph_io>;
2732 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
2733 /*zext*/ NegImm16, L4_isub_memoph_io>;
2734 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32,
2738 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8,
2739 /*anyext*/ LogN2_8, L4_iand_memopb_io>;
2740 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8,
2741 /*sext*/ LogN2_8, L4_iand_memopb_io>;
2742 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8,
2743 /*zext*/ LogN2_8, L4_iand_memopb_io>;
2744 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16,
2745 /*anyext*/ LogN2_16, L4_iand_memoph_io>;
2746 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16,
2747 /*sext*/ LogN2_16, L4_iand_memoph_io>;
2748 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16,
2749 /*zext*/ LogN2_16, L4_iand_memoph_io>;
2750 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32,
2751 LogN2_32, L4_iand_memopw_io>;
2754 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32,
2755 /*anyext*/ Log2_8, L4_ior_memopb_io>;
2756 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32,
2757 /*sext*/ Log2_8, L4_ior_memopb_io>;
2758 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32,
2759 /*zext*/ Log2_8, L4_ior_memopb_io>;
2760 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32,
2761 /*anyext*/ Log2_16, L4_ior_memoph_io>;
2762 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32,
2763 /*sext*/ Log2_16, L4_ior_memoph_io>;
2764 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32,
2765 /*zext*/ Log2_16, L4_ior_memoph_io>;
2766 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32,
2767 Log2_32, L4_ior_memopw_io>;
2771 // --(15) Call -----------------------------------------------------------
2774 // Pseudo instructions.
2775 def SDT_SPCallSeqStart
2776 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2777 def SDT_SPCallSeqEnd
2778 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2780 def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2781 [SDNPHasChain, SDNPOutGlue]>;
2782 def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2783 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2785 def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2787 def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2788 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2789 def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall,
2790 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2791 def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall,
2792 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2794 def: Pat<(callseq_start timm:$amt, timm:$amt2),
2795 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>;
2796 def: Pat<(callseq_end timm:$amt1, timm:$amt2),
2797 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>;
2799 def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>;
2800 def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>;
2801 def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>;
2803 def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>;
2804 def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>;
2805 def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>;
2806 def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>;
2808 def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>;
2809 def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>;
2810 def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>;
2812 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
2813 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2814 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
2816 def: Pat<(retflag), (PS_jmpret (i32 R31))>;
2817 def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>;
2820 // --(16) Branch ---------------------------------------------------------
2823 def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>;
2824 def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>;
2826 def: Pat<(brcond I1:$Pu, bb:$dst),
2827 (J2_jumpt I1:$Pu, bb:$dst)>;
2828 def: Pat<(brcond (not I1:$Pu), bb:$dst),
2829 (J2_jumpf I1:$Pu, bb:$dst)>;
2830 def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst),
2831 (J2_jumpf I1:$Pu, bb:$dst)>;
2832 def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst),
2833 (J2_jumpt I1:$Pu, bb:$dst)>;
2836 // --(17) Misc -----------------------------------------------------------
2839 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
2840 // for C code of the form r = (c>='0' && c<='9') ? 1 : 0.
2841 // The isdigit transformation relies on two 'clever' aspects:
2842 // 1) The data type is unsigned which allows us to eliminate a zero test after
2843 // biasing the expression by 48. We are depending on the representation of
2844 // the unsigned types, and semantics.
2845 // 2) The front end has converted <= 9 into < 10 on entry to LLVM.
2848 // retval = (c >= '0' && c <= '9') ? 1 : 0;
2849 // The code is transformed upstream of llvm into
2850 // retval = (c-48) < 10 ? 1 : 0;
2852 def u7_0PosImmPred : ImmLeaf<i32, [{
2853 // True if the immediate fits in an 7-bit unsigned field and is positive.
2854 return Imm > 0 && isUInt<7>(Imm);
2857 let AddedComplexity = 139 in
2858 def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))),
2859 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>;
2861 let AddedComplexity = 100 in
2862 def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))),
2863 (i32 (extloadi8 (add I32:$b, 3))),
2866 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
2867 (zextloadi8 I32:$b)),
2868 (A2_swiz (L2_loadri_io I32:$b, 0))>;
2871 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
2872 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
2873 // We don't really want either one here.
2874 def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
2875 def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
2878 def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3),
2879 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
2880 def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)),
2881 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
2883 def SDTHexagonALLOCA
2884 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2886 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>;
2888 def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
2889 (PS_alloca IntRegs:$Rs, imm:$A)>;
2891 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
2892 def: Pat<(HexagonBARRIER), (Y2_barrier)>;
2894 // Read cycle counter.
2895 def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
2896 def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
2899 def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
2902 def SDTVecLeaf: SDTypeProfile<1, 0, [SDTCisVec<0>]>;
2904 def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
2905 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
2906 def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
2908 def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
2909 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
2910 def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
2912 def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt),
2913 (REG_SEQUENCE HvxWR, $Rs, vsub_hi, $Rt, vsub_lo)>;
2915 def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
2916 def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
2918 let Predicates = [UseHVX] in {
2919 def: OpR_RR_pat<V6_vpackeb, pf2<HexagonVPACKE>, VecI8, HVI8>;
2920 def: OpR_RR_pat<V6_vpackob, pf2<HexagonVPACKO>, VecI8, HVI8>;
2921 def: OpR_RR_pat<V6_vpackeh, pf2<HexagonVPACKE>, VecI16, HVI16>;
2922 def: OpR_RR_pat<V6_vpackoh, pf2<HexagonVPACKO>, VecI16, HVI16>;
2925 def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
2926 def vzero: PatFrag<(ops), (HexagonVZERO)>;
2928 def VSxtb: OutPatFrag<(ops node:$Vs),
2929 (V6_vshuffvdd (HiVec (V6_vsb $Vs)),
2930 (LoVec (V6_vsb $Vs)),
2932 def VSxth: OutPatFrag<(ops node:$Vs),
2933 (V6_vshuffvdd (HiVec (V6_vsh $Vs)),
2934 (LoVec (V6_vsh $Vs)),
2936 def VZxtb: OutPatFrag<(ops node:$Vs),
2937 (V6_vshuffvdd (HiVec (V6_vzb $Vs)),
2938 (LoVec (V6_vzb $Vs)),
2940 def VZxth: OutPatFrag<(ops node:$Vs),
2941 (V6_vshuffvdd (HiVec (V6_vzh $Vs)),
2942 (LoVec (V6_vzh $Vs)),
2945 let Predicates = [UseHVX] in {
2946 def: Pat<(VecI8 vzero), (V6_vd0)>;
2947 def: Pat<(VecI16 vzero), (V6_vd0)>;
2948 def: Pat<(VecI32 vzero), (V6_vd0)>;
2950 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
2951 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
2952 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
2953 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
2954 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
2955 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
2957 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
2958 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
2959 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
2960 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
2961 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
2962 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
2964 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),
2965 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
2966 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
2967 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
2968 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
2969 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
2971 def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
2972 def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
2973 def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
2975 def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
2976 def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
2977 def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
2979 def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
2980 def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
2981 def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
2983 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
2984 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
2985 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
2986 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
2987 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
2988 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
2990 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
2991 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
2992 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
2993 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
2995 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;
2996 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
2997 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
2998 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
3000 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;
3001 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
3002 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
3003 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;