1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
13 // %vreg176<def> = COPY %vreg170:isub_lo
16 // %vreg176<def> = COPY vreg166
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
21 // %vreg16<def> = NOT_p %vreg15<kill>
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
36 //===----------------------------------------------------------------------===//
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineFunctionPass.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
59 #define DEBUG_TYPE "hexagon-peephole"
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
62 cl::Hidden, cl::ZeroOrMore, cl::init(false),
63 cl::desc("Disable Peephole Optimization"));
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
66 cl::Hidden, cl::ZeroOrMore, cl::init(false),
67 cl::desc("Disable Optimization of PNotP"));
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
70 cl::Hidden, cl::ZeroOrMore, cl::init(true),
71 cl::desc("Disable Optimization of Sign/Zero Extends"));
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
74 cl::Hidden, cl::ZeroOrMore, cl::init(true),
75 cl::desc("Disable Optimization of extensions to i64."));
78 FunctionPass *createHexagonPeephole();
79 void initializeHexagonPeepholePass(PassRegistry&);
83 struct HexagonPeephole : public MachineFunctionPass {
84 const HexagonInstrInfo *QII;
85 const HexagonRegisterInfo *QRI;
86 const MachineRegisterInfo *MRI;
90 HexagonPeephole() : MachineFunctionPass(ID) {
91 initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
94 bool runOnMachineFunction(MachineFunction &MF) override;
96 StringRef getPassName() const override {
97 return "Hexagon optimize redundant zero and size extends";
100 void getAnalysisUsage(AnalysisUsage &AU) const override {
101 MachineFunctionPass::getAnalysisUsage(AU);
106 char HexagonPeephole::ID = 0;
108 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
111 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
112 if (skipFunction(*MF.getFunction()))
115 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
116 QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
117 MRI = &MF.getRegInfo();
119 DenseMap<unsigned, unsigned> PeepholeMap;
120 DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
122 if (DisableHexagonPeephole) return false;
124 // Loop over all of the basic blocks.
125 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
126 MBBb != MBBe; ++MBBb) {
127 MachineBasicBlock *MBB = &*MBBb;
129 PeepholeDoubleRegsMap.clear();
131 // Traverse the basic block.
132 for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
133 NextI = std::next(I);
134 MachineInstr &MI = *I;
135 // Look for sign extends:
136 // %vreg170<def> = SXTW %vreg166
137 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
138 assert(MI.getNumOperands() == 2);
139 MachineOperand &Dst = MI.getOperand(0);
140 MachineOperand &Src = MI.getOperand(1);
141 unsigned DstReg = Dst.getReg();
142 unsigned SrcReg = Src.getReg();
143 // Just handle virtual registers.
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
145 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
146 // Map the following:
147 // %vreg170<def> = SXTW %vreg166
148 // PeepholeMap[170] = vreg166
149 PeepholeMap[DstReg] = SrcReg;
153 // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
154 // %vreg170:DoublRegs, %vreg169:IntRegs
155 if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
156 assert(MI.getNumOperands() == 3);
157 MachineOperand &Dst = MI.getOperand(0);
158 MachineOperand &Src1 = MI.getOperand(1);
159 MachineOperand &Src2 = MI.getOperand(2);
160 if (Src1.getImm() != 0)
162 unsigned DstReg = Dst.getReg();
163 unsigned SrcReg = Src2.getReg();
164 PeepholeMap[DstReg] = SrcReg;
167 // Look for this sequence below
168 // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
169 // %vregIntReg = COPY %vregDoubleReg1:isub_lo.
171 // %vregIntReg = COPY %vregDoubleReg0:isub_hi.
172 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
173 assert(MI.getNumOperands() == 3);
174 MachineOperand &Dst = MI.getOperand(0);
175 MachineOperand &Src1 = MI.getOperand(1);
176 MachineOperand &Src2 = MI.getOperand(2);
177 if (Src2.getImm() != 32)
179 unsigned DstReg = Dst.getReg();
180 unsigned SrcReg = Src1.getReg();
181 PeepholeDoubleRegsMap[DstReg] =
182 std::make_pair(*&SrcReg, Hexagon::isub_hi);
185 // Look for P=NOT(P).
186 if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
187 assert(MI.getNumOperands() == 2);
188 MachineOperand &Dst = MI.getOperand(0);
189 MachineOperand &Src = MI.getOperand(1);
190 unsigned DstReg = Dst.getReg();
191 unsigned SrcReg = Src.getReg();
192 // Just handle virtual registers.
193 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
194 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
195 // Map the following:
196 // %vreg170<def> = NOT_xx %vreg166
197 // PeepholeMap[170] = vreg166
198 PeepholeMap[DstReg] = SrcReg;
203 // %vreg176<def> = COPY %vreg170:isub_lo
204 if (!DisableOptSZExt && MI.isCopy()) {
205 assert(MI.getNumOperands() == 2);
206 MachineOperand &Dst = MI.getOperand(0);
207 MachineOperand &Src = MI.getOperand(1);
209 // Make sure we are copying the lower 32 bits.
210 if (Src.getSubReg() != Hexagon::isub_lo)
213 unsigned DstReg = Dst.getReg();
214 unsigned SrcReg = Src.getReg();
215 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
216 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
217 // Try to find in the map.
218 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
219 // Change the 1st operand.
221 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
223 DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
224 PeepholeDoubleRegsMap.find(SrcReg);
225 if (DI != PeepholeDoubleRegsMap.end()) {
226 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
228 MI.addOperand(MachineOperand::CreateReg(
229 PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
230 false /*isKill*/, false /*isDead*/, false /*isUndef*/,
231 false /*isEarlyClobber*/, PeepholeSrc.second));
237 // Look for Predicated instructions.
240 if (QII->isPredicated(MI)) {
241 MachineOperand &Op0 = MI.getOperand(0);
242 unsigned Reg0 = Op0.getReg();
243 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
244 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
245 // Handle instructions that have a prediate register in op0
246 // (most cases of predicable instructions).
247 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
248 // Try to find in the map.
249 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
250 // Change the 1st operand and, flip the opcode.
251 MI.getOperand(0).setReg(PeepholeSrc);
252 MRI->clearKillFlags(PeepholeSrc);
253 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
254 MI.setDesc(QII->get(NewOp));
262 // Handle special instructions.
263 unsigned Op = MI.getOpcode();
265 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
268 case Hexagon::C2_mux:
269 case Hexagon::C2_muxii:
272 case Hexagon::C2_muxri:
273 NewOp = Hexagon::C2_muxir;
275 case Hexagon::C2_muxir:
276 NewOp = Hexagon::C2_muxri;
280 unsigned PSrc = MI.getOperand(PR).getReg();
281 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
282 BuildMI(*MBB, MI.getIterator(), MI.getDebugLoc(),
283 QII->get(NewOp), MI.getOperand(0).getReg())
285 .add(MI.getOperand(S2))
286 .add(MI.getOperand(S1));
287 MRI->clearKillFlags(POrig);
288 MI.eraseFromParent();
293 } // if (!DisablePNotP)
300 FunctionPass *llvm::createHexagonPeephole() {
301 return new HexagonPeephole();