1 //===--- HexagonPseudo.td -------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The pat frags in the definitions below need to have a named register,
11 // otherwise i32 will be assumed regardless of the register class. The
12 // name of the register does not matter.
13 def I1 : PatLeaf<(i1 PredRegs:$R)>;
14 def I32 : PatLeaf<(i32 IntRegs:$R)>;
15 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
16 def F32 : PatLeaf<(f32 IntRegs:$R)>;
17 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
19 let PrintMethod = "printGlobalOperand" in {
20 def globaladdress : Operand<i32>;
21 def globaladdressExt : Operand<i32>;
25 let isCodeGenOnly = 0 in
26 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
27 (ins s27_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">;
29 def DUPLEX_Pseudo : InstHexagon<(outs),
30 (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>;
33 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
34 isAsmParserOnly = 1 in
35 def TFRI64_V2_ext : InstHexagon<(outs DoubleRegs:$dst),
36 (ins s32_0Imm:$src1, s8_0Imm:$src2),
37 "$dst=combine(#$src1,#$src2)", [], "",
38 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
41 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
42 hasNewValue = 1, opNewValue = 0 in
43 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
45 : InstHexagon<(outs IntRegs:$dst),
46 (ins u16_0Imm:$imm_value),
47 "$dst"#RegHalf#"=#$imm_value", [], "",
48 rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
53 let Inst{26-24} = MajOp;
55 let Inst{20-16} = dst;
56 let Inst{23-22} = imm_value{15-14};
57 let Inst{13-0} = imm_value{13-0};
60 let isAsmParserOnly = 1 in {
61 def LO : REG_IMMED<".l", 0b0, 0b001, 0b1, A2_tfril>;
62 def HI : REG_IMMED<".h", 0b0, 0b010, 0b1, A2_tfrih>;
65 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
66 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
67 "$Rd = CONST32(#$v)", []>;
68 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
69 "$Rd = CONST64(#$v)", []>;
72 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
74 def PS_true : InstHexagon<(outs PredRegs:$dst), (ins), "",
75 [(set I1:$dst, 1)], "", C2_orn.Itinerary, TypeCR>;
77 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
79 def PS_false : InstHexagon<(outs PredRegs:$dst), (ins), "",
80 [(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
83 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
84 ".error \"should not emit\" ", []>;
86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
87 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
88 ".error \"should not emit\" ", []>;
91 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
92 Defs = [PC, LC0], Uses = [SA0, LC0] in {
93 def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset),
98 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
99 Defs = [PC, LC1], Uses = [SA1, LC1] in {
100 def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset),
105 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
106 opExtendable = 0, hasSideEffects = 0 in
107 class LOOP_iBase<string mnemonic, InstHexagon rootInst>
108 : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2),
109 #mnemonic#"($offset,#$src2)",
110 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
116 let Inst{27-22} = 0b100100;
117 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
118 let Inst{20-16} = src2{9-5};
119 let Inst{12-8} = offset{8-4};
120 let Inst{7-5} = src2{4-2};
121 let Inst{4-3} = offset{3-2};
122 let Inst{1-0} = src2{1-0};
125 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
126 opExtendable = 0, hasSideEffects = 0 in
127 class LOOP_rBase<string mnemonic, InstHexagon rootInst>
128 : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
129 #mnemonic#"($offset,$src2)",
130 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
136 let Inst{27-22} = 0b000000;
137 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
138 let Inst{20-16} = src2;
139 let Inst{12-8} = offset{8-4};
140 let Inst{4-3} = offset{3-2};
143 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
144 opExtendable = 0 in {
145 def J2_loop0iext : LOOP_iBase<"loop0", J2_loop0i>;
146 def J2_loop1iext : LOOP_iBase<"loop1", J2_loop1i>;
149 // Interestingly only loop0's appear to set usr.lpcfg
150 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
151 def J2_loop0rext : LOOP_rBase<"loop0", J2_loop0r>;
152 def J2_loop1rext : LOOP_rBase<"loop1", J2_loop1r>;
155 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
156 isExtended = 0, isExtendable = 1, opExtendable = 0,
157 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
158 class T_Call<string ExtStr>
159 : InstHexagon<(outs), (ins a30_2Imm:$dst),
160 "call " # ExtStr # "$dst", [], "", J2_call.Itinerary, TypeJ>,
162 let BaseOpcode = "call";
166 let Inst{27-25} = 0b101;
167 let Inst{24-16,13-1} = dst{23-2};
171 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
173 def CALLProfile : T_Call<"">;
175 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
176 Defs = [PC, R31, R6, R7, P0] in
177 def PS_call_stk : T_Call<"">;
180 let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
181 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
182 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
185 let isPredicatedFalse = 1;
188 let Inst{27-21} = 0b0000101;
189 let Inst{20-16} = Rs;
192 let isCall = 1, hasSideEffects = 1,
193 isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
194 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
195 class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops,
197 : Pseudo<(outs), iops, "">, PredRel {
200 let opExtentBits = nbits;
201 let isPredicable = 0; // !if(isPred, 0, 1);
202 let isPredicated = 0; // isPred;
203 let isPredicatedFalse = isFalse;
206 def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii), J2_call.Itinerary>;
207 //def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst),
208 // J2_callt.Itinerary>;
209 //def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst),
210 // J2_callf.Itinerary>;
212 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
213 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
215 class T_JMPr <InstHexagon rootInst>
216 : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
217 "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
221 let Inst{27-21} = 0b0010100;
222 let Inst{20-16} = dst;
225 // A return through builtin_eh_return.
226 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
227 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
228 def EH_RETURN_JMPR : T_JMPr<J2_jumpr>;
230 // Indirect tail-call.
231 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
232 isTerminator = 1, isCodeGenOnly = 1 in
233 def PS_tailcall_r : T_JMPr<J2_jumpr>;
236 // Direct tail-calls.
237 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
238 isTerminator = 1, isCodeGenOnly = 1 in
239 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
241 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
242 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
244 // Generate frameindex addresses. The main reason for the offset operand is
245 // that every instruction that is allowed to have frame index as an operand
246 // will then have that operand followed by an immediate operand (the offset).
247 // This simplifies the frame-index elimination code.
249 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
250 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
251 def PS_fi : Pseudo<(outs IntRegs:$Rd),
252 (ins IntRegs:$fi, s32_0Imm:$off), "">;
253 def PS_fia : Pseudo<(outs IntRegs:$Rd),
254 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
257 class CondStr<string CReg, bit True, bit New> {
258 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
260 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
261 string S = Mnemonic # !if(Taken, ":t", ":nt");
263 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
264 hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
265 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak, InstHexagon rootInst>
266 : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
267 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
268 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
269 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
272 let isPredicatedFalse = PredNot;
273 let isPredicatedNew = isPredNew;
279 let Inst{27-22} = 0b001101;
280 let Inst{21} = PredNot;
281 let Inst{20-16} = dst;
282 let Inst{12} = isTak;
283 let Inst{11} = isPredNew;
287 let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
288 isBarrier = 1, BaseOpcode = "JMPret" in {
289 def PS_jmpret : T_JMPr<J2_jumpr>, PredNewRel;
290 def PS_jmprett : T_JMPr_c<0, 0, 0, J2_jumprt>, PredNewRel;
291 def PS_jmpretf : T_JMPr_c<1, 0, 0, J2_jumprf>, PredNewRel;
292 def PS_jmprettnew : T_JMPr_c<0, 1, 0, J2_jumprtnew>, PredNewRel;
293 def PS_jmpretfnew : T_JMPr_c<1, 1, 0, J2_jumprfnew>, PredNewRel;
294 def PS_jmprettnewpt : T_JMPr_c<0, 1, 1, J2_jumprtnewpt>, PredNewRel;
295 def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel;
298 //defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>;
300 // The reason for the custom inserter is to record all ALLOCA instructions
301 // in MachineFunctionInfo.
302 let Defs = [R29], hasSideEffects = 1 in
303 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
304 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
307 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
308 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
309 def LDriw_pred : LDInst<(outs PredRegs:$dst),
310 (ins IntRegs:$addr, s32_0Imm:$off),
311 ".error \"should not emit\"", []>;
314 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
315 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
316 def LDriw_mod : LDInst<(outs ModRegs:$dst),
317 (ins IntRegs:$addr, s32_0Imm:$off),
318 ".error \"should not emit\"", []>;
321 let isCodeGenOnly = 1, isPseudo = 1 in
322 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
323 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
324 ".error \"should not emit\" ", [], "", A2_tfrpt.Itinerary, TypeALU32_2op>;
326 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
328 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
329 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
330 class T_JMP: InstHexagon<(outs), (ins b30_2Imm:$dst),
332 [], "", J2_jump.Itinerary, TypeJ>, OpcodeHexagon {
336 let Inst{27-25} = 0b100;
337 let Inst{24-16} = dst{23-15};
338 let Inst{13-1} = dst{14-2};
341 // Restore registers and dealloc return function call.
342 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
343 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
344 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP;
346 let isExtended = 1, opExtendable = 0 in
347 def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP;
349 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
350 def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP;
352 let isExtended = 1, opExtendable = 0 in
353 def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP;
357 // Restore registers and dealloc frame before a tail call.
358 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
359 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
361 let isExtended = 1, opExtendable = 0 in
362 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
364 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
365 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel;
367 let isExtended = 1, opExtendable = 0 in
368 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel;
372 // Save registers function call.
373 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
374 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
376 let isExtended = 1, opExtendable = 0 in
377 def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
380 def SAVE_REGISTERS_CALL_V4STK : T_Call<"">, PredRel;
382 let Defs = [P0], isExtended = 1, opExtendable = 0 in
383 def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<"">, PredRel;
385 let Defs = [R14, R15, R28] in
386 def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel;
388 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
389 def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel;
391 let Defs = [R14, R15, R28, P0] in
392 def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<"">, PredRel;
394 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
395 def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel;
398 // Vector store pseudos
399 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
400 mayStore = 1, hasSideEffects = 0 in
401 class STrivv_template<RegisterClass RC, InstHexagon rootInst>
402 : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src),
403 "", [], "", rootInst.Itinerary, rootInst.Type>;
405 def PS_vstorerw_ai: STrivv_template<VecDblRegs, V6_vS32b_ai>,
406 Requires<[HasV60T,UseHVXSgl]>;
407 def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32b_ai_128B>,
408 Requires<[HasV60T,UseHVXDbl]>;
410 def PS_vstorerwu_ai: STrivv_template<VecDblRegs, V6_vS32Ub_ai>,
411 Requires<[HasV60T,UseHVXSgl]>;
412 def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32Ub_ai_128B>,
413 Requires<[HasV60T,UseHVXDbl]>;
415 // Vector load pseudos
416 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
417 mayLoad = 1, hasSideEffects = 0 in
418 class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
419 : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
420 "", [], "", rootInst.Itinerary, rootInst.Type>;
422 def PS_vloadrw_ai: LDrivv_template<VecDblRegs, V6_vL32b_ai>,
423 Requires<[HasV60T,UseHVXSgl]>;
424 def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32b_ai_128B>,
425 Requires<[HasV60T,UseHVXDbl]>;
427 def PS_vloadrwu_ai: LDrivv_template<VecDblRegs, V6_vL32Ub_ai>,
428 Requires<[HasV60T,UseHVXSgl]>;
429 def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32Ub_ai_128B>,
430 Requires<[HasV60T,UseHVXDbl]>;
432 // Store vector predicate pseudo.
433 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
434 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
435 def PS_vstorerq_ai : STInst<(outs),
436 (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1),
437 ".error \"should not emit\" ", []>,
438 Requires<[HasV60T,UseHVXSgl]>;
440 def PS_vstorerq_ai_128B : STInst<(outs),
441 (ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1),
442 ".error \"should not emit\" ", []>,
443 Requires<[HasV60T,UseHVXSgl]>;
445 def PS_vloadrq_ai : STInst<(outs),
446 (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
447 ".error \"should not emit\" ", []>,
448 Requires<[HasV60T,UseHVXDbl]>;
450 def PS_vloadrq_ai_128B : STInst<(outs),
451 (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
452 ".error \"should not emit\" ", []>,
453 Requires<[HasV60T,UseHVXDbl]>;
456 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
457 class VSELInst<dag outs, dag ins, InstHexagon rootInst>
458 : InstHexagon<outs, ins, "", [], "", rootInst.Itinerary, rootInst.Type>;
460 def PS_vselect: VSELInst<(outs VectorRegs:$dst),
461 (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
462 V6_vcmov>, Requires<[HasV60T,UseHVXSgl]>;
463 def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
464 (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
465 V6_vcmov>, Requires<[HasV60T,UseHVXDbl]>;
467 def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
468 (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3),
469 V6_vccombine>, Requires<[HasV60T,UseHVXSgl]>;
470 def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
471 (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
472 V6_vccombine>, Requires<[HasV60T,UseHVXDbl]>;
475 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
476 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
477 def STriw_pred : STInst<(outs),
478 (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),
479 ".error \"should not emit\"", []>;
481 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
482 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
483 def STriw_mod : STInst<(outs),
484 (ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1),
485 ".error \"should not emit\"", []>;
487 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
488 isAsmParserOnly = 1 in
489 def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst),
490 (ins u64_0Imm:$src1),
491 "$dst = #$src1", [], "",
492 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
494 // Hexagon doesn't have a vector multiply with C semantics.
495 // Instead, generate a pseudo instruction that gets expaneded into two
496 // scalar MPYI instructions.
497 // This is expanded by ExpandPostRAPseudos.
499 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
500 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
503 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
504 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
507 def DuplexIClass0: InstDuplex < 0 >;
508 def DuplexIClass1: InstDuplex < 1 >;
509 def DuplexIClass2: InstDuplex < 2 >;
510 let isExtendable = 1 in {
511 def DuplexIClass3: InstDuplex < 3 >;
512 def DuplexIClass4: InstDuplex < 4 >;
513 def DuplexIClass5: InstDuplex < 5 >;
514 def DuplexIClass6: InstDuplex < 6 >;
515 def DuplexIClass7: InstDuplex < 7 >;
517 def DuplexIClass8: InstDuplex < 8 >;
518 def DuplexIClass9: InstDuplex < 9 >;
519 def DuplexIClassA: InstDuplex < 0xA >;
520 def DuplexIClassB: InstDuplex < 0xB >;
521 def DuplexIClassC: InstDuplex < 0xC >;
522 def DuplexIClassD: InstDuplex < 0xD >;
523 def DuplexIClassE: InstDuplex < 0xE >;
524 def DuplexIClassF: InstDuplex < 0xF >;